TW201629955A - Method and apparatus for providing three-dimensional integrated nonvolatile memory and dynamic random access memory memory device - Google Patents

Abstract

A memory system able to store information using a hybrid volatile and nonvolatile memory device organized in a stacking configuration is disclosed. The memory system, in one aspect, includes memory components, a drain select gate ("DSG") transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory ("DRAM") function.

Description

A method for providing a three-dimensional integrated memory device of a volatile memory and a dynamic random access memory device

Exemplary embodiments of the invention relate to the field of semiconductor and integrated circuits. In particular, exemplary embodiments of the invention relate to memory and storage devices.

In today's technology world, non-volatile memory such as NAND or NOR flash memory has been widely used. Its unique unit and array structure provide small cell size, high density, low write current, and efficient filtering. Non-volatile memory such as NAND-type flash memory is the main storage memory type for various devices and systems such as memory cards, USB flash drives, and solid state disks. Some exemplary applications of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, electronic game machines, scientific instruments, industrial robots, and medical appliances.

With the recent development of semiconductor process technology, it has become possible to convert NAND flash memory from two-dimensional (2D) to three-dimensional (3D). For example, a three-dimensional NAND flash memory can achieve a storage capacity of 128 to 256 gigabits (Gb). Although conventional three-dimensional NAND flash memory technology can use 16 nanometer (nm) technology, NAND is comparable to the speed of dynamic random access memory (DRAM) or static random access memory (SRAM). The general speed of flash memory is still relatively slow.

However, a problem associated with general three-dimensional NAND-type flash memory is the transfer of data between non-volatile memory (NVM) chips and random access memory (such as DRAM and/or SRAM). Since conventional NVM and DRAM are fabricated on different dies, communication between the NVM and the DRAM via external routing typically hampers the overall data transfer rate.

Another disadvantage associated with conventional NAND type flash memory is that it has a relatively low programming speed. One reason for slow programming speeds and/or erase speeds is that conventional NAND flash memory is performed by single page programming. In some applications, slower programming speeds and/or erase speeds in non-volatile memory will be limiting.

One embodiment of the present invention discloses a memory-storable memory system that uses a hybrid volatile and non-volatile memory device arranged in a stacked configuration. In one aspect, the memory system includes a plurality of memory elements, a drain select gate (DSG) transistor, and a capacitive element. In one example, each memory element includes a source terminal, a gate terminal, a gate terminal, and a non-volatile cell. The memory elements are arranged in a string and the elements are connected between the source terminal and the drain terminal. The NMOS terminal of the DSG transistor is coupled to the source terminal of a memory device, and the gate terminal of the DSG transistor is coupled to a DSG signal. The 汲 extreme of the capacitive element is coupled to the source terminal of the first DSG transistor. The capacitive component is configured to perform a dynamic random access memory (DRAM) function.

Other features and advantages of the present invention will become more apparent from the following description of the appended claims.

100, 101, 390, 396, 398, 490, 491, 492, 494‧‧‧ block diagram

102‧‧‧Storage

106‧‧‧DRAM

108‧‧‧NVM

150‧‧‧ processor

152‧‧‧NVM storage

156‧‧‧Line Manager

158‧‧‧ cable

160‧‧‧ memory

170‧‧‧NVM/DRAM memory device

172‧‧‧NVM storage

176‧‧‧DRAM section

178‧‧‧NVM part

201‧‧‧DRAM unit

202‧‧‧NAND strings

203‧‧‧Selecting a crystal

204‧‧‧MOS capacitor

205, 206‧‧‧Diffusion zone

207‧‧‧ channel

208‧‧‧Substrate

209‧‧‧Dielectric material

210‧‧‧Charge trapping layer

211‧‧‧metal layer

290, 291, 392, 493, 495 ‧ ‧ schematic

292‧‧‧ Timing diagram

301‧‧‧Channel area

401-404‧‧‧ capacitor

401‧‧‧ dielectric material layer

402, 406, 507, 509‧‧‧ ONO layers

403a, 403b, 403c, 403d‧‧‧ capacitors

404a, 404b, 404c‧‧‧ memory unit

405a, 405b, 405c‧‧‧ memory unit

405-408‧‧‧Bungee selection gate

411-414‧‧‧MOS capacitor

415-418‧‧‧DSG

501‧‧‧ channel

502‧‧‧Select gate

503‧‧‧MOS capacitor

504a, 504b, 504c, 505a, 505b, 505c‧ ‧ capacitor

506a, 506b, 506c, 508a, 508b, 508c‧‧‧ NAND flash memory unit

550, 552‧‧‧ vertical strings

590, 592‧‧‧Three-dimensional NVM/DRAM unit structure

601‧‧‧DRAM unit

602‧‧‧NAND cell string

603‧‧‧MOS capacitor

604‧‧‧ extremely selective gate

605, 606‧‧‧DSG

607, 608‧‧‧ MOS capacitors

609‧‧‧DRAM selection gate

610‧‧‧ logical part

612‧‧‧Second source selection gate

690‧‧‧3D hybrid NVM/DRAM memory device

701-705‧‧‧NAND string

706, 707‧‧‧ source line

708, 1708‧‧‧ substrates

801, 802, 803‧‧‧ INT layer

901‧‧‧First DRAM unit

902‧‧‧Second DRAM unit

903‧‧‧NAND NVM string

904, 905‧‧‧DPG

1001, 1105, 1205, 1402, 1502, 1601, 1701‧‧‧ NAND strings

1002, 1003, 1101-1104, 1201-1204, 1303, 1401, 1501, 1602, 1702‧‧ ‧ DRAM unit

1301‧‧‧ Pipe section

1302‧‧‧Selecting the gate

1390‧‧‧Hybrid NVM/DRAM Array Structure

1392‧‧‧3D hybrid NVM/DRAM array structure

1403‧‧‧ DRAM cell selection gate

1404‧‧‧MOS capacitor

1503‧‧‧Cylindrical Capacitors

1504‧‧‧Interconnect layer

1603‧‧‧Channel/Path

1604‧‧‧Interconnects

1605‧‧‧The upper interconnection

1703‧‧‧ interconnection rod

1704‧‧‧PIP capacitors

1705‧‧‧VIA

1706‧‧‧Source and bungee diffusion layers

1707‧‧‧MOS selection gate

1709‧‧‧Independence gate

1800, 1900‧‧‧ flow chart

1802, 1804, 1806, 1902, 1904, 1906, 1908‧‧‧

DSG‧‧‧Bunge selection gate

SSG‧‧‧Source selection gate

CAP‧‧‧ capacitor

WL, WL0-3‧‧‧ character line

SL‧‧‧Semiconductor layer

BL, BL0-3‧‧‧ bit line

DWL, DWL0-3‧‧‧DRAM word line

CAP1, CAP2, CAPM‧‧‧ control signals

BG‧‧‧ back gate

WL0-WLN‧‧‧ tandem unit

DWL0-1‧‧‧DRAM selection gate

SSG1‧‧‧First source selection gate

SSG2‧‧‧Second source selection gate

DSG0-3‧‧‧ signal

INT‧‧‧Interconnection

DPG‧‧‧DRAM transfer gate

ISO‧‧‧ independent gate

M0-M8‧‧‧O crystal

More thorough geography through the detailed description below and the drawings of various embodiments of the present invention The present invention is to be construed as being limited to the specific embodiments.

1A to 1B are diagrams showing a digital processing system capable of storing data using a three-dimensional (3D) non-volatile memory (NVM) array and a dynamic random access memory (DRAM) according to an embodiment of the present invention. Figure.

2A-2B are schematic diagrams showing a hybrid NVM/DRAM memory device having a plurality of NVM strings arranged in a 3D configuration in accordance with an embodiment of the present invention.

2C is a timing diagram showing waveforms associated with various gate signals for managing three-dimensional NVM and DRAM (NVM/DRAM) storage configurations in accordance with an embodiment of the present invention.

3A through 3D are block diagrams showing a 3D physical layout associated with a 3D hybrid NVM/DRAM memory device in a vertical direction in accordance with an embodiment of the present invention.

4A through 4F are block diagrams showing other aspects of displaying a physical layout in a vertical direction of a 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention.

5A through 5F are block diagrams showing other aspects of the physical layout in the vertical direction of the 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention.

Figures 6A through 6F show 3D block diagrams of physical layouts associated with 3D hybrid NVM/DRAM memory devices in accordance with an embodiment of the present invention.

7A through 7B are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device using different serial mode in accordance with an embodiment of the present invention.

8A through 8C are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device using different DRAM word line (DWL) configurations in accordance with an embodiment of the present invention.

9A through 9B are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device using different DRAM transfer gate (DPG) configurations in accordance with an embodiment of the present invention.

10A through 10B are 3D block diagrams showing other aspects of a physical layout of a 3D hybrid NVM/DRAM memory device using different DRAM transfer gate (DPG) configurations in accordance with an embodiment of the present invention.

11A through 11B are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device having a multi-layered capacitor layer in accordance with an embodiment of the present invention.

12A through 12B are 3D block diagrams showing other aspects of the physical layout of a 3D hybrid NVM/DRAM memory device having a multi-layered capacitive layer in accordance with an embodiment of the present invention.

13A through 13B are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device using other vertical structures in accordance with an embodiment of the present invention.

Figure 14 is a 3D block diagram showing a side view of a physical layout of a 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention.

15 through 17 are 3D block diagrams showing the physical layout of a 3D hybrid NVM/DRAM memory device using different capacitance layers in accordance with an embodiment of the present invention.

Figure 18 is a flow chart showing the operation of a 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention.

Figure 19 is a flow chart showing the manufacturing procedure of a 3DNVM/DRAM memory device in accordance with an embodiment of the present invention.

The present invention will be described below in order to provide simultaneous use of volatiles and non-volatiles. A method, apparatus and apparatus for a storage device for a volatile memory device.

It is to be understood by those skilled in the art that the invention The advantages of other embodiments of the present invention are readily apparent to those skilled in the art. The details of the exemplary embodiments of the present invention are described with reference to the accompanying drawings. In the drawings and the detailed description below, the same reference numerals (numbers) will refer to the same or similar parts.

In accordance with embodiments of the present invention, the components, process steps, and/or data structures described herein can be implemented via various operating systems, computing platforms, computer programs, and/or general purpose machines. Wherein, the method comprising a series of process steps is performed by a computer or a machine, and the process steps can be stored by the machine in the form of a series of readable instructions, which can be stored on a tangible medium, such as a computer. Memory devices such as ROM (read only memory), PROM (programmable read-only memory), EEPROM (electronic erasable programmable read-only memory), flash memory, flash drives, and the like; magnetic storage media Such as tapes, drives and the like; optical storage media such as CD-ROMs, DVD-ROMs, paper cards and tapes and the like; and other known types of program memory.

It will be appreciated by those skilled in the art that the devices described herein can be formed on a conventional semiconductor substrate, or they can be simply formed over a substrate, such as glass, in the form of a thin film transistor (TFT). SOG), sapphire (SOS) within the insulating layer (SOI), or other substrates known to those of ordinary skill in the art. It will also be appreciated by those skilled in the art that the substrate can perform its function within a range of doping concentrations. Basically, any pFET and nFET can be formed to function. The doped regions can be formed by diffusion or implantation.

The term "system" is used herein to describe generally any number of components, components, subsystems, devices, combination of switching elements, combination switches, routers, networks, computers, and/or A communication device or mechanism or a combination of the aforementioned elements. The term "computer" is used herein to describe any number of computers in general, including but not limited to personal computers, embedded processors and systems, control logic, ASICs, chips, workstations, mainframes, and the like. The term "device" is used herein to generally describe any form of mechanism, including a computer or system or elements thereof. The terms "task" and "program" are used throughout this document to describe any type of program execution, including but not limited to a computer program, tasks, threads, execution applications, operating systems, user programs, devices. Driver, source code, machine or other language, etc., and may be interactive and/or non-interactive, local and/or remote execution, foreground and/or background execution, user and/or operating system address Space execution, inventory programs, and/or stand-alone applications, and are not limited to any specific memory cutting technology. The steps and associations of the signals and information are illustrated in, but not limited to, the blocks and the flowcharts, and in various embodiments, which are generally in a sequential or parallel order and/or via different components and / or by different connection relationships, but are consistent with the scope and spirit of the invention.

One embodiment of the present invention discloses a memory-storable memory system that uses a hybrid volatile and non-volatile memory device arranged in a stacked configuration. In one aspect, the memory system includes a plurality of memory elements, a drain select gate (DSG) transistor, and a capacitive element. In one example, each memory element includes a source terminal, a gate terminal, a gate terminal, and a non-volatile cell. The memory elements are arranged in a string and the elements are connected between the source terminal and the drain terminal. The NMOS terminal of the DSG transistor is coupled to the source terminal of a memory device, and the gate terminal of the DSG transistor is coupled to a DSG signal. The 汲 extreme of the capacitive element is coupled to the source terminal of the first DSG transistor. The capacitive component is configured to perform a dynamic random access memory (DRAM) function.

1A is a block diagram 100 showing one of the embodiments of the present invention. A digital processing system that stores data using a three-dimensional (3D) non-volatile memory (NVM) array and dynamic random access memory (DRAM). In one embodiment, block diagram 100 includes a processor 150, NVM storage 152, and a row of wires 158. The processor 150 further includes a chip built-in memory 160 and a line manager 156. The chip built-in memory 160 further includes a 3D dual function memory 102 capable of performing DRAM functions and/or NVM functions according to mode selection. . In one embodiment, the storage device 102 is a 3D hybrid NVM and DRAM (NVM/DRAM) memory device, wherein the three-dimensional NVM 108 is located in a section of the storage 102, and the three-dimensional DRAM 106 is located in the storage 102. Another section. In one example, DRAM 106 is coupled to NVM 108 for data storage and emergency backup. In one aspect, the NVM can be a NAND type flash memory, a NOR type flash memory, a floating gate unit, a charge trap type unit, a SONOS unit, a PMOS unit, a split gate unit, a phase change memory element (PCM). , EEPROM (erasable programmable read only memory) or a combination of NAND, NOR, PCM, and / or EEPROM memory. To simplify the foregoing discussion, a NAND type flash memory will be used as an exemplary NVM in the specification. It should be noted, however, that even if one or more blocks (or devices) are added or removed from block diagram 100, the basic concepts of the exemplary embodiments of the present invention are not altered.

The storage 102 including the hybrid NVM unit 108 and the DRAM unit 106 may be referred to as 3D hybrid NVM/DRAM or DRAM-NAND (DNAND). It should be noted that the DRAM cell and the NAND cell are coupled to each other to enhance memory performance. In one aspect, the DNAND cell has a NAND-like cell structure similar to the NAND cell, wherein the DNAND cell can be used as a NAND cell and a DRAM cell depending on the mode of operation. Although the memory 160 is an embedded memory in a central processing unit (CPU) 150, the memory 160 can also be a separate memory chip that provides dual functions of NVM and DRAM.

Since the three-dimensional NVM/DRAM 102 uses a similar NAND string to simultaneously provide DRAM storage The memory function and the NAND flash memory function, the three-dimensional NVM/DRAM 102 can simultaneously place the DRAM cells and the NAND cells on a single wafer or die. To create or fabricate DRAMs that are compatible with NAND processes, NAND and DRAM cells can be fabricated simultaneously on a single die or die. The NAND array and DRAM array can also be embedded in a microcontroller or any other wafer.

In operation, the on-chip memory 160 facilitates the transfer of data between the NVM/DRAM 102 and the NVM 152 via the cable 158. The cable manager 156 can simultaneously transfer data between the NVM/DRAM 102 of the memory 160 and the NVM 152. In another embodiment, the on-chip memory 160 can back up data within the DRAM 106 to the NVM unit 108 during an emergency shutdown or power outage.

One advantage of using a on-chip memory 160 that includes both DRAM and NVM is that it facilitates simultaneous programming of multiple pages of NVM and erasure of multiple blocks. In addition, the on-chip memory 160 can also improve the data transfer rate between the on-chip memory 160 and the NVM 152 using the three-dimensional NVM/DRAM 102. Moreover, another advantage of using the on-chip memory 160 is that data can be backed up from the DRAM unit 106 to the NVM unit 108 in an emergency.

1B is a block diagram 101 showing a digital processing system for storing data using a 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention. In one embodiment, block diagram 101 includes a processor 150, NVM storage 172, and a row of wires 158. The NVM storage 172 further includes one or more 3D hybrid NVM/DRAM memory devices that can perform DRAM functions as well as NVM functions. In one embodiment, the hybrid NVM/DRAM memory device 170 includes one or more 3D arrays 172, wherein each 3D array 172 includes a DRAM portion 176 and an NVM portion 178. In one embodiment, DRAM portion 176 includes one or more data that can be temporarily stored. DRAM unit. The NVM portion 178 includes one or more NVM strings that can store data for a long time. In one aspect, the DRAM cell is coupled to the NVM cell for data storage and emergency backup.

2A-2B are schematic diagrams 290-291 illustrating a hybrid NVM/DRAM memory device having a plurality of NVM strings arranged in a 3D configuration, in accordance with an embodiment of the present invention. Schematic 290 shows a 2D array embodiment in accordance with an embodiment of the present invention. The 2D array includes metal oxide semiconductor (MOS) capacitors 401-404 to the string of cells, wherein MOS capacitors 401-404 are capable of holding a charge. In addition, a set of secondary drain select gates (DSGs) 405-408 are added to the strings to manage the operation of the DRAM and/or the operation of the NVM. It should be noted that even if one or more blocks (or devices) are added or removed from the schematic 290, the basic concepts of the exemplary embodiments of the present invention are not altered.

In one embodiment, the hybrid NVM/DRAM memory device includes a plurality of memory elements, a DSG transistor, and a capacitive element configured to store information. Each memory element has a source terminal, a gate terminal, a terminal electrode, and a non-volatile unit. The memory elements are arranged in a string and are connected between the source terminal and the drain terminal of the memory element. In one example, the string refers to a NAND-type NVM string, a NAND string, a NAND cell, an NVM cell string, or the like.

The DSG transistor has a source terminal, a terminal extreme, and a gate terminal, wherein a drain of the DSG transistor is coupled to a source terminal of the memory element. The gate of the DSG transistor is coupled to a first DSG signal for controlling the logic state of the DSG transistor. The hybrid NVM/DRAM memory device further includes an SSG (Source Select Gate), wherein a source terminal of the SSG component is coupled to a terminal of one of the string of memory elements.

In one aspect, the capacitive element includes a source terminal, a drain terminal, and a gate terminal, wherein a drain of the capacitive element is coupled to a source terminal of the DSG transistor. The capacitive element can perform the function of a DRAM. In one aspect, the hybrid NVM/DRAM memory device further includes a second A DSG transistor, wherein a 汲 extreme of the second DSG transistor is coupled to a source terminal of the capacitive element. The capacitive element can be any kind of semiconductor capacitor such as a MOS capacitor, a PIP (poly-insulator-poly-capacitor) capacitor, a stacked capacitor, a cylindrical capacitor, and the like.

2B shows a schematic 291 similar to schematic 290, the difference being that schematic 291 illustrates a three-dimensional NVM/DRAM array structure using 3D layout techniques. In one example, MOS capacitors (CAP) 411-414 are used to hold charge. In addition, a set of secondary DSGs 415-418 are added to manage the operation of the DRAM and/or the operation of the NVM. In these array configurations, the data for each page is stored in MOS capacitors 411-414 and then reprogrammed to the selected cells. The gates of MOS capacitors 411-414 are connected to a suitable capacitor voltage, such as VDD or other voltages that can activate MOS capacitors 411-414.

One advantage of using a three-dimensional NVM/DRAM memory device is that the device can perform multiple page read operations as well as multiple page write operations.

2C is a timing diagram 292 depicting waveforms associated with various gate signals for managing a three-dimensional NVM/DRAM storage configuration in accordance with an embodiment of the present invention. Timing diagram 292 shows the programming waveform of the three-dimensional NVM/DRAM array structure shown in FIG. 2A or 2B. At T0, the data for each page is applied to the BL (bit line), and the DSG[0]-DSG[N] is applied with a VDD pulse to page the data into the MOS capacitors page by page. After loading the MOS capacitors, at T1, the DSG is applied with VDD to activate the secondary DSGs, and data is loaded from the MOS capacitors to the strings of cells. These WLs are applied with Vpgm and Vpass for programming. At T2, the WL voltages are discharged and the programming pulse is completed.

According to an embodiment of the present invention, the 2D and 3D array structures as shown in FIGS. 2A to 2B can perform a multi-block erase operation. There are at least three ways to erase. The first way is to apply a high voltage Vers (eg 18V to 20V) to the P well in the units Area. The WL of the selected plurality of blocks is applied with 0V, which can be injected into a channel region from a floating gate by the Fowler-Nordheim tunneling effect to lower the Vt (threshold voltage) of the cell. At the same time, the WL of the unselected block is floating, whereby WL is coupled to 18-20V via the P-well region, so that the unselected cells are not erased.

The second way is to place the units in multiple P well areas, such as placing a block into a P well area. During the erase operation, the P wells of the selected plurality of blocks are subjected to Vers (such as an erase voltage of 18-20 V), while WL is applied with 0 V to erase the cells. The P well area of the unselected block and the WL are applied with 0V to prevent the erase operation.

The third method requires a negative WL voltage. The WL of the selected plurality of blocks is applied with a negative high voltage, such as -18V to -20V. The P well region is applied with 0V, which will cause electrons to be injected into the channel region from the floating gate to erase the cells. The WL of the unselected block is applied with 0V to prevent the erasure from occurring.

It should be noted that the NVM units within the three-dimensional NVM/DRAM memory device can be any type of NVM unit including, but not limited to, NAND flash memory, floating gate (FG) units, such as SONOS (矽a charge trapping unit of a oxy-zinc nitride-oxygen-oxide unit, a PMOS unit, a split gate unit, and the like.

3A is a block diagram 390 showing a vertical 3D physical layout associated with a 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention. Block diagram 390 illustrates a hybrid NVM and DRAM layout in which a DRAM cell 201 is stacked on top of a three dimensional NAND string 202. In an alternative embodiment, the three-dimensional NAND-type NVM string 202 extends to include the DRAM cell 201, wherein both the NVM string 202 and the DRAM cell 201 are integrated into a channel or channel 207. It should be noted that even if one or more blocks (or devices) are added or removed from block diagram 390, the basic concepts of the exemplary embodiments of the present invention are not changed.

DRAM cell 201 includes a select transistor 203 and a MOS capacitor 204, wherein select transistor 203 is coupled to the DRAM word line (DWL) and MOS capacitor 204 is coupled to the capacitor (CAP) voltage. The CAP voltage is normally a positive voltage for the NMOS and a negative voltage for the PMOS, wherein the function of the CAP voltage is to activate the channel region of the MOS capacitor 204. In one aspect, DRAM cell 201 includes a plurality of capacitors to enhance random access storage capabilities.

The three-dimensional NAND string 202, which may also be referred to as a three-dimensional NAND-type NVM string, is a cell string of a three-dimensional NAND flash memory. The NAND string 202 includes a DSG, an SSG, and a plurality of series connected cells WL0-WLN. In one example, the select gate (eg, DSG or SSG) has a longer channel length due in part to the need to turn off one or more programmed high voltages. It should be noted that the NVM units are placed in a lateral orientation so that one NVM unit can be stacked on top of another NVM unit. In one aspect, NAND string 202 can include a number of cells ranging from 8 to 128 NVM cells. NAND string 202 and DRAM cell 201 are coupled via channel 207.

Channel 207, which may be a polychannel, includes two diffusion regions 205-206. Diffusion regions 205-206 may be fabricated or formed via an N-type doping procedure and thus may be referred to as an NMOS transistor. Alternatively, the diffusion region is fabricated by a P-type doping procedure and thus may generally be referred to as a PMOS transistor. Channel 207 is formed or made of tantalum or polydazole. In one example, channel 207 is not doped or is only lightly doped with dopants, which in the latter are doped with diffusion species 205-206 with opposite species of dopants or dopants. In one aspect, the channel 207 is formed of a gate oxide or a high K dielectric material 209. Alternatively, an ONO (oxide-nitride-oxide) layer or any other type of charge trapping layer 210 may be used to store charge such as electrons or holes representing unit data. The substrate 208 for the NMOS can be a P-SUB, and the PMOS can be a N well, wherein the channel 207 is constructed to have an orientation substantially perpendicular to the substrate 208. The metal layer 211 is used to receive or transmit via a bit line (BL) data.

Figure 3B is a schematic 392 showing a circuit substantially equivalent to the three-dimensional DRAM and NAND cell strings shown in Figure 3A. Schematic 392 includes a transistor or component M7-M8 for use in a DRAM cell. In addition, NVM cells or transistors M0-M6 are used to construct the three-dimensional NAND string.

One advantage of using a hybrid NVM/DRAM memory device is that it integrates a three-dimensional NVM cell string with a DRAM cell on the same wafer to improve overall data throughput for high speed applications. For example, for non-volatile storage, the DRAM cell data can be written into a selected page of the three-dimensional NAND string. When the system needs to store data in the NAND-NVM string, it can read the data from the selected page in the NVM unit to the DRAM unit. Since the read/write operation between the DRAM and the NAND cell can be performed simultaneously for a plurality of memory strings, the hybrid NVM/DRAM memory device can achieve high-speed read and write operations.

3C through 3D are block diagrams 396, 398 showing a vertical 3D physical layout associated with a three dimensional NVM/DRAM in accordance with an embodiment of the present invention. Block diagram 396 shows a 3D layout similar to the 3D layout shown in block diagram 390 (FIG. 3A), with the difference that the channel region 301 of the MOS capacitor is doped with dopants used in the remaining channels 207. The opposite category. The channel region 301 of the MOS capacitor facilitates the MOS capacitor 204 to be a depletion transistor, whereby it will not require a gate voltage CAP to activate the channel region. The 3D figure is a schematic diagram 398 which shows the equivalent circuit of the cell string shown in FIG. 3A. It should be noted that the MOS capacitor M8 represents a depletion transistor.

4A is a block diagram 490 showing another aspect of the physical layout of a three-dimensional NVM/DRAM memory device in a vertical direction in accordance with an embodiment of the present invention. The memory device shown in block diagram 490 is similar to the memory device shown in block diagram 390 (FIG. 3A). The MOS capacitor 204 includes a high K value dielectric material layer 401, while the select gates such as DSG and SSG have a gate oxide layer 209. The high K dielectric material is similar to cerium oxide, wherein the K system refers to a material having a high dielectric constant K value.

4B is a block diagram 491 showing another aspect of the physical layout of a three-dimensional NVM/DRAM memory device in a vertical direction in accordance with an embodiment of the present invention. The memory device shown in block 491 is similar to the memory device shown in block 390 of FIG. 3A, except that the select gate, cell, and capacitor have the same or substantially the same use as the gate dielectric layer. ONO layer 402. The benefit of using the ONO layer 402 is that it simplifies the overall fabrication process, thereby reducing manufacturing costs and resources.

In operation, the DSG and SSG of the NAND string should control the voltage difference between the gate and the channel to avoid unintended programming of the capacitor or NVM cell. For example, the voltage difference between the gate and the channel should not exceed a predetermined desired voltage, such as 10 volts (V), as it may cause electron tunneling. It should be noted that the operating voltage of the DRAM cell is normally low, so the unintended cell programming between the NVM cell and the capacitor should also be low.

4C is a block diagram 492 showing another aspect of the physical layout of a three-dimensional NVM/DRAM in a vertical direction in accordance with an embodiment of the present invention. 4D is a schematic diagram 493 showing an equivalent circuit of a three-dimensional NVM/DRAM cell structure shown in block 492 of FIG. 4C. The memory device shown in block 492 is similar to the memory device shown in block 390 of FIG. 3A, except that the capacitive portion is divided into a plurality of capacitors 403a through 403d. The gate terminals of capacitors 403a-403d are connected to different control signals CAP1, CAP2 and/or CAPM. In one example, the control signals CAP1, CAP2, and CAPM can be connected to the same signal. Alternatively, the control signals CAP1, CAP2, and CAPM can be connected to different voltages to activate and/or turn off the channels of the capacitors, thereby changing or adjusting the capacitance portion such as the capacitive element 201. The capacity of the capacitor. One advantage of using multiple capacitors 403a-403d is that they can use the same process module to form a plurality of capacitor word lines.

4E is a block diagram 494 showing an alternative example of a physical layout of a three-dimensional NVM/DRAM memory device in a vertical direction in accordance with an embodiment of the present invention. FIG. 4F is a schematic diagram 495 showing an equivalent circuit of the three-dimensional NVM/DRAM cell structure shown in block diagram 494 of FIG. 4E. The memory device shown in block 494 is similar to the memory device shown in block 492 of FIG. 4C, except that the plurality of capacitors are replaced with a plurality of memory cells 404a-404c. In one aspect, the channel 207 associated with the DRAM cell 201 uses an ONO layer 406 or other type of charge trapping layer to store cell data. Memory cells 404a-404c are coupled to control signals or word lines, such as WL0a, WL1a, and WLMa.

In one embodiment, memory units 404a-404c are operable in two modes of operation. In one mode, the memory cells can be used as NAND flash memory cells to store data. In another mode, the cells can be used as MOS capacitors to temporarily store data in a cell channel such as a DRAM cell. In the DRAM mode of operation, data can be programmed to the selected word line of the NAND flash memory cells 405a-405c at the NAND-NVM string or bottom portion 202. Similarly, memory units 405a-405c can also have two modes of operation. In one mode, memory cells 405a-405c can be used as NAND flash memory cells. In another mode, memory cells 405a-405c can also be used as DRAM cells to temporarily hold data and then program it to the upper portions of NAND flash memory cells 404a-404c. In one aspect, the DRAM Selective Transistor (DWL) 203 is configured to have a longer channel length, whereby higher voltages are processed in the programming loop of memory cells 404a-404c.

5A through 5F are block diagrams showing an alternative aspect of the physical layout of a vertical 3D hybrid NVM/DRAM memory device in accordance with an embodiment of the present invention. Figure 5A An embodiment of a three-dimensional NVM/DRAM cell structure 590 is shown that is similar to the three-dimensional NVM/DRAM cell structure shown in FIG. 3A, with the difference that the string is folded between adjacent two vertical strings 550-552. . Each of the vertical strings 550-552 includes one or a half of the NAND cells. In one aspect, the vertical strings 550-552 are connected by a channel 207 or a portion of the channel 501 (duct), wherein the channel 207 is configured as a U-string.

The bottom portion of the U-string is a conduit 501 that is located on the back gate (BG). The BG is deposited on the substrate 208 to initiate the passage of the conduit 501. In one embodiment, the SL (semiconductor layer) is connected to a metal layer. During the manufacturing process, a multi-layer and NAND-type NVM cell for vertical strings 550-552 is deposited over substrate 208. After depositing the select gates (i.e., DSG and SSG) over the strings 550-552, the foregoing plurality of layers are etched to separate the strings. After forming the NVM type string, its process continues to deposit DRAM cells on the BL side. When the deposition of the DRAM cell is completed, the process ends after the BL and SL are applied.

Figure 5B illustrates a three-dimensional NVM/DRAM cell structure 592 that is similar to the cell structure depicted in Figure 5A, except that the two strings have the same structure from the bottom to the DRAM select gate. In one embodiment, the three-dimensional NVM/DRAM memory device includes an additional DRAM cell and a select gate 502. The additional DRAM cell includes a MOS capacitor 503 on the SL side. During operation, data can be stored to two DRAM cells. In another embodiment, the DRAM cell can also be turned off. For example, the source side of the DRAM cell can be turned off via the enable select gate 502 and the MOS capacitor 503, thereby making the DRAM cell a disable device.

Fig. 5C shows a three-dimensional NVM/DRAM cell structure similar to the cell structure shown in Fig. 5A, except that a single capacitor system is divided into a plurality of capacitors 504a-504c. The 5D diagram shows another three-dimensional NVM/DRAM cell structure similar to the cell structure shown in FIG. 5B, except that the capacitors 204 and 503 are respectively divided into a plurality of capacitors 504a-504c and 505a-505c.

Figure 5E shows a three-dimensional NVM/DRAM cell structure similar to the cell structure shown in Figure 5C, with the difference that the plurality of capacitors 504a-504c are replaced by a plurality of NAND flash memory cells 506a-506c. In one embodiment, the ONO layer 507 or any other type of charge trapping layer is used to store or capture cell data. In one example, the units can have two modes of operation, namely NAND flash memory mode and DRAM mode.

Figure 5F shows a three-dimensional NVM/DRAM cell structure similar to the cell structure shown in Figure 5D, with the difference that the plurality of capacitors 504a-504c and 505a-505c are respectively a plurality of NAND flash memory cells 506a-506c And 508a-508c are replaced. In one embodiment, ONO layers 507 and 509 or other types of charge trapping layers can be used to store cell data.

6A to 6F are 3D block diagrams showing an embodiment of a physical layout related to a 3D hybrid NVM/DRAM memory device of one embodiment of the present invention. 6A is an exemplary 3D hybrid NVM/DRAM memory device 690, where the device 690 includes a DRAM cell 601 and a NAND cell string 602. To simplify the description, only the four (4) NAND type NVM cells having the word line WL0-3 are shown. In an actual product, each string can contain more than 32 NVM units. The device 390 shown in Figure 3A is a cross-sectional view of the device 690 along the axis C-C. In one embodiment, like other select gates and NVM cells, MOS capacitor 603 can be formed of the same material, such as polysilicon or metal. It should be noted that the NAND strings have a common drain select gate 604. During operation, when the DSG 604 is enabled, all DRAM cell data can be written to or from the selected word line of the NAND string.

Fig. 6B is a view showing an embodiment of a 3D array structure similar to the structure shown in Fig. 6A, except that the array is formed in an upside down configuration. DRAM cell 601 is located at the bottom of the 3D array structure and NAND string 602 is located at the top of the 3D array structure. Use up and down One advantage of the inverted 3D array structure is that the overall array can be built or deposited on top of the logic portion 610. Logic portion 610 (eg, a microprocessor and a cable) can read data from or write data to the DRAM, and the DRAM can read data from or write data to the NAND-type NVM unit. The upside down 3D array structure is suitable for embedded or SOC (wafer system) applications.

Figure 6C shows an embodiment of a 3D array structure in which the DRAM cell 601 is located on the SL side (or bottom) of the NAND string 602. MOS capacitor 603 is deposited over a second source select gate (SSG2) 612 deposited over SL. The first source select gate (SSG1) can be enabled to write data to the DRAM cell based on the value of BL0-3. SSG1 can also program data from the DRAM cell to the NVM cell based on the selected WL0-3. During a read operation, SSG2 612 is used to turn on or off the connection between the NAND string and the SL. In DRAM mode, capacitor 603 will be separated from SL after SSG2 612 is turned off.

Figure 6D shows an alternative embodiment of a 3D structure similar to that shown in Figure 6A, except that the NAND strings have separate DSGs 605-606. For example, the gate is connected to the signal DSG0-3 of the decoder. The array structure can selectively read and/or write portions of the data from the DRAM cells. Fig. 6E shows another embodiment of a 3D array structure similar to the structure shown in Fig. 6D, except that it has separate MOS capacitors 607-608. The physical structure including separate MOS capacitors 607-608 allows the patterns of DRAM select gate 609, MOS capacitor 607, and NAND drain select gate 605 to be etched together in a single process step. The separate capacitors can be connected to the same capacitor voltage CAP.

7A through 7B are 3D block diagrams showing the physical layout of 3D hybrid NVM/DRAM using different serial forms in accordance with an embodiment of the present invention. Fig. 7A shows a 3D array structure similar to that shown in Fig. 6B, except that the NAND serial form is a physical separator as shown by the numerals 605 and 701-705. It should be noted that this hybrid NVM/DRAM The device can be fabricated in certain semiconductor process recipes. Various etching processes can be used to form a layered form from top to bottom with the substrate being at the bottom. The separate word lines and source select gates located at the same horizontal plane may be connected to each other outside the array. In the manufacturing process, depending on the actual application, the select gate 609 of the DRAM cell and the capacitor 607 may have a different physical form than the NAND string. Depending on the application, the NAND strings and DRAM cells can have similar or substantially identical physical forms. To create an NVM/DRAM device having a similar physical form, the top-to-bottom layering other than the BL layer can be etched together in a process step.

Figure 7B shows an embodiment of a 3D array structure similar to that shown in Figure 7A, except that source lines 706-707 are formed in substrate 708 rather than a SL layer. The source lines located within or within the substrate 708 can be produced by a particular process. In an example, the source lines can be decoded or connected to each other.

8A through 8C are 3D block diagrams showing the physical layout of a three dimensional NVM/DRAM memory device using different configurations of DRAM word lines in accordance with an embodiment of the present invention. Figure 8A shows an embodiment of a 3D hybrid NVM/DRAM array using an interconnect (INT) layer. INT layers 801-802 are added between the DRAM cells and the NAND strings. The interconnect layer can be made of a conductive material, such as a DRAM cell that can be connected to a plurality of NAND strings, such as poly germanium or metal. One advantage of using the INT layers 801-802 is that the number of DRAM cells can be reduced. After the interconnect layer connects a DRAM cell to two NAND strings, data stored in the DRAM cell can be written to the two NAND strings or written from the NAND string by selecting one of the NAND DSGs 605-606. Into the DRAM unit.

Fig. 8B shows another exemplary aspect of a 3D hybrid type NVM/DRAM device using the interconnect layer 803. After a DRAM is connected to the four NAND strings, data stored in the DRAM can be written to or taken from the four NAND strings. It should be noted that the application of the interconnect layer enables The 3D hybrid NVM/DRAM is flexible in use, whereby the ratio of the number of DRAMs and NAND cells can be optimized. The interconnect layer can reduce the number of DRAM cells, whereby the pitch between the DRAM cells can be relaxed as shown in Figs. 8A to 8B. Figure 8C shows another aspect of a 3D hybrid NVM/DRAM array in which the number of DRAM select gates DWL0-1 and bit lines BL0-1d can be reduced by half. An advantage of the layout shown in Figure 8C is that the pitch of the physical layout of the hybrid NVM/DRAM array can be relaxed.

9A through 9B are 3D block diagrams showing different aspects of the physical layout of a three dimensional NVM/DRAM using different configurations of DRAM pass gates (DPGs) in accordance with an embodiment of the present invention. FIG. 9A illustrates a hybrid three-dimensional NVM/DRAM array structure including a NAND NVM string 903, a first DRAM unit 901, and a second DRAM unit 902. Although the hybrid array structure shown in FIG. 9A includes two DRAM cells 901-902, each string in the hybrid array structure may contain more than two DRAM cells. It should be noted that even if one or more blocks (or layers) are added or removed from Figures 9A through 9B, the basic concepts of the exemplary embodiments of the present invention are not changed.

In one aspect, the hybrid NVM/DRAM array includes DRAM cells 901-902 and NAND strings 903, wherein DRAM cells 901-902 are stacked on top of NAND string 903. The first DRAM cell 901 can be accessed by BL0-3 via DWL0-3 selection. In one embodiment, the second DRAM cell 902 is configured to pass through the DRAM pass gate (DPG) as an accessor. In operation, the hybrid NVM/DRAM structure enables a system to write data to or from one or more NVM cells in NAND string 903 while the second DRAM cell 902 is being read. Unit 901 performs the access.

In the application of MLC (Multi-Level Storage Cell), the two-bit metadata can be simultaneously stored in two DRAM cells, such as DRAM cells 901-902. After storage, the binary data can be written The NVM unit in the NAND string 903 is entered. When an MLC read operation is performed, the binary data of the NAND cell can be read and stored in the aforementioned two DRAM cells.

Figure 9B is a diagram showing another embodiment of a hybrid three-dimensional NVM/DRAM array structure similar to that shown in Figure 9A, in that a plurality of independent DPGs 904-905 are used to facilitate inter-cell DRAM units. Communication. DPG 904-905 or the transfer gate can be selected and/or controlled by DPG0-3. One advantage of using a stand-alone DPG 904-905 is that it enables a memory system to carry data to a portion of the second DRAM cell and NVM cells written in the NAND string.

10A through 10B are 3D block diagrams showing alternative physical states of a 3D hybrid NVM/DRAM array structure using different configurations of DRAM transfer gates (DPGs) in accordance with an embodiment of the present invention. kind. FIG. 10A illustrates an exemplary embodiment of a hybrid NVM/DRAM array structure including a NAND string 1001 and DRAM cells 1002-1003. The hybrid NVM/DRAM array structure shown in Fig. 10A is similar to the array structure shown in Fig. 9A, except that the DRAM cells 1002-1003 are located at the bottom of the structure adjacent to the substrate. A NAND cell or NAND string 1001 is deposited on top of the DRAM cells 1002-1003. In one aspect, multiple DPSs are used to facilitate communication between DRAM cells 1002-1003 and NAND string 1001. Fig. 10B is another embodiment showing a three-D hybrid NVM/DRAM array structure similar to the structure shown in Fig. 10A, except that the DPG system located between the DRAM cells 1001-1002 is reconfigured into a plurality of Transfer gates DPG0-3 that are independent or separate from each other.

11A through 11B are block diagrams showing the physical layout of a 3D hybrid NVM/DRAM array structure having a multi-layered capacitive layer in accordance with an embodiment of the present invention. FIG. 11A is a diagram showing a structure having four DRAM cells 1101-1104 disposed above the NAND string 1105. The additional DRAM cells enable a system to perform a pipelining operation in which, for example, four pages of data can be loaded into the four levels of DRAM cells 110-1104. Number loaded The NVM cells of the NAND string 1105 can be written in sequence. Figure 11B shows another embodiment of a 3D hybrid NVM/DRAM array structure similar to that shown in Figure 11A, except that DRAM cells 1101-1104 are located at the bottom of the structure. In one example, a NAND cell or NAND string 1105 is located or deposited on top of a DRAM cell.

It should be noted that one of the four DRAM cell structures illustrated in FIGS. 11A-11B is for illustrative purposes only, and additional DRAM cells may be added to or removed from the 3D hybrid NVM/DRAM array structure.

12A through 12B are 3D block diagrams showing an alternative physical layout of a 3D hybrid NVM/DRAM array structure having multiple layers of capacitive layers in accordance with an embodiment of the present invention. Figure 12A shows a hybrid NVM/DRAM array structure comprising a plurality of DRAM cells 1201-1204 stacked on top of NAND string 1205. In one embodiment, the DRAM cells (eg, DRAM cells 1202, 1203) are in series with each other. In one aspect, the DRAM cells are arranged or fabricated to be connectable to the BL in parallel, which is a known NOR array structure. In one example, the NOR array structure allows a system to access the DRAM cells in a completely random manner. Fig. 12B shows another embodiment of a hybrid NVM/DRAM array structure similar to that shown in Fig. 12A, except that DRAM cells 1201-1204 are located or disposed at the bottom portion of the structure. In one aspect, NAND cells or NAND strings 1205 are located or disposed on top of DRAM cells 1201-1204. It should be noted that the features of the embodiments illustrated in Figures 11A and 12A can be combined with one another such that the DRAM cell has a plurality of levels in series with each other and a plurality of levels in parallel with each other.

13A through 13B are 3D block diagrams showing the physical layout of a three-dimensional NVM/DRAM using an alternative vertical structure in accordance with an embodiment of the present invention. Figure 13A illustrates an embodiment of a hybrid NVM/DRAM array structure 1390 associated with structure 590 of Figure 5A, wherein Structure 590 is a schematic cross-sectional view of structure 1390 taken along the A-A axis. The NAND strings are of a folded structure. The two folding strings are connected via a pipe portion 1301. The BG (back gate) is routed into the conduit 1301. Figure 13B shows another embodiment of a 3D hybrid NVM/DRAM array structure 1392 associated with structure 592 shown in Figure 5B. The structure 592 shown in Fig. 5B is a schematic cross-sectional view of the structure 1392 taken along the B-B axis. The hybrid array structure 1392 further includes a DRAM cell 1303 on the SL side and is coupled to the SL via a select gate 1302.

Figure 14 is a 3D block diagram showing the physical layout of a hybrid NVM/DRAM array structure in accordance with an embodiment of the present invention. Figure 14 shows a hybrid structure having a DRAM cell 1401 and a plurality of NAND cells or strings 1402, wherein the structures are seated or disposed in a horizontal manner, rather than in a vertical manner. In one embodiment, DRAM cell select gate 1403 and MOS capacitor 1404 are either seated or fabricated in a horizontal manner.

15 through 17 are 3D block diagrams showing the physical layout of a hybrid NVM/DRAM array structure using different capacitive layers in accordance with an embodiment of the present invention. Figure 15A shows an embodiment of a hybrid NVM/DRAM array structure including a plurality of cylindrical capacitors 1503. It should be noted that other kinds of semiconductor capacitors, such as MOS capacitors, PIP (polysilicon-insulated-poly) capacitors, stacked capacitors or the like, may be used instead of the cylindrical capacitor 1503. Due to the large size of the DRAM cells, DRAM cells 1501 can be located on top of NAND string 1502, while interconnect layer 1504 can be used to increase the spacing between DRAM cells. The hybrid NVM/DRAM array structure shows that each DRAM cell is connected to four NAND cells. Figure 15B shows a top view of four DRAM cells coupled to vertical select gate DWL0-1.

Figure 16A shows another configuration of a 3D hybrid NVM/DRAM array structure similar to that shown in Figure 15A, except that DRAM cell 1602 is located below the structure (below NAND string 1601). To connect DRAM cell 1602 to NAND string 1601, use more The channels and/or paths 1603 connect the lower interconnect 1604 to the upper interconnect 1605. One advantage of placing the DRAM cells close to the lower portion of the structure of the substrate is that it allows the onboard logic or CPU to more easily access the DRAM cells. In one aspect, each DRAM cell is connected to four NAND cells to increase the spacing between DRAM cells. Figure 16B shows a top view of a DRAM cell CAP using a 3D vertical select gate DWL0-1.

Figure 17A illustrates a 3D physical layout of a hybrid NVM/DRAM array structure that can be fabricated via a 2D process of a DRAM cell. In one embodiment, DRAM cell 1702 is located below NAND string 1701 and above substrate 1708 or well. DRAM cell 1702 includes a PIP capacitor 1704 and a MOS select gate 1707. Source and drain diffusion layers 1706 are deposited on substrate 1708. A separate gate (ISO) 1709 is used to separate or separate one of the active regions of the unit from adjacent cells. Since DRAM cell 1702 is located on substrate 1708, DRAM cell 1702 is coupled to NAND string 1701 using VIA 1705. In one aspect, a plurality of interconnecting bars 1703 are used to facilitate communication between each DRAM cell and the four NAND cells of string 1701. Figure 17B shows a top view of four DRAM cells Cap connected to the NVM cell via vertical select gates.

Examples of the invention include various processing steps, which are described below. The example steps can be performed via machine or computer executable instructions. The instructions can be used to execute a general purpose or special purpose system that is programmed with instructions to perform the example steps of the present invention. Alternatively, the example steps of the present invention may be performed by a particular hardware component that includes the routing logic that can perform the steps, or by a programmed computer component or a customized hardware component.

Figure 18 is a flow chart 1800 showing the operation of a hybrid NVM/DRAM storage device in accordance with an embodiment of the present invention. At block 1802, when a first DSG is enabled within the first time frame, the program for programming the multi-page synchronization in a hybrid NVM/DRAM storage device latches the first data from a BL to A first DRAM cell. The first DRAM unit The first NVM string is coupled via a first channel.

At block 1804, when a second DSG is initiated in the first time frame, the second data is latched from the BL to a second DRAM unit. It is to be noted that the second DRAM cell is coupled to a second NVM string via a second channel.

At block 1806, when a write DSG signal is enabled, a first data frame from the first DRAM cell is stored in the first NVM string in a second time frame responsive to one of the voltage values of the plurality of WLs. And the second data from the second DRAM is stored in the second NVM string. The program can also stop the SSG signal and initiate a source line signal before starting the WL. The program further causes the first data to pass from the first DRAM cell to the first NVM string via a first pass channel in a direction toward the substrate.

Figure 19 is a flow chart 1900 showing a manufacturing process for a three-dimensional NVM/DRAM storage device in accordance with an embodiment of the present invention. At block 1902, a program for generating a 3D hybrid NVM/DRAM memory device deposits a first plurality of semiconductor layers (MSL) on a substrate to construct a plurality of sources including a source select gate. Floor.

At block 1904, a second set of MSLs are deposited on the first set of MSLs to form a string of NVM cells in a vertical configuration for permanent data storage. In one embodiment, 32 NVM units are stacked one on another in a direction perpendicular and away from the substrate for long-term data storage.

At block 1906, the program deposits a third set of MSLs on the second set of MSLs to form a plurality of drain layers including at least one drain select gate layer.

At block 1908, a fourth set of MSLs are deposited on the third set of MSLs to form a DRAM layer that can temporarily store data. A fifth set of MSLs is deposited on the fourth set of MSLs to form a DRAM word line (DWL) layer to provide capacitance management. In an embodiment, the program may also set at least one capacitor layer in the fourth group of MSLs so that the charge can be captured and counted. According to the storage.

The present invention has been shown and described with respect to the specific embodiments of the present invention, and it should be understood by those of ordinary skill in the art that Change and modification. Therefore, the scope of the appended claims is intended to cover any modifications and

100‧‧‧block diagram

102‧‧‧Storage

106‧‧‧DRAM

108‧‧‧NVM

150‧‧‧ processor

152‧‧‧NVM storage

156‧‧‧Line Manager

158‧‧‧ cable

160‧‧‧ memory

Claims (24)

A memory device capable of storing information, comprising: a plurality of memory elements capable of storing information, each of the plurality of memory elements having a source terminal, a gate terminal, a terminal extreme, and a non-volatile unit, wherein the plurality of memory elements The memory elements are arranged in a string, and the memory elements are connected between the source terminal and the drain terminal; a first drain select gate (DSG) transistor having a source terminal, a terminal and a gate terminal, The first extreme of the first DSG transistor is coupled to the source terminal of the plurality of memory elements, the gate terminal of the first DSG transistor is coupled to a first DSG signal; and a capacitive element having a source terminal, At one extreme and one gate extreme, the capacitive element is coupled to the source terminal of the first DSG transistor, wherein the capacitive element is configured to perform a dynamic random access memory (DRAM) function. The device of claim 1, further comprising a second DSG transistor having a source terminal, a terminal, and a gate terminal, wherein the second DSG transistor is coupled to the capacitor The source of the component is extreme. The device of claim 2, further comprising a source select gate (SSG) element having a source terminal, a terminal extreme and a gate terminal, the source terminals of the SSG being coupled to each other An extreme of one of a plurality of memory elements of a string. The device of claim 3, wherein the gate terminal of the SSG component is coupled to an SSG signal, and the drain terminal of the SSG component is coupled to a source line. The device of claim 3, wherein the gate terminal of the second DSG transistor is coupled to a DSG signal, and the source terminal of the second DSG transistor is coupled to a bit line. The device of claim 3, wherein the plurality of memory elements are NAND type flash memories. The device of claim 3, wherein each gate of the plurality of memory elements The end system is coupled to a unique word line. The device of claim 1, wherein the plurality of memory elements are non-volatile memory storage devices of a neodymium-oxygen-niobium-oxygen-strontium (SONOS) type. The device of claim 3, wherein the plurality of memory elements, the first DSG transistor, the second DSG transistor, and the capacitive element structure are in a three-dimensional (3D) layout stack structure. The device of claim 9, wherein the capacitive element is physically located above the plurality of memory elements in the 3D layout. A non-volatile memory system capable of storing data, comprising a plurality of sets of memory elements in a 3D layout as described in claim 10 of the patent application. A non-volatile semiconductor memory device comprising: a substrate layer; a diffusion layer layer deposited on the substrate layer and operatively coupled to a source line; a plurality of memory layers deposited on the diffusion layer a layer, and configured to store information in a non-volatile memory unit corresponding to the word line; a capacitor layer deposited on the plurality of memory layers and configured to dynamically store information A random access memory (DRAM); and a DRAM word line (DWL) layer deposited on the capacitor layer and configured to initiate DRAM functionality. The device of claim 12, further comprising a metal layer deposited on the DWL layer, which is a one-dimensional line. The device of claim 12, wherein the plurality of memory layers comprise a source select gate (SSG) layer deposited on the diffusion layer and operable to provide a source Select a function. The device of claim 12, wherein the plurality of memory layers comprise a drain select gate (DSG) layer deposited on the diffusion layer and operable to provide a drain selection function . The device of claim 12, further comprising a polysilicon channel extending from the plurality of memory layers to the capacitor layer along a direction perpendicular to the substrate layer. The device of claim 12, wherein the capacitor layer comprises a first capacitor layer configured to store information and a second capacitor layer configured to store information. A method for simultaneously writing multiple pages in a non-volatile memory, comprising the steps of: when a first drain select gate (DSG) is activated in a first time frame, via a first channel, The first data is latched from a bit line (BL) to a first dynamic random access memory (DRAM) unit coupled to a first non-volatile memory (NVM) string; when a second DSG is in the When a time frame is activated, the second data is latched from the bit line (BL) to the first DRAM unit coupled to a second NVM string via a second channel; when a DSG signal is written When activated, in response to the voltage values of the plurality of word lines (WL) in a second time frame, substantially simultaneously the first data and the second data from the first DRAM unit and the second DRAM unit Data is stored in the first NVM string and the second NVM string. The method of claim 18, further comprising the steps of: stopping a plurality of source select gate (SSG) signals, and starting a source line before starting the WL. The method of claim 18, wherein the first data is allowed to move from the first DRAM to the first NVM string via a first channel along a direction toward a substrate. A method of producing a three-dimensional (3D) memory device, comprising the steps of: depositing a first plurality of layers of semiconductor (MSL) on a substrate to construct a source comprising Selecting a plurality of source layers of the gate layer; depositing a second set of MSLs on the first set of MSLs to form a string of non-volatile memory (NVM) in a vertical configuration for long-term storage of data; A third set of MSL is deposited on the second set of MSLs to form a multi-layered drain layer comprising a drain select gate layer; and a fourth set of MSLs are deposited on the third set of MSLs to form a temporary storage A multi-layer dynamic random access memory (DRAM) layer of data. The method of claim 21, further comprising the step of depositing a fifth set of MSLs on the fourth set of MSLs to form a multi-layer DRAM word line (DWL) layer for providing capacitance management. . The method of claim 21, wherein the step of depositing a fourth set of MSLs on the third set of MSLs to form a multilayer dynamic random access memory (DRAM) layer further comprises: depositing at least one captureable A capacitive layer of charge to store data. The method of claim 21, wherein depositing a second set of MSLs on the first set of MSLs to form a string of NVMs further comprises: stacking 32 NVM units along a vertical direction away from the substrate For long-term storage of data.