TW201629760A - System on chips for controlling power using workloads, methods of operating the same, and computing devices including the same - Google Patents

Abstract

A system on chip may include: a master device configured to execute a dynamic voltage and frequency scaling (DVFS) program; a slave device configured to communicate with the master device; and/or a performance monitoring unit configured to receive first events generated while instructions are being processed by the master device, configured to generate a first count value by counting a number of second events corresponding to a total number of the instructions related with the first events and configured to generated a second count value counting a number of third events related with first instructions that can be processed by interaction between the master device and the slave device among the first events. The DVFS program may be configured to generate a control signal for controlling DVFS of at least one of the master device and the slave device based on the first count value and the second count value.

Description

System wafer for controlling power using a workload, method of operating the same, and computing device comprising the same

Certain exemplary embodiments of the inventive concept may be generally related to a system on chip (SoC). Certain exemplary embodiments of the inventive concept may be generally related to a slave device for controlling dynamic voltage and frequency scaling (DVFS) and controlling communication with a master device according to a workload type of the master device. System chip for dynamic voltage and frequency scaling. Certain exemplary embodiments of the inventive concept may be generally related to methods of operation of the system wafer. Certain exemplary embodiments of the inventive concept may be generally related to computing devices including the system wafers.

Traditionally, dynamic voltage and frequency scaling can be performed in a computing system using information only about dynamic voltage and frequency scaling of the target device. In the dynamic voltage and frequency scaling of a central processing unit (CPU), the frequency of the clock signal applied to the central processing unit when the current load measured in the central processing unit is above the upper threshold And the level of the operating voltage can be increased and can be reduced when the current load is below the lower threshold.

If the operating frequency of the central processing unit communicating with the memory system is low while the operating frequency of the memory system is low, the conventional dynamic voltage and frequency scaling method can increase the central processing unit when the workload of the central processing unit increases. Operating frequency and operating voltage. However, when the workload of the central processing unit is a memory-oriented workload, even if the operating frequency and operating voltage of the central processing unit increase, the performance of the central processing unit may not increase, but Only the power consumption of the central processing unit may increase.

Certain exemplary embodiments of the inventive concept may provide a system wafer for controlling dynamic voltage and frequency scaling based on the type of workload of the primary device.

Certain exemplary embodiments of the inventive concept may provide a system wafer for controlling dynamic voltage and frequency scaling of a slave device in communication with the master device.

Certain exemplary embodiments of the inventive concept may provide a method of operation of the system wafer.

Certain exemplary embodiments of the inventive concept may provide a computing device including the system wafer.

In some exemplary embodiments, a system die may include: a master device for performing a dynamic voltage and frequency scaling (DVFS) program; a slave device for communicating with the master device; and/or a performance monitoring unit, And a first event generated by the processing of the instruction by the primary device to generate a first count value by counting the number of the second event, and used to Counting the number of third events to generate a second count value, the number of second events corresponding to a total number of the instructions associated with the first event, the third event being capable of being A first instruction that is processed by the interaction between the device and the slave device is associated. The dynamic voltage and frequency scaling program can be configured to generate dynamic voltage and frequency scaling for controlling at least one of the primary device and the secondary device based on the first count value and the second count value Control signal.

In some exemplary embodiments, the main device may be a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), and a digital device. One of a digital signal processor (DSP) and a multimedia processor. The slave device can be one of a memory interface and an input/output interface.

In some exemplary embodiments, the system chip may further include: a clock management unit configured to control the first clock signal applied to the host device according to the control signal At least one of a first frequency and a second frequency applied to the second clock signal of the slave device.

In some exemplary embodiments, the system chip may further include: a power management unit configured to control the power management integrated circuit to control the applied to the host device according to the control signal At least one of a level of the first voltage and a level of a second voltage applied to the slave device.

In some exemplary embodiments, the second event is associated with an instruction executed by the primary device, and the third event is associated with an L2 cache miss.

In some exemplary embodiments, the dynamic voltage and frequency scaling program may be used to calculate misses-per-kilo-instructions based on the first count value and the second count value. The MPKI) value, and/or can be used to generate the control signal based on the value per thousand instructions. The second count value may be an L2 cache miss count.

In some exemplary embodiments, a computing device may include: a master device to perform a dynamic voltage and frequency scaling (DVFS) program; a slave device to communicate with the master device; and a performance monitoring unit to receive a first event generated while the master device processes the instruction to generate a first count value by counting the number of second events, and for using the third event in the first event Counting the number to generate a second count value, the number of second events corresponding to a total number of the instructions associated with the first event, the third event being capable of being a first instruction related to the interaction between the devices; and/or a power management integrated circuit (PMIC) for providing a corresponding operating voltage to the master device, the slave device And the performance monitoring unit. The dynamic voltage and frequency scaling program can be configured to generate dynamic voltage and frequency scaling for controlling at least one of the primary device and the secondary device based on the first count value and the second count value Control signal.

In some exemplary embodiments, the main device may be a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), and a multimedia processor. One of them. The slave device can be one of a memory interface and an input/output interface.

In some exemplary embodiments, the computing device may further include: a clock management unit configured to control a first frequency of the first clock signal applied to the host device according to the control signal and At least one of a second frequency applied to the second clock signal of the slave device.

In some exemplary embodiments, the computing device may further include: a power management unit configured to control the power management integrated circuit to control the first applied to the primary device in response to the control signal A level of voltage and at least one of a level of a second voltage applied to the slave device.

In some exemplary embodiments, the second event is related to an instruction executed by the primary device, and the third event is associated with an L2 cache miss.

In some exemplary embodiments, the dynamic voltage and frequency scaling program may be used to calculate a value per thousand instructions (MPKI) based on the first count value and the second count value, and/or available The control signal is generated based on the value per thousand instructions. The second count value can be obtained by counting the L2 cache miss.

In some exemplary embodiments, the computing device may further include: a memory. The main device may be one of a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), and a multimedia processor. The slave device can be a memory interface for controlling the operation of the memory according to the control of the master device.

In certain exemplary embodiments, a method of operating a system wafer including a master device for performing a dynamic voltage and frequency scaling (DVFS) program and a slave device in communication with the master device is provided, The method can include receiving a first event generated while the master device processes the instruction, and generating a first count value corresponding to the number of the instructions in the first event; and/or the dynamic voltage and A frequency scaling program controls dynamic voltage and frequency scaling of the master device and dynamic voltage and frequency scaling of the slave device based on the first count value.

In some exemplary embodiments, the main device may be a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), and a multimedia processor. One of them. The slave device can be one of a memory interface and an input/output interface.

In some exemplary embodiments, the method may further include: generating a second count value by counting a number of the second events in the first event, the second event being capable of A first instruction that is processed by the interaction between the master device and the slave device is associated. The dynamic voltage and frequency scaling program can be used to control the dynamic voltage and frequency scaling of the primary device and the dynamic voltage and frequency scaling of the slave device based on the first count value and the second count value.

In some exemplary embodiments, the first count value may be a cycles per instruction (CPI) value and the second count value is an L2 cache miss count.

In some exemplary embodiments, the dynamic voltage and frequency scaling program can be used to control the dynamic voltage and frequency scaling of the primary device when the each command cycle value is less than the first reference value. The dynamic voltage and frequency scaling program may be configured to control the dynamic voltage of the master device when each command cycle value is greater than the first reference value and the L2 cache miss count is less than a second reference value And frequency scaling.

In some exemplary embodiments, the dynamic voltage and frequency scaling program may be used to calculate a value per thousand instructions (MPKI) based on the first count value and the second count value, and/or available Controlling the dynamic voltage and frequency scaling of the master device and the dynamic voltage and frequency scaling of the slave device based on the value per thousand instructions, wherein the first count value is The total number, wherein the second count value is an L2 cache miss count.

In some exemplary embodiments, the dynamic voltage and frequency scaling program may be used to control the dynamic voltage and frequency scaling of the primary device when the value per thousand instructions is less than the first reference value, and may be used to Controlling the dynamic voltage and frequency scaling of the slave device when the number of misses per thousand instructions is greater than or equal to a second reference value, and/or may be used to have a value greater than or equal to the value in the thousand instructions per thousand instructions The dynamic voltage and frequency scaling of the primary device and the dynamic voltage and frequency scaling of the slave device are controlled when the first reference value is less than the second reference value.

In some exemplary embodiments, a computing device may include: a first device to execute a program; a second device to communicate with the first device; and a third device to receive the first device And generating, by the device, the first event generated by the instruction, by using the number of the second event to generate a first count value, and for counting the number of the third event in the first event Generating a second count value, the number of the second events corresponding to a total number of the instructions associated with the first event, the third event being capable of being by the first device and the second The first instruction associated with the interaction between the devices is associated; and/or the fourth device is configured to provide an operating voltage to the first device or the second device. The program may be configured to generate a control signal for controlling the first device, the slave device, or the first device and the second device based on the first count value and the second count value .

In some exemplary embodiments, the program may include a dynamic voltage and frequency scaling (DVFS) program.

In certain exemplary embodiments, the program can be used to control the supply of operating voltages to the first device and the second device.

In some exemplary embodiments, the first device may include a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), or a multimedia processor. .

In some exemplary embodiments, the second device may include a memory interface or an input/output interface.

In some exemplary embodiments, the computing device may further include: a fifth device to control a frequency provided to the first device or the second device.

In certain exemplary embodiments, the computing device may further include: a fifth device to control a level of an operating voltage provided to the first device or the second device.

Exemplary embodiments will now be more fully explained with reference to the following drawings. However, the embodiments may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, the exemplary embodiments are provided so that this disclosure will be thorough and complete, and the scope of the disclosure will be fully conveyed by those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

It should be understood that when a component is referred to as being "on" or "connected to", "electrically connected to", or "coupled to" In another component, the component can be directly located on the other component, or connected to, electrically connected to, or coupled to the other component, or an intermediate component can be present. Conversely, when a component is referred to as being "directly", or "directly connected to" or "directly electrically connected to", or When "directly coupled to" another component, there is no intermediate component. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers, and/or sections, the elements, components , zones, layers, and/or sections should not be limited by these terms. The terms are only used to distinguish between various elements, components, regions, layers, and/or sections. The elements, components, regions, layers, and/or sections may be referred to as the second elements, components, regions, layers, and/or sections, without departing from the teachings of the exemplary embodiments. content.

As shown in the figure, for convenience of explanation, for example, "beeath", "below", "lower", "above", Spatially relative terms such as "upper" are used to describe a component and/or feature in relation to another component and/or feature, or other component and/or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation illustrated.

The terminology used herein is for the purpose of the description of the exemplary embodiments embodiments The singular forms "a", "an" and "the" It is to be understood that the terms "comprises and/or "comprising" or "includes" and "includes" when used in this specification mean the stated features, integers, steps, operations, components, and / The existence of components or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, components, and/or groups thereof.

Exemplary embodiments may be described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized exemplary embodiments (and intermediate structures). Thus, deviations from the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances are contemplated. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the regions illustrated herein. For example, an implanted region shown as a rectangle will typically have a circular or curved feature and/or a gradient of implant concentration at its edges, rather than a binary from the implanted region to the non-implanted region. Variety. Similarly, a buried region formed by implantation can cause some implantation in the region between the buried region and the surface through which the implantation takes place. The area illustrated in the figures is therefore intended to be illustrative, and is not intended to limit the scope of the exemplary embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the related art, and should not be construed as being Ideal or too formal.

Reference will now be made to the exemplary embodiments illustrated in the drawings in which the same reference

FIG. 1 is a schematic block diagram of a computing device 100 in accordance with some exemplary embodiments of the inventive concept. The computing device 100 can include a controller 200, a power management integrated circuit (PMIC) 300, and a memory 400. Computing device 100 can be a personal computer (PC) or a mobile computing device. The mobile computing device can be a laptop computer, a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), Enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device Or portable navigation device (PND), handheld game console, mobile internet device (MID), wearable computer, internet of things (internet of Things, IoT) devices, internet of everything (IoE) devices, or e-books, but the inventive concept is not limited to the exemplary embodiments.

The controller 200 can control the operation of the power management integrated circuit 300 and the operation of the memory 400. The controller 200 can be implemented as a host, an integrated circuit (IC), a mother board, a system chip (SoC), an application processor (AP), and a mobile application processor ( Mobile AP), or chipset. When the controller 200 is formed as a first package including a system wafer, an application processor, or a mobile application processor and the memory 400 is formed as a second package, the second package may be stacked on the first package On a package. The controller 200 may include a bus architecture 201, a central processing unit (CPU) 210, a memory interface 220, a clock management unit (CMU) 230, a power management unit (PMU) 240, and an input/output (I/). O) interface 250 and internal memory 260.

In some exemplary embodiments of the inventive concept, the master device or the master device may be a central processing unit 210, a graphics processing unit (CPU), an image signal processor (ISP), a digital signal processor (DSP), and a communication process. (communication processor, CP), or multimedia processor, but the inventive concept is not limited to the exemplary embodiments. The communication processor can be a data processor chip. In some exemplary embodiments of the inventive concept, the slave device or the slave device may be the memory interface 220 or the input/output interface 250, but the inventive concept is not limited to the exemplary embodiments.

The master device can independently process at least some of the instructions to be processed by itself during a given time period and can process the remaining instructions together with the slave device. The instructions may represent a workload. The at least one master device and the at least one slave device transmit signals and/or data to each other via the bus bar architecture 201.

In some exemplary embodiments of the inventive concept, it is assumed that the central processing unit 210 is a master device and the memory interface 220 or the input/output interface 250 is a slave device, but the inventive concept is not limited to the exemplary embodiments. In some exemplary embodiments, a component that operates as a master device can operate as a slave device, and vice versa.

The busbar architecture 201 can be implemented as an advanced microcontroller bus architecture (AMBAÒ), an advanced high-performance bus (AHB), and an advanced peripheral bus (APB). , advanced extensible interface (AXI), advanced system bus (ASB), AXI Coherency Extensions (ACE), or a combination of the above, but the inventive concept It is not limited to the exemplary embodiments.

According to certain exemplary embodiments of the inventive concept, central processing unit 210 may execute a dynamic voltage and frequency scaling (DVFS) program. A dynamic voltage and frequency scaling method that is controlled according to a dynamic voltage and frequency scaling program is performed by the master device (e.g., the central processing unit 210 can be applied to the master device and/or slave device as set forth above).

The performance monitoring unit 211 can be implemented in a hardware (eg, a performance monitoring circuit) within the central processing unit 210. The performance monitoring unit 211 can measure or count the performance parameters of the central processing unit 210. For example, the performance monitoring unit 211 can measure or count parameters such as an instruction cycle, a cache hit, a cache miss, and a branch miss. For example, performance monitoring unit 211 can measure or count the number of events associated with corresponding performance parameters among the total number of events that occurred during a given duration.

The performance monitoring unit 211 can receive all events (eg, first events) generated while the instructions (eg, workloads) are processed by the central processing unit 210 for a given duration, by all events (eg, the first event) The number of events (eg, the second event) corresponding to the total number of the (executed) instructions is counted to generate a first count value, which can be obtained by the central processing unit 210 and the memory interface 220 The number of events (eg, third events) associated with the processed instruction is counted to generate a second count value, and the first count value and the second count value may be output. For example, the performance monitoring unit 211 can include a first counter 211-1 for generating a first count value and a second counter 211-2 for generating a second count value.

The dynamic voltage and frequency scaling program executed by the central processing unit 210 can calculate the number of misses per thousand instructions (MPKI) using the first count value and the second count value, and can be generated for control according to the number of misses per thousand instructions. The dynamic voltage and frequency scaling of the central processing unit 210, the dynamic voltage and frequency scaling of the memory interface 220, and the dynamic voltage and frequency scaling control signals of the input/output interface 250. At this time, the second count value may be an L2 cache miss count that may indicate the number of L2 cache misses.

Alternatively, the performance monitoring unit 211 can generate and CPI (cycles per instruction, clock cycles per instruction, or number of clocks per instruction). )) the associated first count value, and/or the second count value corresponding to the L2 cache miss count. At this time, the dynamic voltage and frequency scaling program executed by the central processing unit 210 can generate the dynamic voltage and frequency scaling for controlling the central processing unit 210 and the memory interface 220 by using the first count value and/or the second count value. Dynamic voltage and frequency scaling, and control signals for dynamic voltage and frequency scaling of the input/output interface 250.

As is well known, the CPI can be defined by the following equation: Where CCI is the number of clock cycles of a given instruction type or the number of instructions of a given type, and IC is the total instruction count.

As an example of the slave device, the memory interface 220 can control a write operation or a read operation to the memory 400 according to the control of the central processing unit 210. The memory interface 220 can control the writing to the memory 400 based on the second frequency of the second clock signal CLK2 output from the clock management unit 230 and the level of the fourth operating voltage PW4 output from the power management integrated circuit 300. Enter an operation or a read operation. Each of the second frequency of the second clock signal CLK2 and the level of the fourth operating voltage PW4 can be adjusted according to the dynamic voltage and the frequency scaling.

Although a memory interface 220 and a memory 400 are shown in FIG. 1 for convenience of explanation, the memory interface 220 may be a memory interface group including a plurality of different memory interfaces, and the memory 400 may be included. Memory groups of different memories. For example, when the memory 400 is a dynamic random access memory (DRAM) and a flash memory (for example, a reverse flash memory (logical inverse) or a reverse Or a type of memory of a flash memory (logical inverse), the memory interface 220 may be a memory interface group including a dynamic random access memory controller and a flash memory controller, but the inventive concept It is not limited to the exemplary embodiments.

The memory 400 can be formed from volatile memory and/or non-volatile memory. Volatile memory can be random access memory (RAM), dynamic random access memory, static random access memory (SRAM), thyristor RAM (thyristor RAM, T-RAM), zero-capacitor random access memory (Z-RAM), or twin transistor RAM (TTRAM), but the inventive concept is not limited to the exemplary Example. Non-volatile memory can be electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic random access memory (MRAM), spin Spin-transfer torque magnetic random access memory, ferroelectric random access memory (FRAM), phase-change RAM (PRAM), resistive random access Resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate memory (nano floating gate memory, NFGM), holographic memory, molecular electronic memory device, or insulator resistance change memory, but the inventive concept is not limited to the exemplary embodiments. .

The memory 400 can be implemented as a solid state drive or a solid state disk (SSD), an embedded solid state disk (eSSD), a multimedia card (MMC), and a built-in type. An embedded card (embedded MMC, eMMC), or a universal flash storage (UFS), but the inventive concept is not limited to the exemplary embodiments.

The clock management unit 230 can adjust the first clock signal applied to the central processing unit 210 according to the first control signal CTR1 output from the central processing unit 210 or the dynamic voltage and frequency scaling program executed by the central processing unit 210. The first frequency of CLK1, the second frequency of the second clock signal CLK2 applied to the memory interface 220, and/or the third frequency of the third clock signal CLK3 applied to the input/output interface 250. In some exemplary embodiments, "for adjustment" may mean for increasing, for maintaining, or for reducing.

The power management unit 240 may generate a third for controlling the operation of the power management integrated circuit 300 in response to the second control signal CTR2 output from the central processing unit 210 or the dynamic voltage and frequency scaling program executed by the central processing unit 210. Control signal CTR3.

The power management integrated circuit 300 can adjust the level of each of the first to seventh operating voltages PW1 to PW7 in response to the third control signal CTR3. For example, the power management integrated circuit 300 can control the level of the first operating voltage PW1 applied to the central processing unit 210 and the second operating voltage applied to the clock management unit 230 in response to the third control signal CTR3. The level of PW2, the level of the third operating voltage PW3 applied to the power management unit 240, the level of the fourth operating voltage PW4 applied to the memory interface 220, and the fifth operating voltage applied to the memory 400 The level of PW5, the level of the sixth operating voltage PW6 applied to the input/output interface 250, and the level of the seventh operating voltage PW7 applied to the internal memory 260, but the inventive concept is not limited to these An exemplary embodiment.

Each of the first control signal CTR1, the second control signal CTR2, and the third control signal CTR3 may include at least one analog signal or at least one digital signal.

An input/output interface 250 is provided for inputting and outputting data. The input/output interface 250 can transmit data or receive data based on the third clock signal CLK3 output from the clock management unit 230 and the sixth operating voltage PW6 output from the power management integrated circuit 300. The third frequency of the third clock signal CLK3 and the level of the sixth operating voltage PW6 can be adjusted according to the dynamic voltage and the frequency scaling.

The input/output interface 250 can support serial advanced technology attachment (SATA), SATA express (SATAe), serial attached SCSI (small computer system interface) , SAS), peripheral component interconnect-express (PCIe), non-volatile memory express (NVMe), or mobile industry processor interface (MIPIÒ), However, the inventive concept is not limited to the exemplary embodiments.

Internal memory 260 can be the operational memory of central processing unit 210. For example, the internal memory 260 may be formed of a read-only memory (ROM) or a static random access memory (SRAM), but the inventive concept is not limited to the exemplary embodiments. If the memory 400 is formed of non-volatile memory, the dynamic voltage and frequency scaling program stored in the memory 400 can be loaded into the internal memory 260 and executed by the central processing unit 210 when the computing device 100 is booted.

2 is a diagram of a module included in a dynamic voltage and frequency scaling (DVFS) program 213 executed by the master device of FIG. Referring to FIGS. 1 and 2, the dynamic voltage and frequency scaling program 213 may include a dynamic voltage and frequency scaling (DVFS) regulator 215, a clock management unit device driver 217, and a power management unit device driver 218.

The dynamic voltage and frequency scaling adjuster 215, the clock management unit device driver 217, and the power management unit device driver 218 may be modules. In some exemplary embodiments, a module may be a computer code or software that performs the functions and operations corresponding to its name. The dynamic voltage and frequency scaling regulator 215 can control the dynamic voltage and frequency scaling program 213 or the overall operation of the dynamic voltage and frequency scaling. The dynamic voltage and frequency scaling adjuster 215 can include a workload awareness program (WAP) 216. The dynamic voltage and frequency scaling regulator 215 can control the execution of the workload awareness program 216.

The workload awareness program 216 can control the clock management unit device driver 217 and the power management unit device driver 218 in response to the first count value NOI and/or the second count value NOCM. The first count value NOI and the second count value NOCM may be values having different information or materials.

As described above, the first count value NOI may correspond to the first event corresponding to all executed (committed) instructions in the first event generated while the central processing unit 210 processes the instruction (eg, workload) during a given time period. The number of two events, or the value required to calculate the value of each instruction cycle. The second count value NOCM may correspond to the number of third events in the first event generated while the central processing unit 210 processes all of the instructions during the given time, the third event being capable of being For example, central processing unit 210) is associated with instructions that are processed from interactions between devices (eg, memory interface 220 or input/output interface 250). For example, the second count value NOCM may correspond to the L2 cache miss count, but is not limited thereto.

For example, the first event, the second event, and the third event are illustrated using power management unit events used in an AMRÒ Cortex(R)-A series processor.

Table 1

The first event may refer to an event having the same function or similar function as all events generated while processing the instruction, such as SW_INCR, L1I_CACHE_REFILL, INST_RETIRED, CPU_CYCLES, MEM_ACCESS, L2D_CACHE_REFILL, and BUS_CYCLES described in Table 1. The second event may refer to an event having the same function or similar function as the event INST_RETIRED in the first event. The third event may refer to an event having the same function or similar function as the event L2D_CACHE_REFILL in the first event.

The workload awareness program 216 may calculate a value per thousand instructions or a value of each instruction cycle based on the first count value NOI and/or the second count value NOCM, and may transmit the first intermediate control signal to the clock according to the calculation result. The management unit device drives the machine 217. The clock management unit device driver 217 can output the first control signal CTR1 to the clock management unit 230 in response to the first intermediate control signal.

The workload awareness program 216 may calculate a value per thousand instructions or a value of each instruction cycle based on the first count value NOI and/or the second count value NOCM, and may transmit the second intermediate control signal to the power management according to the calculation result. The unit device drives the machine 218. The power management unit device driver 218 can output the second control signal CTR2 to the power management unit 240 in response to the second intermediate control signal.

The performance monitoring unit 211 may generate a third count value by counting the number of fourth events in the first event generated by the central processing unit 210 while processing all the instructions during a given time period, the fourth event corresponding to The number of instructions that can be processed independently by central processing unit 210. A third count value can be provided to the workload awareness program 216. At this time, the workload awareness program 216 may calculate a value per thousand instructions or a value of each instruction cycle based on the first count value NOI, the second count value NOCM, and/or the third count value.

When the memory interface 220 is a slave device, the second count value NOCM may correspond to a memory constraint and the third count value may correspond to a computation constraint. The term "computation constraint" can refer to a core constraint, a computational constraint, or a central processing unit constraint.

The term "memory constraint" may refer to a situation in which the time for completing the task performed by the central processing unit 210 is determined by the access speed to the memory 400. However, the computational constraints may refer to the situation in which the time for completing the tasks performed by the central processing unit 210 is primarily determined by the speed of the central processing unit 210.

When the input/output interface 250 is a slave device, the second count value NOCM may correspond to an input/output constraint and the third count value may correspond to a calculation constraint. The input/output constraints may refer to the case where the time for completing the tasks performed by the central processing unit 210 is determined by the speed of the input/output interface 250. For example, when the first count value NOI is the sum of the second count value NOCM and the third count value, the workload awareness program 216 can calculate the third count value by using the first count value NOI and the second count value NOCM. The first count value NOI may correspond to the workload of the master device (eg, central processing unit 210).

3 is a conceptual diagram of the interaction between a master device and a slave device (eg, a memory constraint). The slave device (eg, the memory interface 220) can store the data output by the autonomous device (eg, the central processing unit 210) in the memory 400 during the write operation, and can be during the read operation according to the control of the master device. The data read from the memory 400 is transferred to the host device.

4 is a conceptual diagram of dynamic voltage and frequency scaling of at least one of a master device and a slave device based on a computational constraint ("CB") workload or a memory constraint ("MB") workload. 5 is a flow chart of dynamic voltage and frequency scaling of at least one of a master device and a slave device based on a workload of the master device. The dynamic voltage and frequency scaling program 213 executed in the master device (eg, the central processing unit 210) may detect the center based on at least one of the first count value NOI and the second count value NOCM output from the performance monitoring unit 211. The current workload of the processing unit 210 is a computational constraint or a memory constraint (or an input/output constraint), and can control the dynamic voltage and frequency scaling of the master device (eg, the central processing unit 210) and the slave device according to the detection result ( For example, dynamic voltage and frequency scaling of memory interface 220 or input/output interface 250).

For example, when the dynamic voltage and frequency scaling program 213 detects that the workload of the central processing unit 210 is a memory constraint or an input/output constraint, even if the workload of the central processing unit 210 is large or the load of the central processing unit 210 is high. The dynamic voltage and frequency scaling program 213 also does not perform an operation of increasing the voltage and/or frequency on the central processing unit 210, but the dynamic voltage and frequency scaling program 213 is for the slave device (eg, the memory interface 220 or the input/output interface 250). Perform an operation to increase the voltage and/or frequency. In other words, the dynamic voltage and frequency scaling program 213 performs an operation of increasing the voltage and/or frequency on the slave device (eg, the memory interface 220 or the input/output interface 250), and thus, there may be a memory for the central processing unit 210. Guided workload improvements.

However, when the dynamic voltage and frequency scaling program 213 detects that the workload of the central processing unit 210 is a memory constraint or an input/output constraint and the workload of the central processing unit 210 is large or the load of the central processing unit 210 is high, the conventional dynamic The voltage and frequency scaling routine only performs operations to increase voltage and/or frequency to the central processing unit 210, but does not perform voltage and/or frequency increases on the slave device (eg, memory interface 220 or input/output interface 250). operating. At this time, although the voltage and/or frequency of the central processing unit 210 increases, the performance of the controller 200 including the central processing unit 210 and the slave device (eg, the memory interface 220 or the input/output interface 250) does not increase and The power consumption of the central processing unit 210 is increased. Therefore, the power efficiency of the central processing unit 210 is lowered.

In operation S10, the performance monitoring unit 211 may perform calculation on the workload based on the first event, the second event, and/or the third event generated while the central processing unit 210 processes the instruction, and may correspond to the calculation At least one of the resulting first count value NOI and second count value NOCM is output to the workload awareness program 216 of the dynamic voltage and frequency scaling program 213. The workload awareness program 216 can calculate each instruction cycle value or the value per thousand instructions by using at least one of the first count value NOI and the second count value NOCM. The value per thousand instructions may refer to the second count value NOCM divided by the first count value NOI (eg, NOCM/NOI). In other words, the second count value NOCM may refer to the L2 cache miss count and the first count value NOI may refer to the total number of instructions executed by the central processing unit 210 during a given time.

In operation S20, when the slave device is the memory interface 220, the workload awareness program 216 may detect the workload of the central processing unit 210 as a calculation based on at least one of the first count value NOI and the second count value NOCM. Constraints are still memory constraints. When it is detected in operation S20 that the workload of the central processing unit 210 is a computational constraint (in the case of YES), the workload awareness program 216 may generate the first intermediate control signal and the second intermediate control signal to enable The dynamic voltage and frequency scaling of the central processing unit 210 is performed. The clock management unit device driver 217 can generate the first control signal CTR1 according to the first intermediate control signal, and the power management unit device driver 218 can generate the second control signal CTR2 according to the second intermediate control signal. The power management unit 240 may generate the third control signal CTR3 based on the second control signal CTR2.

The clock management unit 230 operating in response to the first control signal CTR1 can increase the first frequency of the first clock signal CLK1 applied to the central processing unit 210. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the first operating voltage PW1 applied to the central processing unit 210. In other words, the dynamic voltage and frequency scaling of the central processing unit 210 can be performed in operation S30.

However, when it is detected in operation S20 that the workload of the central processing unit 210 is not a computational constraint (in the case of NO), the workload awareness program 216 may detect the central processing unit 210 in operation S40. Whether the workload is a memory constraint. When it is detected in operation S40 that the workload of the central processing unit 210 is a memory constraint (in the case of YES), the workload awareness program 216 may generate the first intermediate control signal and the second intermediate control signal to The dynamic voltage and frequency scaling of the memory interface 220 is performed. In other words, even when the workload of the central processing unit 210 is large, the workload awareness program 216 can generate the first intermediate control signal and the second intermediate control signal to perform dynamic voltage and frequency scaling of the memory interface 220 instead of performing central processing. The dynamic voltage and frequency scaling of unit 210.

The clock management unit device driver 217 can generate the first control signal CTR1 according to the first intermediate control signal, and the power management unit device driver 218 can generate the second control signal CTR2 according to the second intermediate control signal. The power management unit 240 may generate the third control signal CTR3 based on the second control signal CTR2.

The clock management unit 230 operating in response to the first control signal CTR1 can increase the second frequency of the second clock signal CLK2 applied to the memory interface 220. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the fourth operating voltage PW4 applied to the memory interface 220. In other words, the dynamic voltage and frequency scaling of the memory interface 220 can be performed in operation S50.

When it is detected that the workload of the central processing unit 210 is neither a computational constraint nor a memory constraint (for example, in the case of "NO" in operations S20 and S40), the workload awareness program 216 may generate The first intermediate control signal and the second intermediate control signal are such that the dynamic voltage and frequency scaling of the central processing unit 210 and the dynamic voltage and frequency scaling of the memory interface 220 are performed simultaneously or in parallel.

The clock management unit device driver 217 can generate the first control signal CTR1 according to the first intermediate control signal, and the power management unit device driver 218 can generate the second control signal CTR2 according to the second intermediate control signal. The power management unit 240 may generate the third control signal CTR3 based on the second control signal CTR2.

The clock management unit 230 operating in response to the first control signal CTR1 can increase the first frequency of the first clock signal CLK1 applied to the central processing unit 210. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the first operating voltage PW1 applied to the central processing unit 210. In other words, the dynamic voltage and frequency scaling of the central processing unit 210 can be performed in operation S60. The clock management unit 230 operating in response to the first control signal CTR1 can simultaneously or in parallel increase the second frequency of the second clock signal CLK2 applied to the memory interface 220. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the fourth operating voltage PW4 applied to the memory interface 220. In other words, the dynamic voltage and frequency scaling of the memory interface 220 can be performed in operation S60.

When the slave device is the input/output interface 250, the workload awareness program 216 can detect the workload of the central processing unit 210 based on at least one of the first count value NOI and the second count value NOCM in operation S20. Calculate constraints or input/output constraints. When it is detected in operation S20 that the workload of the central processing unit 210 is a computational constraint (in the case of YES), the dynamic voltage and frequency scaling of the central processing unit 210 may be performed in operation S30. However, when it is detected in operation S20 that the workload of the central processing unit 210 is not a computational constraint (in the case of NO), the workload awareness program 216 may detect the central processing unit 210 in operation S40. Whether the workload is an input/output constraint.

When it is detected in operation S40 that the workload of the central processing unit 210 is an input/output constraint (in the case of YES), the workload awareness program 216 can generate the first intermediate control signal and the second intermediate control signal. The dynamic voltage and frequency scaling of the input/output interface 250 is performed. In other words, even when the workload of the central processing unit 210 is large, the workload awareness program 216 can generate the first intermediate control signal and the second intermediate control signal to perform dynamic voltage and frequency scaling of the input/output interface 250 instead of central processing. The dynamic voltage and frequency scaling of unit 210.

The clock management unit 230 operating in response to the first control signal CTR1 can increase the third frequency of the third clock signal CLK3 applied to the input/output interface 250. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the sixth operating voltage PW6 applied to the input/output interface 250. In other words, the dynamic voltage and frequency scaling of the input/output interface 250 can be performed in operation S50.

When it is detected that the workload of the central processing unit 210 is neither a computational constraint nor an input/output constraint (for example, in the case of "NO" in operations S20 and S40), the workload awareness program 216 may generate a An intermediate control signal and a second intermediate control signal are used to cause dynamic voltage and frequency scaling of the central processing unit 210 and dynamic voltage and frequency scaling of the input/output interface 250 to be performed simultaneously or in parallel.

The clock management unit 230 operating in response to the first control signal CTR1 can increase the first frequency of the first clock signal CLK1 applied to the central processing unit 210. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the first operating voltage PW1 applied to the central processing unit 210. In other words, the dynamic voltage and frequency scaling of the central processing unit 210 can be performed in operation S60. The clock management unit 230 operating in response to the first control signal CTR1 can simultaneously or in parallel increase the third frequency of the third clock signal CLK3 applied to the input/output interface 250. The power management integrated circuit 300 operating in response to the third control signal CTR3 can increase the level of the sixth operating voltage PW6 applied to the input/output interface 250. In other words, the dynamic voltage and frequency scaling of the input/output interface 250 can be performed in operation S60.

As shown in FIG. 4, the workload awareness program 216 can calculate each instruction cycle value or the value per thousand instructions by using at least one of the first count value NOI and the second count value NOCM. When each command cycle value or value per thousand command is less than the first reference value REF1, the workload awareness program 216 can detect that the workload of the central processing unit 210 is a computational constraint and can be generated for controlling the central processing unit. The dynamic voltage and frequency of 210 are scaled by a first control signal CTR1 and a second control signal CTR2. The workload awareness program 216 may generate the control unit 216 for controlling the central processing unit 210 simultaneously or in parallel when each instruction cycle value or value per thousand command is equal to or greater than the first reference value REF1 and less than the second reference value REF2. The dynamic voltage and frequency scaling and the first control signal CTR1 and the second control signal CTR2 of the dynamic voltage and frequency scaling of the slave device (eg, the memory interface 220 or the input/output interface 250). The workload awareness program 216 can detect that the workload of the central processing unit 210 is a memory constraint or an input/output constraint when each instruction cycle value or a value per thousand instructions is equal to or greater than the second reference value REF2, and A first control signal CTR1 and a second control signal CTR2 for controlling dynamic voltage and frequency scaling of the slave device (eg, memory interface 220 or input/output interface 250) may be generated. The central processing unit 210 can program the first reference value REF1 and the second reference value REF2 according to design specifications.

6 is a conceptual diagram of a scheme for controlling dynamic voltage and frequency scaling of a master device and scaling of dynamic voltage and frequency from a device. When the workload of the central processing unit 210 is a computational constraint (CB), the first frequency (eg, CPU frequency) of the first clock signal CLK1 applied to the central processing unit 210 may increase along the first line GP1 and be The level of the first operating voltage PW1 applied to the central processing unit 210 may also increase along the first line GP1. Each of the curves EP1 to EPn may refer to an equivalent voltage line.

When the workload of the central processing unit 210 is a memory constraint (MB), the second frequency (memory interface frequency (MIF)) of the second clock signal CLK2 applied to the memory interface 220 may be along The level of the fifth line GP5 is increased and the fourth operating voltage PW4 applied to the memory interface 220 may also increase along the fifth line GP5.

The dynamic voltage and frequency scaling of the central processing unit 210 and the dynamic voltage and frequency scaling of the slave device (eg, the memory interface 220 or the input/output interface 250) are performed simultaneously or in parallel according to the workload of the central processing unit 210. The first frequency of the first clock signal CLK1 applied to the central processing unit 210 and the level of the first operating voltage PW1 are applied to the slave device (eg, the memory interface 220 or the input/output interface 250). The frequency of the second clock signal CLK2 or the third clock signal CLK3 and the level of the fourth operating voltage PW4 or the sixth operating voltage PW6 may increase along one of the second line GP2 to the fourth line GP4. .

The line GP1 to the line GP5 and the equivalent voltage line EP1 to the equivalent voltage line EPn are only examples. The inventive concept is not limited to the number and shape of the line GP1 to the line GP5, the number of the equivalent voltage line EP1 to the equivalent voltage line EPn, or the gap between the equivalent voltage line EP1 to the equivalent voltage line EPn.

7 is a flow chart of a method of operating a system wafer in accordance with certain exemplary embodiments of the inventive concepts. Referring to FIGS. 1 through 7, in operation S110, the performance monitoring unit 211 may generate a first generated while the master device (eg, the central processing unit 210) processes all instructions (or all workloads) during a given time. The number of second events in the event (eg, the total number of instructions executed) is counted and a first count value NOI can be generated. In operation S120, the performance monitoring unit 211 may count the number of third events in the first event (eg, the number of L2 cache misses) and may generate a second count value NOCM, the third event and capable The processed instructions (or workload) are related by the interaction between the master device (e.g., central processing unit 210) and the slave device (e.g., memory interface 220 or input/output interface 250).

In operation S130, the dynamic voltage and frequency scaling program 213 and, more specifically, the workload awareness program 216 may select one or more target devices for dynamic voltage and frequency scaling based on the first count value NOI and the second count value NOCM. The method of selecting one or more target devices for dynamic voltage and frequency scaling is the same or similar to the method described above with reference to FIG. 4 or FIG.

The workload awareness program 216 can generate a first control signal CTR1 and a second control signal CTR2 for controlling dynamic voltage and frequency scaling of at least one target device. The clock management unit 230 can adjust (eg, increase or decrease) at least one of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 according to the first control signal CTR1. Frequency of. The power management integrated circuit 300 can adjust (eg, increase or decrease) the bit of at least one of the first operating voltage PW1, the fourth operating voltage PW4, and the sixth operating voltage PW6 in response to the third control signal CTRL3. quasi. In other words, in operation S140, the controller 200 may perform dynamic voltage and frequency scaling of at least one target device using a value per thousand instructions determined based on the first count value NOI and the second count value NOCM.

FIG. 8 is a flowchart of a method of operating a system wafer, according to an exemplary embodiment of the inventive concept. Referring to FIGS. 1 through 6 and 8, in operation S210, the performance monitoring unit 211 may calculate each instruction cycle value based on the total number of instructions (or workloads) processed by the central processing unit 210 during a given time, Each command cycle value can be output as the first count value NOI. Each command cycle value may not be a count value in a true literal sense, but is referred to as a first count value NOI to coincide with the first count value NOI described with reference to FIGS. 1 through 7.

If the constraint program is calculated, there are no many events associated with the instructions (or workloads) used to access the memory 400. These events can mostly be related to L1 cache hits or L2 cache hits. At this point, the memory delay can be close to 0 cycles, so each command cycle value can be less than 1 or close to 1.

In operation S220, the workload awareness program 216 may compare each instruction cycle value with a reference value REF and may detect whether the workload of the central processing unit 210 is a computational constraint or a memory constraint. When the value of each instruction loop is less than the reference value REF (for example, 1) in operation S220 (in the case of YES), the workload awareness program 216 may detect the workload of the central processing unit 210 in operation S230. The first control signal CTR1 and the second control signal CTR2 for controlling the dynamic voltage and frequency scaling of the central processing unit 210 are generated according to the detection result. However, when the operation performed in the central processing unit 210 is complicated or involves a floating point, in operation S220, even if there is no access to the memory 400, the value of each instruction cycle may be Greater than the reference value REF (eg, 1) (ie, it may be "No").

The performance monitoring unit 211 can count the number of third events in the first event related to all instructions (or workloads) processed by the central processing unit 210 during a given time, and can generate a second count value NOCM, and A second count value NOCM can be provided to the workload awareness program 216, wherein the third event can be coupled to the slave device (eg, the memory interface 220 or the input/output interface 250 by the master device (eg, central processing unit 210) The interaction between the instructions (or workload) that is processed by the interaction, the first event. As described above, the second count value NOCM can be an L2 cache miss count.

The workload awareness program 216 can detect whether the workload of the central processing unit 210 is a computational constraint or a memory constraint based on the second count value NOCM. For example, in operation S240, the workload awareness program 216 can detect whether each instruction loop value has been caused by an event related to an instruction for accessing the memory 400 or has been complicated based on the second count value NOCM. The operation actually increases.

When the value of each instruction loop is greater than the reference value REF due to an event related to the instruction for accessing the memory 400, the workload awareness program 216 can detect the workload of the central processing unit 210 as a memory in operation S250. The first control signal CTR1 and the second control signal CTR2 for controlling the dynamic voltage and frequency scaling of the slave device (for example, the memory interface 220 or the input/output interface 250) are generated according to the detection result.

However, when the value of each instruction loop is greater than the reference value REF due to a complicated operation, in operation S230, the workload awareness program 216 can detect that the workload of the central processing unit 210 is a calculation constraint, and can be based on the detection result. The first control signal CTR1 and the second control signal CTR2 for controlling the dynamic voltage and frequency scaling of the central processing unit 210 are generated. In other words, when the second count value NOCM is smaller than the reference value REF, operation S230 may be performed. When the second count value NOCM is equal to or greater than the reference value REF, operation S250 may be performed. Each command cycle value can be affected by the second count value NOCM.

As described above, according to some exemplary embodiments of the inventive concept, the system wafer controls the dynamic voltage and frequency scaling of the master device and the dynamic voltage of the slave device communicating with the master device according to the type of the workload of the master device. Frequency scaling to improve performance.

Techniques for implementing or controlling the techniques discussed in this application (eg, for system wafers, for dynamic voltage and frequency scaling, for controlling power using a workload, for operating methods, and for associated computing devices) Algorithms can be used to implement or control more general purpose devices and/or device control methods.

The method for implementing or controlling the techniques discussed in this application can be written as a computer program and can be implemented in a general-purpose digital computer that uses a computer-readable recording medium to execute the program. Furthermore, the data structures used in the method can be recorded in a computer readable recording medium in various ways. Examples of computer readable recording media include storage media such as magnetic storage media (eg, read only memory, random access memory, universal serial bus (USB), floppy disk, hard disk, etc.) and An optical recording medium (for example, a compact disc read-only memory (CD-ROM) or a digital video disc (DVD)).

Moreover, certain exemplary embodiments may also be implemented by computer readable code/instructions in/on a medium (eg, computer readable medium) to control at least one processing element to implement certain exemplary Example. The media may correspond to any medium that allows storage and/or transmission of computer readable codes.

Computer readable codes can be recorded/delivered on the media in a variety of ways, including recording media such as magnetic storage media (eg, read only memory, floppy disks, hard drives, etc.) and optical recording media (eg, , CD-read-only memory or digital video discs; and transmission media, such as Internet transmission media. Thus, the media can be such defined and measurable structures that contain or carry signals or information, such as devices that carry bitstreams in accordance with certain exemplary embodiments. The media may also be a distributed network such that the computer readable code is stored/delivered and executed in a distributed manner. Furthermore, the processing elements can include a processor or a computer processor, and the processing elements can be distributed and/or included in a single device.

In some exemplary embodiments, certain components may be implemented as "modules." According to certain exemplary embodiments, a "module" may be interpreted as a software-based component or a hardware component, such as a field programmable gate array (FPGA) or an application specific integrated circuit (application specific integrated) Circuit, ASIC), and the module can perform certain functions. However, the module is not limited to software or hardware. The module can be configured to be placed in an executable storage medium or to perform one or more processes.

For example, a module may include components such as a software component, an object-oriented software component, a class component, and a task component, processes, functions, attributes, programs, and secondary functions. , code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided by the components and modules can be combined into a smaller number of components and modules, or can be separated into additional components and modules. In addition, the components and modules can execute one or more central processing units (CPUs) in the device.

Certain exemplary embodiments may be implemented by controlling a medium comprising computer readable code/instructions to control at least one processing element of the above-described embodiments, such as a computer readable medium. Such media may correspond to media that can store and/or transmit computer readable codes.

The computer readable code can be recorded in the media or can be transmitted over the Internet. For example, the media can include read only memory, random access memory, optical disk-read only memory, magnetic tape, floppy disk, optical recording medium, or carrier wave (eg, data transmission over the Internet). Additionally, the media can be a non-transitory computer readable medium. Since the media can be a distributed network, the computer readable code can be stored, transmitted, and executed in a distributed manner. Moreover, by way of example, processing elements can include a processor or a computer processor, and can be distributed and/or included in a device.

While certain exemplary embodiments of the present invention have been shown and described with reference to certain exemplary embodiments, Various changes in form and detail may be made in the spirit and scope of the inventive concept.

It is understood that the exemplary embodiments described herein are to be considered in a Descriptions of features or aspects within the exemplary embodiments are generally considered to be available for other similar features or aspects in other exemplary embodiments.

100‧‧‧ computing device
200‧‧‧ controller
201‧‧‧ Bus Bar Architecture
210‧‧‧Central Processing Unit (CPU)
211‧‧‧ Performance Monitoring Unit
211-1‧‧‧First counter
211-2‧‧‧Second counter
213‧‧‧Dynamic Voltage and Frequency Scaling (DVFS) Program
215‧‧‧Dynamic Voltage and Frequency Scaling (DVFS) Regulator
216‧‧‧Workload Awareness Program (WAP)
217‧‧‧ Clock Management Unit (CMU) device driver
218‧‧‧Power Management Unit (PMU) device driver
220‧‧‧ memory interface
230‧‧‧ Clock Management Unit (CMU)
240‧‧‧Power Management Unit (PMU)
250‧‧‧Input/Output (I/O) interface
260‧‧‧ internal memory
300‧‧‧Power Management Integrated Circuit (PMIC)
400‧‧‧ memory
CB‧‧‧ Calculation constraints
CLK1‧‧‧ first clock signal
CLK2‧‧‧ second clock signal
CLK3‧‧‧ third clock signal
CTR1‧‧‧ first control signal
CTR2‧‧‧second control signal
CTR3‧‧‧ third control signal
EP1, EP2, EPn‧‧‧ equivalent voltage line
GP1~GP5‧‧‧ line
MB‧‧‧ memory constraints
NOCM‧‧‧second count value
NOI‧‧‧ first count value
PW1‧‧‧First operating voltage
PW2‧‧‧second operating voltage
PW3‧‧‧ third operating voltage
PW4‧‧‧ fourth operating voltage
PW5‧‧‧ fifth operating voltage
PW6‧‧‧ sixth operating voltage
PW7‧‧‧ seventh operating voltage
REF1‧‧‧ first reference value
REF2‧‧‧ second reference value
S10, S20, S30, S40, S50, S60‧‧‧ operations
S110, S120, S130, S140‧‧‧ operations
S210, S220, S230, S240, S250‧‧‧ operations

The above and/or other aspects and advantages will become more apparent and more readily understood from the following detailed description of exemplary embodiments of the invention in which <RTIgt; A schematic block diagram of the device. 2 is a diagram of a module included in a dynamic voltage and frequency scaling (DVFS) program executed by the master device shown in FIG. 1. Figure 3 is a conceptual diagram of the interaction between a master device and a slave device. 4 is a conceptual diagram of dynamic voltage and frequency scaling of at least one of a master device and a slave device based on a computationally constrained workload or a memory-constrained workload. 5 is a flow chart of dynamic voltage and frequency scaling of at least one of a master device and a slave device based on a workload of the master device. 6 is a conceptual diagram of a scheme for controlling dynamic voltage and frequency scaling of a master device and scaling of dynamic voltage and frequency from a device. 7 is a flow chart of a method of operating a system wafer (SoC) in accordance with certain exemplary embodiments of the inventive concepts. 8 is a flow chart of a method of operating a system wafer in accordance with certain exemplary embodiments of the inventive concept.

213‧‧‧Dynamic Voltage and Frequency Scaling (DVFS) Program

215‧‧‧Dynamic Voltage and Frequency Scaling (DVFS) Regulator

216‧‧‧Workload Awareness Program (WAP)

217‧‧‧ Clock Management Unit (CMU) device driver

218‧‧‧Power Management Unit (PMU) device driver

CTR1‧‧‧ first control signal

CTR2‧‧‧second control signal

NOCM‧‧‧second count value

NOI‧‧‧ first count value

Claims (25)

A system chip comprising: a master device for performing a dynamic voltage and frequency scaling program; a slave device for communicating with the master device; and a performance monitoring unit for receiving a command generated while the master device processes the command a first event, configured to generate a first count value by counting the number of second events, and to generate a second count value by counting the number of third events in the first event, The number of the second events corresponds to a total number of the instructions associated with the first event, the third event being able to be processed by interaction between the master device and the slave device The first instruction related, wherein the dynamic voltage and frequency scaling program is configured to generate at least one of the master device and the slave device based on the first count value and the second count value Dynamic voltage and frequency scaling control signals. The system chip of claim 1, wherein the main device is one of a central processing unit, a graphics processing unit, a video signal processor, a digital signal processor, and a multimedia processor, and wherein The slave device is one of a memory interface and an input/output interface. The system chip of claim 1, further comprising: a clock management unit configured to control a first frequency of the first clock signal applied to the main device according to the control signal At least one of a second frequency applied to the second clock signal of the slave device. The system chip of claim 1, further comprising: a power management unit configured to control the power management integrated circuit to control a bit of the first voltage applied to the main device in response to the control signal At least one of a level of a second voltage applied to the slave device is permitted. The system wafer of claim 1, wherein the second event is related to an instruction executed by the host device, and the third event is associated with an L2 cache miss. The system chip of claim 1, wherein the dynamic voltage and frequency scaling program is configured to calculate a value per thousand instructions based on the first count value and the second count value, and The control signal is generated based on the number of values per thousand instructions, and wherein the second count value is an L2 cache miss count. A computing device comprising: a master device for performing a dynamic voltage and frequency scaling program; a slave device for communicating with the master device; and a performance monitoring unit for receiving a command generated while the master device processes the command a first event, configured to generate a first count value by counting the number of second events, and to generate a second count value by counting the number of third events in the first event, The number of the second events corresponds to a total number of the instructions associated with the first event, the third event being able to be processed by interaction between the master device and the slave device The first instruction related, the power management integrated circuit is configured to provide a corresponding operating voltage to the main device, the slave device, and the performance monitoring unit; wherein the dynamic voltage and frequency scaling program is used to The first count value and the second count value generate a control signal for controlling dynamic voltage and frequency scaling of at least one of the master device and the slave device. The computing device of claim 7, wherein the main device is one of a central processing unit, a graphics processing unit, a video signal processor, a digital signal processor, and a multimedia processor, and wherein The slave device is one of a memory interface and an input/output interface. The computing device of claim 7, further comprising: a clock management unit configured to control a first frequency of the first clock signal applied to the main device and to be controlled according to the control signal At least one of a second frequency applied to the second clock signal of the slave device. The computing device of claim 7, further comprising: a power management unit configured to control the power management integrated circuit to control a first voltage applied to the primary device in response to the control signal a level and at least one of a level of a second voltage applied to the slave device. The computing device of claim 7, wherein the second event is related to an instruction executed by the host device, and the third event is associated with an L2 cache miss. The computing device of claim 7, wherein the dynamic voltage and frequency scaling program is configured to calculate a value per thousand instructions based on the first count value and the second count value, and The control signal is generated based on the number of values per thousand instructions, and wherein the second count value is an L2 cache miss count. The computing device of claim 7, further comprising: a memory; wherein the main device is one of a central processing unit, a graphics processing unit, a video signal processor, a digital signal processor, and a multimedia processor. And wherein the slave device is a memory interface for controlling the operation of the memory device according to the control of the master device. A method of operating system chips, the system wafer including a master device for performing a dynamic voltage and frequency scaling program and a slave device in communication with the master device, the method comprising: receiving a processing instruction at the same time as the master device a first event generated, and generating a first count value corresponding to the number of instructions in the first event; and the dynamic voltage and frequency scaling program controlling the master device based on the first count value Dynamic voltage and frequency scaling and dynamic voltage and frequency scaling of the slave device. The method of claim 14, wherein the master device is one of a central processing unit, a graphics processing unit, a video signal processor, a digital signal processor, and a multimedia processor, and The slave device is one of a memory interface and an input/output interface. The method of claim 14, wherein the method further comprises: generating a second count value by counting the number of the second events in the first event, the second event The first instruction related to the processing by the interaction between the master device and the slave device; wherein the dynamic voltage and frequency scaling program is configured to be based on the first count value and the second count value And controlling the dynamic voltage and frequency scaling of the master device and the dynamic voltage and frequency scaling of the slave device. The method of claim 16, wherein the first count value is each instruction cycle value and the second count value is an L2 cache miss count. The method of claim 16, wherein the dynamic voltage and frequency scaling program is configured to control the dynamics of the master device when each of the command cycle values is less than a first reference value Voltage and frequency scaling, and wherein the dynamic voltage and frequency scaling program is configured to control the each of the command cycle values when the value is greater than the first reference value and the L2 cache miss count is less than a second reference value The dynamic voltage and frequency scaling of the master device. The method of claim 16, wherein the dynamic voltage and frequency scaling program is configured to calculate a value per thousand instructions based on the first count value and the second count value. And controlling the dynamic voltage and frequency scaling of the master device and the dynamic voltage and frequency scaling of the slave device based on the value of the per thousand instructions, wherein the first count value is the The total number of instructions, wherein the second count value is an L2 cache miss count. The method of claim 19, wherein the dynamic voltage and frequency scaling program is configured to control the master device when the value per thousand instructions is less than a first reference value Dynamic voltage and frequency scaling for controlling the dynamic voltage and frequency scaling of the slave device when the value per thousand instructions is greater than or equal to a second reference value, and is used to The dynamic voltage and frequency scaling of the master device and the dynamic voltage and frequency scaling of the slave device are controlled when the value is greater than or equal to the first reference value but less than the second reference value. A computing device, comprising: a first device for executing a program; a second device for communicating with the first device; and a third device for receiving a first generated by the first device processing an instruction An event for generating a first count value by counting the number of second events, and for generating a second count value by counting the number of third events in the first event, The number of second events corresponds to a total number of the instructions associated with the first event, the third event being capable of being processed by interaction between the first device and the second device And the fourth device is configured to provide an operating voltage to the first device or the second device; wherein the program is configured to be based on the first count value and the second count value And generating a control signal for controlling the first device, the slave device, or the first device and the second device. The computing device of claim 21, wherein the package comprises a dynamic voltage and frequency scaling program. The computing device of claim 21, wherein the program is configured to provide an operating voltage to the first device and the second device. The computing device of claim 21, wherein the first device comprises a central processing unit, a graphics processing unit, an image signal processor, a digital signal processor, or a multimedia processor. The computing device of claim 21, wherein the second device comprises a memory interface or an input/output interface.