TW201628140A - Composite interface material with tunable CTE - Google Patents

Abstract

Representative implementations of devices and techniques provide a tunable interfacing material for encapsulating integrated circuit(IC) dice, discrete components, and the like, mounted to a common carrier base layer. A predetermined quantity of particles is combined with a filler in a predetermined spatial arrangement to form the tunable interfacing material. A coefficient of thermal expansion (CTE) of the interfacing material is tunable to match the CTE of encapsulated devices and/or the common carrier, based on the quantity and the spatial arrangement of the particles.

Description

Composite interface material with adjustable thermal expansion coefficient Cross-references to priority claims and related applications

This patent application claims priority to U.S. Provisional Patent Application Serial No. 62/065,747, filed on Jan. Incorporate.

The present invention is directed to a composite interface material having an adjustable coefficient of thermal expansion.

As the integrated circuit (IC) wafer technology matures, smaller packages can be achieved due to the smaller and denser IC relationships. In many cases, multiple small IC chips can be packaged together in a common package. In one example, the plurality of IC chips can include a plurality of devices or systems that together function as part of a larger device or system. For example, the IC chips can be mounted to a common carrier (eg, substrate, wafer, etc.) or a base layer, and sometimes can be mounted in conjunction with multiple of the common carrier. Discrete devices or the like are packaged together. The devices, IC chips, ... and the like may be interconnected by one or more windings or one or more interconnect layers associated with the common carrier.

In many cases, the multiple IC chips (and other devices, if The package in the case may be filled with a filler, an encapsulation layer, an interface material, or the like. In some cases, the filler or encapsulant layer may completely encase the IC wafers or may include the package itself. The filler provides a sealing layer surrounding the wafers and has a protective function to prevent environmental damage. In some cases, the filler can block heat transfer from the IC wafers or devices within the package during operation. As the number of IC chips or devices in the package increases, this heat transfer situation may deteriorate.

The heat from the operation of the IC chips and other devices within the package can result in an increase in the physical size or length (or height, area, etc.) of portions of the devices within the package, which are used to form the portions. The coefficient of thermal expansion (CTE) of each material is based. This would include the IC wafers, devices, filters, common carrier boards, and materials for encapsulating enclosures. When the CTEs of adjacent coupling portions are different, the adjacent coupling portions may expand or expand to different degrees at different rates. The difference in sufficient expansion of the adjacent coupling portions can cause damage to one or more of the IC chips, devices, common carrier boards, enclosures, or the like.

One aspect of the invention discloses an adjustable composite interface material for encapsulating a microelectronic component, comprising: a filler material having a first coefficient of thermal expansion (CTE); and a quantity A particle comprising a material having a second CTE that will bond the filler material in a predetermined spatial arrangement, the CTE of the composite interface material being based on the number of particles and the predetermined spatial arrangement.

Another aspect of the invention discloses a microelectronic assembly comprising: a common carrier substrate layer; one or more microelectronic components coupled to the common carrier; and an adjustable a composite interface material for encapsulating the microelectronic components, comprising: a filler material having a first coefficient of thermal expansion (CTE); and a quantity of particles comprising a material having a second CTE, The filler material is combined in a predetermined spatial arrangement, the CTE of the composite interface material being based on the number of the particles and the predetermined spatial arrangement.

Yet another aspect of the present invention discloses a method comprising: providing a filler material for encapsulating a microelectronic component, the filler material having a first coefficient of thermal expansion (CTE); Having a quantity of particles and the filler material to form an adjustable composite interface material, the predetermined number of particles comprising a material having a second CTE; and determining the number based on the number of particles and the spatial arrangement The CTE of the composite interface material.

100‧‧‧Microelectronics package

102‧‧‧ Carrier Board

104‧‧‧ channel

106‧‧‧Microelectronic components (components)

108‧‧‧Filling materials

110‧‧‧Upper carrier board

112‧‧‧Contacts

200‧‧‧Current expansion coefficient (CTE) adjustable interface material

202‧‧‧ granules

400‧‧‧Microelectronics package

502‧‧‧ gel layer

504‧‧‧ polymer layer

506‧‧‧ gel layer

508‧‧‧ polymer layer

602‧‧‧Interfacial material layer

604‧‧‧Interfacial material layer

606‧‧‧Interfacial material layer

608‧‧‧Under filler or passivation layer

902‧‧‧ Larger size granules

904‧‧‧Small sized particles

1002‧‧‧bonding area

1102‧‧‧Particles

The invention is described in detail with reference to the accompanying drawings. In these figures, the leftmost digit of a component symbol indicates the first occurrence of the component symbol. The same component symbols are used in different drawings to indicate similar or identical items.

For the purposes of this discussion, the devices and systems shown in the figures will be shown as having multiple devices. However, as described herein, the manner in which the various devices and/or systems are implemented may also include fewer devices and still fall within the scope of the present disclosure. Alternatively, the manner in which other devices and/or systems are implemented may also include additional devices or various combinations of such described devices, and still fall within the scope of the present disclosure.

Figure 1 shows an example of a wafer-to-wafer process flow.

2 is an example of a particulate impregnated filler material having an adjustable coefficient of thermal expansion in accordance with an embodiment.

Figure 3 shows a particle impregnated with an adjustable coefficient of thermal expansion according to an embodiment. Another example of a filler material.

4 illustrates an exemplary process for forming a microelectronic device package in accordance with an embodiment, the package including an interface material having an adjustable thermal expansion coefficient.

Figure 5 shows another example of an interface material having an adjustable coefficient of thermal expansion in accordance with another embodiment.

6 illustrates an exemplary process for forming a microelectronic device package in accordance with an embodiment, the package including a layered interface material having an adjustable coefficient of thermal expansion.

Figure 7 illustrates another exemplary process for forming a microelectronic device package in accordance with another embodiment, the package comprising a layered interface material having an adjustable coefficient of thermal expansion.

Figure 8 illustrates another example of a particulate impregnated filler material having an adjustable coefficient of thermal expansion in accordance with another embodiment.

Figure 9 shows an example of an adjustable composite interface material in accordance with an embodiment.

Another example of an adjustable composite interface material in accordance with an embodiment is shown in FIG.

Figure 11 shows a further example of an adjustable composite interface material in accordance with an embodiment.

Figure 12 illustrates an exemplary process flow diagram for forming a microelectronic device package in accordance with an implementation, the package including an interface material having an adjustable thermal expansion coefficient.

summary

Representative devices and techniques of the present invention provide an interface material having an adjustable coefficient of thermal expansion (CTE) for use in encapsulated integrated circuit (IC) dies, discrete devices, and the like, for example These integrated circuit (IC) dies, discrete devices, and the like can be mounted to a common carrier substrate. The preset number of particles will be preset The spatial arrangement is combined with a filler to form the adjustable interface material. For example, the CTE of the interface material can be adjusted based on the number of particles and the spatial arrangement of the particles to match the CTE of the encapsulated device and/or the common carrier.

In one mode of operation, the filler has a first CTE based on the material(s) of the filler, and the particles have a second CTE based on the material(s) of the particles. In various embodiments, the filler and the particles can each be composed of one or more materials having different CTEs. The final CTE of the filler may thus be based on a combination of the materials of the filler. The final CTE of the particles may be based on a combination of materials comprising the particles, or based on particles comprising different materials (e.g., having different CTEs), or various combinations of the foregoing.

Combining the particles and the filler creates the CTE adjustable interface material. By combining a predetermined number of particles with the filler, and by arranging the particles in a predetermined spatial arrangement, the resulting interface material can have a desired CTE. For example, it may be desirable to have the CTE of the interface material similar to the CTE of the various devices in a package, the CTE of the common carrier plate to which the devices are coupled, the CTE of the package or the enclosure itself, or , similar to the above combination.

As mentioned above, in one embodiment, the adjustable interface material comprises one or more other particles in addition to the first particles, including one or more other CTEs. One or more other materials. When combined with the filler material in one or more other predetermined spatial arrangements, the CTE of the composite interface material may be the number of the first particles, the one or more other particles, the The predetermined spatial arrangement of the first particles and the one or more other predetermined spatial arrangements of the other particles are adjusted based on the arrangement.

For example, in certain modes of operation, the filler may incorporate multiple types and/or shapes of particles that may be composed of different materials. Combining such particles with the filler in a predetermined spatial arrangement can achieve the purpose of an infinitely customizable interface material.

In another mode of operation, the CTE adjustable interface material can be constructed of multiple layers. For example, in one embodiment, the particles are arranged in a plurality of layers within the filler material. In one example, the particles are arranged in a plurality of layers by the average size (ie, diameter, cross section, section, etc.) of the particles, and the particles in each layer have a preselected average size. . In another example, the particles are arranged in a plurality of layers by the type of particles (for example, the shape of the particles, the material of the particles, etc.), and the particles in each layer have particles of a previously selected type.

In another embodiment, the CTE tunable interface material is comprised of a plurality of layers of particulate/filler combinations. For example, the interface material as a whole may contain several layers of interface material that is custom adjusted or customizable. In this embodiment, the individual layers may each be composed of a filler material in combination with one or more types and one or more numbers of particles, arranged in a predetermined arrangement on the filler material. inside. Stacking or combining the individual custom-tuned layers can produce the desired CTE for the entire stack.

In various examples, laminating the interface material (with multiple layers of particles in a single layer of filler, or with multiple layers of filler/particle composite) produces a gradient CTE for the entire interface material. For example, the CTE of the interface material may be lower at one of the ranges of the interface material (for example, at the top layer or the first region of the interface material), and the CTE is another one of the interface materials The range (for example, near the bottom layer or the second region of the common carrier) may be larger; vice versa. In these examples, the stack will be in the CTE adjustable interface. Another dimension is added to the material's customizable capabilities.

In various modes of implementation, the techniques and devices described herein can also be arranged to reduce or adjust the substrate or package warpage, resulting in higher assembly package yields. For example, the CTE of the interface material that closely matches the CTE of the substrate or package reduces the warpage of the substrate or package. In addition, the interface material can also be customized to have a CTE that is very different from the CTE of the substrate or package to match the thermal expansion to cause the desired warpage of the substrate or package.

In addition, these techniques and devices are very easy to scale for use in smaller or larger devices, packages, interposers, and the like. Further, certain substrate processing issues can be reduced or eliminated by adjusting the CTE.

Reference is made herein to electrical and electronic devices and various carrier boards to discuss various modes of implementation and arrangement. Although specific devices are mentioned herein (ie, Printed Circuit Board (PCB), wafer, substrate, integrated circuit (IC) die, discrete devices, etc.); however, this does not The purpose of the restriction is for the purpose of easy discussion and easy explanation. The techniques and devices discussed herein can be applied to any type or number: electrical devices (eg, sensors, transistors, diodes, etc.); circuits (eg, integrated circuits (ICs) ), hybrid circuits, ASICs, memory devices, processors, etc.); a collection of multiple devices; packaged devices; structures (for example, wafers, panels, boards, PCBs, etc.) ); and similar. Each of such devices, circuits, wafers, structures, and the like is often referred to as a "microelectronic component."

A number of examples will be used below to explain in more detail the manner in which the present invention is practiced. Various implementations and examples are discussed here and below; however, by combining multiple individual performers The features and components of the formula and examples may lead to further implementation and examples.

Sample interface with adjustable CTE

1 is an example of a wafer-to-wafer process flow for forming a microelectronic device package 100. The package 100 represents an exemplary environment for an application of an interface material having an adjustable coefficient of thermal expansion (CTE) according to an exemplary implementation. 2, 3, 5, and 8 through 11 show plan views of various example CTE adjustable interface materials 200 in accordance with various embodiments. 4, 6, and 7 show an exemplary alternative process for forming a microelectronic device package 400 that includes various example CTE adjustable interface materials 200 in accordance with various embodiments. The techniques, devices, and devices described herein with respect to the example CTE adjustable interface materials 200 and the microelectronic device packages 400 are not limited to the illustrations of FIGS. 1 through 11, and may be applied to other electrical devices. Other designs, types, arrangements, and configurations are not departing from the scope of the present disclosure.

12 is an exemplary process flow diagram for forming a CTE adjustable interface material 200 in accordance with an implementation. A text-based flow chart of Figure 12 is used to illustrate an example of the process without limitation. Further, FIGS. 1 through 11 and their individual discussion also illustrate an exemplary process for forming CTE adjustable interface material 200 and/or microelectronic device package 400 in a graph-based flow diagram. Each of the processes described with respect to Figures 1 through 12 of the present invention also illustrates a corresponding apparatus, structure, system, or the like that includes one or more CTE-adjustable interface materials 200.

The techniques described herein may also be performed using alternative devices of the devices explicitly mentioned herein, unless explicitly stated in detail. In various modes of implementation, a CTE is adjustable The entire interface material 200 can be a stand-alone type, or it can be part of a system, device, structure, or the like (eg, microelectronic device package 400). For example, the techniques described herein can be applied to multi- or multi-layer CTE adjustable interface materials 200 that are formed on a die, wafer, package, or other device.

Referring to Figure 1, a wafer-to-wafer process flow example is shown for ease of discussion; however, it can be applied to any carrier, die, package, substrate, interposer, panel, or other microelectronics. element. At (A), a carrier 102 is prepared to have a plurality of channels 104, such as a Through Silicon Via (TSV) or the like. At (B), one or more microelectronic components ("elements") 106 (eg, IC wafer dies or discrete electronic components) may be attached to the prepared channel side of carrier 102. At (C), a filler material 108 (eg, an encapsulation layer) is applied to the elements 106 and the carrier 102. In one example, the filler 108 can be planarized as necessary to prepare the top surface of the filler 108 for use in additional layers. In one example, a thin adhesive layer of the filler 108 can be maintained on the component(s) 106 for attaching the upper carrier 110.

At (D), the upper carrier 110 will be attached to the filler 108. In various examples, the upper carrier 110 can be added to process or protect the package 100. In one example, for example, when an element 106 includes an optical sensor, the upper carrier 110 will transmit light. At (E), the bottom surface of the carrier 102 will be removed (for example, by grinding) to expose the channel 104 on the bottom side of the carrier 102. A metal layer (not shown) will be added to the prepared bottom surface of the carrier 102 to electrically couple the elements 106 via the channels 104. A contact 112 (e.g., a solder bump) will be coupled to the desired portion of the metal layer(s).

As shown in Figure 1, the results in the figure produce a microelectronic component ("封封 Install") 100. In various embodiments, the package 100 can include additional devices (eg, interposer, multiple stacked components 106, . . . , etc.), or the package can contain fewer devices and still fall within the present disclosure. Within the scope.

2 and 3 are examples of particle impregnated filler materials (i.e., CTE adjustable interface material 200) having an adjustable coefficient of thermal expansion in accordance with various embodiments. As shown in FIGS. 2 and 3, the interface material 200 can be applied to the carrier 102 and the component(s) 106 in the same manner as the filler 108 described above with respect to FIG. For example, the carrier 102 and the component(s) 106 can be coated with an interface material 200. The interface material 200 can be coated with a polymer after solvent evaporation (eg, cyclobutene (BCB), polymethyl methacrylate (PMMA), epoxy based photoresist (eg, SU8), ring Oxygen resin, natural fiber composite (NFR), etc.). The interface material 200 can be planarized to achieve a flat surface for use in preparing the upper carrier layer 110. Further, the interface material 200 can be cured before or after application of various package 100 devices. In addition, an adhesive coating can also be applied to the installed upper carrier layer 110.

In various modes of operation, the interface material 200 is comprised of a filler material 108 having a first coefficient of thermal expansion (CTE) and a plurality of particles 202 comprising a material having a second CTE. The particles 202 will bond the filler material 108 in a predetermined spatial arrangement. In these modes of operation, the CTE of the composite interface material 200 is based on the number of particles 202 and the predetermined spatial arrangement. In some embodiments, the CTE of the composite interface material 200 is based on the size of the particles 202.

The figures of Figures 2 and 3 are the general spatial arrangement of the particles 202. In other embodiments, as shown below, the particles may be arranged in a predetermined arrangement to create the interface. The desired CTE of material 200. Further, as shown in the figures of Figures 2 and 3, in one embodiment, the particles 202 can have a wide variety of sizes and/or shapes. In other embodiments, as shown below, the particles may have a previously selected size and shape to produce the desired CTE of the interface material 200.

In an embodiment, the adjustable interface material 200 comprises a plurality of types of particles 202 comprising various materials having various CTEs. In this mode of operation, the plurality of types of particles 202 will bond the filler material 108 in various predetermined spatial arrangements to determine the desired CTE of the composite interface material 200. Accordingly, the CTE of the interface material 200 will be based on the CTE of the filler 108 and the CTE of the various particles 202, the number of the various particles 202, and the predetermined spatial arrangement of the various particles.

In various embodiments, the filler material 108 can comprise a polymer (eg, cyclobutene (BCB) or polymethyl methacrylate (PMMA)), an epoxy or an epoxy based photoresist ( For example, SU8), natural fiber composite (NFR), or the like. In various modes of implementation, the particles 202 may comprise inorganic materials (eg, glass, titanium oxide, carbon nanotubes, nanotubes, tungsten, etc.), organic materials (eg, fullerene, ...etc.), or the like. Further, the particles may be solid or hollow and may be substantially spherical, oval, prismatic, irregular, flake, film particles, or the like.

In some embodiments, as shown in FIG. 3, certain particles 202 may be larger than desired. In these embodiments, the larger particles 202 may be planarized by the interface material 200 to a desired height. In other embodiments, the particles 202 are not greater than (diameter, cross-section, or cut) 5 microns. In one example, the particles 202 have a normal distribution and have an average size of less than 5 microns. Further, in some embodiments, The particles 202 are nanoparticle and will not be larger than tens of nanometers or hundreds of nanometers. In one example, the particles 202 have a substantially uniform size, for example, a diameter or cross-sectional variation that falls within 20%.

4 illustrates an exemplary process for forming a microelectronic device package 400 in accordance with an embodiment. For the purposes of this disclosure, the package 400 is a package 100 plus an interface material 200 having an adjustable coefficient of thermal expansion. For example, the package 400 includes one or more microelectronic components 106 coupled to a common carrier 102 and an adjustable composite interface material 200 for encapsulating the microelectronic components 106, the adjustable Composite interface material 200 includes a filler material 108 having a first coefficient of thermal expansion (CTE) and a plurality of particles 202 comprising a material having a second CTE. When the particles 202 are bonded to the filler material 108 in a predetermined spatial arrangement, the CTE of the composite interface material 200 is based on the number of the particles 202 and the predetermined spatial arrangement.

At (A), the components 106 and the carrier 102 are encapsulated by the interface material 200. At (B), the interface material 200 (and, as the case may be, a portion of the elements 106) will planarize as desired. At (C), after an adhesive layer is applied to the planarized surface, an upper carrier 110 (eg, a carrier substrate) is attached to the planarized surface.

In various embodiments, the upper carrier 110 can be made of glass, tantalum, polycrystalline germanium, metallurgical silicon, tantalum carbide, carbon fiber-polyimine laminate, or the like. At (D), the upper carrier 110 will be planarized as necessary. At (E), the channels 104 are exposed by removing a portion of the underside of the carrier 102, and the metal layer(s) (not shown) will be applied to the carrier 102. On the underside that has been prepared, the contacts 112 will be coupled to the metal layer(s) and the packages will be cut. As shown in Figure 4, the result is a microelectronic component Package 400.

In a mode of implementation, the CTE of the composite interface material 200 is substantially identical to the CTE of the common carrier 102, the CTE of one or more of the microelectronic components 106, or the common carrier 102. And the CTE of one or more of the microelectronic elements 106. For the purposes of this disclosure, essentially the same CTE is no more than 10% difference.

Figure 5 shows an example of a 200 having an interface material having an adjustable coefficient of thermal expansion in accordance with another embodiment. In the embodiment shown in FIG. 5, the interface material 200 is a multilayer (502 to 508) composed of a polymer-reinforced sol-gel network. For example, the interface material 200 can comprise alternating gel layers (502 and 506) reinforced via alternating polymer layers (504 and 508) (for example, thicknesses of 10 to 20 microns) (for example The thickness can be 10 to 20 microns). The alternating layers may continue to alternate until the desired thickness of the interface material 200 is applied.

In one mode of operation, the individual layers (502 to 508) are applied separately and the polymer can be allowed to diffuse into the gel network prior to curing. The layered interface material 200 can be planarized and, if necessary, attached to an upper carrier plate 110 prior to curing. The polymer layers may include BCB, SU8, epoxy, PMMA, NFR, and the like.

In another embodiment, the adjustable composite interface material 200 comprises a plurality of layers, wherein each layer comprises a quantity of particles 202 that incorporate a filler material 108 in a predetermined spatial arrangement. In this mode of operation, the CTE of the composite interface material 200 is based on the number of the particles 202 in each layer, the size of the particles 202 in each layer, and the pre-forms of the particles 202 in each layer. Set the space arrangement as the basis.

6 and 7 illustrate an exemplary process for forming a package 400 having an adjustable interface material 200 comprising a plurality of layers (602 to 606). In an embodiment, as shown in FIG. 6, the elements 106 and the carrier 102 are encapsulated by a plurality of layers of different interface materials 200. In one embodiment, the elements 106 are adjacent to an underfill layer or passivation layer 608, and if necessary, the underfill layer or passivation layer 608 is interposed between the elements 106 and the carrier 102.

For example, in one embodiment, each of the plurality of layers (602 to 606) of interface material 200 has particles 202 of different average sizes. For example, in one of the layers (for example, 602), the average size of the particles 202 is greater than the average size of the particles 202 in the other layers (for example, 604 and 606). Further, in another layer (for example, 606), the average size of the particles 202 is less than the average size of the particles 202 in other layers (for example, 602 and 604).

In another embodiment, the layers (602 to 606) are arranged based on the average size of the particles 202 in the layer. In other words, the relative spatial position of a layer within the plurality of layers (602 to 606) is determined by the average size of the particles within the layer. In this embodiment, the CTE of the interface material 200 can be varied layer by layer.

In a further embodiment, the plurality of layers (602 to 606) are arranged in a gradient order according to the average size of the particles 202 in each layer (as suggested above), from maximum to minimum or from minimum to maximum. In this embodiment, the CTE of the interface material 200 is also varied in accordance with the gradient based on the CTE of each layer (602 to 606). For example, in an implementation, the plurality of layers (602 through 606) are arranged in a gradient arrangement such that the layers (602 through 606) having the largest particles 202 are closer to the common carrier 102 and have the smallest particles 202. The layers (602 to 606) will be farthest from the common carrier 102; vice versa.

Referring to Figure 6, at (A), the elements 106 and the carrier 102 are encapsulated by multiple layers (602 to 606) of different interface materials 200. At (B), the elements 106 and the carrier 102 are completely encapsulated by the plurality of layers (602 to 606). At (C), the multilayer interface material 200 will be planarized as necessary. At (D), an upper carrier plate 110 is attached and will also be planarized as necessary. At (E), the assembly 400 is ready for any further processing.

Referring to Figure 7, the elements 106 and the carrier 102 are encapsulated by multiple layers (602 to 606) of different interface materials 200 having particles 202 of different sizes, different materials, or different CTEs. At (A), the elements 106 and the carrier 102 are coated by the first layer 602 of the interface material 200. The carrier 102 having the first layer 602 can be agitated or vibrated prior to continuing the process to increase the density of the particles 202. At (B), the elements 106 and the carrier 102 are coated by the second layer 604 of the interface material 200. The carrier 102 having the first and second layers (602 and 604) can be agitated or vibrated prior to continuing the process to increase the density of the particles 202. At (C), the elements 106 and the carrier 102 are coated by a third layer 606 of the interface material 200. The carrier 102 having the first, second, and third layers (602 to 606) may be agitated or vibrated prior to continuing the process to increase the density of the particles 202. At (D), the layers (602 to 606) of the interface material 200 may be planarized as necessary. This component is ready for any subsequent processing steps.

In an embodiment, as shown in FIG. 8, the particles 202 of the interface material 200 may comprise nanoparticle. In one mode of operation, the particles 202 comprise nanoparticles of the micellar phase. In other modes of operation, other nanoparticles or particles 202 having a nanometer scale may be used alone or in combination with other particles 202 in the interface material 200.

In another mode of operation, as shown in FIGS. 9-11, the predetermined spatial arrangement of the particles 202 is arranged within the interface material 200, which includes one or more layers within the filler material 108. Particle 202 or region. For example, a uniform layer comprises a plurality of particles 202 of substantially uniform size. In other words, the particles 202 are arranged in multiple layers depending on the average size of the particles 202. The larger sized particles 902 are incorporated into a layer separate from the smaller sized particles 904 (the smaller sized particles 904 are arranged in a separate layer). For the purposes of this disclosure, a substantially uniform size is a particle size that differs by no more than 20%.

In other embodiments, the particles 202 may be disposed of the particles 202 within the filler 108 (which includes the average size of the particles 202, the material of the particles 202, the density of the particles 202 within the filler 108, and The shape of the particles 202, the CTE of the particles 202, the spatial arrangement of the particles 202, and the like are arranged in two or more regions. In an alternate embodiment, various such configurations of one or more particles 202 and one or more fillers 108 may be arranged to result in a desired CTE for each of the two or more regions. For example, each of the two or more regions may have a different CTE as desired.

In one embodiment, as shown in FIG. 9, multilayer particles 202 will be disposed within the filler material 108 such that a layer having larger particles 902 will be surrounded by a layer having smaller particles 904. As shown in Figure 9, this results in a more symmetrical particle 202 size profile in the arrangement of the class matrix.

In a further embodiment, as shown in Figure 10, the layers are arranged in a gradient arrangement within the filler material 108 such that the layer having the largest particles 902 (for example, one of the regions) is compared Close to the common carrier 102 and having a minimum particle 904 The layer (for example, another area) will be farthest from the common carrier 102. This results in a gradient of the size of the particle 202 in the arrangement of the class matrix. In some embodiments, this will also result in a gradient CTE profile within the interface material 200 based at least in part on the material of the particles 202.

For example, the CTE of one of the regions having the largest particle 902 can be determined in advance to have a CTE that is substantially identical to the CTE of the common carrier 102, while the CTE of another region having the smallest particle 904 can be determined in advance. It is a CTE having a CTE that is substantially identical to the microelectronic element 106. In this example, the CTEs of the regions may be an actual or relative number of particles (902, 904) in the regions, individual spatial arrangements of the particles (902, 904) in the regions, or the like. The basis to adjust (that is, configuration).

In one example, as shown in FIG. 10, an adhesive region 1002 can be formed or retained at the upper surface of the interface material 200 for bonding an upper carrier 110 as necessary. For example, the bonding region 1002 can be formed or left after planarization of the interface material, and can be relatively free of particles 202 in some cases.

In an embodiment, as shown in FIG. 11, the particles 202 can be of a hybrid type (902, 904, 1102). In this mode of operation, the interface material 200 can comprise another number of different particles 1102 comprising another material and having another CTE. The other particles 1102 can be combined with the filler material 108 in a predetermined spatial arrangement, similar to the particles 202. The different particles may be arranged in one or more layers separate from the number of particles (shown as 902 and 904 in this figure). In this mode of operation, the CTE of the composite interface material 200 is in the number of particles 202, one or more other quantities of other particles 1102, a predetermined spatial arrangement of the particles 202, and the one of the other particles 1102. Or more other preset spaces arranged as a base foundation.

In the example shown in FIG. 11, the interface material 200 comprises spherical (902, 904) and non-spherical (1102) particles 202. In one embodiment, the larger bottom particles 904 may be comprised of tantalum, tantalum carbide, aluminum, or the like. The topmost particles 1102 may be composed of a thin sheet or a thin layer-like structure (as in mica, some carbon, graphite, ..., etc.).

In various embodiments, the adhesive layer 1002 can be formed or retained at the topmost layer of the interface material 200 after planarization, if necessary. For example, the adhesive layer can include a minimum of particles (for example, a cross section of less than 1 micron and a facet of less than 0.05 microns).

12 is a flow diagram of an exemplary process 1200 for forming a CTE adjustable interface material (eg, CTE adjustable interface material 200) in accordance with various modes of operation. The block of Figure 12 will refer to the CTE adjustable interface material shown at Figures 2-11.

At a block 1202, the process includes providing a filler material (eg, filler material 108) for encapsulating the microelectronic component having a first coefficient of thermal expansion (CTE).

At a block 1204, the process includes combining a predetermined number of particles (eg, particles 202) in a predetermined spatial arrangement (the particles include a material having a second CTE) and the filler material to form a Adjusted composite interface material. In one mode of operation, the process includes arranging particles positioned within the filler material into a plurality of layers based on the size and/or shape of the particles. In another mode of operation, the process includes arranging the particles in the interface material in a random arrangement. In a further embodiment, the particles may be substantially evenly distributed throughout the interface material.

At a block 1206, the process includes the number of particles and the plurality of particles The spatial arrangement of the particles is based on determining the CTE of the composite interface material. In various embodiments, the process includes adjusting or adjusting the CTE of the interface material based on adjusting the number of particles and/or the spatial arrangement of the particles.

In one implementation, the process includes forming a microelectronic component (eg, package 400) by coupling one or more microelectronic components (eg, component 106) to a common carrier substrate layer (eg, The carrier board 102) adjusts the CTE of the composite interface material to substantially the same CTE of the common carrier, the CTE of one or more of the microelectronic components, or the common carrier and the micro a CTE of one or more microelectronic elements in the electronic component; and utilizing the composite interface material to encapsulate the one or more microelectronic components.

In one implementation, the process includes combining one or more other numbers of other particles (eg, particles 1102) in one or more other predetermined spatial arrangements (which include one or more other One or more other materials of the CTE) and the filler material to form the adjustable composite interface material; and the number of the particles, the one or more other numbers of other particles, the spatial arrangement, and The one or more other spatial arrangements are used to determine the CTE of the composite interface material.

In one mode of operation, the process includes forming a plurality of layers, each layer comprising a quantity of particles bonded to a filler material in a predetermined spatial arrangement. Further, the process includes determining the composite interface material based on the number of the particles in each layer, the size of the particles in each layer, and the spatial arrangement of the particles in each layer. CTE. In one embodiment, the process includes arranging the plurality of layers in a relative spatial order based on the average size of the particles in the layers.

Different configurations of the CTE adjustable composite interface material 200 can be utilized Different ways of implementation to achieve. Various alternative combinations and designs of the interface material 200 are also within the scope of the present disclosure in alternative implementations. The elements of these variations may be fewer than the number of elements illustrated in the examples shown in Figures 1 through 11, or they may have more or alternative elements than those shown.

The order in which the processes are described herein is not intended to be limiting, and any number of process blocks in the described process blocks can be combined in any order to perform the processes or alternative processes. In addition, individual blocks can also be deleted from the processes without departing from the spirit and scope of the main content described herein. Furthermore, the processes can be carried out in any suitable material or a combination thereof without departing from the scope of the main content described herein. In alternative implementations, other techniques may be incorporated in various combinations in such processes, and are still within the scope of the present disclosure.

in conclusion

The manner in which the present disclosure has been described in the context of structural features and/or method-specific actions has been described herein; however, it should be understood that such implementations are not necessarily limited to the described features or actions. Rather, the specific features and acts are disclosed herein as representative forms of example devices and techniques.

102‧‧‧ Carrier Board

104‧‧‧ channel

106‧‧‧Microelectronic components (components)

108‧‧‧Filling materials

200‧‧‧Current expansion coefficient (CTE) adjustable interface material

202‧‧‧ granules

Claims (24)

An adjustable composite interface material for encapsulating a microelectronic component, comprising: a filler material having a first coefficient of thermal expansion (CTE); and a quantity of particles comprising a material having a second CTE, The filler material is bonded in a predetermined spatial arrangement, the CTE of the composite interface material being based on the number of the particles and the predetermined spatial arrangement. The adjustable composite interface material of claim 1 further comprising one or more other numbers of other particles comprising one or more other materials having one or more other CTEs, The filler material is bonded in one or more other predetermined spatial arrangements, the CTE of the composite interface material being arranged in the number of the particles, the one or more other numbers of the other particles, the predetermined spatial arrangement And the one or more other spatial arrangements are based. The adjustable composite interface material according to claim 1 further comprising a plurality of layers, each layer comprising a certain number of particles combined with a filler material in a predetermined spatial arrangement, the CTE of the composite interface material being The number of such particles in each layer, the size of the particles in each layer, and the predetermined spatial arrangement of the particles in each layer are based. An adjustable composite interface material according to claim 3, wherein the relative spatial position of a layer within the multilayer is determined by the average size of the particles within the layer. An adjustable composite interface material according to claim 3, wherein the multilayer is arranged in a gradient order according to an average size of particles in each layer, from maximum to minimum or from minimum to maximum. The adjustable composite interface material of claim 1, wherein the composite interface material comprises one or more layers of a gel network. The adjustable composite interface material according to claim 1, wherein the predetermined spatial arrangement comprises a uniform layer of one or more particles in the filler material, wherein a uniform layer comprises a substantially uniform size particle. The adjustable composite interface material according to claim 1, wherein the particles have a diameter or a cross section of 5 microns or less. The adjustable composite interface material according to claim 1, wherein the particles comprise nanoparticle. A microelectronic assembly comprising: a common carrier substrate layer; one or more microelectronic components coupled to the common carrier; and an adjustable composite interface material for encapsulating the microelectronic components And comprising: a filler material having a first coefficient of thermal expansion (CTE); and a quantity of particles comprising a material having a second CTE that will bond the filler material in a predetermined spatial arrangement, The CTE of the composite interface material is based on the number of such particles and the predetermined spatial arrangement. The microelectronic assembly of claim 10, wherein the CTE of the composite interface material is substantially identical to the CTE of the common carrier, the CTE of one or more of the microelectronic components, or the A common carrier and a CTE of one or more of the microelectronic components. The microelectronic assembly of claim 10, wherein the predetermined spatial arrangement comprises a uniform layer of one or more particles within the filler material, wherein a uniform layer comprises particles of substantially uniform size. The microelectronic assembly of claim 12, further comprising another quantity of different particles comprising another material having another CTE that will bond the filler material in a predetermined spatial arrangement, the differences The particles are arranged in one or more layers separate from the number of particles comprising the material having the second CTE. The microelectronic assembly of claim 12, wherein the layers are arranged in the filler material such that a layer having larger particles is surrounded by a layer having smaller particles. The microelectronic assembly of claim 12, wherein the layers are arranged in a gradient arrangement within the filler material such that the layer having the largest particles is closer to the common carrier and has a minimum particle size The layer will be farthest from the common carrier. The microelectronic assembly of claim 10, wherein the one or more microelectronic components are taken from a group comprising: an integrated circuit (IC) wafer, a plurality of IC wafers Stacking and a discrete electronic device. A method comprising: providing a filler material for encapsulating a microelectronic component, the filler material having a first coefficient of thermal expansion (CTE); combining a predetermined amount of particles and the filler material in a predetermined spatial arrangement And forming an adjustable composite interface material, the predetermined number of particles comprising a material having a second CTE; and determining a CTE of the composite interface material based on the number of the particles and the spatial arrangement. The method of claim 17, further comprising: coupling one or more microelectronic components to a common carrier substrate; adjusting a CTE of the composite interface material to substantially the same CTE of the common carrier, Some of these a CTE of one or more microelectronic elements in the microelectronic component or a CTE of the common carrier and one or more of the microelectronic components; and encapsulating the composite using the composite interface material Or more microelectronic components. The method of claim 17, further comprising arranging particles positioned within the filler material into a plurality of particles according to the size and/or shape of the particles. The method of claim 17, further comprising combining one or more other numbers of other particles with the filler material in one or more other predetermined spatial arrangements to form the adjustable composite An interface material, the one or more other numbers of other particles comprising one or more other materials having one or more other CTEs; and the one or more others of the number of such particles, other particles The CTE of the composite interface material is determined based on the number, the spatial arrangement, and the one or more other spatial arrangements. The method of claim 17, further comprising forming a plurality of layers, each layer comprising a certain number of particles combined with a filler material in a predetermined spatial arrangement, and the number of the particles in each layer The CTE of the composite interface material is determined based on the size of the particles in each layer and the spatial arrangement of the particles in each layer. The method of claim 21, further comprising arranging the plurality of layers in a relative spatial order based on an average size of the particles in the layers. An adjustable composite encapsulation layer comprising: a first region comprising a first configuration of one or more particles and one or more fillers having particles in the first configuration a combined first thermal expansion coefficient (CTE) based on a filler; and a second region comprising one or more particles and one or more fillers A second configuration having a combined second CTE based on the particles and the filler of the second configuration, the second CTE being different from the first CTE. The adjustable composite encapsulation layer of claim 23, wherein the adjustable composite encapsulation layer encapsulates a microelectronic component coupled to a carrier substrate layer, and wherein the first region Adjacent to the microelectronic element and having a CTE substantially identical to the CTE of the microelectronic element, and the second region being adjacent to the carrier base layer and having a CTE substantially identical to the CTE of the carrier base layer .