TW201624768A - Method for manufacturing opto-electronic device with light emitting diodes - Google Patents

Abstract

The invention relates to a method of manufacturing optoelectronic devices including the successive steps of: providing a substrate (10) including a first surface; forming, on the first surface, assemblies of light-emitting diodes including wire-shaped, conical, or tapered semiconductor elements; covering the entire first surface of a layer (40) encapsulating the light-emitting diodes; decreasing the substrate thickness; and sawing the obtained structure to separate each assembly of light-emitting diodes.

Description

Method for manufacturing an optoelectronic device having a light emitting diode

The invention generally relates to a photovoltaic device based on the manufacture of a semiconductor material Methods. More specifically, the present invention relates to a method of fabricating a photovoltaic device comprising a light-emitting diode, wherein the light-emitting diode is formed of a three-dimensional element, particularly a semiconductor micron thin wire or a nanowire.

The phrase "optoelectronic device with light-emitting diode" means electrical A device that converts a signal into electromagnetic radiation, and in particular a device that is dedicated to emitting electromagnetic radiation, in particular light. Examples of the three-dimensional element that can form the light-emitting diode are micron thin wires and nanowires including a compound semiconductor material, mainly including at least one Group III element and one Group V element (for example, gallium nitride GaN) (hereinafter referred to as It is a group III-V compound) or mainly includes at least one Group II element and one Group VI element (for example, zinc oxide ZnO) (hereinafter referred to as a Group II-VI compound).

Three-dimensional components, especially semiconductor micron thin wires or nanowires, one Typically formed on a substrate, followed by sawing to define individual optoelectronic devices. Each optoelectronic device is then placed in the package, especially to protect Protect these three-dimensional components. The package is then attached to a support, such as a printed circuit board.

The disadvantage of this optoelectronic device manufacturing method is that it must be for each The photovoltaic device independently performs the step of protecting the three-dimensional semiconductor component. In addition, the volume of the package is more pronounced than the active area of the optoelectronic device including the light-emitting diode.

Accordingly, it is an object of the specific embodiments to at least partially overcome the A disadvantage of the above-described photovoltaic device of a photodiode (especially having micron thin wires or nanowires).

Another object of the specific embodiment is to abolish the inclusion of the light-emitting diode Individual protective packages for optoelectronic devices.

Another object of the specific embodiment is that it can be industrial scale and low Photoelectric devices comprising a light-emitting diode made of a semiconductor material are originally manufactured.

Accordingly, a specific embodiment provides a method for fabricating an optoelectronic device comprising the following sequential steps: (a) providing a substrate having a first surface; (b) forming a thin line on the first surface, a light emitting diode assembly of a conical or tapered semiconductor component; (c) forming an electrode layer and a conductive layer for each of the light emitting diode components, the electrode layer covering each of the light emitting diodes of the component, the conducting a layer covering the electrode layer around the light emitting diode of the component; (d) covering an entire first surface of a layer encapsulating the light emitting diode; (e) reducing the thickness of the substrate, the substrate having a second surface opposite the first surface after step (e); (f) forming a conductive element that is insulated from the substrate and completely crossed from the second surface Substrate to at least the first surface, the conductive element is in contact with the conductive layer; (g) forming at least one first conductive spacer on the second surface in contact with the substrate; and (h) obtained by sawing Structure to separate each LED assembly.

According to a particular embodiment, the method includes forming at least one second conductive shim in contact with the conductive element on the second surface in step (f).

According to a particular embodiment, the method includes forming at least one additional conductive element insulated from the substrate and completely over the substrate from the second surface to at least the first surface, and with at least one of the light emitting diodes Base contact.

According to a specific embodiment, the forming the conductive element continuously includes: after the step (e), etching an opening from the second surface in the substrate, forming an insulating layer on at least a lateral wall portion of the opening, and Forming a conductive layer covering one of the insulating layers or filling the opening with a conductive material.

According to a specific embodiment, the forming the conductive element comprises: etching an opening from the first surface in the substrate before the step (b), crossing a portion of the thickness of the substrate, the opening being open after the thinning step of the substrate The second surface.

According to a particular embodiment, the electrode layer and the conductive layer are further formed in the opening.

According to a specific embodiment, the method comprises: before step (b), to An insulating portion is formed on the lateral wall portion of the opening and filled with a conductive material.

According to a particular embodiment, in step (e), the substrate is completely removed.

According to a particular embodiment, the method further includes depositing, for each of the light emitting diode assemblies, at least one conductive layer in contact with a base of the diode of the component.

According to a particular embodiment, the method comprises the step of attaching a pedestal to the layer encapsulating the luminescent diode prior to step (e).

According to a particular embodiment, the layer encapsulating the light emitting diode comprises a phosphor between the light emitting diodes.

According to a particular embodiment, the method includes the step of forming a phosphor layer covering the layer enclosing the light emitting diode or covering the support.

According to a specific embodiment, the method includes the step of forming a layer between the layer encapsulating the light emitting diode and the phosphor layer, the layer transmitting light emitted by the light emitting diode and reflecting The light emitted by the phosphor.

According to a specific embodiment, the method includes, between the substrate and the layer encapsulating the light emitting diode, at a height of 50% greater than a height of the light emitting diode around the light emitting diode The step of forming a reflector.

DEL‧‧‧Light Emitting Diode

10‧‧‧ Wafer/Substrate

12‧‧‧ dotted line

14‧‧‧Optoelectronic devices

22‧‧‧ Surface

24‧‧‧ seeding gasket

26‧‧‧ Thin line

28‧‧‧The lower part of the thin line

30‧‧‧ upper part of the thin line

32‧‧‧Insulation

34‧‧‧ shell

36‧‧‧First electrode/first electrode layer

38‧‧‧Transmission layer

40‧‧‧Encapsulation layer

42‧‧‧ handle

43‧‧‧ surface

44‧‧‧ surface

45‧‧‧Insulation

46‧‧‧ openings

48‧‧‧Insulation

50‧‧‧ openings

52‧‧‧second electrode

54‧‧‧Transmission layer

56‧‧‧Vertical connection

60‧‧‧ Conductive gasket

62‧‧‧Insulation

64‧‧‧ openings

66‧‧‧second electrode

68‧‧‧Insulation

70‧‧‧ openings

72‧‧‧Bumps

74‧‧‧ seed layer

76‧‧‧Vertical connection

80‧‧‧metal layer

82‧‧‧Metal parts

84‧‧‧Metal parts

86‧‧‧Insulation

88‧‧‧second electrode

90‧‧‧ Conductive gasket

91‧‧‧TSV

92‧‧‧ openings

94‧‧‧Insulation

96‧‧‧ openings

98‧‧‧TSV

100‧‧‧Support

102‧‧‧Connecting gasket

104‧‧‧Connecting gasket

106‧‧‧TSV/vertical connection

110‧‧‧Vertical connection

120‧‧‧ openings

122‧‧‧ openings

124‧‧‧Partial filling material

125‧‧‧ openings

126‧‧‧Insulation

128‧‧‧ openings

130‧‧‧ openings

132‧‧‧ Conductive gasket

134‧‧‧ Conductive gasket

136‧‧‧Insulation

138‧‧‧ openings

140‧‧‧ openings

142‧‧‧second electrode

144‧‧‧ Conductive gasket

145‧‧‧TSV

150‧‧‧Back surface of the structure

152‧‧‧ openings

154‧‧‧ mirror layer

156‧‧‧Transmission layer

158‧‧‧shims

160‧‧‧Part mirror layer

162‧‧‧Partial conductive layer

164‧‧‧shims

166‧‧‧Part mirror layer

168‧‧‧Partial conductive layer

170‧‧‧Insulation

172‧‧‧ openings

174‧‧‧ openings

176‧‧‧Transmission layer

178‧‧‧ Conductive gasket

180‧‧‧second electrode

182‧‧‧Transmission section

190‧‧‧Optoelectronic devices

192‧‧‧Optoelectronic devices

194‧‧‧ Groove

196‧‧‧ sawing line

198‧‧‧ Groove

200‧‧‧ surrounding parts

202‧‧‧Insulation section

205‧‧‧Optoelectronic devices

206‧‧‧Fluorescent layer

208‧‧‧ glue layer

210‧‧‧Optoelectronic devices

215‧‧‧Optoelectronic devices

216‧‧‧ Groove

220‧‧‧Optoelectronic devices

222‧‧‧Intermediate

224‧‧‧The surface of the encapsulation layer

226‧‧‧ interface

228‧‧‧ Surface of the phosphor layer

230‧‧‧Optoelectronic devices

232‧‧‧ Block

234‧‧‧metal layer

236‧‧‧ lateral edges

240‧‧‧Optoelectronic devices

242‧‧‧ Block

244‧‧‧ lateral edges

245‧‧‧Optoelectronic devices

246‧‧‧ cavity

248‧‧‧ lateral side

250‧‧‧Insulation

252‧‧‧metal layer

255‧‧‧Optoelectronic devices

256‧‧‧ Groove

260‧‧‧Optoelectronic devices

262‧‧‧ Groove

264‧‧‧Central Block

266‧‧‧ surrounding blocks

268‧‧‧metal layer

269‧‧‧ glue layer

270‧‧‧ lateral side

275‧‧‧Optoelectronic devices

276‧‧‧Insulation

278‧‧‧reflective layer

280‧‧‧ surface of the reflective layer

285‧‧‧Optoelectronic devices

286‧‧‧reflective layer

288‧‧‧The surface of the reflective layer

290‧‧‧Optoelectronic devices

292‧‧‧Convergence lens

295‧‧‧Optoelectronic devices

296‧‧‧ lens

The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of the specific embodiments, in which: 1 is a partially simplified top plan view of an example of a semiconductor substrate wafer having a plurality of photovoltaic devices, wherein the plurality of photovoltaic devices are formed with micron thin wires or nanowires; and FIGS. 2A through 2F are included for use in manufacturing. Partially simplified cross-sectional view of a structure obtained in a continuous step of a method of optoelectronic device of micron fine lines or nanowires; Figures 3A and 3B are diagrams of another method for fabricating an optoelectronic device comprising micron thin wires or nanowires A partially simplified cross-sectional view of the structure obtained in a sequential step of a specific embodiment; FIGS. 4 and 5 are structures obtained in successive steps of another embodiment of a method for fabricating an optoelectronic device comprising micron thin wires or nanowires Partially simplified cross-sectional view; FIGS. 6A to 6C are partially simplified cross-sectional views of the structure obtained in a continuous step of another embodiment of a method for fabricating an optoelectronic device including micron thin wires or nanowires; FIGS. 7A and 7B are a partially simplified cross-sectional view of the resulting structure in a sequential step of another embodiment of a method for fabricating an optoelectronic device comprising micron thin wires or nanowires; 8 to 10 are partially simplified cross-sectional views of the structure obtained in successive steps of another specific embodiment of a method for manufacturing a photovoltaic device including micron thin wires or nanowires; and Figs. 11A to 11D are for use in manufacturing A further simplified cross-sectional view of a structure obtained in a continuous step in another embodiment of a method comprising a photovoltaic device of micron thin wires or nanowires; 12A through 12E are partially simplified cross-sectional views of the structure obtained in a continuous step of another embodiment of a method for fabricating an optoelectronic device including micron thin wires or nanowires; and Fig. 13 is included before sawing the substrate A partially simplified cross-sectional view of a specific embodiment of a photovoltaic device of micron thin wires or nanowires formed on a substrate wafer; Fig. 14 is a partially simplified top view of the photovoltaic device of Fig. 13; and Figs. 15 to 27 A partially simplified cross-sectional view of a particular embodiment of an optoelectronic device comprising micron or nanowires.

For the sake of clarity, the same elements are denoted by the same element symbols in the various figures, and in addition, as is generally the case for electronic circuits, the various figures are not actual dimensions. Moreover, only those elements that are illustrated and will be described for understanding the present invention will be described. In particular, the optoelectronic device control device described hereinafter is within the capabilities of those skilled in the art to which the invention pertains, and thus will not be described.

In the following description, terms such as "substantially", "probably" and "in the rank of" mean "within 10%" unless otherwise specified. Further, "a compound mainly formed of a material" or "a material base compound" means a compound including a ratio of the material of 95% or more, and the ratio is preferably more than 99%.

The present invention relates to optoelectronic devices comprising three-dimensional elements such as micron thin wires, nanowires, tapered elements or conical elements. In the following description, A specific embodiment of an optoelectronic device comprising micron thin wires or nanowires is illustrated. However, these specific embodiments can also be implemented on three-dimensional elements other than micron thin wires or nanowires, such as pyramidal three-dimensional elements.

The term "micron thin line" or "nano thin line" refers to an option a three-dimensional structure having an elongated shape in a direction having at least two dimensions (referred to as a minor dimension) in the range of 5 nm to 2.5 μm, preferably in the range of 50 nm to 2.5 μm The third dimension (referred to as the primary dimension) is at least equal to 1 time, preferably at least 5 times, and more preferably at least 10 times the longest secondary dimension. In some embodiments, the minor dimension is less than or approximately equal to 1 micron, preferably in the range of from 100 nanometers to 1 micrometer, and more preferably in the range of from 100 nanometers to 300 nanometers. In some embodiments, the height of each micron or nanowire may be greater than or equal to 500 nanometers, preferably in the range of 1 micrometer to 50 micrometers.

In the following description, the term "thin line" is used to mean "micron fine" Line or nano thin line." Preferably, the average line body of the center of gravity of the thin line passing through the cross section (in a plane perpendicular to the preferred direction of the thin line) is substantially linear, and is hereinafter referred to as the "axis" of the thin line.

1 is a simplified top view of a portion of a wafer 10 of a semiconductor substrate, Thin lines are formed on the wafer 10. By way of illustration, it is a single crystal germanium wafer having an initial thickness in the range of 500 microns to 1500 microns (eg, about 725 microns) and a diameter in the range of 100 mm to 300 mm (eg, about 200 mm). Advantageously, it is a germanium wafer currently used in microelectronic circuit fabrication methods, particularly metal oxide field effect transistors or metal oxide semiconductor (MOS) transistors. As a variant, any microelectronics manufacturer can be used Other single crystal semiconductors that are compatible with the process, such as germanium. Preferably, the semiconductor substrate can be doped to reduce the resistivity of the substrate to an acceptable level of series resistance of the light emitting diode and to a resistivity close to the metal resistivity, preferably less than a few milliohms - Centimeters (mohm.cm).

A plurality of optoelectronic devices 14 including light emitting diodes are simultaneously formed On the wafer 10. The dotted line 12 shows an example of the separation restriction between the photovoltaic devices 14. The number of light emitting diodes may vary depending on the optoelectronic device 14. Optoelectronic device 14 occupies portions of wafer 10 having different surface areas. Optoelectronic device 14 is separated by the step of sawing wafer 10 along a sawing path as indicated by line 12.

According to a specific embodiment, including a three-dimensional element (especially a semi-conductive The manufacturing method of the light-emitting diode photo-electric device 14 formed by the thin body line comprises the steps of: forming a light-emitting diode of the photovoltaic device on the first surface of the wafer 10; protecting the light-emitting diode assembly with the encapsulation layer; A light-emitting diode for each of the photovoltaic devices is formed on the side opposite the encapsulation layer for biasing the contact pads; and the wafer 10 is sawed to separate the photovoltaic devices.

The encapsulation layer protects the light emitting diode during the contact pad formation step, And it remains after the optoelectronic device has been separated. The encapsulation layer continues to protect the light-emitting diodes after the substrate has been sawed, so that after the optoelectronic device has been separated, there is no need to provide a protective package for the light-emitting diodes attached to the device for each of the optoelectronic devices. The volume of the photovoltaic device can be reduced.

In addition, the step of protecting the light emitting diode of the photovoltaic device 14 is by The thin wire is encapsulated in an encapsulation layer that is deposited entirely on the wafer 10 prior to the step of sawing the wafer 10. This step can therefore be performed only once for all optoelectronic devices 14 formed on the wafer 10, thus reducing each The manufacturing cost of an optoelectronic device.

Therefore, the encapsulation is after the micron thin wire or nanowire manufacturing step Executed on a wafer scale. This wafer-scale collective encapsulation reduces the number of steps dedicated to encapsulation, thereby reducing encapsulation costs. In addition, the surface area of the finally encapsulated optoelectronic component will be approximately the same as the area of the active area of the illuminated wafer, which can reduce the size of the optoelectronic component.

2A to 2F are specific examples of the manufacturing method of the photovoltaic device A partially simplified cross-sectional view of a structure corresponding to an optoelectronic device obtained in a continuous step, which is formed, for example, as described above, and which emits electromagnetic radiation. Figs. 2A to 2F correspond to one of the photovoltaic devices formed on the substrate 10.

Figure 2A illustrates a structure including (from the top to the bottom in FIG. 2A): 22 includes an upper surface of the semiconductor substrate 10; promoting seed pad 22 on the surface 24 of the thin line growth and arrangement; a height H of _a thin line 26 (two are shown), each of the thin wires 26 is in contact with one of the seeding pads 24, each of the thin wires 26 including a contact with the seeding pad 24, a height H _{2 lower} portion 28, and a subsequent a lower portion 28 having a height H ₃ upper portion 30; an insulating layer 32 extending over the surface 22 of the substrate 10 and lateral sides of the lower portion 28 of each of the thin wires 26; including a semiconductor layer stack structure covering each of the upper portions 30 A shell layer 34; a first electrode layer 36 covering each of the shell layers 34 and further extending over the insulating layer 32; and a conductive layer 38 covering the electrode layer 36 between the thin lines 26 but not extending over the thin lines 26.

Components formed by each of the thin wires 26, associated seeding spacers 24 The shell layer 34 forms a light-emitting diode DEL. Base pair of diode DEL The spacer 24 should be seeded. The shell layer 34 in particular comprises an active layer which is a layer which emits electromagnetic radiation transmitted by most of the light-emitting diodes DEL.

The substrate 10 corresponds to a one-piece structure, or corresponds to a cover by another material One layer of the support made of material. For example, substrate 10 is a semiconductor substrate, preferably a semiconductor substrate that is compatible with the fabrication methods implemented in the microelectronics industry, such as substrates made of tantalum, niobium, or alloys of these compounds. The substrate is doped, so the substrate resistivity will be less than a few milliohms.

Preferably, the substrate 10 is a semiconductor substrate such as a germanium substrate. Substrate The 10 series is doped with a first conductivity type, such as an N-type dopant. Surface 22 of substrate 10 can be a <100> surface.

The seeding spacer 24, also referred to as a seed crystal island, is formed by the promotion thin line 26 Made of long material. As a variant, the seed mask 24 can be replaced with a seed layer covering the surface 22 of the substrate 10. In the case of a seeding spacer, a treatment is further provided to protect the lateral edges of the seeding spacer and the surface of the portion of the substrate that is not covered by the seeding spacer to avoid lateral side portions of the seeding spacer And growing thin lines on the surface of the portion of the substrate that is not covered by the seed crystal spacer. The processing includes forming a dielectric region on a lateral side of the seeding pad, the dielectric region extending over and/or inside the substrate, and a pad in the pair of pads for each pair of pads The sheet is attached to another spacer in the pair and there is no thin line growth on the dielectric region.

By way of illustration, the material forming the seed spacer 24 may be a nitride, carbide or boride of a transition metal in rows IV, V or VI of the Periodic Table of the Elements, or a combination of these compounds. By way of illustration, the seed mask 24 may be composed of aluminum nitride (AlN), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN). ), Hf, HfN, Nb, NbN, Zr, ZrB ₂ , ZrN, Zr , tantalum carbonitride (TaCN), magnesium nitride having a form of Mg _x N _y (where x is approximately equal to 3 and y is approximately equal to 2, such as magnesium nitride in the form of Mg ₃ N ₂ ), or gallium magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN), or a combination thereof.

The seed spacer 24 is doped with the same conductivity type or opposite conductivity type as the substrate 10.

The insulating layer 32 is made of a dielectric material such as hafnium oxide (SiO ₂ ), tantalum nitride (Si _x N _y , where x is approximately equal to 3 and y is approximately equal to 4, such as Si ₃ N ₄ ), and aluminum oxide ( Al ₂ O ₃ ), cerium oxide (HfO ₂ ) or diamond. By way of illustration, the thickness of the insulating layer 32 is in the range of from 5 nanometers to 800 nanometers, for example equal to about 30 nanometers.

The thin lines 26 are formed based at least in part on at least one semiconductor material. The semiconductor material can be tantalum, niobium, tantalum carbide, a III-V compound, a II-VI compound, or a combination of these compounds.

The thin line 26 is at least partially formed of a semiconductor material, and mainly includes a III-V compound such as a III-N compound. Examples of the Group III element include gallium (Ga), indium (In), or aluminum (Al). Examples of the III-N compound are GaN, AlN, InN, InGaN, AlGaN, or AlInGaN. Other Group V elements such as phosphorus or arsenic may also be used. In general, the elements in the III-V compound can be combined in different molar ratios.

The thin lines 26 are formed based, at least in part, on the semiconductor material, and include primarily Group II-VI compounds. Examples of Group II elements include Group IIA elements, particularly beryllium (Be) and magnesium (Mg), and Group IIB elements, especially zinc (Zn) and Cadmium (Cd). Examples of Group VI elements include Group VIA elements, particularly oxygen (O) and tellurium (Te). Examples of the II-VI compound are ZnO, ZnMgO, CdZnO or CdZnMgO. In general, the elements in the II-VI compound are combined in different molar ratios.

The thin line 26 can include a dopant. As an example, the III-V compound In general, the dopant is from a P-type dopant including Group II (for example, Mg Mg, zinc Zn, cadmium Cd, or mercury Hg), a Group D P-type dopant (for example, carbon C) or Group IV. A group of N-type dopants (for example, 矽Si, 锗Ge, selenium Se, sulfur S, 鋱Tb, or tin Sn) is selected.

The cross section of the thin line 26 may have a different shape, such as an ellipse, a circle or a polygon, in particular a triangle, a rectangle, a square or a hexagon. Therefore, it should be understood that the "diameter" mentioned in the description relating to the thin line or the section of the layer deposited on the thin line refers to the magnitude associated with the surface area of the target structure in this section, corresponding to, for example, having The diameter of the dish with the same surface area as the thin line section. The average diameter of each of the thin wires 26 is in the range of 50 nm to 2.5 μm. The height H ₁ of each of the thin wires 26 is in the range of 250 nm to 50 μm.

Each of the thin wires 26 has a semiconductor structure that is elongated along an axis D that is substantially perpendicular to the surface 22. Each of the thin wires 26 has a substantially cylindrical shape.

The axes of the two thin lines 26 are from 0.5 micrometers to 10 micrometers apart, and preferably from 1.5 micrometers to 4 micrometers. As an illustration, the thin lines 26 are regularly distributed. By way of illustration, the thin lines 26 are distributed as a hexagonal network.

By way of illustration, the lower portion 28 of each of the thin wires 26 is formed primarily of a III-N compound (e.g., gallium nitride) having a dopant of the first conductivity type (e.g., ruthenium). A lower portion 28 extending for a height H _2, H ₂ is a height in the range 100 nm to 25 microns.

By way of illustration, the upper portion 30 of each of the thin wires 26 is at least partially made of a III-N compound, such as GaN. The upper portion 30 can be doped to a first conductivity type or not deliberately doped. The upper portion 30 extends up to a height H _3, the height H ₃ is in the range 100 nm to 25 microns.

In the example where the thin line 26 is mainly made of GaN, the thin line 26 The crystal structure may be a wurtzite crystal form, and the fine lines extend along the axis C. The crystal structure of the thin line 26 may also be cubic.

The shell layer 34 may include an active layer covering the upper portion 30 of the associated thin line 26. A stacked structure with a bonding layer between the active layer and the electrode 36.

The active layer is for emitting most of the electrodes transmitted by the light-emitting diode DEL a layer of radiation. According to one example, the active layer includes confined elements, such as multiple quantum wells, such as a GaN layer having a thickness between 5 and 20 nanometers (eg, 8 nanometers) and a thickness between 1 and 10 nanometers (eg, 2.5 nanometers). The InGaN layers are alternately formed. The GaN layer may be doped, for example, having an N-type or a P-type. According to another example, the active layer comprises a single layer of InGaN, for example having a thickness greater than 10 nanometers.

The bonding layer is a stacked structure corresponding to a semiconductor layer or a semiconductor layer. And a P-N or P-I-N junction may be formed with the active layer and/or the upper portion 30. It can inject holes into the active layer via electrodes 36. The stacked structure of the semiconductor layer includes an electron blocking layer and an additional layer for providing good electrical contact between the electrode 36 and the active layer. The electron blocking layer is made of a ternary alloy such as gallium nitride aluminum ( AlGaN) or indium aluminum nitride (AlInN), electron barrier layer and active layer And an additional layer contact; the additional layer is made of, for example, gallium nitride (GaN) and is in contact with the electron blocking layer and in contact with the electrode 36. The bonding layer can be doped to a conductivity type opposite to the upper portion 30, such as a P-type dopant.

The electrode 36 is capable of biasing the active layer of each of the thin wires 26 and enabling the hair The electromagnetic radiation emitted by the photodiode DEL passes. The material forming the electrode 36 is a transparent conductive material such as indium tin oxide (ITO), aluminum zinc oxide or graphene. By way of illustration, electrode 36 has a thickness in the range of 10 nm to 150 nm, depending on the desired wavelength of illumination.

The conductive layer 38 is a single layer, or a stack structure corresponding to two or more layers. The conductive layer 38 can further at least partially reflect the radiation emitted by the light emitting diode DEL. By way of illustration, the conductive layer 38 corresponds to a single metal layer. According to another example, the conductive layer 38 corresponds to a layer stack structure, for example comprising a metal layer covered with a dielectric layer or covered with a plurality of dielectric layers. The metal layer of conductive layer 38 is formed on the bonding layer, such as titanium. By way of illustration, the conductive metal layer forming material layer 38 (monolayer or multilayer) can be aluminum, aluminum-based alloys (particularly AlSi _z, Al _x Cu _y (e.g., x equals 1 and y equals 0.8%)) , silver, gold, nickel, chromium, ruthenium, osmium, palladium, or an alloy of two of these compounds, or an alloy of two or more of these compounds. By way of illustration, the conductive layer 38 (single or multilayer) has a thickness in the range of from 100 nanometers to 2000 nanometers.

A specific embodiment of the manufacturing method for providing the structure shown in FIG. 2A includes the following steps:

(1) A seed spacer 24 is formed on the surface 22 of the substrate 10.

The seed spacer 24 can be, for example, chemical vapor deposition (CVD) or gold. It is obtained by organic chemical vapor deposition (MOCVD) (also known as metal organic vapor phase epitaxy (MOVPE)). However, for example, molecular beam epitaxy (MBE), gas source molecular beam epitaxy (GSMBE), metal organic MBE (MOMBE), plasma assisted MBE (PAMBE), atomic layer epitaxy (ALE), Hydrogen phase epitaxy (HVPE) and atomic layer deposition (ALD). Further, for example, an evaporation method or a reactive cathode sputtering method can also be used.

When the seed spacers 24 are made of aluminum nitride, they are substantially textured and have a preferred polarity. The texture of the spacer 24 is derived from additional processing performed after depositing the seed spacer 24. For example, annealing is carried out under an ammonia gas stream (NH ₃ ).

(2) The portion of the surface 22 of the protective substrate 10 that is not covered with the seed pad 24 is prevented from subsequent growth of the thin wires on these portions. This can be achieved by a nitridation step which forms a tantalum nitride region (e.g., Si ₃ N ₄ ) between the seed pads 24 at the surface of the substrate 10.

(3) The lower portion 28 of each of the thin wires 26 is grown to a height H ₂ . Each of the thin wires 26 grows from the top of the seed crystal spacer 24 below.

Can be by CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, HVPE type process to grow thin line 26. In addition, electrochemical processes such as chemical bath deposition (CBD), hydrothermal processes, liquid aerosol pyrolysis, or electrodeposition can also be used.

By way of illustration, the method of thin line growth involves injecting a precursor of a Group III element with a precursor of a Group V element into the reactor. Examples of precursors of Group III elements are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMAl). Examples of precursors of Group V elements are ammonia (NH ₃ ), tert-butylphosphine (TBP), arsine (AsH ₃ ) or dimethyl hydrazine (UDMH).

According to a specific embodiment of the present invention, in the first growth phase of the fine line of the group III-V compound, in addition to the precursor of the group III-V compound, a precursor of an additional element is excessively added. This extra element is bismuth (Si). An example of a precursor of ruthenium is decane (SiH ₄ ).

By way of illustration, in an example where the upper portion 28 is made of heavily doped N-type GaN, a gallium precursor gas (eg, trimethylgallium (TMGa)) can be injected into the MOCVD reactor in the form of a showerhead. The MOCVD method is carried out with a nitrogen precursor gas such as ammonia (NH ₃ ). As an illustration, a 3x2" MOCVD reactor in the form of a shower head commercially available from AIXTRON can be used. The molecular flow ratio between trimethylgallium and ammonia is in the range of 5 to 200, preferably. It is in the range of 10-100, which can promote the growth of fine wires. As an example, the carrier gas which ensures that the organometallic element diffuses into the reactor in all directions is filled with the organometallic element in the TMGa bubbler. The standard operating conditions and settings. for example, select 60 sccm TMGa (standard cubic centimeters per minute) of flow, the flow rate of NH ₃ using the 300-sccm (standard cylinders NH _3). use of about 800 mbar (800hPa) of The gas mixture further comprises a decane injected into the MOCVD, the material being a precursor of ruthenium. The decane can be diluted with hydrogen to 1000 ppm and provide a flow rate of 20-sccm. The temperature in the reactor is, for example, between 950 ° C and 1100 ° C. Within the range, preferably from 990 ° C to 1060 ° C. To transport species from the outlet of the bubbler to the two reactor plenums, a 2000-sccm carrier gas is used (eg, distributed between the two plenums) Nitrogen) flow. Said gas flow based only values shown are provided, and should be employed according to the size of the reactor and specifications.

The presence of decane in the precursor gas results in the inclusion of ruthenium in the GaN compound. A lower N-doped portion 28 can thus be obtained. This is further explained by the formation of a tantalum nitride layer (not shown) which, as the portion 28 grows, covers the periphery of the portion 28 of height H ₂ (except for the top).

(4) The upper portion 30 of each of the thin wires 26 is grown on the top of the lower portion 28 (the height is H ₃ ). For the growth of the upper portion 30, as an example, the aforementioned operating conditions of the MOCVD reactor are maintained, but the amount of decane in the reactor is reduced, for example, by a factor of greater than or equal to 10. Since the dopant originating from the adjacent passivation portion diffuses in the active portion, or because of the GaN residual doping, the upper portion 30 is N-type doped even if the decane flow rate is stopped.

(5) The layer body forming the shell layer 34 of each of the thin wires 26 is formed by epitaxy. The deposition of the layer forming the shell 34 occurs only in the upper portion 30 of the thin line 26 in the presence of a layer of tantalum nitride covering the periphery of the lower portion 28.

(6) above the overall structure obtained in the step (5), for example, a conformal deposition This layer is etched and etched to expose the shell 34 of each of the thin lines 26, thereby forming the insulating layer 32. In the foregoing specific embodiment, the insulating layer 32 does not cover the shell layer 34. As a variant, the insulating layer 32 may cover a portion of the shell layer 34. Further, the insulating layer 32 may be formed before the shell layer 34.

(7) The electrode 36 is formed by, for example, conformal deposition.

(8) The conductive layer 38 is formed on the entire structure obtained in the step (7) by, for example, physical vapor deposition (PVD), and this layer is etched to expose the respective thin lines 26. FIG. 2B illustrates the resulting structure after the encapsulation layer 40 has been deposited on the monolithic wafer 10. The maximum thickness of the encapsulation layer 40 is between, for example, 12 microns to In the range of 1000 microns (approximately 50 microns), the encapsulation layer 40 completely covers the electrode 36 at the top of the light-emitting diode DEL. The encapsulation layer 40 is made of an at least partially transparent insulating material.

The encapsulation layer 40 is made of an at least partially transparent inorganic material.

By way of illustration, the inorganic material is selected from the group consisting of cerium oxide (type having SiO _x or having SiO _y N _z , where x is a real number between 1 and 2, and y and z are between 0 and 1 A group of real numbers) and a group of aluminas (for example, Al ₂ O ₃ ). The inorganic material is then deposited by low temperature CVD, particularly at temperatures below 300 °C to 400 °C, such as by PECVD (plasma enhanced chemical vapor deposition).

The encapsulation layer 40 is made of an at least partially transparent organic material. As an example The encapsulation layer 40 is a silicone polymer, an epoxide polymer, an acrylic polymer, or a polycarbonate. The encapsulation layer 40 is then deposited by spin coating, ink jet printing or silk screen printing. It is also possible to use a time/pressure distributor or a volume divider dispensing method in the automatic mode of the programmable device.

Figure 2C illustrates the attachment of an additional support 42 on the encapsulation layer 40 (referred to as The structure obtained after the handle). By way of illustration, the handle has a thickness in the range of 200 microns to 1000 microns.

According to a specific embodiment, once sawing is performed, the handle 42 is to be protected. Stay on the optoelectronic device. The handle 42 is made of an at least partially transparent material which may be glass, particularly borosilicate glass (e.g., Pyrex glass) or sapphire. The observer can perceive the light emitted by the LED DEL on the surface 43 of the handle 42 opposite the encapsulation layer 40.

According to another specific embodiment, in a subsequent step of the manufacturing method, The handle 42 is to be removed. In this example, the handle 42 is made of any type of material that is compatible with the subsequent steps of the manufacturing process. It can be any flat substrate that is compatible with or compatible with the flatness conditions of the microelectronic components.

The handle 42 is attached to the encapsulation layer 40 by any means, such as Bonding, or by using an organic temperature-crosslinkable glue (not shown), or by molecular bonding (direct bonding) or optical bonding of UV-curing glue. When the encapsulating layer 40 is made of an organic material, this material can be used as a glue for the handle 42. When a glue layer is used, it should be at least partially transparent.

FIG. 2D illustrates the junction obtained after the step of thinning the substrate 10. Structure. After thinning, the thickness of the substrate 10 may range from 20 microns to 200 microns, such as about 30 microns. The thinning step can be carried out by one or more grinding or etching steps, and/or by chemical mechanical polishing (CMP). The thinned substrate 10 includes a surface 44 opposite the surface 22. Surfaces 22 and 44 are preferably parallel.

Fig. 2E illustrates the structure obtained after the following steps: - An insulating layer 45 is formed on the rear surface of the substrate 10, which is made of, for example, cerium oxide (SiO ₂ ) or cerium oxynitride (SiON). The insulating layer 45 is implemented, for example, by conformal deposition of PECVD; - for each optoelectronic device, at least one opening 46 is etched across the insulating layer 45, the substrate 10, the insulating layer 32, and the electrode 36 to expose the metal layer 38 portion. The etching of the substrate 10 may be deep reactive ion etching (DRIE). The etching of portions of the insulating layer 32 can also be performed by plasma etching using the chemistry of the insulating layer 32. At the same time, the electrode layer 36 is etched. As a variant, the layer 36 may be removed from the area where the vias 46 are formed prior to the step of forming the metal layer 38. The opening 46 has a circular cross section. The diameter of the opening 46 is in the range of 5 microns to 200 microns, depending on the size of the unit photovoltaic member 14 as shown in Figure 1, for example about 15 microns. A plurality of circular openings 46 are then formed simultaneously to create parallel connections. This reduces the resistance of the connection. Such a connection portion is disposed around a region where the light-emitting diode DEL is formed. As a variant, the opening 46 corresponds to a groove, for example extending along at least one side of the optoelectronic device. Preferably, the groove width is in the range of 15 micrometers to 200 micrometers, depending on the size of the unit photovoltaic member 14 as shown in FIG. 1, for example, about 15 micrometers; An insulating layer 48 is formed on the inner wall and possibly on layer 45. The insulating layer 48 is for example made of SiO ₂ or of SiON, the portion of layer 48 covering layer 45 is not shown in the drawings. The insulating layer 48 is formed, for example, by conformal PECVD. The insulating layer 48 has a thickness in the range of 200 nanometers to 5000 nanometers, for example, about 3 micrometers; - the insulating layer 48 is etched to expose the conductive layer 38 at the bottom of the opening 46. The etch is anisotropic; and at least one opening 50 is etched into the insulating layer 45 to expose a portion of the surface 44 of the substrate 10. To perform this etching, for example, resin is used to temporarily block the opening 46.

2F illustrates the structure obtained after the second electrode 52 is formed in the opening 50 and the conductive layer 54 is formed on the insulating layer 48. The conductive layer 54 covers the inner wall portion of the opening 46 to be in contact with the metal portion 36 and extends over On the surface 44 around the opening 46. The electrode 52 and the conductive layer 54 comprise two layers (as shown in the figure) Shown) or a stack of more than two layers. For example, it is TiCu or TiAl. This layer may be covered with another metal layer, such as gold, copper, or a eutectic alloy (Ni/Au or Su/Ag/Cu) to carry out the soldering process. The second electrode 52 and the conductive layer 54 are formed by electrochemical deposition (ECD), particularly in the case of copper. The thickness of electrode layer 52 and conductive layer 54 is in the range of from 1 micron to 10 microns, such as about 5 microns.

The assembly including the opening 46, the insulating layer 48 and the conductive layer 54 form a vertical connection 56 or TSV (twisted perforation). The vertical connection portion 56 can bias the first electrode 36 from the rear surface of the substrate 10, and the bias of the thin wire 26 is obtained by penetrating the second electrode 52 of the substrate 10.

3A and 3B are partial simplified cross-sectional views of the structure obtained in a continuous step of another embodiment of a method of fabricating a photovoltaic device having a thin line, the method comprising the following description with respect to FIGS. 2A-2E All the steps.

Figure 3A illustrates the resulting structure after the following steps: - formation of a conductive spacer 60 in the opening 50 of the insulating layer 44; - deposition of an insulating layer 62, in particular covering the metal spacer 60. The insulating layer 62 is made of yttrium oxide or tantalum nitride, or a stack structure corresponding to two stacked layers or more stacked layers, and has a thickness of between 200 nm and 1000 nm; and - An opening 64 is etched into the insulating layer 62 to expose a portion of the conductive spacer 60.

FIG. 3B illustrates the steps of forming the second electrode 66 in the opening 64 and forming the conductive layer 54 in the opening 46 in the same manner as described above with respect to the 2F drawing. The resulting structure.

The particular embodiment described with respect to Figures 3A and 3B can advantageously adjust the position and size of the second electrode 66.

Figure 4 illustrates another embodiment of the fabrication method which, after the foregoing steps of Figure 2F, comprises the steps of: - depositing an insulating layer 68, which in particular covers the spacer 52 and fills the opening 46. It may be an insulating polymer such as a BCB (benzocyclobutene) resist having a thickness ranging from 2 micrometers to 20 micrometers, or a cerium oxide having a thickness ranging from 200 nanometers to 1000 nanometers or Tantalum nitride, or both; - An opening 70 is formed in the insulating layer 68 to expose a portion of the second electrode 52 and the conductive layer 54. When the insulating layer 68 is made of an inorganic material, the etching is plasma etching; and when the insulating layer 68 is made of a resist, it is a light and development step; and - forming a conductive bump in the opening 70 72. The bump 72 is made of a material that is compatible with the soldering operation in the electronics industry, such as tin-based or gold-based alloys. Bumps 72 are used to attach the optoelectronic device to a mount (not shown). In the foregoing specific embodiment, current flows between the first electrode 36 and the second electrode 52, 66 through the substrate 10.

Figure 5 illustrates another embodiment in which the light emitting diode is directly biased at the base of the thin wire 26. The thin lines 26 are formed on the seed layer 74, which is then common to the components of the light-emitting diode DEL of the photovoltaic device. The vertical connection portion 76 is formed on the substrate 10, for example, similar to the vertical connection portion 56, but with the difference that the vertical connection portion 76 is connected to the seed layer 74.

6A to 6C are partially simplified cross-sectional views of the structure obtained in a continuous step of another embodiment of the method of manufacturing a photovoltaic device having a thin line, the method including all the steps described in relation to Figs. 2A to 2E.

Figure 6A illustrates the resulting structure after depositing a thick metal layer 80, such as copper. It is an ECD. The thickness of the metal layer 80 is, for example, in the order of 10 microns. Metal layer 80 is thick enough to fill opening 46.

FIG. 6B illustrates the resulting structure after the step of grinding the metal layer 80 to define the metal portion 82 in the opening 50 and the metal portion 84 in the opening 46. The planarization step of layer 80 can be implemented by CMP.

6C illustrates a structure after a step similar to that previously described with respect to FIGS. 3A and 3B, including depositing an insulating layer 86 on the entire rear surface of the substrate 10 and forming a second electrode 88 and a conductive spacer 90, wherein The second electrode 88 passes over the layer 86 in contact with the metal portion 82, and the conductive spacer 90 passes over the layer 86 in contact with the metal portion 84. A passivation layer is deposited over the structure of the side of the back surface, particularly a passivation layer made of a polymer, and an opening is formed in the passivation layer to expose the electrode 88 and the conductive spacer 90.

The assembly including the opening 46, the insulating layer 48, the metal portion 84 and the metal spacer 90 forms the TSV 91, which plays the same role as the previously described TSV 56. Metal spacers 88 and 90 are used to assemble optoelectronic components that are encapsulated on a final support, such as a circuit board. The assembly method is carried out by welding. Choose a metal stack structure that is compatible with the soldering operations used in electronics, especially with organic solder resist polishing (OSP) or Ni-Au polishing (by chemical process (ENIG, electroless plating) Nickel immersion gold) or electrochemical), Sn, Sn-Ag, Ni-Pd-Au, Sn-Ag-Cu, Ti-Wn-Au, or ENEPIG (without electricity) Nickel-plated/electroless palladium/immersion gold) copper-welded compatible soldering operations.

7A and 7B are manufacturers of photovoltaic devices with thin wires A further simplified cross-sectional view of the structure resulting from the sequential steps of another embodiment of the process.

The initial steps include the steps previously described with respect to Figure 2A, the difference It is to form the opening 92 in the substrate 10 before the steps (5) to (7). The opening 92 is formed by etching of the DRIE type. After the thinning step, the depth of the opening 92 is strictly greater than the thickness of the substrate 10. By way of illustration, the depth of the opening 92 is in the range of 10 microns to 200 microns, such as on the order of 35 microns.

In the implementation of steps (5) to (7), the insulating layer 32, the electrode 36 and the conduction Layer 38 is also formed in opening 92.

Figure 7B illustrates the resulting structure after performing the following steps: - Deposition of the encapsulation layer 40, similar to that previously described with respect to Figure 2B. The encapsulation layer 40 partially or completely enters the opening 92; - the handle 42 is mounted, similar to that previously described with respect to FIG. 2C; - thinning the substrate 10, similar to the previous description of the opening 92 as a whole with respect to the 2D diagram; An insulating layer 94 is formed on the rear surface 44 of the substrate 10 while protecting the opening 92; and an opening 96 is formed in the insulating layer 94 to expose a portion of the substrate 10.

The assembly of the insulating layer 32 including the opening 92 and portions extending in the opening 92, a portion of the electrode layer 36, and a portion of the conductive layer 38 form the TSV 98, which plays the same role as the previously described TSV 56.

The subsequent steps of the method are the same as those previously described with respect to Figure 2F.

Figure 8 illustrates a particular embodiment in which the substrate 10 is sawed at least once on the TSV level, the TSV corresponding to one of the previously described TSVs 56, 91 or 98. The sawing exposes a portion of the conductive layer that extends over the inner wall of the TSV. Next, the bias of the first electrode 36 of the light-emitting diode DEL is performed from the photovoltaic device side. By way of illustration, the optoelectronic device can be attached to the pedestal 100 by a connection pad 102 that contacts the rear surface of the substrate 14 and a connection pad 104 that contacts the laterally exposed portion of the TSV.

Figure 9 illustrates a specific embodiment of the TSV 106 disposed at the level of each of the thin wires 26 of the optoelectronic device. Each TSV 106 will be in contact with the seeding pad 24 of the associated thin wire 26. The TSVs 106 may not be connected to each other. The thin lines 26 can then be individually biased. As a variant, electrodes (not shown) provided on the side of the rear surface 44 of the substrate 10 can be connected to all of the vertical connections 106 associated with the same optoelectronic device.

Figure 10 illustrates a specific embodiment in which the TSV 110 is simultaneously in contact with the seed spacer 24 of the plurality of thin wires 26. The vertical connecting portions 106, 110 are formed according to any of the manufacturing methods for forming the TSVs 56, 91, and 98 as previously described.

11A to 11D are partially simplified cross-sectional views showing a structure obtained by a continuous step of another specific embodiment of a method of manufacturing a photovoltaic device having a thin line.

Fig. 11A and Fig. 11B illustrate the structure obtained after the steps before the step (1) described in the previous Fig. 2A are carried out.

Figure 11A illustrates the structure obtained after performing the following steps: - etching the opening 120 in the substrate 10. Opening 120 is formed by reactive ion etching type etching, such as DRIE etching. After the thinning step, the depth of the opening 120 will be strictly greater than the target thickness of the substrate 10. By way of illustration, the depth of the opening 120 is in the range of 10 microns to 200 microns, such as about 35 microns. The distance between the lateral wall portions of the opening 120 is in the range of 1 to 10 microns, and is, for example, 2 microns; and - forming an insulating portion made of, for example, yttria on the lateral wall portion of the opening 120 122, for example, by a heating oxidation process. In this step, an insulating portion may also be formed on the bottom of the opening 120 and the remaining substrate 10. The thickness of the insulating portion is in the range of 100 nm to 3000 nm, for example about 200 nm.

Figure 11B illustrates the resulting structure after performing the following steps: - an isotropically etched insulating portion at the bottom of the opening 120 and an insulating portion covering the surface 22 of the substrate 10 to remain in the lateral wall portion of the opening 120 The upper insulating portion 122. As an illustration, etching of the insulating portion covering the surface 22 of the substrate 10 may be omitted. In this example, a mask formed by photolithography is used to protect the unetched insulating portion; - the opening 120 is filled with a filling material such as polysilicon, tungsten or refractory metal material, which supports at high temperatures The implementation, in particular with regard to the thermal budget in the aforementioned steps of steps 2A to 2D, is carried out, for example, by LPCVD. The polycrystalline germanium advantageously has a coefficient of thermal expansion close to that of germanium, and thus can reduce the mechanical stresses that are carried out at elevated temperatures, particularly with respect to the aforementioned steps of steps 2A to 2D; the layer of filler material is removed, for example in a CMP type process. As in the opposite The etching of the insulating portion of the surface 22 of the cover substrate 10 is omitted during the anisotropic etching of the insulating portion at the bottom of the port 122, and the aforementioned unetched layer is advantageously used as a termination layer when the layer of the filling material is removed. In this case, the removal of the fill layer is followed by the step of etching the insulating portion of the surface 22 of the substrate 10. A portion 124 of the filler material is thus obtained.

Figure 11C illustrates the implementation of the foregoing and Figures 2A through 2D. The structure resulting from the similar steps is described in this example, including the step of etching the opening 125 in the electrode layer 36 and etching the insulating layer 32 to bring the conductive layer 38 into contact with the portion 124 prior to forming the conductive layer 38.

Figure 11D illustrates the structure obtained after performing the following steps (similar to the foregoing description of Figures 7B, 3A and 3B): - thinning the substrate 10 to the conductive portion 124; - on the back surface of the substrate 10 An insulating layer 126 is formed over 44; - an opening 128 is formed in the insulating layer 126 to expose a portion of the back surface 44 of the substrate 10, and an opening 130 is formed in the insulating layer 126 to expose the conductive portion 124; - the opening 128 Forming a conductive spacer 132 in contact with the substrate 10, and forming a conductive spacer 134 in the opening 130 to be in contact with the conductive portion 124; - forming an insulating layer 136 covering the insulating layer 126 and the conductive pads 132, 134; An opening 138 is formed in the insulating layer 136 to expose a portion of the conductive pad 132, and an opening 140 is formed to expose the conductive pad 134; and a second electrode 142 is formed in the opening 138 to contact the conductive pad 132, A conductive pad 144 is formed in the opening 130 to contact the conductive pad 134.

A portion 124 of the filler material defined by the insulating portion 122 The components form TSV 145, which plays the same role as TSV 56 previously described. The conductive portion 124 of the connection pad 144 and the metal layer 38 is formed by a portion 124 of conductive material.

As a variant, there may be no insulating layer 126, but a conductive spacer 132 and 144 are formed directly on the substrate 10.

According to another variation, instead of forming a portion 124 of a fill material that is insulated from the substrate 10 by the insulating portion, the method can include the step of forming an insulating recess (which acts as the portion 124) that defines a portion of the substrate. Preferably, heavily doped germanium (e.g., having a doping concentration greater than or equal to 10 ¹⁹ atoms per cubic centimeter) is used to reduce the electrical resistance of the junction. The conductive portion is formed by one or a plurality of turns of the trench around the active region, or by one or a plurality of insulating germanium vias.

The foregoing specific embodiment regarding FIGS. 11A to 11D can be implemented The vertical connecting portions 106 and 110 as described above with respect to FIGS. 9 and 10 are formed.

12A to 12E are diagrams showing the manufacture of photovoltaic devices having thin wires A partially simplified cross-sectional view of the structure resulting from successive steps in another embodiment of the method. The initial steps include the associated steps of Figures 2A through 2C as previously described, with the difference that there is no conductive layer 38.

Figure 12A illustrates the result obtained after the step of removing the substrate 10. structure. The removal of the substrate 10 is performed by one or more etching steps. The structural back surface that is exposed after the substrate is removed is indicated by the symbol 150. In Fig. 12A, the etching stops on the insulating layer 32 and the seed pad On the sheet 24. As a variant, the method may further comprise removing the seeding spacer 24.

Figure 12B illustrates the structure obtained after performing the following steps: - etching the opening 152 in the insulating layer 32; - depositing a mirror layer 154 on the back surface 150 and in the opening 152; and - depositing a conductive layer 156 covering the mirror layer 154.

The mirror layer 154 is a single layer or corresponds to a stacked structure containing two or more layers. By way of illustration, mirror layer 154 corresponds to a metal monolayer. According to another example, the mirror layer 154 corresponds to a layer stack structure including a metal layer covered with a dielectric layer or covered with a plurality of dielectric layers. The metal layer in the mirror layer 154 is formed on the bonding layer, for example, made of titanium. The thickness of the mirror layer 154 (single or multilayer) is greater than 15 nanometers, for example, in the range of 30 nanometers to 2 micrometers. The mirror layer 154 can be deposited by ECD.

According to a specific embodiment, the mirror layer 154 can at least partially reflect the radiation emitted by the light emitting diode DEL.

According to a specific embodiment, the composite optical index of the material forming the seed pad 24 and the mirror layer 154 (single layer or multilayer) and the thickness of the seed pad 24 and the mirror layer 154 can be selected to enhance the seed pad. The average reflectance of the sheet 24 and the mirror layer 154. The average reflectivity of a layer or layer stack structure refers to the average of the ratio of electromagnetic energy reflected by the layer or layer stack structure of all possible incident angles to incident electromagnetic energy at a known wavelength. It is desirable that the average reflectance be as high as possible, preferably greater than 80%.

The composite optical index (also known as the composite refractive index) is a dimensionless number that represents the optical properties of the medium, particularly the absorption and diffusion characteristics. The refractive index is equal to the real part of the composite optical index. The extinction coefficient (also known as the attenuation coefficient) measures the energy loss of electromagnetic radiation through this material. The extinction coefficient is equal to the opposite of the imaginary part of the composite optical index. The refractive index and extinction coefficient of the material can be determined, for example, by an ellipsometer. The analytical method of ellipsometry data is described in Hiroyuki Fujiwara's "Spectroscopic ellipsometry, Principles and Applications" (published by John Wiley & Sons Co., Ltd. in 2007).

As an illustration, the metal in the mirror layer 154 (single or multilayer) is formed The material of the layer is aluminum, silver, chromium, ruthenium, rhodium, palladium, or an alloy of two or more of these compounds or two or more of these compounds.

According to a specific embodiment, the thickness of the various crystal spacers 24 is less than or equal to 20 nanometers.

According to a specific embodiment, the reflectance of the various crystal spacers 24 is in the range of 1 to 3 for the wavelength range of 380 nm to 650 nm.

According to a specific embodiment, the extinction coefficients of the various crystal spacers 24 are less than or equal to 3 for the wavelength range of 380 nm to 650 nm.

By way of illustration, the materials from which the various crystal spacers 24 are formed correspond to the foregoing examples.

Conductive layer 156 can be made of aluminum, silver, or any other conductive material. By way of illustration, it has a thickness in the range of from 30 nanometers to 2000 nanometers. Conductive layer 156 can be deposited from ECD. The mirror layer 154 and the conductive layer 156 can be mixed.

Figure 12C illustrates the resulting structure after etching the conductive layer 156 and the mirror layer 154 to define the spacer 158, including connection to the electrode layer 36 and A portion 160 of the mirror layer 154 of the spacer 164 and a portion 162 of the conductive layer 156 includes a portion 166 of the mirror layer 154 and a portion 168 of the conductive layer 156 that are coupled to the seed spacer 24.

Figure 12D illustrates the structure obtained after the following steps: - depositing an insulating layer 170 extending over the pads 158, 164 and between the pads 158, 164; - etching the exposed conductive pads 158 in the insulating layer 170 Opening 172 and opening 174 exposing conductive pad 164; and - depositing conductive layer 176 that covers insulating layer 170 and enters openings 172, 174.

The insulating layer 170 is made of cerium oxide deposited by low temperature PECVD, or made of an organic material of the BCB or epoxy type, and has a thickness of several micrometers, typically 3 to 5 micrometers.

The conductive layer 176 is made of TiCu or TiCl. By way of illustration, it has a thickness in the range of from 500 nanometers to 2 micrometers.

Figure 12E illustrates the steps after etching the conductive layer 176 to delineate the conductive pads 178 connected to the conductive pads 158, the second electrodes 180 connected to the conductive pads 164, and the conductive portions 182 in contact with the insulating layer 170. The resulting structure. The conductive portion 182 acts as a radiator. The insulating layer 170 particularly insulates the heat sink 182 from the electrical contact pads 158 and/or is electrically isolated from the conductive layer 156.

The specific embodiment described with respect to FIGS. 12A to 12E has an advantage of suppressing the series resistance due to the substrate 18.

Figure 13 and Figure 14 show the specific implementation of the photovoltaic device 190, respectively. In part and simplified cross-sectional and top views, the optoelectronic device 190 has thin lines formed on the substrate wafer 10 after the step of thinning the substrate 10 and before sawing the substrate 10. In Fig. 13, the optoelectronic device 192 adjacent to the optoelectronic device 190 has been further partially shown.

Each of the optoelectronic devices 190, 192 is filled with one or more of an insulating material A recess 194 (two in this example) surrounds the recess 194 extending between the overall thickness of the thinned substrate 10. By way of illustration, each groove has a width greater than 1 micron, such as about 2 microns. The distance between the two grooves 194 is greater than 5 microns, such as about 6 microns. The sawing line of substrate 10 (shown by short dashed line 196) is formed between recess 194 of optoelectronic device 190 and recess 194 of adjacent optoelectronic device 192. The grooves 194 provide lateral electrical isolation of the germanium substrate from the optoelectronic device 190 after sawing.

As shown in Figure 14, the additional recess 198 connects two adjacent optoelectronics The outer groove 194 of the device 190, 192. After sawing, a portion 200 of the substrate 10 remains there around the photovoltaic devices 190, 192. The groove 198 can divide the surrounding portion 200 into a plurality of insulating segments 202. This reduces the risk of short circuit if the conductive pads are in contact with these segments.

According to a specific embodiment, the optoelectronic device further comprises a phosphor, When excited by the light emitted by the light-emitting diode, the phosphor emits light having a wavelength different from that of the light emitted from the light-emitting diode. As an illustration, the light emitting diode emits blue light, and the phosphor emits yellow light when excited by blue light. Therefore, the observer perceives light composed of blue light and yellow light, and according to the ratio of each light. It is essentially white light. The final color perceived by the observer is characterized by a chromaticity coordinate as defined, for example, by the International Commission on Illumination.

According to a specific embodiment, a phosphor layer is provided within the encapsulation layer 40. Preferably, the average diameter of the phosphors can be selected such that during formation of the encapsulation layer 40, at least a portion of the phosphors are distributed between the filaments 26. Preferably, the phosphor has a diameter in the range of from 45 nanometers to 500 nanometers. The phosphor concentration and the thickness of the phosphor layer can then be adjusted according to the target chromaticity coordinates.

The light extraction rate of an optoelectronic device is generally defined as the light that the photovoltaic device escapes. The ratio of the number of sub-numbers to the amount of photons emitted by the light-emitting diode. Each of the light-emitting diodes emits light in all directions, and in particular toward adjacent light-emitting diodes. The active layer of the light emitting diode tends to capture photons having wavelengths less than or equal to the wavelength of the transmission. Therefore, the active layer of the adjacent light-emitting diode captures a portion of the light emitted by the light-emitting diode. The advantage of providing a phosphor between the thin lines 26 is that the phosphor converts a portion of the light emitted by the light-emitting diode (eg, blue light) to a higher wavelength light before the blue light reaches the adjacent light-emitting diode. (eg yellow light). Since the yellow light is not absorbed by the active layer of the adjacent light-emitting diode, the light extraction rate of the photovoltaic device can be increased.

Another advantage is that since the phosphor is relatively close to the substrate 10, Substrate emissions that generate heat during heating of the phosphor during operation can be enhanced.

Another advantage is that since the phosphor is not located in a separate layer, Therefore, the total thickness of the photovoltaic device can be reduced.

Another advantage is that the uniformity of light emitted by the photovoltaic device can be improved Sex. Indeed, the light in all directions that escape from the encapsulation layer 40 corresponds to the combination of the light emitted by the light-emitting diode and the light emitted by the phosphor.

Figure 15 illustrates the light including all the components as shown in Figure 2F. A specific embodiment of the electrical device 205 further includes a phosphor layer 206 extending over the encapsulation layer 40 and a glue layer 208 extending over the phosphor layer 206 between the encapsulation layer 40 and the handle 42. And a handle 42 extending over the glue layer 208. The thickness of the phosphor layer 206 can range from 50 microns to 100 microns. The phosphor layer 206 corresponds to a silicone layer or an epoxide polymer layer in which a phosphor is embedded. The phosphor layer 206 can be deposited by a spin coating method, an inkjet printing method, or a silk screen method or a sheet deposition method. The phosphor concentration and the thickness of the phosphor layer 206 are adjusted according to the target chromaticity coordinates. In contrast to the specific embodiment in which the phosphor is present in the encapsulation layer 40, larger diameter phosphors can be used herein. Furthermore, the phosphor distribution in the phosphor layer 206 and the thickness of the phosphor layer 206 can be more easily controlled.

Figure 16 illustrates the arrangement of the photovoltaic device 205 as shown in Figure 15 A particular embodiment of a component optoelectronic device 210 differs in that the phosphor layer 206 covers the handle 42. A protective layer (not shown) covers the phosphor layer 206. In this particular embodiment, the phosphor layer 206 is advantageously formed in the last few steps of the optoelectronic device fabrication process. Therefore, the color development characteristics of the photovoltaic device can be further adjusted during most of the photovoltaic device manufacturing method. In addition, if desired, the color rendering characteristics of the photovoltaic device can be easily corrected at the end of the process by adjusting the phosphor layer (e.g., adding another phosphor layer).

Figure 17 illustrates the optoelectronic device 210 as shown in Figure 16 A particular embodiment of optoelectronic device 215 for all of the components, and further includes a recess 216 extending into the handle 42 and filled with a phosphor layer 206. Preferably, the recess 216 extends between the overall thickness of the handle 42. The distance between the lateral wall portions of each recess 216 is preferably substantially equal to the phosphor layer covering the handle 42. The thickness of 206.

For the photovoltaic device 210 shown in Fig. 16, the light emitting diode A portion of the light emitted by DEL will escape from the lateral edges of the handle 42 without passing through the phosphor layer 206. Thus, the color of the laterally escaping light will be different from the color of the light passing through the phosphor layer 206, which is undesirable when uniform light color is desired. For optoelectronic device 215, light escaping from the side of handle 42 will pass through recess 216 filled with phosphor layer 206. Thus, light escaping from the shank 42 through the surface 43 or laterally advantageously has a uniform color.

Figure 18 illustrates the optoelectronic device 205 including Figure 15 A specific embodiment of the optoelectronic device 220 of all components differs in that the glue layer 208 is not shown and an intermediate layer 222 is interposed between the encapsulation layer 40 and the phosphor layer 206.

The intermediate layer 222 allows the light emitting diode DEL to emit at a first wavelength, Or light emitted in the first wavelength range passes, and the light emitted by the phosphor may be reflected at the second wavelength or in the second wavelength range. The light extraction rate of the photovoltaic device 220 can be advantageously increased. By way of example, the intermediate layer 222 corresponds to a dichroic mirror that reflects light having a wavelength within a specific range and allows light of a wavelength not belonging to this range to pass. The dichroic mirror can be formed from a stacked structure of dielectric layers having different optical indices.

According to another example, the intermediate layer 222 has a refractive index less than the encapsulation layer. A single layer of material having a refractive index of 40 and less than the refractive index of the phosphor layer. The intermediate layer 222 corresponds to a silicone layer or an epoxide polymer layer. Further, the surface 224 of the encapsulation layer 40 may be subjected to a surface treatment (referred to as texturing) to form a raised region on the surface 224 prior to forming the intermediate layer 222. In the middle layer 222 with The interface 226 between the phosphor layers 206 is substantially flat.

Even if the refractive index of the intermediate layer 222 is smaller than the refractive index of the encapsulation layer 40, The light emitted by the LED DEL will still pass through the irregular interface 224, while the light emitted by the phosphor is mainly reflected on the interface 226 because the interface 226 is flat and the refractive index of the intermediate layer 222 is less than The refractive index of the phosphor layer 206.

A texturing method that can form a raised region at the surface is applied to the handle The surface 43 of the portion 42 and/or the surface 228 of the phosphor layer 206 that is in contact with the handle 42.

For a layer made of an inorganic material layer, the surface of the layer surface The physicochemical method includes a chemical etching step or a mechanical grinding step, which can be performed under the treated surface having the mask protective portion to promote the formation of the raised region at the surface. For a layer made of an organic material, the method of texturing the surface of the layer includes steps such as embossing, molding, and the like.

For the optoelectronic device previously described, the light-emitting diode DEL A portion of the emitted light escapes through the lateral edges of the encapsulation layer 40. This is generally undesirable because the viewer does not perceive the light under normal operating conditions of the optoelectronic device. According to a specific embodiment, the optoelectronic device further includes means for reflecting light escaping laterally from the optoelectronic device to increase the amount of light escaping from the surface 43 of the handle 42.

Figure 19 illustrates a particular embodiment of optoelectronic device 230 including all of the components of the optoelectronic device shown in Figure 2F, and further including a block 232 disposed on insulating layer 32 and at least partially surrounding the components of light emitting diode DEL. Each of the blocks 232 is covered with a metal layer 234, for example corresponding to the conductive layer 38. Extension. By way of illustration, block 232 corresponds to a resist block formed on insulating layer 32 prior to deposition of encapsulation layer 40. Preferably, the height of the block 232 is less than the maximum height of the encapsulation layer 40. In FIG. 19, the lateral edge 236 of the block 232 is substantially perpendicular to the surface 22 of the substrate 10. As a variant, the lateral sides 236 can be inclined relative to the surface 22 to promote light reflection toward the surface 43 of the handle 42.

Figure 20 illustrates a particular embodiment of optoelectronic device 240 including all of the components of the optoelectronic device shown in Figure 2F, and further including a block 242 disposed on insulating layer 32 and at least partially surrounding the components of light emitting diode DEL. Block 242 is made of a reflective material that can be a silicone filled with reflective particles (e.g., titanium oxide TiO ₂ particles). By way of illustration, block 242 is formed on insulating layer 32 by a silkscreen process prior to deposition of encapsulation layer 40. Preferably, the height of the block 242 is less than the maximum height of the encapsulation layer 40. In FIG. 20, the lateral edge 244 of the block 242 is substantially perpendicular to the surface 22 of the substrate 10. As a variant, the lateral edge 244 can be inclined relative to the surface 22 to promote light reflection toward the surface 43 of the handle 42.

Figure 21 illustrates a specific embodiment of a photovoltaic device 245 comprising all of the components of the photovoltaic device as shown in Figure 2F, with the difference that the light-emitting diode DEL is formed in the cavity 246 formed in the substrate 10. The lateral sides 248 of the cavity 246 are covered with an insulating layer 250 (e.g., corresponding to the extension of the insulating layer 32) and are covered with a metal layer 252 (e.g., corresponding to the extension of the conductive layer 38). Preferably, the depth of the cavity portion 246 is less than the maximum height of the encapsulation layer 40. In FIG. 21, the lateral sides 248 of the cavity are substantially perpendicular to the surface 43 of the handle 42. As a variant, the lateral sides 248 can be inclined relative to the surface 43 to promote light direction The surface 43 of the handle 42 is reflected.

Figure 22 illustrates all the structures of the photovoltaic device shown in Figure 2F. A particular embodiment of a photovoltaic device 255, and which further includes a recess 256 surrounding the light emitting diode DEL, a single recess is illustrated in FIG. The groove 256 passes through the substrate 10 and the encapsulation layer 40. The inner wall of each recess 256 is covered with a reflective layer 258, such as a metal layer, for example, made of a layer of silver or aluminum or varnish, and having a thickness in the range of from 30 nanometers to 2000 nanometers. An insulating layer (not shown) is provided to insulate the reflective layer 258 from the substrate 10. The groove 256 is formed after the thinning step of the substrate 10 previously described with respect to FIG. 2D. One advantage over the optoelectronic devices 230, 240 and 245 is that the encapsulation layer 40 can be formed on a flat surface, which makes it easier to deposit.

Figure 23 illustrates all the structures including the photovoltaic device as shown in Fig. 2F. A particular embodiment of a photovoltaic device 260, and which further includes a recess 262 formed in the encapsulation layer 40 and surrounding the light emitting diode DEL, wherein only a single recess is depicted in FIG. The groove 262 is filled with air. When the encapsulation layer 40 is made of an inorganic material, the recess 262 may be formed by etching after the step of forming the encapsulation layer 40. In the encapsulation layer 40, the recess 262 defines a central block 264 and a surrounding block 266, the central block 264 is embedded with a light emitting diode, and the surrounding block 266 at least partially surrounds the central block 264. Each of the surrounding blocks 266 is covered with a metal layer 268, such as silver or aluminum, and has a thickness in the range of 30 nm to 2000 nm. The glue layer 269 is disposed between the handle 42 and the blocks 264, 266. In FIG. 23, the lateral sides 270 of the perimeter block 266 are substantially perpendicular to the surface 22 of the substrate 10. As a variant, the lateral sides 270 can be inclined relative to the surface 22 to promote light toward the handle 42. The surface 43 is reflected. One advantage over the optoelectronic devices 230, 240 and 245 is that the encapsulation layer 40 can be formed on a flat surface, which makes it easier to deposit.

Figure 24 illustrates all of the components including the photovoltaic device as shown in Figure 2F and further comprising an optoelectronic device 275 extending over the electrode layer 32 between the light-emitting diodes DEL and not covering the insulating layer 276 of the light-emitting diode DEL. Specific embodiment. The insulating layer 276 is covered with a reflective layer 278. Reflective layer 278 is preferably a metal layer, for example made of aluminum, aluminum alloy (especially AlSi _z, Al _x Cu _y, for example, x equals 1 and y is equal to 0.8%) is made, or of silver, gold Made of nickel or palladium. By way of illustration, reflective layer 278 has a thickness between 30 nanometers and 2000 nanometers. The reflective layer 278 can comprise a stacked structure of a plurality of layers, particularly including a bonding layer (eg, made of titanium). The thickness of the insulating layer 276 and the thickness of the reflective layer 278 are selected such that the surface 280 of the reflective layer in contact with the encapsulating layer 40 is near the end of the shell 34, such as less than 1 micron from the end of the shell layer 34. Compared to the previously described specific embodiment, the reflective surface 280 can advantageously prevent the light emitted by the shell 34 of the LED DEL from reaching the outside of the LED and penetrating into the lower portion 28 or adjacent to the LED. The lower portion 28 of the light emitting diode. Therefore, the light extraction rate can be increased.

Figure 25 illustrates a specific embodiment of a photovoltaic device 285 comprising all of the components of the photovoltaic device 275 shown in Figure 24, with the difference that the insulating layer 276 and the reflective layer 280 are replaced by extending over the electrode layer 32 to the light emitting diode. The reflective layer 286 of the light-emitting diode DEL is not covered between the DELs. It is a silicone layer filled with reflective particles (for example, TiO ₂ particles) or a TiO ₂ layer. The thickness of the reflective layer 286 is selected such that the surface 288 of the reflective layer 286 in contact with the encapsulation layer 40 is adjacent the end of the shell layer 34, such as less than 1 micron from the end of the shell layer 34. Therefore, the light extraction rate can be increased.

According to a particular embodiment, a surface 43 is provided on the surface 42 of the handle 42 Or a plurality of lenses. These lenses increase the focus of light leaking from surface 43 in a direction perpendicular to surface 43, thereby increasing the amount of light perceived by the user viewing surface 43.

Figure 26 illustrates all of the optoelectronic devices 230 shown in Figure 19 A particular embodiment of the optoelectronic device 290 of the component differs in that the handle 42 is absent. Furthermore, for each of the light-emitting diodes DEL, the optoelectronic device 290 includes a converging lens 292 disposed on the encapsulation layer 40.

Figure 27 is a specific embodiment 295 similar to the view of Figure 26, in which lens 296 is associated with a plurality of light emitting diodes DEL.

Specific embodiments of the invention have been described. Various modifications and modifications will occur to those skilled in the art. Moreover, while in the foregoing embodiment, each of the thin wires 26 includes a passivation portion 28 at the base of the thin wire that contacts one of the seed spacers 24, the passivation portion 28 may not be provided.

Moreover, while the specific embodiment is illustrated with respect to the optoelectronic device in which the shell layer 34 covers the top of the associated thin line 26 and a portion of the lateral side of the thin line 26, it is also possible to provide the shell layer only at the top of the thin line 26.

DEL‧‧‧Light Emitting Diode

10‧‧‧Substrate

22‧‧‧ Surface of the substrate

40‧‧‧Encapsulation layer

42‧‧‧ handle

44‧‧‧ Surface of the substrate

Claims (12)

A method for fabricating an optoelectronic device (14) comprising the following sequential steps: (a) providing a substrate (10) having a first surface (22); (b) forming a thin surface on the first surface a light emitting diode (DEL) component of a linear, conical or tapered semiconductor component; (c) forming an electrode layer (36) and a conductive layer (38) for each of the light emitting diode components, the electrode layer covering the Each of the light emitting diodes of the component, the conductive layer covering the electrode layer around the light emitting diode of the component; (d) covering the entire first surface of the layer (40) encapsulating the light emitting diode (e) reducing the thickness of the substrate, the substrate having a second surface (44) opposite the first surface (22) after the step (e); (f) forming a conductive element (56) The substrate is insulated and completely passes from the second surface to the at least the first surface (22), the conductive element is in contact with the conductive layer; (g) forming at least one first contact with the substrate on the second surface Conductive pads (52; 60; 82; 102; 132); and (h) saw-cut structures to separate each of the light-emitting diode assemblies. The method of claim 1, comprising the steps of: at step (f), forming at least one second conductive spacer (72; 90; in contact with the conductive element (56) on the second surface (44); 134). The method of claim 1 or 2, comprising the steps of: forming at least one additional conductive element (106, 110) insulated from the substrate and completely crossing the substrate from the second surface to at least the first surface (22 And contacting the base of at least one of the light emitting diodes (DEL). The method of claim 1, wherein the step of forming the conductive element (56) continuously comprises the step of: etching a second surface (44) from the second surface (44) in the substrate (10) after the step (e) The opening (46) forms an insulating layer (48) on at least the lateral wall portion of the opening, and forms a conductive layer (54) covering the insulating layer or fills the opening with a conductive material. The method of claim 1 wherein step (f) is performed at least partially prior to step (b) and includes the step of etching a first surface (22) from the first surface (22) prior to step (b) The opening (92), traversing a portion of the thickness of the substrate, is open to the second surface (44) during step (e). The method of claim 5, wherein the electrode layer (36) and the conductive layer (38) are further formed in the opening (92). The method of claim 5, comprising the step of forming an insulating portion (122) on at least a lateral wall portion of the opening (92) prior to step (b) and filling the opening with a conductive material. The method of any one of claims 1 to 7, comprising the steps of: Prior to step (e), a seat (42) is attached to the layer (40) enclosing the light emitting diode (DEL). The method of any one of claims 1 to 8, wherein the layer (40) encapsulating the light emitting diode (DEL) comprises a phosphor between the light emitting diodes. The method of claim 8, comprising the step of forming a phosphor layer (206) covering the layer (40) enclosing the light emitting diode (DEL) or covering the support (42) ). The method of claim 10, comprising the step of forming a layer (222) between the layer (40) encapsulating the light emitting diode (DEL) and the phosphor layer (206), the layer (222) The light emitted by the light emitting diode can be transmitted, and the light emitted by the phosphor can be reflected. The method of any one of claims 1 to 11, comprising the light emitting diode between the substrate (10) and the layer (40) encapsulating the light emitting diode (DEL) ( A step of forming a reflector (232; 242) around the DEL) having a height 50% greater than the height of the light-emitting diode.