TW201624475A - Memory device and power control method thereof - Google Patents

Abstract

A memory device and a power control method thereof are disclosed. The power control method, adopted by the memory device including a DRAM, a SRAM, and a data controller, includes determining, by the data controller, the importance of a data; and when the importance of the data belongs to important data, storing, by the power controller, the data into the SRAM.

Description

Memory device and its power control method

The present invention relates to power management, and more particularly to a power control method suitable for use in a memory device.

As wearable devices come to market, the demand for dynamic random access memory with low power consumption has also increased. Since the wearable device itself is not under long-term operation, the wearable device often requires a long time without charging and most of the time in standby mode.

Therefore, there is a need for a memory device and a power control method for reducing the current of the wearable device in the standby mode.

Based on the above, the present invention discloses a memory device including a dynamic random access memory (DRAM), a static random access memory (SRAM), and a static random access memory (SRAM). Data bus, one address bus, and one command line. The data bus is coupled to the DRAM and the SRAM to transmit a data. The address bus is coupled to the DRAM and the SRAM to transmit a memory address. The instruction line is coupled to the DRAM and the SRAM, and transmits an instruction.

The invention further discloses a power control method suitable for inclusion a memory device of a DRAM, an SRAM, and a data controller, comprising: determining, by the data controller, the importance of the data; and when the data determines that the importance is important, storing the data in the SRAM .

1‧‧‧ memory device

10‧‧‧ Random Access Memory (RAM)

100‧‧‧Dynamic Random Access Memory (DRAM)

102‧‧‧Static Random Access Memory (SRAM)

12‧‧‧ instruction decoder

14‧‧‧ address decoder

16‧‧‧Power Controller

18‧‧‧ data controller

CLK‧‧‧ clock signal

CS‧‧‧ wafer selection signal

CKE‧‧‧ signal

RAS/CAS‧‧‧ column address selection signal/row address selection signal

W/R‧‧‧Read or write instructions

AD‧‧‧ address data

RAD/CAD‧‧‧List address/row address

DQ‧‧‧ memory data

1000, 1004, 1006, 1010, 1014, 1018‧‧‧ DRAM sense amplifiers (DRAM S/A)

1002, 1008, 1012, 1016‧‧‧ DRAM memory unit

1022‧‧‧SRAM sense amplifier (SRAM S/A)

1020‧‧‧SRAM memory unit

S300, S302, ..., S310‧‧‧ steps

1 is a block diagram of a memory device 1 in an embodiment of the present invention.

Fig. 2 is a detailed schematic view of the memory device 1 of Fig. 1.

FIG. 3 is a flow chart of another power control method 3 in the embodiment of the present invention.

The various embodiments and examples set forth in the following disclosure are intended to illustrate various technical features disclosed herein, and the specific examples or arrangements described herein are used to simplify the invention. It is not intended to limit the invention. In addition, the same reference numerals and symbols may be used in the different embodiments or examples, and the repeated reference numerals and symbols are used to illustrate the disclosure of the present invention, and are not intended to represent different embodiments or The relationship between the examples.

The low power mode proposed in the disclosure of the specification may also be referred to as an idle mode, a standby mode, a sleep mode, a sleep mode, a hibernation mode, a power saving mode, a deep power down (DPD), or other off power. Or the power mode of a partial memory power supply.

1 is a block diagram of a memory device 1 according to an embodiment of the present invention, including a random access memory (RAM) 10, an instruction decoder 12, an address decoder 14, and a power controller 16. Take And data controller 18. The memory device 1 is suitable for use in a wearable or other portable device that operates with limited power, such as a battery, is idle for most of the time, and has a need for no charging for a long time. The above wearable or other portable device may be, for example, a smart watch or a smart phone.

The RAM 10 is a temporary memory, and includes a Dynamic Random Access Memory (DRAM) 100 and a Static Random Access Memory (SRAM) 102. The RAM 10 is a temporary data storage medium for the operating system or other programs being executed, and loads various programs and data for direct execution by the system's Central Processing Unit (CPU) (not shown). And use.

The CPU can access the memory data DQ, such as 128-bit memory data DQ, from the DRAM 100 and the SRAM 102 of the RAM 10 through a data bus (not shown). The instruction decoder 12 and the address decoder 14 are coupled to the DRAM 100 and the SRAM 102 of the RAM 10 via command lines (not shown) and an address bus (not shown). The power controller 16 can be directly divided into two connections to the DRAM 100 and the SRAM 102, one to control the power supply of the DRAM 100, and one to control the power supply of the SRAM 102. The power supply to the DRAM 100 is directly turned off in the low voltage mode. The command decoder 12 externally receives the clock signal CLK, the chip select signal CS, CKE, the column address selection/row address selection signal RAS/CAS, and generates a read or write command W/R. The address decoder 14 receives the address data AD, for example, the 32-bit address data AD is used to generate the column address/row address RAD/CAD, and the above column address/row address RAD/CAD is used to designate the RAM. 10 records to be read or written Recall the unit address.

The DRAM 100 includes a DRAM memory cell array (not shown), wherein each DRAM memory cell includes a transistor and a capacitor (1-Transister 1-Capacitor, 1T1C), and data or information is stored in the capacitor. Since the capacitor leaks, it is necessary to constantly charge (refresh) to maintain the potential and the stored data or information. The DRAM 100 is referred to as "dynamic" random access memory because of constant timing charging. The SRAM 102 includes an array of SRAM memory cells (not shown), wherein each of the SRAM memory cells is implemented by a latching circuit, such as a self-locking circuit formed of a transistor. The SRAM memory unit does not have to be charged automatically, and the only moment when charging or discharging occurs is when writing. If there is no written command, the data or information stored in the SRAM memory unit will not be changed. Because the SRAM memory unit in the SRAM 102 does not need to be periodically charged to maintain its stored data or information when it is turned on, it is called a "static" random access memory. Although the SRAM memory unit does not require periodic charging, it still requires standby current to maintain its circuit operation and the data or information recorded. When the memory device 1 is turned off and no power is supplied to the DRAM 100 and the SRAM 102, the internal stored data or information of the DRAM 100 may completely disappear, and the internal stored data or information of the SRAM 102 may be lost.

When turned on, the memory device 1 can operate in a normal mode or a low power mode. In the normal mode, the DRAM 100 and the SRAM 102 are normally supplied with power and the DRAM 100 is periodically charged to normally access the memory data in the RAM 10. In the low power mode, standby current is supplied to the SRAM 102 and the DRAM 100 stops powering and stops timing charging to reduce the power consumption of the DRAM 100, saving power consumption of the memory device 1 and increasing the wearable or portable device. Electricity The pool continues to power. In an embodiment, since the DRAM 100 may have some important data, when entering the low power mode, some important data on the DRAM 100 is first moved to the SRAM 102, and then the DRAM 100 is completely powered off and timed. . Since important data has been stored on the SRAM 102, when the low power mode is entered, timing charging is not required at all, so the charging current can be reduced. It is then possible to bring the SRAM 102 into the DPD mode to achieve further power savings. In another embodiment, important data is accessed in advance through SRAM 102 in normal mode, and unimportant or non-critical data is accessed through DRAM 100. Therefore, when entering the low power mode, there is no need to perform data relocation.

In another embodiment, the DRAM 100 will power and periodically charge a portion of the DRAM 100 memory cells in the low power mode and stop powering and timing charging the remaining portion of the DRAM 100 memory cells. This can reduce the power consumption of the memory device 1.

When the memory device 1 returns to the normal mode again from the low power mode, power is normally supplied to the DRAM 100. In an embodiment, the active data is moved back to the DRAM 100 from the SRAM 102 in normal mode, and the DRAM 100 is timed to maintain the internally stored data. In another embodiment, the normal mode continues to retain important data in the SRAM 102 without additional relocation.

For example, when the memory device 1 is not used or required for more than a predetermined period of time, for example, more than 2 minutes, the CPU can issue a low power mode to the RAM 10, such as a deep power down (hereinafter referred to as DPD). Instructions. Corresponding to the above instructions for entering the low power mode, the RAM 10 stores some important data in the DRAM 100 onto the SRAM 102 before entering. Low power mode, completely stopping (partial or full) DRAM 100 power and timing charging. In low power mode, the (partial or full) DRAM 100 that loses power loses all stored data. At the same time, since the DRAM 100 does not need to be powered, the battery life can be improved. When the memory device 1 is woken up and returns to the normal mode, for example, when the user operates a wearable or timed background program trigger, the CPU can issue an instruction to the RAM 10 to return to the normal mode. Corresponding to the normal mode command described above, the RAM 10 restores the important data stored in the SRAM 102 to the DRAM 100, whereby the application can continue to be executed using the important data.

In another example, important data is accessed in advance through SRAM 102 in normal mode, and unimportant data is accessed through DRAM 100. When the memory device 1 is not used or required for more than a predetermined period of time, for example, more than 2 minutes, the CPU can issue an instruction to the RAM 10 to enter a low power mode, such as DPD. Corresponding to the above-mentioned instruction to enter the low power mode, since important data has been previously stored in the SRAM 102, data relocation is not required, and power supply to the DRAM 100 is completely stopped. When the memory device 1 returns to the normal mode, for example, when the user operates a wearable or timed background program trigger, the CPU can issue an instruction to the RAM 10 to return to the normal mode. In response to the normal mode command described above, the RAM 10 continues to store important data within the SRAM 102.

The power controller 16 can define a power supply address when the location of the memory unit of the SRAM 102 is in the low power mode. Upon entering the low power mode, the data controller 18 can move the important data to the SRAM 102 memory unit designated by the power supply address, and the power controller 16 only supplies power to the SRAM 102.

2 is a detailed schematic view of the memory device 1 of FIG. 1 The medium RAM 10 includes a DRAM 100 and an SRAM 102. DRAM 100 includes sense amplifier DRAM S/A 1000, 1004, 1006, 1010, 1014, and 1018 and DRAM memory cells 1002, 1008, 1012, and 1016; SRAM 102 includes sense amplifier SRAM S/A 1022 and SRAM memory unit 1020.

The DRAM 100 and the SRAM 102 share the same address bus receiving memory address data AD, such as 32-bit address data AD, the same data bus receiving memory data DQ, such as 128-bit memory data DQ, and sharing. The command line receives the command data W/R, such as the read/write command data W/R. Memory data within DRAM 100 and SRAM 102 can be accessed through a shared address bus, data bus, and command line. The DRAM 100 and the SRAM 102 can transfer the memory data DQ in series, and transmit the address data AD and the instruction data W/R in parallel. In the embodiment of FIG. 2, the DRAM 100 and SRAM 102 transfer the memory data DQ at the DRAM memory unit 1016 of the last memory segment of the DRAM 100 and the SRAM memory unit 1020 of the memory segment of the SRAM 102, but are familiar with this. The skilled artisan will appreciate that the coupling point of DRAM 100 and SRAM 102 to transfer memory data DQ can occur between any of the memory sections of DRAM 100 and the memory section of SRAM 102.

As described in FIG. 1, the memory device 1 operates in two power modes, a normal mode or a low power mode, and the address of the SRAM memory unit 1020 of the memory segment in the SRAM 102 can be defined as the power supply in the low power mode. Address. In an embodiment, the data controller 18 in the low power mode first moves the important data stored in the DRAM memory cells 1002, 1008, 1012, and 1016 of the memory segment of the DRAM 100 to the power supply address in the low power mode. , that is, the SRAM memory unit 1020 of the memory section of the SRAM 102, and then The DRAM 100 is completely powered off and timed. Since important data has been stored on the SRAM 102, there is no need for timing charging or power supply when entering the low power mode, which can reduce the charging current. In another embodiment, the data controller 18 in the normal mode directly accesses the important data through the SRAM 102, and the unimportant data is accessed through the DRAM 100. When entering the low power mode, since important data has been previously stored in the SRAM 102, no additional relocation data is required.

In some embodiments, a portion of the memory segment of DRAM 100 may also be defined as a power supply address in a low power mode, such as memory segment 1016. The memory segment 1016, which only maintains the power address in the low power mode, is powered and charged in the low power mode without powering and charging the remaining memory segments 1012, 1008, and 1002. This method does not require prior movement of the important data of the memory segment 1016 but consumes current to charge the memory segment 1016.

Upon returning to the normal mode, the power controller 16 will normally supply power to all of the memory sections of the DRAM 100 and SRAM 102. In one embodiment, the data controller 18 moves the important data from the SRAM memory unit 1020 of the SRAM 102 memory segment back to the DRAM memory cells 1002, 1008, 1012, and 1016 of the DRAM 100, and periodically charges the DRAM 100 to maintain Internally stored data. In another embodiment, when the memory device 1 returns to the normal mode, important data is continuously stored within the SRAM 102.

Fig. 3 is a flow chart showing another power control method 3 in the embodiment of the present invention, using the memory device 1 of the first and second figures. The power control method 3 can be implemented by logic circuitry within the power controller 16 or in the form of a code.

The power controller 16 executes the power control method 3 (S300) after the power is turned on. First, the power controller 16 periodically determines the power mode of the memory device 1. In the formula (S302), for example, the power mode is judged every 10 seconds. The power modes described above may be changed by instructions issued by one or more external CPUs, processors, or controllers. For example, when the memory device 1 is not used or required for more than a predetermined period of time, for example, more than 2 minutes, the external CPU can issue a low power mode to the memory device 1, such as a deep power down (hereinafter referred to as DPD). instruction. When the wearable device including the memory device 1 is turned on, or the user touches the wearable device to turn on the device, or a background application triggers the wake-up memory device 1, the external CPU can issue an instruction to the memory device 1 to enter the normal mode.

When the data controller 18 determines that the power mode is the low power mode, some important data in the DRAM 100 is first stored in the SRAM 102 (S304) through the data bus and then enters the low power mode, and the pair (partially or completely) is completely stopped. The DRAM 100 is powered and timed (S306). Since (partial or full) DRAM 100 does not require power supply, battery life can be improved.

When the data controller 18 determines that the power mode is the normal mode, it first restores the power supply of the DRAM 100, and then transfers the important data stored in the SRAM 102 back to the DRAM 100 through the data bus and periodically charges the DRAM 100 (S308), thereby continuing to use. Important information to execute related applications.

The power control method 3 ends here (S310).

The memory device 1 and the power control method 3 thereof disclosed in FIGS. 1 to 3 can be loaded with the SRAM 102 in the memory device 1 in the low power mode, and the important data can be saved in the SRAM 102 that is not required to be charged, and is in a normal state. In the mode, the important data can be moved back to the DRAM 100 to continue to use, or the important data can be stored in the SRAM 102 without further relocation, thereby increasing the battery life without sacrificing the operation performance of the memory device 1.

Those skilled in the art will appreciate that the various logical blocks, modules, processors, actuators, circuits, and algorithm steps described in the specification can be implemented by circuit hardware (eg, digitally implemented hardware, analog hardware, or both). Combination of the following, which can be designed and implemented by source code or other related technologies), using various forms of code or design code of instructions (also referred to herein as software or software modules), or a combination of the two. achieve. To clearly illustrate the interchangeability of the above described software and hardware, the various illustrated elements, blocks, modules, circuits, and steps described in the specification are generally described in terms of their function. The implementation of these features in software or hardware will be related to the specific application and design constraints of the complete system. The described functionality may be implemented in a variety of ways for each particular application, but the implementation is not deviated from the spirit and scope of the invention.

In addition, the various logic blocks, modules, and circuits described herein can be implemented using integrated circuits (integrated circuits, ICs) or by an access terminal or access point. The integrated circuit may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic elements, discrete logic circuits or transistor logic gates, discrete hardware components, electrical components, optical components, mechanical components, or any combination of functions for performing the operations described herein can be performed A code or program instruction in the integrated circuit, external, or both. A general purpose processor may be a microprocessor, or the processor may be any commercially available processor, controller, microprocessor, or state machine. The processor can also be implemented by a combination of computing devices, such as a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors, and A combination of DSP cores, or various other settings.

It will be understood by those skilled in the art that the specific sequence or sequence of steps of the present disclosure is merely exemplary. The specific order or sequence of steps of the program disclosed herein may be re-arranged in other orders, as may be apparent to those skilled in the art. The order of the steps in the method and the requirements of the embodiments of the present invention are merely examples, and are not limited to the specific order or sequence of steps of the present invention.

The method or algorithm step can be implemented by a hardware or a processor, or a combination of the two. Software modules (including executable instructions and related materials) and other data can be stored in the data memory, such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, temporary storage A storage medium (such as a computer readable) that can be read by a device, hard drive, floppy disk, CD, or any other machine. The data storage medium can be coupled to a machine, such as a computer or processor (which can be referred to as a "processor"), which can read and write code from the storage medium. The data storage medium can be integrated into the processor. The processor and storage media can be hosted within the ASIC. The ASIC can reside in the user equipment. Alternatively, the processor and the storage medium may reside within the user equipment in the form of discrete components. In addition, suitable computer program products may include computer readable media, including code disclosed with respect to one or more disclosures. In some embodiments, a suitable computer program product can include packaging materials.

The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

S300, S302, ..., S310‧‧‧ steps

Claims (15)

A memory device includes: a dynamic random access memory (DRAM); a static random access memory (SRAM); a data bus, coupled to the above The DRAM and the SRAM transmit a data; an address bus, coupled to the DRAM and the SRAM, to transmit a memory address; and a command line coupled to the DRAM and the SRAM to transmit an instruction. The memory device of claim 1, further comprising: a data controller coupled to the DRAM and the SRAM to determine the importance of the data. The memory device of claim 2, wherein: when the above-mentioned importance of the data is important, the data controller stores the data in the SRAM. The memory device of claim 2, wherein: when the above-mentioned importance of the data is non-essential data, the data controller stores the data in the DRAM. The memory device of claim 2, wherein: the data controller determines a power mode of the memory device, and when the power mode is a low power mode, storing the important data from the DRAM to the SRAM, and stop charging the above DRAM. The memory device of claim 5, wherein: when the power mode is a normal mode, the power controller stores the important data stored in the SRAM to the DRAM and charges the DRAM. The memory device of claim 1, wherein the data bus is coupled in series with the DRAM and the SRAM. The memory device of claim 1, wherein the SRAM is a self-locking circuit for recording a memory material. A power control method for a memory device including a DRAM, an SRAM, and a data controller, comprising: determining, by the data controller, the importance of the data; and when the above-mentioned importance of the data is important data , the above data is stored in the above SRAM. For example, the power control method described in claim 9 further includes: when the above-mentioned importance of the above information is non-essential data, storing the above data in the DRAM. The power control method of claim 9, wherein the storing the data to the SRAM step comprises: determining, by the data controller, a power mode of the memory device; and when the power mode is a low power In the mode, the above important data is stored from the DRAM to the SRAM, and charging of the DRAM is stopped. The power control method of claim 9, further comprising: determining, by the data controller, a power mode of the memory device; And when the power mode is a normal mode, the important data stored in the SRAM is stored in the DRAM by the power controller, and the DRAM is charged. The power control method of claim 9, wherein the memory device further comprises: a data bus, coupled to the DRAM and the SRAM, and transmitting a memory data; and an address bus, coupled to the DRAM and The SRAM transmits a memory address; and a command line coupled to the DRAM and the SRAM to transmit an instruction. The power control method of claim 13, wherein the data bus is coupled in series with the DRAM and the SRAM. The power control method according to claim 9, wherein the SRAM is a self-locking circuit for recording a memory data.