TW201621648A - Novel basic input/output system - Google Patents

Novel basic input/output system Download PDF

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TW201621648A
TW201621648A TW103143467A TW103143467A TW201621648A TW 201621648 A TW201621648 A TW 201621648A TW 103143467 A TW103143467 A TW 103143467A TW 103143467 A TW103143467 A TW 103143467A TW 201621648 A TW201621648 A TW 201621648A
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logic
output
program
input
basic input
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TW103143467A
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Chinese (zh)
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吳忠良
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立端科技股份有限公司
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Abstract

The present invention provides a novel basic input/output system comprising a flash chip, a jump switch and a logic gate. When applying this novel basic input/output system, a first boost program stored in a first storing region of the flash ship or a second boost program stored in a second storing region of the flash ship can be loaded for boosting a X86 system by way of switching the jump switch to a "High" state or a "Low" state and using CPU's GPIO port(s). By such way, this novel basic input/output system not only provides dual bootloader for the X86 system but also carries out the BIOS backup based on single flash chip.

Description

新穎基本輸入輸出系統 Novel basic input and output system

本發明係關於基本輸入輸出系統的相關領域,尤指一種新穎基本輸入輸出系統。 The present invention relates to the field of basic input and output systems, and more particularly to a novel basic input and output system.

不管是一般個人電腦、伺服器主機、或工業電腦,其開機後所執行的第一個韌體為基本輸入輸出系統(Basic Input/Output System,BIOS),若BIOS因損壞而無法被正確執行,電腦就無法進行後續的作業或者無法開機。 Whether it is a general personal computer, a server host, or an industrial computer, the first firmware executed after booting is the Basic Input/Output System (BIOS). If the BIOS cannot be correctly executed due to damage, The computer cannot perform subsequent operations or cannot boot.

電腦的BIOS主要是儲存在主機板上的快閃記憶體中,於RISC系統中(reduced instruction set computer,精簡指令集)大都是選擇nor-flash來存放BIOS之bootloader開機資料,且在RISC系統中,很多軟體開發商會使用自行開發的BIOS,故在開發及維修時會有切換應用商和硬體商BIOS的需求。如果在更新nor-flash資料發生錯誤而造成無法正常開機的問題時,只能經由昂貴的燒錄製具(比如JTAG)或替換nor-flash來修複,這會造成開發維修的麻煩困擾。 The BIOS of the computer is mainly stored in the flash memory on the motherboard. In the RISC system (reduced instruction set computer, the reduced instruction set) mostly selects the nor-flash to store the BIOS bootloader boot data, and in the RISC system. Many software developers will use the self-developed BIOS, so there will be a need to switch between the application and hardware BIOS during development and maintenance. If the problem of not being able to boot properly due to an error in updating the nor-flash data, it can only be repaired by an expensive burning recording device (such as JTAG) or by replacing nor-flash, which may cause troubles in development and maintenance.

由上述可知,目前BIOS修復方式仍舊非常不便利;有鑑於此,本案之發明人極力加以研究發明,終於研發完成本發明之一種新穎基本輸入輸出系統。 It can be seen from the above that the current BIOS repair method is still very inconvenient; in view of this, the inventor of the present invention has tried to study the invention and finally developed a novel basic input/output system of the present invention.

本發明之主要目的,在於提供一種新穎基本輸入輸出系統;其中,本發明係以一快閃記憶體晶片、一跳針開關與一邏輯閘構成可設置於主機板上的一新穎基本輸入輸出系統。於該新穎基本輸入輸出系統的操作中,使用者可選擇性地將跳針開關設定為“High”或“Low”,並同時搭配主機板上的主處理器之通用型輸入/輸出埠來決定載入儲存於快閃記憶體晶片之一第一儲存區塊的第一開機程式,或者載入儲存於快閃記憶體晶片之一第二儲存區塊的第二開機程式。如此方式,使得本發明不僅實現雙開機程式(Dual Bootloader)啟動主機之強大改良,更同時以單顆快閃記憶體晶片實現了基本輸入輸出系統之開機程式的備援目的;並且,這樣的結果亦帶給開發者、使用者、維修人員極高的便利性。 The main object of the present invention is to provide a novel basic input/output system, wherein the present invention comprises a flash memory chip, a jumper switch and a logic gate to form a novel basic input/output system which can be disposed on the motherboard. . In the operation of the novel basic input/output system, the user can selectively set the jump switch to "High" or "Low", and simultaneously determine the general-purpose input/output port of the main processor on the motherboard. Loading a first booting program stored in one of the first storage blocks of the flash memory chip, or loading a second booting program stored in a second storage block of the flash memory chip. In this way, the present invention not only realizes a powerful improvement of the dual bootloader (Dual Bootloader) booting host, but also realizes the backup purpose of the booting program of the basic input/output system with a single flash memory chip; and, such a result It also brings great convenience to developers, users and maintenance personnel.

因此,為了達成本發明之主要目的,本案之發明人提出一種新穎基本輸入輸出系統,係設置於一主機之一主機板之上,並包括: 一快閃記憶體晶片,係安裝於該主機板之上以耦接該主機板之上的一主處理器,並儲存具有一第一開機程式以及映射於該第一開機程式之一第二開機程式的一基本輸入輸出系統;其中,該第一開機程式與該第二開機程式係分別儲存於該快閃記憶體晶片之一第一儲存區塊與一第二儲存區塊;一跳針開關,係安裝於該主機板之上並至少具有一偏壓腳位、一邏輯控制腳位與一接地腳位;以及一邏輯閘,係設置於該主機板之上並至少具有一第一邏輯輸入端、一第二邏輯輸入端與一邏輯輸出端;其中,該第一邏輯輸入端係耦接至該主處理器之一通用型輸入/輸出埠(General Purpose I/O,GPIO),該第二邏輯輸入端係耦接至該跳針開關之該邏輯控制腳位,且該邏輯輸出端係耦接至該快閃記憶體晶片;其中,該主處理器可透過該通用型輸入/輸出埠輸出一第一邏輯訊號至該第一邏輯輸入端,且藉由將一針腳套套於該跳針開關之上可使得跳針開關輸出一第二邏輯訊號至該第二邏輯輸入端,進而使得該邏輯閘對該第一邏輯訊號與該第二邏輯訊號進行邏輯運算後輸出一開機程式控制訊號至該快閃記憶體晶片,藉此方式選擇載入該第一開機程式或該第二開機程式。 Therefore, in order to achieve the main object of the present invention, the inventor of the present invention proposes a novel basic input/output system which is disposed on one of the motherboards of a host and includes: a flash memory chip mounted on the motherboard to couple a main processor on the motherboard, and having a first booting program and a second booting machine mapped to the first booting program a basic input/output system of the program; wherein the first booting program and the second booting program are respectively stored in one of the first storage block and the second storage block of the flash memory chip; a jump pin switch Mounted on the motherboard and having at least one biasing pin, a logic control pin and a ground pin; and a logic gate disposed on the motherboard and having at least a first logic input a second logic input and a logic output; wherein the first logic input is coupled to a general purpose input/output port (GPIO) of the main processor, the first The logic input terminal is coupled to the logic control pin of the jump pin switch, and the logic output is coupled to the flash memory chip; wherein the main processor can pass the universal input/output port Output a first logic signal to the first a logic input, and the sleeve switch outputs a second logic signal to the second logic input by inserting a pin on the jumper switch, so that the logic gate is coupled to the first logic signal The second logic signal is logically operated to output a boot program control signal to the flash memory chip, thereby selectively loading the first boot program or the second boot program.

<本發明> <present invention>

11‧‧‧快閃記憶體晶片 11‧‧‧Flash memory chip

12‧‧‧跳針開關 12‧‧‧jumper switch

13‧‧‧邏輯閘 13‧‧‧Logic gate

2‧‧‧主處理器 2‧‧‧Main processor

20‧‧‧輸入/輸出單元 20‧‧‧Input/output unit

31‧‧‧控制匯流排 31‧‧‧Control bus

116‧‧‧控制腳位 116‧‧‧Control feet

32‧‧‧資料匯流排 32‧‧‧ data bus

117‧‧‧資料腳位 117‧‧‧Information pin

33‧‧‧位址匯流排 33‧‧‧ address bus

118‧‧‧位址腳位 118‧‧‧ address feet

111‧‧‧第一開機程式 111‧‧‧First boot program

112‧‧‧第二開機程式 112‧‧‧Second boot program

110‧‧‧基本輸入輸出系統 110‧‧‧Basic input and output system

111a‧‧‧第一儲存區塊 111a‧‧‧First storage block

112a‧‧‧第二儲存區塊 112a‧‧‧Second storage block

121‧‧‧偏壓腳位 121‧‧‧ bias pin

122‧‧‧邏輯控制腳位 122‧‧‧Logic control pin

123‧‧‧接地腳位 123‧‧‧ Grounding feet

131‧‧‧第一邏輯輸入端 131‧‧‧First logic input

132‧‧‧第二邏輯輸入端 132‧‧‧Second logic input

133‧‧‧邏輯輸出端 133‧‧‧Logic output

21‧‧‧通用型輸入/輸出埠 21‧‧‧General-purpose input/output埠

1181‧‧‧最高位元位址腳位 1181‧‧‧Highest bit address

15‧‧‧針腳套 15‧‧‧ Pins

Vcc‧‧‧外接偏壓 Vcc‧‧‧ external bias

<習知> <知知>

第一圖係本發明之一種新穎基本輸入輸出系統的示意架構圖;第二圖係邏輯閘的電路架構圖;以及第三A圖與第三B圖係跳針開關之上視圖。 The first figure is a schematic architecture diagram of a novel basic input/output system of the present invention; the second diagram is a circuit architecture diagram of a logic gate; and the third A diagram and the third B diagram are top views of a jumper switch.

為了能夠更清楚地描述本發明所提出之一種新穎基本輸入輸出系統,以下將配合圖式,詳盡說明本發明之較佳實施例。 In order to more clearly describe a novel basic input and output system proposed by the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the drawings.

請參閱第一圖,係本發明之一種新穎基本輸入輸出系統的示意架構圖。如第一圖所示,本發明之新穎基本輸入輸出系統係設置於一主機之一主機板之上,其主要包括:一快閃記憶體晶片11、一跳針開關12與一邏輯閘13;其中,該快閃記憶體晶片11為一NOR型式快閃記憶體晶片,係安裝於該主機板之上以耦接該主機板之上的一主處理器2。 Please refer to the first figure, which is a schematic architecture diagram of a novel basic input/output system of the present invention. As shown in the first figure, the novel basic input/output system of the present invention is disposed on a host board of a host, and mainly includes: a flash memory chip 11, a jump pin switch 12 and a logic gate 13; The flash memory chip 11 is a NOR type flash memory chip mounted on the motherboard to couple a main processor 2 on the motherboard.

承上述之說明,該主處理器2之一輸入/輸出單元20係透過一控制匯流排31(Control Bus)而耦接至該快閃記憶體晶片11之複數個控制腳位116,並且該輸入/輸出單元20係透過一資料匯流排32(Data Bus)而耦接至該快閃記憶 體晶片11之複數個資料腳位117,同時該輸入/輸出單元20係透過一位址匯流排33(Address Bus)而耦接至該快閃記憶體晶片11之複數個位址腳位118。再者,該快閃記憶體晶片11係儲存具有一第一開機程式111以及映射於該第一開機程式之一第二開機程式112的一基本輸入輸出系統110(Basic Input/Output System,BIOS)。於本發明之中,特別地,該快閃記憶體晶片11係被分割為一第一儲存區塊111a與一第二儲存區塊112a,用以分別儲存該第一開機程式111與該第二開機程式112。必須補充說明的是,此處所指的開機程式係BIOS之中所使用的X-loader與Uboot。 In the above description, one of the input/output units 20 of the main processor 2 is coupled to a plurality of control pins 116 of the flash memory chip 11 through a control bus 31 (Control Bus), and the input /output unit 20 is coupled to the flash memory through a data bus 32 (Data Bus) The plurality of data pins 117 of the bulk wafer 11 are coupled to the plurality of address pins 118 of the flash memory chip 11 via an address bus 33 (Address Bus). Furthermore, the flash memory chip 11 stores a basic input/output system 110 (Basic Input/Output System, BIOS) having a first booting program 111 and a second booting program 112 mapped to the first booting program. . In the present invention, in particular, the flash memory chip 11 is divided into a first storage block 111a and a second storage block 112a for storing the first booting program 111 and the second, respectively. Boot program 112. It must be added that the boot program referred to here is the X-loader and Uboot used in the BIOS.

繼續地說明本發明之新穎基本輸入輸出系統。如第一圖所示,該跳針開關12係安裝於該主機板之上並至少具有一偏壓腳位121、一邏輯控制腳位122與一接地腳位123。該邏輯閘13係設置於該主機板之上並至少具有一第一邏輯輸入端131、一第二邏輯輸入端132與一邏輯輸出端133;其中,該第一邏輯輸入端131係耦接至該主處理器2之一通用型輸入/輸出埠21(General Purpose I/O,GPIO),該第二邏輯輸入端132係耦接至該跳針開關12之該邏輯控制腳位122,且該邏輯輸出端133係耦接至該快閃記憶體晶片11之該複數個位址腳位118的一最高位元位址腳位1181。如此設置,該主處理器2可透過該通用型輸入/輸出埠21輸出一第一邏輯訊號至該第一邏輯輸入端 131,且藉由將一針腳套15套於該跳針開關12之上可使得跳針開關12輸出一第二邏輯訊號至該第二邏輯輸入端132,進而使得該邏輯閘13對該第一邏輯訊號與該第二邏輯訊號進行邏輯運算後輸出一開機程式控制訊號至該快閃記憶體晶片11,藉此方式選擇載入該第一開機程式111或該第二開機程式112。 The novel basic input and output system of the present invention will be further described. As shown in the first figure, the jumper switch 12 is mounted on the motherboard and has at least one biasing pin 121, a logic control pin 122 and a ground pin 123. The logic gate 13 is disposed on the motherboard and has at least a first logic input 131, a second logic input 132 and a logic output 133. The first logic input 131 is coupled to the The main processor 2 is a general-purpose input/output port 21 (GPIO), and the second logic input terminal 132 is coupled to the logic control pin 122 of the jumper switch 12, and the The logic output 133 is coupled to a highest bit address pin 1181 of the plurality of address pins 118 of the flash memory chip 11. In this way, the main processor 2 can output a first logic signal to the first logic input through the universal input/output port 21 131, and by placing a pin sleeve 15 on the jumper switch 12, the jumper switch 12 outputs a second logic signal to the second logic input terminal 132, thereby causing the logic gate 13 to be the first The logic signal is logically operated with the second logic signal to output a boot program control signal to the flash memory chip 11, thereby selectively loading the first boot program 111 or the second boot program 112.

繼續地參閱第一圖,並請同時參閱第二圖,係邏輯閘的電路架構圖。如第一圖所示,本發明係以一XOR邏輯閘作為該邏輯閘13,其中,XOR邏輯閘之真值表如下所示。 Continue to refer to the first figure, and also refer to the second figure, which is the circuit diagram of the logic gate. As shown in the first figure, the present invention uses an XOR logic gate as the logic gate 13, wherein the truth table of the XOR logic gate is as follows.

並且,如第二圖所示,熟稔數位電路技術之工程人員應可輕易地以四個NAND邏輯閘構成本發明之該邏輯閘13,且由四個NAND邏輯閘所構成之邏輯閘13,其真值表如上表所示。 Moreover, as shown in the second figure, an engineer skilled in the digital circuit technology should be able to easily form the logic gate 13 of the present invention with four NAND logic gates, and a logic gate 13 composed of four NAND logic gates. The truth table is shown in the table above.

如此,上述說明係已完整說明本發明之新穎基本輸入輸出系統的架構與組成元件。接著,將繼續說明本發明之新穎基本輸入輸出系統的技術特徵。請參閱第一圖,並請同時參閱第三A圖與第三B圖,係該跳針開關12之上 視圖。如第三A圖所示,若使用一針腳套15套住該跳針開關12之偏壓腳位121與邏輯控制腳位122,則邏輯控制腳位122與偏壓腳位121會相互短路;此時,由於偏壓腳位121係耦接一外接偏壓Vcc,因此邏輯控制腳位122係透過偏壓腳位121而耦接該外接偏壓Vcc,進而輸出高準位的一第二邏輯訊號。 Thus, the foregoing description has fully described the architecture and components of the novel basic input and output system of the present invention. Next, the technical features of the novel basic input/output system of the present invention will be further explained. Please refer to the first figure, and please refer to the third A picture and the third B picture at the same time, above the jump pin switch 12 view. As shown in FIG. 3A, if a pin sleeve 15 is used to cover the bias pin 121 and the logic pin 122 of the jumper switch 12, the logic pin 122 and the bias pin 121 are short-circuited to each other; At this time, since the bias pin 121 is coupled to an external bias voltage Vcc, the logic control pin 122 is coupled to the external bias voltage Vcc through the bias pin 121, thereby outputting a second logic of high level. Signal.

承上述說明,根據高準位的該第二邏輯訊號,該主處理器2可透過該通用型輸入/輸出埠21輸出低準位的該第一邏輯訊號,藉此方式分別令該第一開機程式111與該第二開機程式112為該主要開機程式與該備援開機程式;或者,該主處理器2可透過該通用型輸入/輸出埠21輸出高準位的該第一邏輯訊號,藉此方式分別令該第二開機程式112與該第一開機程式111為該主要開機程式與該備援開機程式。 According to the above description, according to the second logic signal of the high level, the main processor 2 can output the first logic signal of the low level through the universal input/output port 21, thereby respectively making the first power on. The program 111 and the second booting program 112 are the main booting program and the backup booting program; or the main processor 2 can output the first logical signal of the high level through the general-purpose input/output port 21, In this manner, the second booting program 112 and the first booting program 111 are the primary booting program and the backup booting program, respectively.

此外,如第三B圖所示,若使用一針腳套15套住該跳針開關12之邏輯控制腳位122與接地腳位123,則邏輯控制腳位122與接地腳位123會相互短路;此時,由於接地腳位123係耦接地,因此邏輯控制腳位122係透過接地腳位123而接地,進而輸出低準位的一第二邏輯訊號。因此,根據低準位的該第二邏輯訊號,該主處理器2可透過該通用型輸入/輸出埠21輸出高準位的該第一邏輯訊號,藉此方式分別令該第一開機程式111與該第二開機程 式112為該備援開機程式與該主要開機程式;或者,該主處理器2可透過該通用型輸入/輸出埠21輸出低準位的該第一邏輯訊號,藉此方式分別令該第二開機程式112與該第一開機程式111為該備援開機程式與該主要開機程式。 In addition, as shown in FIG. B, if a pin sleeve 15 is used to cover the logic control pin 122 and the ground pin 123 of the jumper switch 12, the logic control pin 122 and the ground pin 123 are short-circuited to each other; At this time, since the ground pin 123 is coupled to the ground, the logic control pin 122 is grounded through the ground pin 123, and then outputs a second logic signal of a low level. Therefore, the main processor 2 can output the first logic signal of the high level through the general-purpose input/output port 21 according to the second logic signal of the low level, thereby respectively causing the first booting program 111 With the second boot process The mode 112 is the backup booting program and the main booting program; or the main processor 2 can output the low level first logical signal through the universal input/output port 21, thereby making the second The booting program 112 and the first booting program 111 are the backup booting program and the main booting program.

如此上述說明係已完整介紹本發明之新穎基本輸入輸出系統的架構與技術特徵;並且,經由上述可以得知本發明之新穎基本輸入輸出系統係具有以下之優點: The above description has completely introduced the architecture and technical features of the novel basic input/output system of the present invention; and, through the above, it can be known that the novel basic input/output system of the present invention has the following advantages:

(1)本發明係以一快閃記憶體晶片11、一跳針開關12與一邏輯閘13構成可設置於主機板上的一新穎基本輸入輸出系統。於該新穎基本輸入輸出系統的操作中,使用者可選擇性地將該跳針開關12設定為“High”或“Low”,同時搭配主機板上的主處理器2之通用型輸入/輸出埠21來決定載入儲存於快閃記憶體晶片11之一第一儲存區塊111a的第一開機程式111,或者載入儲存於快閃記憶體晶片11之一第二儲存區塊112a的第二開機程式112。如此方式,使得本發明不僅實現雙開機程式(Dual Bootloader)啟動主機之強大改良,更同時以單顆快閃記憶體晶片11實現了基本輸入輸出系統之開機程式的備援目的;並且,這樣的結果亦帶給開發者、使用者、維修人員極高的便利性。 (1) The present invention comprises a flash memory chip 11, a jumper switch 12 and a logic gate 13 to form a novel basic input/output system which can be disposed on a motherboard. In the operation of the novel basic input/output system, the user can selectively set the jumper switch 12 to "High" or "Low", together with the general-purpose input/output of the main processor 2 on the motherboard. 21, determining to load the first booting program 111 stored in one of the first storage blocks 111a of the flash memory chip 11, or loading the second booting program 112a stored in one of the second memory blocks 112a of the flash memory chip 11. Boot program 112. In this way, the present invention not only realizes a powerful improvement of the dual bootloader (Dual Bootloader) booting host, but also realizes the backup purpose of the booting program of the basic input/output system with a single flash memory chip 11; and, such a The results also bring great convenience to developers, users, and maintenance personnel.

(2)此外,當系統顯示載入第一開機程式111(或第二開機程式112)失敗時,開發者、使用者或維修人員可藉由針腳套15改變跳針開關12之“High”或“Low”,使得系統可 載入另一之正常的開機程式,以利系統正常運行。 (2) In addition, when the system displays that the loading of the first booting program 111 (or the second booting program 112) fails, the developer, the user, or the maintenance personnel can change the "High" of the jumper switch 12 by the pin cover 15 or "Low" makes the system available Load another normal boot program to get the system up and running.

必須加以強調的是,上述之詳細說明係針對本發明可行實施例之具體說明,惟該實施例並非用以限制本發明之專利範圍,凡未脫離本發明技藝精神所為之等效實施或變更,均應包含於本案之專利範圍中。 It is to be understood that the foregoing detailed description of the embodiments of the present invention is not intended to Both should be included in the scope of the patent in this case.

11‧‧‧快閃記憶體晶片 11‧‧‧Flash memory chip

12‧‧‧跳針開關 12‧‧‧jumper switch

13‧‧‧邏輯閘 13‧‧‧Logic gate

2‧‧‧主處理器 2‧‧‧Main processor

20‧‧‧輸入/輸出單元 20‧‧‧Input/output unit

31‧‧‧控制匯流排 31‧‧‧Control bus

116‧‧‧控制腳位 116‧‧‧Control feet

32‧‧‧資料匯流排 32‧‧‧ data bus

117‧‧‧資料腳位 117‧‧‧Information pin

33‧‧‧位址匯流排 33‧‧‧ address bus

118‧‧‧位址腳位 118‧‧‧ address feet

111‧‧‧第一開機程式 111‧‧‧First boot program

112‧‧‧第二開機程式 112‧‧‧Second boot program

110‧‧‧基本輸入輸出系統 110‧‧‧Basic input and output system

111a‧‧‧第一儲存區塊 111a‧‧‧First storage block

112a‧‧‧第二儲存區塊 112a‧‧‧Second storage block

121‧‧‧偏壓腳位 121‧‧‧ bias pin

122‧‧‧邏輯控制腳位 122‧‧‧Logic control pin

123‧‧‧接地腳位 123‧‧‧ Grounding feet

131‧‧‧第一邏輯輸入端 131‧‧‧First logic input

132‧‧‧第二邏輯輸入端 132‧‧‧Second logic input

133‧‧‧邏輯輸出端 133‧‧‧Logic output

21‧‧‧通用型輸入/輸出埠 21‧‧‧General-purpose input/output埠

1181‧‧‧最高位元位址腳位 1181‧‧‧Highest bit address

15‧‧‧針腳套 15‧‧‧ Pins

Vcc‧‧‧外接偏壓 Vcc‧‧‧ external bias

Claims (9)

一種新穎基本輸入輸出系統,係設置於一主機之一主機板之上,並包括:一快閃記憶體晶片,係安裝於該主機板之上以耦接該主機板之上的一主處理器,並儲存具有一第一開機程式以及映射於該第一開機程式之一第二開機程式的一基本輸入輸出系統;其中,該第一開機程式與該第二開機程式係分別儲存於該快閃記憶體晶片之一第一儲存區塊與一第二儲存區塊;一跳針開關,係安裝於該主機板之上並至少具有一偏壓腳位、一邏輯控制腳位與一接地腳位;以及一邏輯閘,係設置於該主機板之上並至少具有一第一邏輯輸入端、一第二邏輯輸入端與一邏輯輸出端;其中,該第一邏輯輸入端係耦接至該主處理器之一通用型輸入/輸出埠(General Purpose I/O,GPIO)),該第二邏輯輸入端係耦接至該跳針開關之該邏輯控制腳位,且該邏輯輸出端係耦接至該快閃記憶體晶片;其中,該主處理器可透過該通用型輸入/輸出埠輸出一第一邏輯訊號至該第一邏輯輸入端,且藉由將一針腳套套於該跳針開關之上可使得跳針開關輸出一第二邏輯訊號至該第二邏輯輸入端,進而使得該邏輯閘對該第一邏輯訊號與該第二邏輯訊號進行邏輯運算後 輸出一開機程式控制訊號至該快閃記憶體晶片,藉此方式選擇載入該第一開機程式或該第二開機程式。 A novel basic input/output system is disposed on a motherboard of a host, and includes: a flash memory chip mounted on the motherboard to couple a main processor on the motherboard And storing a basic input/output system having a first booting program and a second booting program mapped to the first booting program; wherein the first booting program and the second booting program are respectively stored in the flashing a first storage block and a second storage block of the memory chip; a jump pin switch mounted on the motherboard and having at least one biasing pin, a logic control pin and a ground pin And a logic gate disposed on the motherboard and having at least a first logic input, a second logic input, and a logic output; wherein the first logic input is coupled to the main a general purpose input/output port (GPIO) of the processor, the second logic input is coupled to the logic control pin of the jump pin switch, and the logic output is coupled To the flash memory chip; The main processor can output a first logic signal to the first logic input terminal through the universal input/output port, and output a jump pin switch by placing a pin on the jump pin switch. a second logic signal to the second logic input, so that the logic gate performs a logic operation on the first logic signal and the second logic signal A boot program control signal is outputted to the flash memory chip, thereby selectively loading the first boot program or the second boot program. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,該快閃記憶體晶片為一NOR型式快閃記憶體晶片。 The novel basic input/output system according to claim 1, wherein the flash memory chip is a NOR type flash memory chip. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,該邏輯閘為一XOR邏輯閘。 The novel basic input/output system of claim 1, wherein the logic gate is an XOR logic gate. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,該邏輯閘係由四個NAND邏輯閘所構成。 The novel basic input/output system of claim 1, wherein the logic gate is composed of four NAND logic gates. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,當該跳針開關之該邏輯控制腳位所輸出的該第二邏輯訊號為一高準位訊號時,則該第一開機程式即為該基本輸入輸出系統之一主要開機程式,且該第二開機程式為一備援開機程式。 The novel basic input/output system according to claim 1, wherein when the second logic signal output by the logic control pin of the jump pin switch is a high level signal, the first power on The program is one of the main booting programs of the basic input and output system, and the second booting program is a backup booting program. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,當該跳針開關之該邏輯控制腳位所輸出的該第二邏輯訊號為一低準位訊號時,則該第二開機程式即為該基本輸入輸出系統之一主要開機程式,且該第一開 機程式為一備援開機程式。 The novel basic input/output system according to claim 1, wherein when the second logic signal output by the logic control pin of the jump pin switch is a low level signal, the second power on The program is one of the main booting programs of the basic input and output system, and the first open The program is a backup boot program. 如申請專利範圍第1項所述之新穎基本輸入輸出系統,其中,當該邏輯閘之該邏輯輸出端係耦接至該快閃記憶體晶片之複數個位址腳位之一最高位元位址腳位。 The novel basic input/output system of claim 1, wherein the logic output of the logic gate is coupled to one of a plurality of address pins of the flash memory chip. Address pin. 如申請專利範圍第5項所述之新穎基本輸入輸出系統,其中,根據高準位的該第二邏輯訊號,該主處理器可透過該通用型輸入/輸出埠輸出低準位的該第一邏輯訊號,藉此方式分別令該第一開機程式與該第二開機程式為該主要開機程式與該備援開機程式;或者,該主處理器可透過該通用型輸入/輸出埠輸出高準位的該第一邏輯訊號,藉此方式分別令該第二開機程式與該第一開機程式為該主要開機程式與該備援開機程式。 The novel basic input/output system according to claim 5, wherein, according to the second logic signal of the high level, the main processor can output the first level of the low level through the universal input/output port a logic signal, wherein the first boot program and the second boot program are respectively the main boot program and the backup boot program; or the main processor can output a high level through the universal input/output port The first logic signal is configured to cause the second booting program and the first booting program to be the primary booting program and the backup booting program, respectively. 如申請專利範圍第6項所述之新穎基本輸入輸出系統,其中,根據低準位的該第二邏輯訊號,該主處理器可透過該通用型輸入/輸出埠輸出高準位的該第一邏輯訊號,藉此方式分別令該第一開機程式與該第二開機程式為該備援開機程式與該主要開機程式;或者,該主處理器可透過該通用型輸入/輸出埠輸出低準位的該第一邏輯訊號,藉此方式分別令該第二開機程式與該第一開 機程式為該備援開機程式與該主要開機程式。 The novel basic input/output system according to claim 6, wherein the main processor can output the first level of the high level through the universal input/output port according to the second logic signal of the low level a logic signal, wherein the first boot program and the second boot program are respectively the backup boot program and the main boot program; or the main processor can output a low level through the general-purpose input/output port The first logic signal, in this way, respectively, the second boot program and the first open The program is the backup boot program and the main boot program.
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