TW201614485A - Compressing instruction queue for a microprocessor - Google Patents
Compressing instruction queue for a microprocessorInfo
- Publication number
- TW201614485A TW201614485A TW104132590A TW104132590A TW201614485A TW 201614485 A TW201614485 A TW 201614485A TW 104132590 A TW104132590 A TW 104132590A TW 104132590 A TW104132590 A TW 104132590A TW 201614485 A TW201614485 A TW 201614485A
- Authority
- TW
- Taiwan
- Prior art keywords
- queue
- microprocessor
- storage locations
- redirect logic
- locations
- Prior art date
Links
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201462060374P | 2014-10-06 | 2014-10-06 | |
US14/569,313 US10216520B2 (en) | 2014-10-06 | 2014-12-12 | Compressing instruction queue for a microprocessor |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201614485A true TW201614485A (en) | 2016-04-16 |
TWI574206B TWI574206B (zh) | 2017-03-11 |
Family
ID=55632874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104132590A TWI574206B (zh) | 2014-10-06 | 2015-10-02 | 微處理器及其所用之壓縮指令佇列、以及將微指令壓縮至其指令佇列之方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10216520B2 (zh) |
TW (1) | TWI574206B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10929136B2 (en) | 2018-04-11 | 2021-02-23 | Futurewei Technologies, Inc. | Accurate early branch prediction using multiple predictors having different accuracy and latency in high-performance microprocessors |
US20190392287A1 (en) | 2018-06-22 | 2019-12-26 | Samsung Electronics Co., Ltd. | Neural processor |
US20200042322A1 (en) * | 2018-08-03 | 2020-02-06 | Futurewei Technologies, Inc. | System and method for store instruction fusion in a microprocessor |
US11671111B2 (en) | 2019-04-17 | 2023-06-06 | Samsung Electronics Co., Ltd. | Hardware channel-parallel data compression/decompression |
US11243766B2 (en) * | 2019-09-25 | 2022-02-08 | Intel Corporation | Flexible instruction set disabling |
US20210200538A1 (en) * | 2019-12-28 | 2021-07-01 | Intel Corporation | Dual write micro-op queue |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0436341B1 (en) * | 1990-01-02 | 1997-05-07 | Motorola, Inc. | Sequential prefetch method for 1, 2 or 3 word instructions |
JP2532300B2 (ja) * | 1990-10-17 | 1996-09-11 | 三菱電機株式会社 | 並列処理装置における命令供給装置 |
US5604909A (en) * | 1993-12-15 | 1997-02-18 | Silicon Graphics Computer Systems, Inc. | Apparatus for processing instructions in a computing system |
US5581717A (en) * | 1994-03-01 | 1996-12-03 | Intel Corporation | Decoding circuit and method providing immediate data for a micro-operation issued from a decoder |
US6442680B1 (en) | 1999-01-29 | 2002-08-27 | International Business Machines Corporation | Method and system for compressing reduced instruction set computer (RISC) executable code |
US6704856B1 (en) * | 1999-02-01 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Method for compacting an instruction queue |
US6185672B1 (en) * | 1999-02-19 | 2001-02-06 | Advanced Micro Devices, Inc. | Method and apparatus for instruction queue compression |
US6859870B1 (en) | 2000-03-07 | 2005-02-22 | University Of Washington | Method and apparatus for compressing VLIW instruction and sharing subinstructions |
JP3729759B2 (ja) | 2001-08-07 | 2005-12-21 | 株式会社ルネサステクノロジ | 圧縮された命令コードを読み出すマイクロコントローラ、命令コードを圧縮して格納するプログラムメモリ |
US7552316B2 (en) | 2004-07-26 | 2009-06-23 | Via Technologies, Inc. | Method and apparatus for compressing instructions to have consecutively addressed operands and for corresponding decompression in a computer system |
TWI320636B (en) | 2005-11-10 | 2010-02-11 | Realtek Semiconductor Corp | Method for compressing instruction code |
US10346173B2 (en) * | 2011-03-07 | 2019-07-09 | Oracle International Corporation | Multi-threaded instruction buffer design |
-
2014
- 2014-12-12 US US14/569,313 patent/US10216520B2/en active Active
-
2015
- 2015-10-02 TW TW104132590A patent/TWI574206B/zh active
Also Published As
Publication number | Publication date |
---|---|
US10216520B2 (en) | 2019-02-26 |
US20160098277A1 (en) | 2016-04-07 |
TWI574206B (zh) | 2017-03-11 |
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