TW201611304A - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device is provided, which includes a plurality of cup-shaped capacitors, a bottom supporting layer and a top supporting layer. The cup-shaped capacitors are located on a substrate. The bottom supporting layer is disposed on the substrate between a plurality of lower sidewalls of the cup-shaped capacitors. The top supporting layer is surrounded by a plurality of upper sidewalls of the cup-shaped capacitors. There is a gap between the top supporting layer and the bottom supporting layer. The top supporting layer includes a periphery supporting layer and a core supporting layer. The periphery supporting layer is disposed out of the cup-shaped capacitors and connects with the cup-shaped capacitors. The core supporting layer is disposed in the periphery supporting layer. And there is a space between the core supporting layer and the periphery supporting layer, and it connects to any adjacent two cup-shaped capacitors.

Description

Memory element and method of manufacturing same

The present invention relates to a memory element and a method of fabricating the same, and more particularly to a capacitor and a method of fabricating the same.

With the miniaturization of semiconductor technology, traditional capacitor processes are no longer sufficient. Researchers have developed dielectric materials with high dielectric constants and increased the surface area of capacitors to increase the capacitance of capacitors. In general, the most common way to increase surface area is to increase the height or size of the capacitor. However, the above-described manner easily causes a problem of insufficient mechanical strength of the capacitor itself and a problem of short-circuiting of adjacent capacitors. When the mechanical strength of the capacitor is insufficient, it is easy to find the phenomenon that the capacitor structure is deformed or even dumped; and when the adjacent capacitor is short-circuited, the reliability of the product is lowered. In view of this, how to avoid capacitors that are short-circuited by adjacent capacitors and have a reinforced structure at the same time has been highly noticed by the industry.

The invention provides a memory element and a manufacturing method thereof, which can avoid proximity The problem of capacitor short circuit.

The present invention provides a memory element and a method of fabricating the same that increase the mechanical strength of the capacitor.

The present invention provides a memory element that includes a plurality of cup capacitors, a bottom support layer, and a top support layer. A cup capacitor is located on the substrate. The bottom support layer is disposed on the substrate between the plurality of lower sidewalls of the cup capacitor. The top support layer is disposed around a plurality of upper sidewalls of the cup capacitor. The top support layer and the bottom support layer have a gap between each other. The top support layer includes a perimeter support layer and a core support layer. The peripheral support layer is disposed on the periphery of the cup capacitor and connected to the cup capacitor. The core support layer is disposed within the perimeter support layer. Moreover, the core support layer is separated from the peripheral support layer by a gap connecting any adjacent two cup capacitors.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A substrate is provided. There are a plurality of conductor regions on the substrate. A bottom support layer is formed on the substrate. The bottom support layer exposes the conductor area. A plurality of cup-shaped lower electrodes are formed on the substrate. The cup-shaped lower electrode is electrically connected to the conductor region. The bottom support layer is located between a plurality of lower sidewalls of the cup capacitor. A top support layer is formed on the substrate, which is disposed around a plurality of upper sidewalls of the cup capacitor. The top support layer and the bottom support layer have a gap between each other. The top support layer includes a perimeter support layer and a core support layer. The peripheral support layer is located on the periphery of the cup capacitor and is connected to the cup capacitor. The core support layer is located within the peripheral support layer and is separated from the peripheral support layer by a gap. The core support layer connects any two adjacent cup capacitors.

Based on the above, the embodiment of the present invention utilizes two cups arranged in any adjacent The core support layer between the capacitors avoids the Hole Expansion of the adjacent cup capacitors during the etching process, resulting in a short circuit problem of the adjacent cup capacitors. In addition, the core support layer of the embodiment of the present invention can provide additional mechanical strength to avoid deformation or even dumping of the cup capacitor of the embodiment of the present invention.

The above described features and advantages of the invention will be apparent from the following description.

10, 40, 50‧‧‧ Ditch

20, 60‧‧‧ openings

30, 70, 80 ‧ ‧ gap

32, 72‧‧‧ gap

100, 200‧‧‧ base

102, 126, 202, 226‧‧ dielectric layers

104, 204‧‧‧ conductor area

106, 110, 110a, 110b, 111, 118, 118a, 206, 210, 210a, 210b, 211, 218, 218a, 218b‧‧‧ support layer

108, 108a, 208, 208a‧‧‧ insulation

112, 120, 212, 220‧‧ ‧ cover layer

114, 122, 122a, 214, 222, 222a‧‧‧ photoresist layer

116, 118, 216, 218‧‧‧ material layers

116a, 116b, 216a, 216b‧‧ ‧ spacers

123, 223‧‧‧ grooves

124, 128, 224, 228‧‧ ‧ electrodes

130, 230‧‧‧ capacitors

219‧‧‧ fill layer

1A-1H are schematic top views of a manufacturing process of a memory device according to a first embodiment of the present invention.

2A to 2H are schematic cross-sectional views taken along line A-A of Figs. 1A to 1H, respectively.

3A to 3H are schematic cross-sectional views taken along line B-B of Figs. 1A to 1H, respectively.

4A-4F are top schematic views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

5A to 5F are schematic cross-sectional views taken along line A-A of Figs. 4A to 4F, respectively.

6A to 6F are schematic cross-sectional views taken along line B-B of Figs. 4A to 4F, respectively.

1A-1H are schematic top views of a manufacturing process of a memory device according to a first embodiment of the present invention. 2A to 2H are schematic cross-sectional views taken along line A-A of Figs. 1A to 1H, respectively. 3A to 3H are schematic cross-sectional views taken along line B-B of Figs. 1A to 1K, respectively.

Referring to FIG. 1A, FIG. 2A, and FIG. 3A simultaneously, first, the substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Then, a dielectric layer 102 and a plurality of conductor regions 104 are sequentially formed on the substrate 100. The material of the dielectric layer 102 may be, for example, ruthenium oxide, ruthenium oxynitride or a low dielectric constant material, and the formation method thereof may be formed by chemical vapor deposition. Conductor region 104 is disposed in dielectric layer 102. In one embodiment, the conductor regions 104 are arranged in an array. The material of the conductor region 104 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. In an embodiment, the conductor region 104 can be electrically connected, for example, to a buried word line in the substrate 100.

Next, a bottom support layer 106, an insulating layer 108, and a peripheral support layer 110 are sequentially formed on the substrate 100. The bottom support layer 106 and the peripheral support layer 110 may be, for example, tantalum nitride (SiN), bismuth oxynitride (SiON), lanthanum oxynitride (SiCON), tantalum carbide (SiC), or a combination thereof, and the formation method thereof may utilize chemistry. Vapor deposition method. bottom The thickness of the support layer 106 is, for example, 50 angstroms to 1500 angstroms; the thickness of the peripheral support layer 110 is, for example, 50 angstroms to 2,500 angstroms.

The material of the insulating layer 108 may be, for example, cerium oxide or borophosphoquinone glass (BPSG), which may be formed by chemical vapor deposition. The thickness of the insulating layer 108 is, for example, 5,000 angstroms to 30,000 angstroms.

Referring to FIG. 1A, FIG. 2A and FIG. 3A simultaneously, the mask layer 112 and the patterned photoresist layer 114 are sequentially formed on the peripheral support layer 110. In an embodiment, the mask layer 112 may be, for example, a composite layer composed of a hard mask layer and a bottom anti-reflection layer, but the invention is not limited thereto. The material of the hard mask layer may be, for example, a tantalum material, a metal material or a carbon material. The material of the bottom anti-reflection layer may be, for example, an organic polymer, carbon or bismuth oxynitride or the like. The method of forming the hard mask layer and the bottom anti-reflection layer described above can be formed by chemical vapor deposition. The material of the patterned photoresist layer 114 is, for example, carbon, a photoresist material, or an oxynitride.

Referring to FIG. 1A, FIG. 1B, FIG. 2A, FIG. 2B, FIG. 3A and FIG. 3B, the patterned photoresist layer 114 is used as a mask to perform an etching process to form the peripheral supporting layer 110a. The peripheral support layer 110a has a trench 10 therein that exposes the surface of the insulating layer 108. The location of the trench 10 partially overlaps the location of the plurality of conductor regions 104. The shape of the trench 10 includes a square, a rectangle, a racetrack or a star. Next, the patterned photoresist layer 114 and/or the mask layer 112 remaining on the peripheral support layer 110a are removed.

Referring to FIG. 1B, FIG. 2B, and FIG. 3B simultaneously, a spacer material layer 116 is formed on the trench 10. The spacer material layer 116 covers the top surface of the peripheral support layer 110a and the sidewalls and bottom of the trench 10 (as shown in Figures 2D and 3D). In an embodiment The spacer material layer 116 may conformally cover the top surface of the peripheral support layer 110a and the sidewalls and the bottom of the trench 10. The material of the spacer material layer 116 is, for example, cerium oxide (SiO), cerium oxynitride (SiON) or borophosphoquinone glass (BPSG). The formation method is, for example, a chemical vapor deposition method. The material of the spacer material layer 116 is not limited to the above, as long as the etching selectivity ratio with the peripheral support layer 110a is a range covered by the present invention.

Next, referring to FIG. 1C , FIG. 2C , and FIG. 3C , the spacer material layer 116 is anisotropically etched to form the spacers 116 a on the sidewalls of the trenches 10 . Thereafter, a core support layer 118 is formed in the area surrounded by the spacers 116a. Specifically, after the spacers 116a are formed on the sidewalls of the trenches 10, a support material layer is formed on the peripheral support layer 110a to cover the top surface of the peripheral support layer 110a, the sidewalls of the spacers 116a, and the bottom of the trenches 10 (not Painted). Next, an etch back process is performed on the support material layer, a portion of the support material layer is removed, and the top surface of the peripheral support layer 110a is exposed to form a core support layer 118 in the trench 10 (as shown in FIGS. 2F and 3F). In an embodiment, the core support layer 118 can be, for example, in the form of a block. The shape of the core support layer 118 includes a square, a rectangle, a racetrack shape, or a star shape. The core support layer 118 may be, for example, tantalum nitride (SiN), lanthanum oxynitride (SiON), lanthanum oxynitride (SiCON), tantalum carbide (SiC), or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. . In an embodiment, the etch back process can be, for example, a dry etch process or a wet etch process.

Referring to FIG. 1D, FIG. 2D and FIG. 3D simultaneously, the mask layer 120 and the patterned photoresist layer 122 are sequentially formed on the substrate 100. In an embodiment, the mask layer 120 may be, for example, a composite layer composed of a hard mask layer and a bottom anti-reflection layer, and the present invention is not limited thereto. The material of the hard mask layer may be, for example, a tantalum material, a metal material or a carbon material. The germanium material may be, for example, undoped polycrystalline germanium or cerium oxynitride (SiON) or the like. The material of the bottom anti-reflection layer may be, for example, an organic polymer, carbon or bismuth oxynitride or the like. The method of forming the hard mask layer and the bottom anti-reflection layer described above can be formed by chemical vapor deposition. The material of the patterned photoresist layer 122 may be, for example, carbon, a photoresist type material, or an oxynitride or the like. The patterned photoresist layer 122 has a plurality of recesses 123. The position of the groove 123 corresponds to the position of the conductor region 104 below.

Referring to FIG. 1E, FIG. 1F, FIG. 2E, FIG. 2F, FIG. 3E and FIG. 3F, the patterned photoresist layer 122 is used as a mask to perform an etching process to remove a portion of the mask layer 120 to form a patterned layer. Mask layer 120a. Then, using the patterned mask layer 120a as a mask, an etching process is performed to remove a portion of the peripheral support layer 110a, the core support layer 118, the insulating layer 108, and the bottom support layer 106 to form a peripheral support layer 110b and a core support layer. 118a, insulating layer 108a and bottom support layer 106a, and forming a plurality of openings 20 exposing a plurality of conductor regions 104. The patterned photoresist layer 122 is also removed simultaneously during the etching process. In addition, since the material around each opening 20 is substantially the same (mostly the peripheral supporting layer 110b), it can reduce the difference in etching rate due to the difference in etching materials when the etching process is performed, thereby causing the adjacent opening 20 to communicate. Case. In this way, the subsequent capacitor short circuit problem due to the communication of the adjacent opening 20 can be avoided.

Referring to FIG. 1F, FIG. 2F and FIG. 3F simultaneously, a lower electrode 124 is formed on the inner side and the bottom of each opening 20. Specifically, the conformal terrain is first formed on the substrate 100. A layer of electrode material is formed (not shown). A layer of lower electrode material covers the inside and the bottom of each opening 20 and the top surface of the mask layer 120a. Next, an anisotropic etching process is performed to remove a portion of the lower electrode material layer to expose the top surface of the mask layer 120a to form a lower electrode 124 on the inner side and the bottom of each opening 20. The lower electrode 124 in each opening 20 is electrically connected to the corresponding conductor region 104. The material of the lower electrode 124 may be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), aluminum (Al), copper (Cu) or metal telluride, which can be utilized. Formed by chemical vapor deposition.

Referring to FIG. 1F, FIG. 1G, FIG. 2F, FIG. 2G, FIG. 3F and FIG. 3G, an isotropic etching process is performed to remove the patterned mask layer 120a, the spacers 116b and the insulating layer 108a in the core supporting layer. A gap 30 is formed between the 118a and the peripheral support layer 110b. Since the materials of the peripheral support layer 110b, the core support layer 118a and the spacers 116b and the insulating layer 108a are different, and the isotropic etching process has high etching options for the peripheral support layer 110b, the core support layer 118a and the spacers 116b, and the insulating layer 108a. Therefore, the etching rate of the peripheral support layer 110b and the core support layer 118a is slower. Then, the etching liquid flows in from the gap 30, and the insulating layer 108a is removed to form a gap (Gap) 32 between the bottom supporting layer 106a and the peripheral supporting layer 110b and the core supporting layer 118a, exposing the outer side of the portion of the lower electrode 124. That is, the outer side of the lower electrode 124 in the opening 20 is exposed. At this time, after the insulating layer 108a is completely removed, an intermediate hollow structure is formed. The bottom support layer 106a, the peripheral support layer 110b, the core support layer 118a, and the lower electrode 124 support the architecture of the memory element of the first embodiment of the present invention. Since the patterned mask layer 120a on the peripheral support layer 110b is also removed, the top surface of the lower electrode 124 is higher than the top surfaces of the peripheral support layer 110b and the core support layer 118a. Thereby, the charge storage capacity of the cup capacitor 130 formed in the subsequent process is increased (as shown in FIG. 2H and FIG. 3H below). In one embodiment, the isotropic etching process includes a wet etching process, which may be, for example, using an etch buffer (Buffer Oxide Etchant, BOE), hydrofluoric acid (HF), diluted hydrofluoric acid (Diluted Hydrogen Fluoride). , DHF) or buffered hydrofluoric acid (BHF), etc.

As shown in FIG. 1G, the peripheral support layer 110b is surrounded by the core support layer 118a, and has a gap 30 between the peripheral support layer 110b and the core support layer 118a. The peripheral support layer 110b and the core support layer 118a constitute a top support layer 111, and the top support layer 111 is disposed around a plurality of upper sidewalls of the lower electrode 124. Since there is a core support layer 118a between any two adjacent openings 20, and the material of the core support layer 118a and the spacers 116b have a high etching selectivity ratio, it can avoid excessive opening 20 in the above isotropic etching process. The case of reaming. In addition, the core support layer 118a provides additional mechanical strength to support the architecture of the memory element of the first embodiment of the present invention.

Referring to FIG. 1H, FIG. 2H and FIG. 3H simultaneously, a dielectric layer 126 and an upper electrode 128 are conformally formed on the lower electrode 124 to form a plurality of cup capacitors 130. The upper electrode 128 also covers the bottom support layer 106a, the peripheral support layer 110b, and the core support layer 118a. The dielectric layer 126 is interposed between the upper electrode 128 and the lower electrode 124, and between the upper electrode 128 and the bottom support layer 106a, between the upper electrode 128 and the peripheral support layer 110b, and the upper electrode 128 and the core support layer 118a. between. In one embodiment, the dielectric layer 126 comprises a high dielectric constant material layer, the material of which may be, for example, hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide. (TiO), lanthanum oxide (LaO), yttrium oxide (YO), yttrium oxide (GdO), oxygen Tamarind (TaO) or a combination thereof. The material of the upper electrode 126 may be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), aluminum (Al), copper (Cu), or metal telluride. The method of forming the dielectric layer 124 and the upper electrode 126 can be formed by a chemical vapor deposition method or an atomic layer deposition (ALD) process.

Referring to FIGS. 1H and 3H simultaneously, the memory element of the first embodiment of the present invention includes a plurality of cup capacitors 130, a bottom support layer 106a, and a top support layer 111. A cup capacitor 130 is located on the substrate 100. The bottom support layer 106a is disposed on the substrate 100 between the plurality of lower sidewalls of the cup capacitor 130. The top support layer 111 is disposed around a plurality of upper sidewalls of the cup capacitor 130. More specifically, the top support layer 111 includes a peripheral support layer 110b and a core support layer 118a. The peripheral support layer 110b is disposed on the periphery of the cup capacitor 130 and connected to the cup capacitor 130. The core support layer 118a is disposed within the peripheral support layer 110b. The peripheral support layer 110b, the core support layer 118a and the bottom support layer 106a have a gap 32 therebetween. There is a gap 30 between the core support layer 118a and the peripheral support layer 110b, which connects any two adjacent cup capacitors 130. In an embodiment, the gap 32 between the peripheral support layer 110b, the core support layer 118a and the bottom support layer 106a is filled with air. Since the dielectric constant of the filling air approaches 1, it is less likely to generate parasitic capacitance between adjacent cup capacitors 130.

The cup capacitor 130 includes a plurality of lower electrodes 124, an upper electrode 128, and a dielectric layer 126. The lower electrode 124 is located on the substrate 100, wherein the lower electrode 124 can be, for example, a cup-shaped lower electrode. A plurality of lower sidewalls of the lower electrode 124 are connected to the bottom support layer 106a. A plurality of upper side walls of the lower electrode 124 are connected to the top support layer 111. Upper electrode 128 The surface of the lower electrode 126 is covered, that is, covers the inner side, the bottom side, and the outer side of the lower electrode 126. The dielectric layer 126 is disposed at least between the upper electrode 128 and the lower electrode 124. In addition, the upper electrode 128 further covers the bottom support layer 106a and the top support layer 111. The dielectric layer 126 is further interposed between the upper electrode 128 and the bottom support layer 106a and between the upper electrode 128 and the top support layer 111. In one embodiment, the top surface of the cup capacitor 130 is higher than the top surface of the peripheral support layer 110b and the core support layer 118a, which may increase the charge storage capability of the cup capacitor 130. In one embodiment, the memory element of the first embodiment of the present invention further includes a plurality of conductor regions 104 disposed on the substrate 100. Each conductor region 104 is electrically connected to the bottom of the corresponding cup capacitor 130.

4A-4F are top schematic views showing a manufacturing process of a memory element according to a second embodiment of the present invention. 5A to 5F are schematic cross-sectional views taken along line A-A of Figs. 4A to 4F, respectively. 6A to 6F are schematic cross-sectional views taken along line B-B of Figs. 4A to 4F, respectively.

Referring to FIG. 4A, FIG. 5A and FIG. 6A simultaneously, the dielectric layer 202 and the plurality of conductor regions 204 are sequentially formed on the substrate 200 according to the method of the first embodiment. A bottom support layer 206, an insulating layer 208, and a peripheral support layer 210 having a trench 40. A spacer 216a is formed on the sidewall of the trench 40. The dielectric layer 202, the plurality of conductor regions 204, the bottom support layer 206, the insulating layer 208, and the peripheral support layer 210 having the trench 40 and the spacer 216a are formed and formed by the dielectric layer 102, the majority of the first embodiment. The conductor region 104, the bottom support layer 106, the insulating layer 108, the peripheral support layer 210, and the spacers 116a are not described herein.

Next, a support material layer 218 is conformally formed on the peripheral support layer 210a. To cover the top surface of the peripheral support layer 210a, the sidewalls of the spacer 216a, and the bottom of the trench 40. The support material layer 218 may be, for example, tantalum nitride (SiN), lanthanum oxynitride (SiON), lanthanum oxynitride (SiCON), tantalum carbide (SiC), or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. .

Thereafter, referring to FIG. 4B, FIG. 5B and FIG. 6B, the support material layer 218 is subjected to an anisotropic etching process, and a portion of the support material layer 218 is removed to form a core support layer 218a on the sidewall of the spacer 216a. The core support layer 218a encloses the trench 50. In an embodiment, the anisotropic etch process can be, for example, a dry etch process. The dry etching process can be, for example, a reactive ion etching process (RIE). The core support layer 218a is located within the perimeter support layer 210a. The spacer 216a is disposed between the peripheral support layer 210a and the core support layer 218a. In an embodiment, the core support layer 218a can be, for example, annular. The shape of the core support layer 218a includes a square, a rectangle, a racetrack shape, or a star shape.

Referring to FIG. 4B, FIG. 5B, and FIG. 6B simultaneously, a filling layer 219 is formed in the core support layer 218a. Specifically, a filler material layer is formed on the core support layer 218a, which covers the top surface of the peripheral support layer 210a, the spacer 216a, and the core support layer 218a and is filled in the trench 50 (not shown). Then, using a planarization process, a portion of the fill material layer is removed, and the peripheral support layer 210a, the spacers 216a, and the top surface of the core support layer 218a are exposed to form a fill layer 219 in the trench 50. In an embodiment, the planarization process can be, for example, a chemical mechanical polishing process (CMP) or an etch back process. The material of the filling material layer may, for example, include cerium oxide, and the forming method thereof may be formed by chemical vapor deposition.

Referring to FIG. 4C, FIG. 5C and FIG. 6C simultaneously, the steps are as follows, as shown in FIG. 1D, FIG. 2D and FIG. 3D, the mask layer 220 and the patterned photoresist layer 222 are sequentially formed on the peripheral support layer 210a. The mask layer 220 covers the peripheral support layer 210a, the spacers 216a, and the top surface of the core support layer 218a. The patterned photoresist layer 222 has a plurality of recesses 223. The position of the groove 223 corresponds to the position of the conductor region 204 below. The material and formation method of the mask layer 220 and the patterned photoresist layer 222, such as the mask layer 120 and the patterned photoresist layer 122 of the first embodiment described above, are not described herein again.

Referring to FIG. 4D, FIG. 5D and FIG. 6D, the steps are as shown in FIG. 1F, FIG. 2F and FIG. 3F. The patterned photoresist layer 222 is used as a mask to perform an etching process to remove a portion of the mask layer 220. To form a patterned mask layer 220a. Then, using the patterned mask layer 220a as a mask, an etching process is performed to remove a portion of the peripheral support layer 210a, the core support layer 218a, the insulating layer 208, and the bottom support layer 206 to form a peripheral support layer 210b and a core support layer. 218b, insulating layer 208a and bottom support layer 206a, and forming a plurality of openings 60, exposing a plurality of conductor regions 204. The patterned photoresist layer 222 is also removed simultaneously during the etching process. The opening 60 is formed by the opening 20 of the first embodiment described above, and details are not described herein again.

Thereafter, a lower electrode 224 is formed on the inner side and the bottom of each opening 60. The material and formation method of the lower electrode 224 are as described in the lower electrode 124 of the first embodiment described above, and will not be described herein.

Referring to FIG. 4E, FIG. 5E and FIG. 6E simultaneously, an isotropic etching process is performed to remove the patterned mask layer 220a, the spacers 216b, and the insulating layer 208a to expose a portion of the outer side of the lower electrode 224. Removing the insulating layer 208a and the spacer 216b At the same time, the filling layer 219 and the insulating layer 208a under it are also removed to form a gap 70 in the core supporting layer 218b. Specifically, after the isotropic etching process is performed, after the spacers 216b and the filling layer 219 are removed, a gap 80 is formed between the core supporting layer 218b and the peripheral supporting layer 210b, and a gap 70 is formed in the core supporting layer 218b. The material of the peripheral support layer 210b, the core support layer 218b and the spacer 216b, the insulating layer 208a, and the filling layer 219 are different, and the isotropic etching process is performed on the peripheral support layer 210b, the core support layer 218b and the spacer 216b, and the insulating layer 208a. The filling layer 219 has a high etching selectivity ratio, and therefore, the etching rate of the peripheral supporting layer 110b and the core supporting layer 118b is slow. Then, the etchant flows in from the gap 70 and the gap 80, and the insulating layer 208a is removed to form a gap 72 between the bottom support layer 206a and the peripheral support layer 210b and the core support layer 218b, that is, to expose the opening 60. The outer side of the electrode 224. At this time, after the insulating layer 208a is completely removed, an intermediate hollow structure is formed. The support structure of the memory element of the second embodiment of the present invention is supported by the bottom support layer 206a, the peripheral support layer 210b, the core support layer 218b, and the lower electrode 224. In one embodiment, the isotropic etching process includes a wet etching process, which may be, for example, using an etch buffer (Buffer Oxide Etchant, BOE), hydrofluoric acid (HF), diluted hydrofluoric acid (Diluted Hydrogen Fluoride). , DHF) or buffered hydrofluoric acid (BHF), etc.

As shown in FIG. 4E, the peripheral support layer 210b surrounds the core support layer 218b, and there is a gap 80 between the peripheral support layer 210b and the core support layer 218b. The core support layer 218b can be, for example, annular with a gap 70 therein. Since there is a core support layer 218b between any two adjacent openings 60, and the core support layer 218b and the spacer 216b The material has a high etch selectivity ratio and, therefore, avoids the case where the opening 60 is excessively reamed in the above isotropic etching process. Moreover, the core support layer 218b provides additional mechanical strength to support the architecture of the memory element of the second embodiment of the present invention. In addition, there is a gap 70 in the core support layer 218b. In the above-described isotropic etching process, in addition to flowing in from the gap 80, the etching liquid can also flow in from the gap 70 to accelerate the removal of the insulating layer 208a, thereby achieving the effect of saving process time.

Referring to FIG. 4F, FIG. 5F and FIG. 6F simultaneously, the steps are as shown in FIG. 1H, FIG. 2H and FIG. 3H, and the dielectric layer 226 and the upper electrode 228 are conformally formed on the lower electrode 224 to form a plurality of cups. Capacitor 230. The upper electrode 228 further covers the bottom support layer 206a, the peripheral support layer 210b, and the core support layer 218b. The dielectric layer 226 is further interposed between the upper electrode 228 and the bottom support layer 206a and between the upper electrode 228 and the peripheral support layer 210b and the core support layer 218b. The material and formation method of the dielectric layer 226 and the upper electrode 228 are as described above for the dielectric layer 126 and the upper electrode 128 of the first embodiment, and details are not described herein again.

In summary, the embodiment of the present invention utilizes a core support layer disposed between any adjacent two cup capacitors to prevent excessive reaming of adjacent cup capacitors during an isotropic etching process. This causes a short circuit problem between two adjacent cup capacitors. Moreover, the peripheral support layer and the core support layer of the embodiment of the present invention can provide additional mechanical strength to avoid deformation or even dumping of the cup capacitor of the embodiment of the present invention, thereby improving the reliability of the product. Since the gap between the peripheral supporting layer, the core supporting layer and the bottom supporting layer in the embodiment of the present invention is filled with air (the dielectric coefficient thereof is close to 1), it is less likely to be generated between adjacent cup capacitors. send Raw capacitor. In addition, another embodiment of the present invention has a gap in the core supporting layer, which can accelerate the removal of the insulating layer to save the process time.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

30‧‧‧ gap

110b, 118a, 111‧‧‧ support layer

128‧‧‧ electrodes

130‧‧‧ capacitor

Claims (10)

A memory element comprising: a plurality of cup capacitors on a substrate; a bottom support layer disposed on the substrate between the plurality of lower sidewalls of the cup capacitors; and a top support layer disposed thereon a plurality of gaps between the upper sidewalls of the cup-shaped capacitors and the bottom support layer, the top support layer comprising: a peripheral support layer on the periphery of the cup capacitors and connected to the cup capacitors; And a core support layer in the peripheral support layer and separated from the peripheral support layer by a gap to connect any two adjacent cup capacitors. The memory device of claim 1, wherein the cup capacitors comprise: a plurality of cup-shaped lower electrodes on the substrate, and a plurality of lower sidewalls of the cup-shaped lower electrodes are connected to the bottom support layer a plurality of upper sidewalls of the cup-shaped lower electrodes are connected to the top support layer; an upper electrode covering the surfaces of the cup-shaped lower electrodes; and a dielectric layer disposed at least on the upper electrodes and the cups Between the lower electrodes. The memory device of claim 1, wherein the upper electrode further covers the bottom support layer and the top support layer, and the dielectric layer is further between the upper electrode and the bottom support layer and thereon Between the electrode and the top support layer. The memory element according to claim 1, wherein the core support The layer is blocky or ring shaped. The memory element of claim 1, wherein the shape of the core support layer comprises a square, a rectangle, a racetrack or a star. The memory element according to claim 1, wherein the bottom support layer and the material of the top support layer each comprise tantalum nitride (SiN), bismuth oxynitride (SiON), bismuth oxynitride (SiCON), carbonization. Bismuth (SiC) or a combination thereof. The memory device of claim 1, further comprising a plurality of conductor regions disposed on the substrate, wherein each conductor region is electrically connected to the bottom of the corresponding cup capacitors. The memory element of claim 1, wherein the gap between the top support layer and the bottom support layer is filled with air. A method of fabricating a memory device, comprising: providing a substrate having a plurality of conductor regions; forming a bottom support layer on the substrate, the bottom support layer exposing the conductor regions; forming a plurality of the substrate a cup-shaped lower electrode electrically connected to the conductor regions, wherein the bottom support layer is located between a plurality of lower sidewalls of the cup capacitors; and a top support layer is formed on the substrate Arranging around a plurality of upper sidewalls of the cup capacitors, and the bottom support layer has a gap between each other, the top support layer comprising: a peripheral support layer, and the cups on the periphery of the cup capacitors Capacitor connection; A core support layer is disposed in the peripheral support layer and spaced apart from the peripheral support layer by a gap to connect any two adjacent cup capacitors. The method of manufacturing a memory device according to claim 9, wherein the core support layer is in a block shape or a ring shape.