TW201603027A - Semiconductor memory device, memory system, and data writing method - Google Patents
Semiconductor memory device, memory system, and data writing method Download PDFInfo
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Abstract
Description
本發明之實施形態係關於半導體記憶裝置、記憶體系統及資料寫入方法。 Embodiments of the present invention relate to a semiconductor memory device, a memory system, and a data writing method.
已知有一種將記憶體胞三維排列之NAND型快閃記憶體。 A NAND type flash memory in which memory cells are three-dimensionally arranged is known.
本發明之實施形態提供一種可提高資料寫入速度之半導體記憶裝置及資料寫入方法。 Embodiments of the present invention provide a semiconductor memory device and a data writing method that can increase data writing speed.
實施形態之半導體記憶裝置包含複數個記憶體胞、字元線、位元線、及列解碼器。記憶體胞積層於半導體基板上。字元線連接於記憶體胞之閘極。位元線電性連接於記憶體胞之電流路徑,而可傳送資料。列解碼器對字元線施加電壓。對記憶體胞寫入資料係藉由反復進行複數次包含程式動作與驗證動作之程式迴路而執行。在1次程式迴路中,列解碼器對選擇字元線依序施加第1程式電壓、與有別於該第1程式電壓之第2程式電壓。 The semiconductor memory device of the embodiment includes a plurality of memory cells, word lines, bit lines, and column decoders. The memory cell layer is deposited on the semiconductor substrate. The word line is connected to the gate of the memory cell. The bit line is electrically connected to the current path of the memory cell, and the data can be transmitted. The column decoder applies a voltage to the word line. Writing data to the memory cell is performed by repeating a plurality of program loops including the program operation and the verification operation. In the primary program loop, the column decoder sequentially applies the first program voltage to the selected word line and the second program voltage different from the first program voltage.
1‧‧‧NAND型快閃記憶體 1‧‧‧NAND flash memory
5-5‧‧‧線 5-5‧‧‧ line
6-6‧‧‧線 6-6‧‧‧ line
7-7‧‧‧線 7-7‧‧‧ line
10‧‧‧記憶體胞陣列 10‧‧‧ memory cell array
11‧‧‧列解碼器 11‧‧‧ column decoder
12‧‧‧感測放大器模組 12‧‧‧Sense Amplifier Module
13‧‧‧運算模組 13‧‧‧ Computing Module
14‧‧‧資料閂鎖模組 14‧‧‧Information Latching Module
15‧‧‧控制部 15‧‧‧Control Department
20‧‧‧半導體基板 20‧‧‧Semiconductor substrate
21‧‧‧絕緣膜 21‧‧‧Insulation film
22-1‧‧‧絕緣膜 22-1‧‧‧Insulation film
22-2‧‧‧絕緣膜 22-2‧‧‧Insulation film
22-3‧‧‧絕緣膜 22-3‧‧‧Insulation film
22-4‧‧‧絕緣膜 22-4‧‧‧Insulation film
23-1‧‧‧半導體層 23-1‧‧‧Semiconductor layer
23-2‧‧‧半導體層 23-2‧‧‧Semiconductor layer
23-3‧‧‧半導體層 23-3‧‧‧Semiconductor layer
24‧‧‧葉片型積層構造 24‧‧‧ Blade type laminated structure
24-1‧‧‧葉片型構造 24-1‧‧‧ blade structure
24-2‧‧‧葉片型構造 24-2‧‧‧ blade structure
24-3‧‧‧葉片型構造 24-3‧‧‧ Blade type structure
24-4‧‧‧葉片型構造 24-4‧‧‧ blade type structure
25‧‧‧絕緣膜 25‧‧‧Insulation film
26‧‧‧絕緣膜 26‧‧‧Insulation film
27‧‧‧絕緣膜 27‧‧‧Insulation film
28‧‧‧半導體層 28‧‧‧Semiconductor layer
40‧‧‧運算電路 40‧‧‧Operating circuit
210‧‧‧主機介面電路 210‧‧‧Host interface circuit
220‧‧‧內置記憶體(RAM) 220‧‧‧Internal memory (RAM)
230‧‧‧處理器(CPU) 230‧‧‧Processor (CPU)
240‧‧‧緩衝記憶體 240‧‧‧Buffered memory
250‧‧‧NAND介面電路 250‧‧‧NAND interface circuit
260‧‧‧ECC電路 260‧‧‧ECC circuit
ALE‧‧‧位址閂鎖啟用信號 ALE‧‧‧ address latch enable signal
BC1‧‧‧接觸插塞 BC1‧‧‧Contact plug
BC2‧‧‧接觸插塞 BC2‧‧Contact plug
BC3‧‧‧接觸插塞 BC3‧‧‧Contact plug
BC4‧‧‧接觸插塞 BC4‧‧‧Contact plug
BC5‧‧‧接觸插塞 BC5‧‧‧Contact plug
BC6‧‧‧接觸插塞 BC6‧‧‧Contact plug
BL‧‧‧位元線 BL‧‧‧ bit line
BL1‧‧‧位元線 BL1‧‧‧ bit line
BL2‧‧‧位元線 BL2‧‧‧ bit line
BL3‧‧‧位元線 BL3‧‧‧ bit line
BL4‧‧‧位元線 BL4‧‧‧ bit line
BL5‧‧‧位元線 BL5‧‧‧ bit line
BL6‧‧‧位元線 BL6‧‧‧ bit line
/CE‧‧‧晶片啟用信號 /CE‧‧‧Wafer Enable Signal
CGS‧‧‧行選擇閘極 CGS‧‧‧ row selection gate
CGS1‧‧‧行選擇閘極 CGS1‧‧‧ row selection gate
CGS2‧‧‧行選擇閘極 CGS2‧‧‧ row selection gate
CGS3‧‧‧行選擇閘極 CGS3‧‧‧ row selection gate
CGS4‧‧‧行選擇閘極 CGS4‧‧‧ row selection gate
CLE‧‧‧指令閂鎖啟用信號 CLE‧‧‧ instruction latch enable signal
D0~D527‧‧‧資料 D0~D527‧‧‧Information
DAT‧‧‧資料線 DAT‧‧‧ data line
DL0‧‧‧閂鎖電路 DL0‧‧‧Latch circuit
DL1‧‧‧閂鎖電路 DL1‧‧‧Latch circuit
GR1-1‧‧‧串組 GR1-1‧‧‧ string group
GR1-2‧‧‧串組 GR1-2‧‧‧ string group
GR2-1‧‧‧串組 GR2-1‧‧‧ string
GR2-2‧‧‧串組 GR2-2‧‧‧ string group
GR3-1‧‧‧串組 GR3-1‧‧‧ string group
GR4-1‧‧‧串組 GR4-1‧‧‧ string
GSL1‧‧‧選擇閘極線 GSL1‧‧‧Selected gate line
GSL2‧‧‧選擇閘極線 GSL2‧‧‧Selected gate line
I/O1~I/O8‧‧‧輸入輸出信號 I/O1~I/O8‧‧‧ input and output signals
MT1‧‧‧記憶體胞電晶體 MT1‧‧‧ memory cell crystal
MT2‧‧‧記憶體胞電晶體 MT2‧‧‧ memory cell crystal
MT3‧‧‧記憶體胞電晶體 MT3‧‧‧ memory cell
MT4‧‧‧記憶體胞電晶體 MT4‧‧‧ memory cell crystal
MU1‧‧‧記憶體單元 MU1‧‧‧ memory unit
MU2‧‧‧記憶體單元 MU2‧‧‧ memory unit
R/B‧‧‧就緒/忙碌信號 R/B‧‧‧Ready/busy signal
/RE‧‧‧讀取啟用信號 /RE‧‧‧Read enable signal
SC‧‧‧接觸插塞 SC‧‧‧Contact plug
SDL_B‧‧‧閂鎖電路 SDL_B‧‧‧Latch circuit
SDL_M‧‧‧閂鎖電路 SDL_M‧‧‧Latch circuit
SDL_T‧‧‧閂鎖電路 SDL_T‧‧‧Latch circuit
SEL_BOT‧‧‧控制信號 SEL_BOT‧‧‧ control signal
SEL_MID‧‧‧控制信號 SEL_MID‧‧‧ control signal
SEL_TOP‧‧‧控制信號 SEL_TOP‧‧‧ control signal
SR1‧‧‧NAND串 SR1‧‧‧NAND string
SR2‧‧‧NAND串 SR2‧‧‧NAND string
SR3‧‧‧NAND串 SR3‧‧‧NAND string
SSL1‧‧‧控制信號線 SSL1‧‧‧ control signal line
SSL2‧‧‧控制信號線 SSL2‧‧‧ control signal line
SSL3‧‧‧控制信號線 SSL3‧‧‧ control signal line
SSL4‧‧‧控制信號線 SSL4‧‧‧ control signal line
ST1‧‧‧選擇電晶體 ST1‧‧‧Selecting a crystal
ST2‧‧‧選擇電晶體 ST2‧‧‧Selecting a crystal
t1‧‧‧時刻 Time t1‧‧‧
t2‧‧‧時刻 Time t2‧‧‧
t3‧‧‧時刻 Time t3‧‧‧
t4‧‧‧時刻 Time t4‧‧‧
t5‧‧‧時刻 T5‧‧‧ moment
t6‧‧‧時刻 Time t6‧‧‧
t7‧‧‧時刻 Time t7‧‧‧
t8‧‧‧時刻 T8‧‧‧ moment
V1‧‧‧電壓 V1‧‧‧ voltage
Vfy-A‧‧‧驗證電壓 Vfy-A‧‧‧Verification voltage
Vfy-B‧‧‧驗證電壓 Vfy-B‧‧‧Verification voltage
Vfy-C‧‧‧驗證電壓 Vfy-C‧‧‧Verification voltage
VPGM‧‧‧程式電壓 VPGM‧‧‧ program voltage
VPGM1‧‧‧程式電壓 VPGM1‧‧‧ program voltage
VPGM2‧‧‧程式電壓 VPGM2‧‧‧ program voltage
VPGM2a‧‧‧程式電壓 VPGM2a‧‧‧ program voltage
VPGM2b‧‧‧程式電壓 VPGM2b‧‧‧ program voltage
VPGM3‧‧‧程式電壓 VPGM3‧‧‧ program voltage
VQPW‧‧‧電壓 VQPW‧‧‧ voltage
VSG‧‧‧電壓 VSG‧‧‧ voltage
/WE‧‧‧寫入啟用信號 /WE‧‧‧Write enable signal
WL‧‧‧字元線 WL‧‧‧ character line
WL1‧‧‧選擇字元線 WL1‧‧‧Select word line
WL2‧‧‧非選擇字元線 WL2‧‧‧Non-selected word line
WL3‧‧‧非選擇字元線 WL3‧‧‧Non-selected word line
WL4‧‧‧非選擇字元線 WL4‧‧‧Non-selected word line
圖1係第1實施形態之半導體記憶裝置之方塊圖。 Fig. 1 is a block diagram showing a semiconductor memory device according to a first embodiment.
圖2係第1實施形態之記憶體胞陣列之電路圖。 Fig. 2 is a circuit diagram of a memory cell array of the first embodiment.
圖3係第1實施形態之記憶體胞陣列之立體圖。 Fig. 3 is a perspective view of the memory cell array of the first embodiment.
圖4係第1實施形態之記憶體胞陣列之俯視圖。 Fig. 4 is a plan view showing the memory cell array of the first embodiment.
圖5係沿著圖4之5-5線之剖面圖。 Figure 5 is a cross-sectional view taken along line 5-5 of Figure 4.
圖6係沿著圖4之6-6線之剖面圖。 Figure 6 is a cross-sectional view taken along line 6-6 of Figure 4.
圖7係沿著圖4之7-7線之剖面圖。 Figure 7 is a cross-sectional view taken along line 7-7 of Figure 4.
圖8係表示第1實施形態之記憶體胞之閾值分佈之圖表。 Fig. 8 is a graph showing a threshold distribution of memory cells in the first embodiment.
圖9係第1實施形態之記憶體胞陣列之電路圖。 Fig. 9 is a circuit diagram of a memory cell array of the first embodiment.
圖10係表示第1實施形態之資料之寫入方法之流程圖。 Fig. 10 is a flow chart showing a method of writing data according to the first embodiment.
圖11係第1實施形態之資料之寫入時之字元線電位之時序圖。 Fig. 11 is a timing chart showing the word line potential at the time of writing the data of the first embodiment.
圖12係表示資料之寫入時之字元線電位之變化之時序圖。 Fig. 12 is a timing chart showing changes in the word line potential at the time of writing of data.
圖13係表示第2實施形態之資料之寫入方法之流程圖。 Fig. 13 is a flow chart showing a method of writing data according to the second embodiment.
圖14係表示第2實施形態之資料之寫入時之字元線電位之變化之時序圖。 Fig. 14 is a timing chart showing changes in word line potential at the time of writing of the data of the second embodiment.
圖15係表示第3實施形態之資料之寫入方法之流程圖。 Fig. 15 is a flow chart showing a method of writing data according to the third embodiment.
圖16係表示第3實施形態之資料之寫入時之字元線電位之變化之時序圖。 Fig. 16 is a timing chart showing changes in word line potential at the time of writing of the data of the third embodiment.
圖17係表示第4實施形態之資料之寫入方法之流程圖。 Fig. 17 is a flow chart showing a method of writing data according to the fourth embodiment.
圖18係表示第4實施形態之資料之寫入時之字元線及位元線之電位變化之時序圖。 Fig. 18 is a timing chart showing changes in the potential of the word line and the bit line at the time of writing the data of the fourth embodiment.
圖19係第4實施形態之記憶體胞陣列之電路圖。 Fig. 19 is a circuit diagram of a memory cell array of the fourth embodiment.
圖20係表示第4實施形態之記憶體胞之閾值變化之圖表。 Fig. 20 is a graph showing a change in threshold value of a memory cell in the fourth embodiment.
圖21係第5實施形態之感測放大器模組、運算模組、及資料閂鎖模組之方塊圖。 21 is a block diagram of a sense amplifier module, a calculation module, and a data latch module of the fifth embodiment.
圖22係表示第5實施形態之資料之寫入時之字元線電位之變化之圖表。 Fig. 22 is a graph showing changes in word line potential at the time of writing of the data of the fifth embodiment.
圖23係表示第5實施形態之資料之寫入時之字元線及位元線之電位變化之圖表。 Fig. 23 is a graph showing the change in potential of the word line and the bit line at the time of writing the data of the fifth embodiment.
圖24係第6實施形態之記憶體系統之方塊圖。 Figure 24 is a block diagram of a memory system of a sixth embodiment.
圖25係第6實施形態之第1模式之寫入動作時之各種信號之時序 圖。 Figure 25 is a timing chart of various signals in the write operation of the first mode of the sixth embodiment. Figure.
圖26係第6實施形態之第2模式之寫入動作時之各種信號之時序圖。 Fig. 26 is a timing chart showing various signals at the time of the writing operation in the second mode of the sixth embodiment.
以下,參照圖式對實施形態進行說明。該說明時,在全部圖中,對共通之部分標註共通之參照符號。 Hereinafter, embodiments will be described with reference to the drawings. In the description, common parts are denoted by the same reference numerals throughout the drawings.
對第1實施形態之半導體記憶裝置進行說明。以下,作為半導體記憶裝置,舉將記憶體胞積層於半導體基板上之三維積層型NAND型快閃記憶體為例進行說明。 The semiconductor memory device of the first embodiment will be described. Hereinafter, a three-dimensional laminated NAND type flash memory in which a memory cell layer is deposited on a semiconductor substrate will be described as an example of a semiconductor memory device.
首先,對本實施形態之半導體記憶裝置之構成進行說明。 First, the configuration of the semiconductor memory device of the present embodiment will be described.
圖1係本實施形態之半導體記憶裝置之方塊圖。如圖示,NAND型快閃記憶體1包含記憶體胞陣列10、列解碼器11、感測放大器模組12、運算模組13、資料閂鎖模組14、及控制部17。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a semiconductor memory device of the present embodiment. As shown, the NAND flash memory 1 includes a memory cell array 10, a column decoder 11, a sense amplifier module 12, a calculation module 13, a data latch module 14, and a control unit 17.
記憶體胞陣列10具備複數個非揮發性記憶體胞。記憶體胞為具備包含例如電荷累積層與控制閘極之積層閘極之MOS電晶體,且分別與列及行相關連。且,位於同一列之記憶體胞之控制閘極連接於相同之字元線WL,位於同一行之記憶體胞之汲極連接於相同之位元線BL,源極連接於源極線SL。對記憶體胞陣列10之詳細內容將於後敘述。 The memory cell array 10 is provided with a plurality of non-volatile memory cells. The memory cell is a MOS transistor having a gate electrode including, for example, a charge accumulation layer and a control gate, and is associated with columns and rows, respectively. Moreover, the control gates of the memory cells in the same column are connected to the same word line WL, the drains of the memory cells in the same row are connected to the same bit line BL, and the source is connected to the source line SL. The details of the memory cell array 10 will be described later.
列解碼器11選擇記憶體胞陣列10之列方向。即,列解碼器11在資料之寫入、讀取及抹除時選擇字元線WL,並對選擇字元線及非選擇字元線施加適當之電壓。 The column decoder 11 selects the column direction of the memory cell array 10. That is, the column decoder 11 selects the word line WL at the time of writing, reading, and erasing of data, and applies an appropriate voltage to the selected word line and the unselected word line.
感測放大器模組12具備設置於每條位元線之感測電路。感測電 路各者於資料之讀取時,感測、放大自記憶體胞讀取至位元線BL之資料。又,感測電路於資料之寫入時,將應寫入於記憶體胞之資料傳送至位元線BL。 The sense amplifier module 12 has a sensing circuit disposed on each bit line. Sensing electricity Each of the roads senses and amplifies the data read from the memory cell to the bit line BL when the data is read. Moreover, when the sensing circuit writes the data, the data to be written in the memory cell is transferred to the bit line BL.
運算模組13具備設置於每條位元線之運算電路。運算電路各者於資料之讀取時,使用感測電路所感測、放大之資料進行運算。又,運算電路於資料之寫入時,使用寫入資料進行運算,並將運算結果傳送至感測電路。 The arithmetic module 13 includes an arithmetic circuit provided on each bit line. Each of the arithmetic circuits performs calculation using the data sensed and amplified by the sensing circuit when the data is read. Further, when the data is written to the arithmetic circuit, the arithmetic data is used for calculation, and the operation result is transmitted to the sensing circuit.
資料閂鎖模組14具備設置於每條位元線之閂鎖電路。閂鎖電路各者於資料之讀取時,保持經由運算電路自感測電路所傳送之讀取資料。接著,閂鎖電路將讀取資料輸出至外部。又,閂鎖電路於資料之寫入時,暫時保持自外部所接收之寫入資料。且,閂鎖電路經由運算電路將寫入資料傳送至感測電路。 The data latch module 14 has a latch circuit provided on each bit line. Each of the latch circuits maintains the read data transmitted from the sensing circuit via the arithmetic circuit when the data is read. Then, the latch circuit outputs the read data to the outside. Moreover, the latch circuit temporarily holds the write data received from the outside when the data is written. Moreover, the latch circuit transmits the write data to the sensing circuit via the arithmetic circuit.
控制部15控制快閃記憶體1整體之動作。 The control unit 15 controls the overall operation of the flash memory 1.
圖2係本實施形態之記憶體胞陣列10之電路圖。如圖示,記憶體胞陣列10具備複數個記憶體單元MU(MU1、MU2)。雖圖2中僅圖示有2個記憶體單元MU,但亦可為3個以上,其數量並未限定者。 Fig. 2 is a circuit diagram of the memory cell array 10 of the present embodiment. As shown, the memory cell array 10 includes a plurality of memory cells MU (MU1, MU2). Although only two memory cells MU are shown in FIG. 2, they may be three or more, and the number is not limited.
記憶體單元MU各者具備例如4個串組GR(GR1~GR4)。另,在記憶體單元MU1及MU2間進行區分時,將記憶體單元MU1之串組GR分別稱為GR1-1~GR4-1,將記憶體單元MU2之串組GR分別稱為GR1-2~GR4-2。 Each of the memory cells MU includes, for example, four string groups GR (GR1 to GR4). In addition, when the memory unit MU1 and MU2 are distinguished, the serial group GR of the memory unit MU1 is referred to as GR1-1 to GR4-1, and the serial group GR of the memory unit MU2 is referred to as GR1-2~. GR4-2.
串組GR各者具備例如3個NAND串SR(SR1~SR3)。當然,NAND串SR之數量不限於3個,亦可為4個以上。NAND串SR各者具備選擇電晶體ST1及ST2、以及4個記憶體胞電晶體MT(MT1~MT4)。記憶體胞電晶體MT之數量不限於4個,可為5個以上,亦可為3個以下。記憶體胞電晶體MT具備包含控制閘極與電荷累積層之積層閘極,且非揮 發地保持資料。且,記憶體胞電晶體MT串聯連接於選擇電晶體ST1之源極與選擇電晶體ST2之汲極之間。 Each of the string groups GR includes, for example, three NAND strings SR (SR1 to SR3). Of course, the number of NAND strings SR is not limited to three, and may be four or more. Each of the NAND strings SR includes selection transistors ST1 and ST2 and four memory cell transistors MT (MT1 to MT4). The number of memory cell transistors MT is not limited to four, and may be five or more, or may be three or less. The memory cell transistor MT has a gate electrode including a control gate and a charge accumulation layer, and the non-swing Maintain the information. Further, the memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.
在串組GR內,3個NAND串SR1~SR3依序積層於半導體基板上,NAND串SR1形成於最下層,NAND串SR3形成於最上層。且,相同之串組GR所包含之選擇電晶體ST1及ST2分別連接於相同之選擇閘極線GSL1及GSL2,位於同一行之記憶體胞電晶體MT之控制閘極連接於相同之字元線WL。再者,某串組GR內之3個選擇電晶體ST1之汲極連接於互不相同之位元線BL,選擇電晶體ST2之源極連接於相同之源極線SL。 In the string group GR, three NAND strings SR1 to SR3 are sequentially stacked on the semiconductor substrate, the NAND string SR1 is formed on the lowermost layer, and the NAND string SR3 is formed on the uppermost layer. Moreover, the selection transistors ST1 and ST2 included in the same string group GR are respectively connected to the same selection gate lines GSL1 and GSL2, and the control gates of the memory cell transistors MT in the same row are connected to the same word line. WL. Furthermore, the drains of the three selection transistors ST1 in a certain string group GR are connected to the bit lines BL different from each other, and the source of the selection transistor ST2 is connected to the same source line SL.
就奇數序號之串組GR1及GR3、與偶數序號之串組GR2及GR4而言,選擇電晶體ST1及ST2係以使其位置關係相反之方式配置。即,當為圖2之例時,串組GR1及GR3之選擇電晶體ST1配置於NAND串SR之左端,選擇電晶體ST2配置於NAND串SR之右端。與之相對,串組GR2及GR4之選擇電晶體ST1配置於NAND串SR之右端,選擇電晶體ST2配置於NAND串SR之左端。 For the odd-numbered series of groups GR1 and GR3 and the even-numbered series of groups GR2 and GR4, the transistors ST1 and ST2 are selected so that their positional relationship is reversed. That is, in the example of FIG. 2, the selection transistor ST1 of the string groups GR1 and GR3 is disposed at the left end of the NAND string SR, and the selection transistor ST2 is disposed at the right end of the NAND string SR. On the other hand, the selection transistor ST1 of the string groups GR2 and GR4 is disposed at the right end of the NAND string SR, and the selection transistor ST2 is disposed at the left end of the NAND string SR.
且,串組GR1及GR3之選擇電晶體ST1之閘極連接於相同之選擇閘極線GSL1,選擇電晶體ST2之閘極連接於相同之選擇閘極線GSL2。另一方面,串組GR2及GR4之選擇電晶體ST1之閘極連接於相同之選擇閘極線GSL2,選擇電晶體ST2之閘極連接於相同之選擇閘極線GSL1。 Further, the gates of the selection transistors ST1 of the strings GR1 and GR3 are connected to the same selection gate line GSL1, and the gates of the selection transistor ST2 are connected to the same selection gate line GSL2. On the other hand, the gates of the selection transistors ST1 of the strings GR2 and GR4 are connected to the same selection gate line GSL2, and the gates of the selection transistor ST2 are connected to the same selection gate line GSL1.
又,某記憶體單元MU所包含之4個串組GR1及GR2連接於彼此相同之位元線BL,不同之記憶體單元MU連接於互不相同之位元線BL。更具體而言,在記憶體單元MU1中,串組GR1~GR4之NAND串SR1~SR3之選擇電晶體ST1之汲極分別經由行選擇閘極CGS(CGS1~CGS4)而連接於位元線BL1~BL3。行選擇閘極CGS具有與例如記憶體胞電晶體MT或選擇電晶體ST1及ST2等相同之構成,在各記憶體單 元MU中,選擇在位元線BL進行選擇之1個串組GR。因此,與各串組GR相對應之行選擇閘極CGS1~CGS4之閘極係分別由不同之控制信號線SSL1~SSL4控制。 Further, the four string groups GR1 and GR2 included in one memory cell MU are connected to the same bit line BL, and the different memory cells MU are connected to the bit lines BL which are different from each other. More specifically, in the memory cell MU1, the drains of the selection transistors ST1 of the NAND strings SR1 to SR3 of the strings GR1 to GR4 are connected to the bit line BL1 via the row selection gates CGS (CGS1 to CGS4), respectively. ~BL3. The row selection gate CGS has the same configuration as, for example, the memory cell transistor MT or the selection transistors ST1 and ST2, and is in each memory bank. In the element MU, one string group GR selected in the bit line BL is selected. Therefore, the gates of the row selection gates CGS1 to CGS4 corresponding to the respective string groups GR are controlled by different control signal lines SSL1 to SSL4, respectively.
具有以上所說明之構成之記憶體單元MU係在記載圖2之紙面上沿上下方向排列複數個。該等複數個記憶體單元MU係與記憶體單元MU1共有字元線WL、選擇閘極線GSL1及GSL2。另一方面,位元線BL獨立,例如對記憶體單元MU2,相對應有與記憶體單元MU1不同之3條位元線BL4~BL6。與各記憶體單元MU相對應之位元線BL之條數係與1個串組GR所包含之NAND串SR之總數對應。因此,若NAND串為4層,則位元線BL亦設置4條,其他數量之情形亦同樣。又,控制信號SSL1~SSL4亦可在記憶體單元MU間共通,或亦可獨立控制。 The memory unit MU having the above-described configuration is arranged in plural in the vertical direction on the paper surface described in FIG. The plurality of memory cells MU and the memory cell MU1 share a word line WL and select gate lines GSL1 and GSL2. On the other hand, the bit line BL is independent, for example, for the memory cell MU2, there are three bit lines BL4 to BL6 different from the memory cell MU1. The number of bit lines BL corresponding to each memory cell MU corresponds to the total number of NAND strings SR included in one string group GR. Therefore, if the NAND string is 4 layers, the bit line BL is also set to 4, and the same is true for other numbers. Further, the control signals SSL1 to SSL4 may be common to the memory cells MU or may be independently controlled.
在上述構成中,自各記憶體單元MU逐一所選擇之串組GR之連接於相同字元線WL之複數個記憶體胞電晶體MT之集合成為稱為「頁面」之單位。且,資料之寫入及讀取係以頁面為單位進行。 In the above configuration, the set of the plurality of memory cell transistors MT connected to the same word line WL from the memory cells MU selected one by one becomes a unit called "page". Moreover, writing and reading of data is performed on a page-by-page basis.
圖3係記憶體胞陣列10之立體圖,圖4係記憶體胞陣列10之俯視圖,圖5係沿著圖4之5-5線之剖面圖,圖6係沿著圖4之6-6線之剖面圖,圖7係沿著圖4之7-7線之剖面圖。圖3、圖5、及圖7中圖示有1個記憶體單元MU,圖4及圖6圖示有2個記憶體單元MU1及MU2。 3 is a perspective view of the memory cell array 10, FIG. 4 is a plan view of the memory cell array 10, FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 4, and FIG. 6 is along line 6-6 of FIG. FIG. 7 is a cross-sectional view taken along line 7-7 of FIG. 4. 3, 5, and 7 show one memory cell MU, and FIGS. 4 and 6 show two memory cells MU1 and MU2.
如圖示,於半導體基板20上形成絕緣膜21,於絕緣膜21上形成記憶體胞陣列10。 As shown, an insulating film 21 is formed on the semiconductor substrate 20, and a memory cell array 10 is formed on the insulating film 21.
於絕緣膜21上,藉由形成沿著與相對半導體基板20表面之垂直方向即第1方向正交之第2方向之條紋形狀之例如4個葉片型構造24(24-1~24-4),而形成有1個記憶體單元MU。葉片型構造24各者包含交替積層之絕緣膜22(22-1~22-4)及半導體層23(23-1~23-3)。該葉片型構造24各者相當於圖2所說明之串組GR。且,最下層之半導體層23-1相當於NAND串SR1之電流路徑(形成通道之區域),最上層之半導 體層23-3相當於NAND串SR3之電流路徑,位於其間之半導體層23-2相當於NAND串SR2之電流路徑。 For example, four blade-shaped structures 24 (24-1 to 24-4) are formed on the insulating film 21 in a stripe shape along a second direction orthogonal to the first direction of the surface of the semiconductor substrate 20, that is, the first direction. And one memory unit MU is formed. Each of the blade-type structures 24 includes an insulating film 22 (22-1 to 22-4) and a semiconductor layer 23 (23-1 to 23-3) which are alternately laminated. Each of the blade-type structures 24 corresponds to the string group GR illustrated in Fig. 2 . Moreover, the lowermost semiconductor layer 23-1 corresponds to the current path of the NAND string SR1 (the area where the channel is formed), and the uppermost half of the semiconductor The bulk layer 23-3 corresponds to the current path of the NAND string SR3, and the semiconductor layer 23-2 located therebetween corresponds to the current path of the NAND string SR2.
於葉片型構造24之上表面及側面,依序形成有閘極絕緣膜25、電荷累積層26、區塊絕緣膜27、及控制閘極28(參照圖5)。電荷累積層26係由例如絕緣膜形成。又,控制閘極28係以導電膜形成,並作為字元線WL或選擇閘極線GSL1及GSL2發揮作用。字元線WL、選擇閘極線GSL1及GSL2係在複數個記憶體單元MU間,跨越複數個葉片型構造24而形成。另一方面,控制信號線SSL1~SSL4係於每個葉片型構造24內獨立。 On the upper surface and the side surface of the blade structure 24, a gate insulating film 25, a charge accumulating layer 26, a block insulating film 27, and a control gate 28 (see FIG. 5) are sequentially formed. The charge accumulating layer 26 is formed of, for example, an insulating film. Further, the control gate 28 is formed of a conductive film and functions as the word line WL or the selection gate lines GSL1 and GSL2. The word line WL and the selection gate lines GSL1 and GSL2 are formed between a plurality of memory cells MU across a plurality of blade structures 24 . On the other hand, the control signal lines SSL1 to SSL4 are independent in each of the blade type structures 24.
葉片型構造24其一端部被拉出至記憶體胞陣列10之端部,而於所拉出之區域與位元線BL連接。即,作為一例,若著眼於記憶體單元MU1,則奇數序號之葉片型構造24-1及24-3之一端部係沿第2方向拉出至某區域而共通連接,且於該區域形成接觸插塞BC1~BC3。形成於該區域之接觸插塞BC1連接串組GR1及GR3之半導體層23-1與位元線BL1,而與半導體層23-2及23-3絕緣。接觸插塞BC2連接串組GR1及GR3之半導體層23-2與位元線BL2,而與半導體層23-1及23-3絕緣。接觸插塞BC3連接串組GR1及GR3之半導體層23-3與位元線BL3,而與半導體層23-1及23-2絕緣。 The blade-type structure 24 is pulled out to the end of the memory cell array 10 at one end thereof, and is connected to the bit line BL in the pulled-out region. In other words, as an example, when focusing on the memory unit MU1, one end of the odd-numbered blade-type structures 24-1 and 24-3 is pulled out to a certain area in the second direction to be connected in common, and contacts are formed in the area. Plug BC1~BC3. The contact plug BC1 formed in the region is connected to the semiconductor layer 23-1 of the string groups GR1 and GR3 and the bit line BL1, and is insulated from the semiconductor layers 23-2 and 23-3. The contact plug BC2 is connected to the semiconductor layer 23-2 of the string groups GR1 and GR3 and the bit line BL2, and is insulated from the semiconductor layers 23-1 and 23-3. The contact plug BC3 connects the semiconductor layer 23-3 of the string groups GR1 and GR3 with the bit line BL3, and is insulated from the semiconductor layers 23-1 and 23-2.
另一方面,偶數序號之葉片型構造24-2及24-4之一端部拉出至與葉片型構造24-1及24-3之一端部在第2方向對向之區域而共通連接。於該區域形成接觸插塞BC1~BC3。形成於該區域之接觸插塞BC1連接串組GR2及GR4之半導體層23-1與位元線BL1,而與半導體層23-2及23-3絕緣。接觸插塞BC2連接串組GR2及GR4之半導體層23-2與位元線BL2,而與半導體層23-1及23-3絕緣。接觸插塞BC3連接串組GR2及GR4之半導體層23-3與位元線BL3,而與半導體層23-1及23-2絕緣。 On the other hand, one end of the even-numbered blade-type structures 24-2 and 24-4 is pulled out to be commonly connected to the region in which the end portions of the blade-type structures 24-1 and 24-3 are opposed to each other in the second direction. Contact plugs BC1 BC BC3 are formed in this region. The contact plug BC1 formed in this region is connected to the semiconductor layer 23-1 of the string groups GR2 and GR4 and the bit line BL1, and is insulated from the semiconductor layers 23-2 and 23-3. The contact plug BC2 is connected to the semiconductor layer 23-2 of the string groups GR2 and GR4 and the bit line BL2, and is insulated from the semiconductor layers 23-1 and 23-3. The contact plug BC3 is connected to the semiconductor layer 23-3 of the string groups GR2 and GR4 and the bit line BL3, and is insulated from the semiconductor layers 23-1 and 23-2.
當然,上述說明為記憶體單元MU1之情形者;例如記憶體單元MU2之情形時,形成接觸插塞BC4~BC6,其等將半導體層23-1~23-3分別連接於位元線BL4~BL6(參照圖6)。 Of course, the above description is the case of the memory cell MU1; for example, in the case of the memory cell MU2, the contact plugs BC4 to BC6 are formed, and the semiconductor layers 23-1 to 23-3 are respectively connected to the bit line BL4~ BL6 (refer to Figure 6).
又,於葉片型構造24之另一端上形成接觸插塞SC。接觸插塞SC將半導體層23-1~23-3連接於源極線SL。 Further, a contact plug SC is formed on the other end of the blade type structure 24. The contact plug SC connects the semiconductor layers 23-1 to 23-3 to the source line SL.
在上述構成中,NAND串SR1~SR3所包含之記憶體胞電晶體其尺寸互不相同。更具體而言,如圖5所示,在各葉片型構造24中,半導體層23之沿著第3方向之寬度係越位於低層者則越大,而越位於高層者則越小。即,半導體層23-1之寬度最寬,半導體層23-3之寬度最窄,半導體層23-2之寬度為其中間。即,因製造偏差而彼此特性不同之複數個記憶體胞電晶體MT包含於1頁面內。 In the above configuration, the memory cell crystals included in the NAND strings SR1 to SR3 are different in size from each other. More specifically, as shown in FIG. 5, in each of the blade-type structures 24, the width of the semiconductor layer 23 along the third direction is larger as it is located in the lower layer, and is smaller as it is higher. That is, the width of the semiconductor layer 23-1 is the widest, the width of the semiconductor layer 23-3 is the narrowest, and the width of the semiconductor layer 23-2 is the middle. That is, a plurality of memory cell transistors MT having different characteristics from each other due to manufacturing variations are included in one page.
圖8表示本實施形態之記憶體胞電晶體MT可取得之閾值分佈。如圖示,記憶體胞電晶體MT可根據其閾值保持例如2位元之資料。該2位元資料自閾值較低者依序為例如“Ep”位準、“A”位準、“B”位準、及“C”位準。 Fig. 8 shows a threshold distribution which can be obtained by the memory cell transistor MT of the present embodiment. As illustrated, the memory cell transistor MT can maintain, for example, 2-bit data based on its threshold. The 2-bit data from the lower threshold is, for example, the "Ep" level, the "A" level, the "B" level, and the "C" level.
“EP”位準為已抹除資料之狀態之閾值,例如具有正值,且低於驗證電壓Vfy_A。“A”~“C”位準為於電荷累積層內注入有電荷之狀態之閾值,“A”位準具有高於驗證電壓Vfy_A且低於驗證電壓Vfy_B之閾值;“B”位準具有高於驗證電壓Vfy_B且低於驗證電壓Vfy_C之閾值;“C”位準具有較驗證電壓Vfy_C更高之閾值 The "EP" level is the threshold for the state of the erased data, for example, has a positive value and is lower than the verification voltage Vfy_A. The "A" to "C" level is a threshold for injecting a state of charge in the charge accumulation layer, and the "A" level has a threshold higher than the verification voltage Vfy_A and lower than the verification voltage Vfy_B; the "B" level has a high value The verification voltage Vfy_B is lower than the threshold of the verification voltage Vfy_C; the "C" level has a higher threshold than the verification voltage Vfy_C
如此,藉由可取得4個閾值位準,各個記憶體胞電晶體MT可記憶2位元之資料(4-level data)。 Thus, by obtaining four threshold levels, each memory cell MT can memorize 2-level data.
接著,對本實施形態之資料之寫入動作進行說明。在說明寫入動作時,為基於其位置(層)與寫入資料定義記憶體胞電晶體MT,使 用圖9進行說明。圖9係記憶體胞陣列10之電路圖,為簡化說明,顯示記憶體胞陣列10中僅包含2個記憶體單元MU1及MU2之情形,且圖示有藉由選擇控制信號線SSL1及SSL5而選擇有記憶體單元MU1之串組GR1-1與記憶體單元MU2之串組GR1-2之情形。因此,由串組GR1-1及GR1-2中連接於相同字元線WL之6個記憶體胞電晶體MT形成頁面。另,從紙面考慮,僅圖示有所選擇之串組GR1-1及GR1-2,且省略行選擇閘極CGS之圖示。以下所進行之說明係選擇有其他串組之組合之情形亦相同。 Next, the writing operation of the data of the present embodiment will be described. When describing the write operation, the memory cell transistor MT is defined based on its position (layer) and written data. This will be described with reference to Fig. 9 . 9 is a circuit diagram of the memory cell array 10. For simplicity of explanation, the memory cell array 10 is shown to include only two memory cells MU1 and MU2, and is illustrated by selecting control signal lines SSL1 and SSL5. There is a case where the string group GR1-1 of the memory unit MU1 and the string group GR1-2 of the memory unit MU2. Therefore, the pages are formed by the six memory cell transistors MT connected to the same word line WL among the string groups GR1-1 and GR1-2. Further, from the viewpoint of the paper, only the selected string groups GR1-1 and GR1-2 are illustrated, and the illustration of the row selection gate CGS is omitted. The following description is made in the same manner as selecting a combination of other string groups.
如上所述,在某串組GR中,位於最下層之記憶體胞電晶體MT(NAND串SR1)其半導體層23之寬度最大。因此,資料之寫入速度最高。另一方面,位於最上層之記憶體胞電晶體MT(NAND串SR3)其半導體層23之寬度最小。因此,資料之寫入速度最低。 As described above, in a certain string group GR, the memory cell MT (NAND string SR1) located at the lowermost layer has the largest width of the semiconductor layer 23. Therefore, the data is written at the highest speed. On the other hand, the memory cell MT (NAND string SR3) located at the uppermost layer has the smallest width of the semiconductor layer 23. Therefore, the data is written at the lowest speed.
因此,在以頁面為單位寫入資料時,最早結束寫入(寫入速度高)之記憶體胞電晶體為位於葉片型構造24之最下層,且寫入“A”位準之記憶體胞電晶體MT。在以下說明中,將如此之記憶體胞電晶體MT稱為第1胞。與之相對,最遲結束寫入(寫入速度低)之記憶體胞電晶體為位於葉片型構造24之最上層,且寫入“C”位準之記憶體胞電晶體MT。將如此之記憶體胞電晶體MT稱為第3胞。且,將其他記憶體胞電晶體MT稱為第2胞。 Therefore, when data is written in units of pages, the memory cell whose earliest end of writing (high writing speed) is the lowermost layer of the blade type structure 24, and the memory cell of the "A" level is written. Transistor MT. In the following description, such a memory cell transistor MT is referred to as a first cell. On the other hand, the memory cell which ends writing at the latest (low writing speed) is the uppermost layer of the blade type structure 24, and the memory cell transistor MT of the "C" level is written. Such a memory cell transistor MT is referred to as a third cell. Further, other memory cell transistors MT are referred to as second cells.
接著,使用圖9至圖11對資料之寫入方法進行說明。圖10係寫入方法之流程圖,圖11係寫入時之施加至選擇字元線WL之電壓之時序圖。 Next, a method of writing data will be described using FIG. 9 to FIG. Fig. 10 is a flow chart of the writing method, and Fig. 11 is a timing chart of the voltage applied to the selected word line WL at the time of writing.
首先,列解碼器11響應控制部15之命令而選擇任一條字元線WL,且對選擇字元線WL施加程序化電壓VPGM,以對資料進行編程。在圖9之例中,選擇字元線WL1,於串組GR1-1及GR1-2中連接於字元線WL1之6個記憶體胞電晶體MT中對資料進行編程(步驟S10)。 First, the column decoder 11 selects any word line WL in response to a command from the control unit 15, and applies a program voltage VPGM to the selected word line WL to program the material. In the example of Fig. 9, the word line WL1 is selected, and the data is programmed in the six memory cell transistors MT connected to the word line WL1 among the string groups GR1-1 and GR1-2 (step S10).
此時,列解碼器11如圖11所示般將程式電壓VPGM1、VPGM2、及VPGM3依序施加至選擇字元線WL1。電壓VPGM1~VPGM3為分別用於第1~第3胞之程式化用電壓,且存在VPGM1<VPGM2<VPGM3之關係。又,列解碼器11對非選擇字元線WL2~WL4施加電壓VPASS。電壓VPASS係不論保持資料,皆使記憶體胞電晶體MT導通之電壓,且為較程式電壓VPGM1~VPGM3更低之電壓。又,列解碼器11對選擇閘極線GSL1施加電壓VSG,對選擇閘極線GSL2施加例如0V。電壓VSG係使成為編程對象之NAND串SR之選擇電晶體ST1導通,且使成為非編程對象之NAND串SR之選擇電晶體ST1斷開之電壓。另,藉由對控制信號線SSL2~SSL4賦予“低”電壓,而使非選擇串組GR2~GR4與位元線BL電性分離。 At this time, the column decoder 11 sequentially applies the program voltages VPGM1, VPGM2, and VPGM3 to the selected word line WL1 as shown in FIG. The voltages VPGM1 to VPGM3 are used for the staging voltages of the first to third cells, respectively, and there is a relationship of VPGM1 < VPGM2 < VPGM3. Further, the column decoder 11 applies a voltage VPASS to the unselected word lines WL2 to WL4. The voltage VPASS is a voltage at which the memory cell transistor MT is turned on regardless of the data held, and is a voltage lower than the program voltages VPGM1 to VPGM3. Further, the column decoder 11 applies a voltage VSG to the selection gate line GSL1 and applies, for example, 0V to the selection gate line GSL2. The voltage VSG is a voltage at which the selection transistor ST1 of the NAND string SR to be programmed is turned on, and the selection transistor ST1 of the NAND string SR to be non-programmed is turned off. Further, by giving a "low" voltage to the control signal lines SSL2 to SSL4, the non-selected string groups GR2 to GR4 are electrically separated from the bit line BL.
列解碼器11將電壓VPGM1施加至選擇字元線WL1期間,感測放大器模組12對連接有第1胞之位元線BL(在圖9之例中為BL1)施加0V。藉此,在包含第1胞之NAND串SR1中導通選擇電晶體ST1,而於第1胞中對資料進行編程。又,列解碼器11對連接有第2胞及第3胞之位元線BL(在圖9之例中為BL2~BL6)施加電壓V1(>0V)。藉此,在包含第2胞及第3胞之NAND串SR中切斷選擇電晶體ST1,而禁止對第2胞及第3胞之編程。 While the column decoder 11 applies the voltage VPGM1 to the selected word line WL1, the sense amplifier module 12 applies 0 V to the bit line BL to which the first cell is connected (BL1 in the example of FIG. 9). Thereby, the selection transistor ST1 is turned on in the NAND string SR1 including the first cell, and the data is programmed in the first cell. Further, the column decoder 11 applies a voltage V1 (>0 V) to the bit line BL (BL2 to BL6 in the example of FIG. 9) to which the second cell and the third cell are connected. Thereby, the selection transistor ST1 is turned off in the NAND string SR including the second cell and the third cell, and the programming of the second cell and the third cell is prohibited.
接著,於列解碼器11將電壓VPGM2施加至選擇字元線WL1期間,感測放大器模組12對連接有第2胞之位元線BL(在圖9之例中為BL2~BL5)施加0V。藉此,在包含第2胞之NAND串SR中導通選擇電晶體ST1,而於第2胞中對資料進行編程。又,列解碼器11對連接有第1胞及第3胞之位元線BL(在圖9之例中為BL1及BL6)施加電壓V1。藉此,禁止對第1胞及第3胞之編程。 Next, during the application of the voltage VPGM2 to the selected word line WL1 by the column decoder 11, the sense amplifier module 12 applies 0V to the bit line BL to which the second cell is connected (BL2 to BL5 in the example of FIG. 9). . Thereby, the selection transistor ST1 is turned on in the NAND string SR including the second cell, and the data is programmed in the second cell. Further, the column decoder 11 applies a voltage V1 to the bit line BL (BL1 and BL6 in the example of FIG. 9) to which the first cell and the third cell are connected. Thereby, programming of the first cell and the third cell is prohibited.
接著,於列解碼器11將電壓VPGM3施加至選擇字元線WL1期間,感測放大器模組12對連接有第3胞之位元線BL(在圖9之例中為 BL6)施加0V。藉此,於第3胞中對資料進行編程。又,列解碼器11對連接有第1胞及第2胞之位元線BL(在圖9之例中為BL1~BL5)施加電壓V1。藉此,禁止對第1胞及第2胞之編程。 Next, during the application of the voltage VPGM3 to the selected word line WL1 by the column decoder 11, the sense amplifier module 12 pairs the bit line BL to which the third cell is connected (in the example of FIG. BL6) Apply 0V. Thereby, the data is programmed in the third cell. Further, the column decoder 11 applies a voltage V1 to the bit line BL (BL1 to BL5 in the example of FIG. 9) to which the first cell and the second cell are connected. Thereby, programming of the first cell and the second cell is prohibited.
藉由以上3個步驟,於連接於字元線WL1之第1~第3胞中依序對資料進行編程。記憶體胞電晶體MT相當於第1~第3胞之何者,可根據記憶體胞電晶體MT之位址判斷。即,控制部15及列解碼器11可根據成為寫入對象之記憶體胞電晶體MT之位址、與應寫入於該記憶體胞電晶體MT之資料,而決定施加第1至第3程式電壓之何者。 By the above three steps, the data is sequentially programmed in the first to third cells connected to the word line WL1. The memory cell transistor MT corresponds to the first to third cells, and can be judged based on the address of the memory cell transistor MT. In other words, the control unit 15 and the column decoder 11 can determine the first to third applications based on the address of the memory cell MT to be written and the data to be written in the memory cell MT. Which of the program voltages.
接著,控制部15驗證步驟S10中之編程之結果即於記憶體胞電晶體MT中所編程之資料(步驟S11)。 Next, the control unit 15 verifies the result of the programming in step S10, that is, the data programmed in the memory cell transistor MT (step S11).
此時,列解碼器11響應控制部15之命令,而如圖11所示般將驗證電壓Vfy_A、Vfy_B、及Vfy_C依序施加至選擇字元線WL1。又,列解碼器11對非選擇字元線WL2~WL4施加電壓VREAD。電壓VREAD係不論保持資料,皆為使記憶體胞電晶體MT導通之電壓。又,列解碼器11對選擇閘極線GSL1及GSL2施加高位準,以使選擇電晶體ST1及ST2導通。另,藉由對控制信號線SSL2~SSL4賦予“低”位準,而使非選擇串組GR2~GR4與位元線BL電性分離。 At this time, the column decoder 11 responds to the command of the control unit 15 to sequentially apply the verification voltages Vfy_A, Vfy_B, and Vfy_C to the selected word line WL1 as shown in FIG. Further, the column decoder 11 applies a voltage VREAD to the unselected word lines WL2 to WL4. The voltage VREAD is a voltage that turns on the memory cell MT regardless of the data. Further, the column decoder 11 applies a high level to the selection gate lines GSL1 and GSL2 to turn on the selection transistors ST1 and ST2. Further, the non-selected string groups GR2 to GR4 are electrically separated from the bit line BL by giving a "low" level to the control signal lines SSL2 to SSL4.
在驗證動作期間,感測放大器模組12對位元線BL1~BL6施加預充電電壓,而感測、放大流動於位元線BL1~BL6之電流。藉此,判別記憶體胞電晶體MT中所編程之資料。 During the verifying operation, the sense amplifier module 12 applies a precharge voltage to the bit lines BL1 BLBL6 to sense and amplify the current flowing through the bit lines BL1 BLBL6. Thereby, the data programmed in the memory cell transistor MT is discriminated.
施加有驗證電壓Vfy_A時,若於應寫入“A”位準之記憶體胞電晶體MT之所連接之位元線BL內流動有電流,則該記憶體胞電晶體MT之閾值未上升至“A”位準,故可知對該記憶體胞電晶體MT之編程未完成(將其稱為驗證失敗)。另一方面,若流動有電流,則該記憶體胞電晶體MT之閾值已上升至“A”位準,故可知對該記憶體胞電晶體之編程已完成(稱其為通過驗證)。對“B”位準及“C”位準之編程 亦相同。 When the verification voltage Vfy_A is applied, if a current flows in the bit line BL connected to the memory cell MT to which the "A" level is to be written, the threshold of the memory cell MT does not rise to The "A" level is known, so that the programming of the memory cell MT is not completed (referred to as verification failure). On the other hand, if a current flows, the threshold of the memory cell MT has risen to the "A" level, so that the programming of the memory cell is completed (referred to as verification). Programming of the "B" level and the "C" level The same is true.
步驟S11之結果,若對第1胞之編程完成(步驟S12:YES),對第3胞之編程完成(步驟S13:YES),對第2胞之編程完成(步驟S14:YES),則控制部15判斷為對選擇頁面之所需之資料之編程已正常完成,而結束寫入動作。 As a result of the step S11, if the programming of the first cell is completed (step S12: YES), the programming of the third cell is completed (step S13: YES), and the programming of the second cell is completed (step S14: YES), then control is performed. The part 15 judges that the programming of the material required for selecting the page has been normally completed, and ends the writing operation.
步驟S11之結果,若對第1胞之編程完成(步驟S12:YES),而對第3胞之編程未完成(步驟S13:NO),則控制部15省略電壓VPGM1之施加,且一面將電壓VPGM2及VPGM3升壓(步驟S15),一面重複進行步驟S10之處理。 As a result of the step S11, if the programming of the first cell is completed (step S12: YES) and the programming of the third cell is not completed (step S13: NO), the control unit 15 omits the application of the voltage VPGM1, and the voltage is applied to one side. The VPGM2 and VPGM3 are boosted (step S15), and the process of step S10 is repeated.
步驟S11之結果,若對第1胞之編程未完成(步驟S12:NO),且對第3胞之編程亦未完成(步驟S16:NO),則控制部15一面將電壓VPGM1~VPGM3升壓(步驟S17),一面重複進行步驟S10之處理。若對第3胞之編程已完成(步驟S16:YES),則控制部15省略電壓VPGM3之施加,且一面將電壓VPGM1及VPGM2升壓(步驟S18),一面重複進行步驟S10之處理。 As a result of the step S11, if the programming of the first cell is not completed (step S12: NO), and the programming of the third cell is not completed (step S16: NO), the control unit 15 boosts the voltages VPGM1 to VPGM3. (Step S17), the process of Step S10 is repeated. When the programming of the third cell is completed (step S16: YES), the control unit 15 omits the application of the voltage VPGM3, and increases the voltages VPGM1 and VPGM2 (step S18), and repeats the process of step S10.
步驟S11之結果,若對第1及第3胞之編程完成(步驟S12:YES;步驟S13:YES),而對第2胞之編程未完成(步驟S14:NO),則控制部15省略電壓VPGM1及VPGM3之施加,而一面將電壓VPGM2升壓(步驟S19),一面重複進行步驟S10之處理。 As a result of the step S11, if the programming of the first and third cells is completed (step S12: YES; step S13: YES), and the programming of the second cell is not completed (step S14: NO), the control unit 15 omits the voltage. When VPGM1 and VPGM3 are applied, the voltage VPGM2 is boosted (step S19), and the process of step S10 is repeated.
在圖11之例中,第2次編程之結果,第1胞通過驗證(時刻t4)。因此,控制部15在第3次編程中省略電壓VPGM1之施加。又,第3次編程之結果,第3胞通過驗證(時刻t6)。因此,控制部15在第4次編程中進而省略電壓VPGM3之施加。 In the example of Fig. 11, as a result of the second programming, the first cell passes the verification (time t4). Therefore, the control unit 15 omits the application of the voltage VPGM1 in the third programming. Further, as a result of the third programming, the third cell passes the verification (time t6). Therefore, the control unit 15 further omits the application of the voltage VPGM3 in the fourth programming.
若為本實施形態之構成,則可提高資料之寫入速度。以下,對本效果進行說明。 According to the configuration of the embodiment, the writing speed of the data can be increased. Hereinafter, the effect will be described.
圖12係NAND型快閃記憶體之通常之寫入方法之字元線電壓之時序圖。如圖示,在資料之編程時,將程式電壓VPGM施加至選擇字元線,而對應寫入“A”~“C”位準之記憶體胞電晶體MT統一將資料進行編程,其後,執行驗證動作。即,由1次程式電壓VPGM之施加與驗證動作構成1次程式迴路,該程式迴路係將程式電壓升壓而反復進行。 Fig. 12 is a timing chart of the word line voltage of the usual writing method of the NAND type flash memory. As shown in the figure, during the programming of the data, the program voltage VPGM is applied to the selected word line, and the memory cell MT corresponding to the "A" to "C" level is uniformly programmed to program the data, and thereafter, Perform a verification action. In other words, the application and verification operation of the primary program voltage VPGM constitutes a primary program loop, which is repeated by stepping up the program voltage.
然而,將此種寫入方法應用於利用圖2至圖6所說明之快閃記憶體之情形時,有寫入所需時間非常長之虞。如圖2至圖6般,於將NAND串SR中串聯連接之記憶體胞電晶體MT平行配置於半導體基板面,進而將NAND串SR積層於相對半導體基板面之垂直方向之情形時,1頁面中所含之記憶體胞電晶體MT之電流路徑之寬度不同,而於寫入速度上產生偏差。即,在同一頁面中,混合存在寫入較快之記憶體胞電晶體MT與較慢之記憶體胞電晶體MT。其理由係記憶體胞陣列10之製造過程所致。即,記憶體胞陣列10係藉由在於半導體基板20上積層絕緣膜22-1~22-4及半導體層23-1~23-4後,對該等層22-1~22-4及23-1~23-4統一進行圖案化而形成。其結果,如圖5所示,導致於葉片型構造24中產生錐角。 However, when such a writing method is applied to the case of using the flash memory explained with reference to Figs. 2 to 6, there is a long time required for writing. As shown in FIG. 2 to FIG. 6 , when the memory cell transistors MT connected in series in the NAND string SR are arranged in parallel on the surface of the semiconductor substrate, and the NAND string SR is laminated in the vertical direction with respect to the surface of the semiconductor substrate, 1 page The width of the current path of the memory cell MT included in the memory is different, and a deviation occurs in the writing speed. That is, in the same page, the memory cell transistor MT and the slower memory cell transistor MT which are written faster are mixed. The reason is due to the manufacturing process of the memory cell array 10. That is, the memory cell array 10 is formed by laminating the insulating films 22-1 to 22-4 and the semiconductor layers 23-1 to 23-4 on the semiconductor substrate 20, and then the layers 22-1 to 22-4 and 23 -1~23-4 are formed by patterning in a unified manner. As a result, as shown in FIG. 5, a taper angle is generated in the blade-type structure 24.
因此,在寫入資料時,需要對資料寫入速度最高之記憶體胞電晶體MT加以注意,以免過度編程。即,圖12之最初之程式迴路中所使用之電壓VPGM設定為充分低之值,以免對位於最下層之層且寫入“A”位準之記憶體胞電晶體MT過度編程。 Therefore, when writing data, it is necessary to pay attention to the memory cell MT with the highest data writing speed to avoid over programming. That is, the voltage VPGM used in the initial program loop of FIG. 12 is set to a sufficiently low value to avoid over programming the memory cell transistor MT located at the lowest layer and writing the "A" level.
如此,如圖12所示,寫入動作之前半段程式動作實質上僅有助於寫入速度較高之記憶體胞電晶體MT(即第1胞),該期間之編程脈衝對寫入速度較低之第3胞之閾值電壓幾乎不會造成影響。且,在進行到寫入動作之後半段程式動作時,方對第3胞開始實質性之編程。 Thus, as shown in FIG. 12, the program operation in the first half of the write operation substantially contributes only to the memory cell MT (ie, the first cell) having a higher write speed, and the program pulse pair write speed during the period. The threshold voltage of the lower third cell hardly affects. Moreover, when the program is operated halfway after the writing operation, the third cell starts to be substantially programmed.
即,資料編程雖係以頁面為單位統一執行,但實質上係依序對 頁面內之第1至第3胞進行編程。因此,程式迴路次數非常多,以致在寫入時間上需要較長時間。 That is, data programming is performed uniformly on a page-by-page basis, but in essence The first to third cells in the page are programmed. Therefore, the number of program loops is so large that it takes a long time to write.
與之相對,若為本實施形態,藉由在1次程式迴路中準備複數種程式電壓,在最初之程式迴路中亦可對第3胞進行實質性之編程,從而可縮短寫入時間。 On the other hand, in the present embodiment, by preparing a plurality of program voltages in a single program loop, the third cell can be substantially programmed in the first program loop, thereby shortening the writing time.
即,在本實施形態中,將程式電壓VPGM分離為以下3個脈衝。 That is, in the present embodiment, the program voltage VPGM is separated into the following three pulses.
(1)位於寫入較快之層,施加至“A”位準寫入胞(第1胞)之脈衝:VPGM1 (1) A pulse applied to the "A" level write cell (first cell) at a faster write level: VPGM1
(2)位於寫入較慢之層,施加至“C”位準寫入胞(第3胞)之脈衝:VPGM3 (2) A pulse placed on the slower write layer and applied to the "C" level write cell (3rd cell): VPGM3
(3)施加至上述(1)及(2)以外之胞(第2胞)之脈衝:VPGM2。 (3) Pulse applied to cells other than the above (1) and (2) (second cell): VPGM2.
且,在1次程式迴路中,依序施加上述(1)至(3)之脈衝。該等脈衝之初始值係根據利用該等脈衝予以編程之記憶體胞電晶體MT之寫入速度及寫入資料而設為最佳值。即,電壓VPGM3之初始值只要為不會對第3胞過度編程之值,則亦可為對第1胞或第2胞過度編程之值。當然,電壓VPGM1之初始值設定為在1次程式動作中不會對第1胞過度編程之值。 Further, in the first program loop, the pulses of the above (1) to (3) are sequentially applied. The initial values of the pulses are set to optimum values based on the write speed of the memory cell MT programmed with the pulses and the write data. That is, the initial value of the voltage VPGM3 may be a value that is over programmed for the first cell or the second cell as long as it is a value that does not over-program the third cell. Of course, the initial value of the voltage VPGM1 is set to a value that does not over-program the first cell in one program operation.
藉此,可自最初之程式迴路,對第1胞至第3胞全體執行實質性之編程。換言之,在最初之程式迴路中,亦可使第3胞之閾值電壓有效上升。其結果,可大幅減少程式迴路次數,而提高寫入速度。 Thereby, substantial programming can be performed on the first to third cells from the initial program loop. In other words, in the initial program loop, the threshold voltage of the third cell can also be effectively raised. As a result, the number of program loops can be greatly reduced, and the write speed can be increased.
另,圖11中雖顯示先省略VPGM1,繼而省略VPGM3之例,但亦可為相反之情形,或亦可為同時省略VPGM1及VPGM3之情形。 In addition, although FIG. 11 shows an example in which VPGM1 is omitted first, and then VPGM3 is omitted, it may be the reverse case, or the case where VPGM1 and VPGM3 are omitted at the same time.
作為採用上述寫入方法之結果,在任一程式迴路中,列解碼器11對選擇字元線WL依序施加M次(M為1以上之自然數)程式電壓(圖11之t5~t6、t7~t8),接著對選擇字元線WL依序施加N次(N大於M,且為3以上之自然數)驗證電壓Vfy(圖11之t6~t7、及t7以後)。且,在任意 之程式迴路中,程式電壓之施加次數均不會超過驗證電壓之施加次數,或與驗證電壓之施加次數相同,或其以下。 As a result of the above-described writing method, in any of the program loops, the column decoder 11 sequentially applies M times (M is a natural number of 1 or more) to the selected word line WL (t5 to t6, t7 in Fig. 11). ~t8), then the selected word line WL is sequentially applied N times (N is greater than M, and is a natural number of 3 or more) to verify the voltage Vfy (t6 to t7, and after t7 in Fig. 11). And, at random In the program loop, the application voltage is not applied more than the number of times the verification voltage is applied, or the same as the number of times the verification voltage is applied, or less.
進而換言之,對記憶體胞之資料之寫入係藉由反復進行複數次包含對選擇字元線WL施加程式電壓之程式動作、與對選擇字元線施加驗證電壓之驗證動作之程式迴路而執行。在該重複複數次之程式迴路中、連續之2次程式迴路(圖11之t3~t5與t5~t6)之間,列解碼器11一面使驗證電壓Vfy之施加次數不變,一面使第2次程式迴路(圖11之t5~t6)之程式電壓之施加次數(3次:VPGM1-VPGM3)相較於第1次程式迴路(圖11之t3~t5)減少(2次:VPGM2、VPGM3)。 Furthermore, in other words, the writing of the data of the memory cell is performed by repeating a plurality of program steps including a program operation for applying a program voltage to the selected word line WL and a verification operation for applying a verification voltage to the selected word line. . Between the repeated program loops and the two consecutive program loops (t3 to t5 and t5 to t6 in FIG. 11), the column decoder 11 keeps the number of times the verification voltage Vfy is applied while making the second The number of times the program voltage is applied to the secondary program loop (t5 to t6 in Fig. 11) (3 times: VPGM1-VPGM3) is reduced compared to the first program loop (t3 to t5 in Fig. 11) (2 times: VPGM2, VPGM3) .
例如,列解碼器11在某程式循環中對上述選擇字元線依序施加M次程式電壓。將該M次中之任一程式電壓(圖11及圖16之VPGM1)施加至選擇字元線WL時,將位於最下層之第1記憶體胞設為編程對象,至少位於最上層之第3記憶體胞設為非編程對象。且,列解碼器11在下一個程式迴路中,省略對上述選擇字元線施加上述任一程式電壓(圖11及圖16之VPGM1)(圖11之t5-t6及圖16之t5以後)。該例為較VPGM3更先停止施加VPGM1之情形。 For example, the column decoder 11 sequentially applies the program voltage to the selected word line M times in a certain program loop. When the voltage of any one of the M times (VPGM1 of FIG. 11 and FIG. 16) is applied to the selected word line WL, the first memory cell located at the lowermost layer is set as the programming object, and at least the third layer of the uppermost layer. Memory cells are set to non-programming objects. Further, in the next program loop, the column decoder 11 omits the application of any of the above program voltages (VPGM1 of Figs. 11 and 16) to the selected word line (t5-t6 in Fig. 11 and t5 after Fig. 16). This example is the case where VPGM1 is stopped earlier than VPGM3.
另一方面,將M次中之其他程式電壓(圖11及圖14之VPGM3)施加至選擇字元線WL時,將位於最上層之第3記憶體胞設為編程對象,至少位於最下層之第1記憶體胞設為非編程對象。且,列解碼器11在下一個程式迴路中,省略施加上述任一程式電壓(圖11及圖14之VPGM3)(圖14之t5以後)。該例為較VPGM1更先停止施加VPGM3之情形。 On the other hand, when the other program voltages of M times (VPGM3 of FIGS. 11 and 14) are applied to the selected word line WL, the third memory cell located at the uppermost layer is set as the programming object, at least in the lowermost layer. The first memory cell is set as a non-programming object. Further, in the next program loop, the column decoder 11 omits the application of any of the above program voltages (VPGM3 of Figs. 11 and 14) (after t5 of Fig. 14). This example is the case where VPGM3 is stopped first than VPGM1.
當然,在下一個程式迴路中,亦可為同時停止施加複數個程式電壓之情形。 Of course, in the next program loop, it is also possible to stop applying a plurality of program voltages at the same time.
在圖12之例中,亦可在1次程式迴路中施加複數次程式電壓。然而,圖12之情形時,將該等程式電壓與寫入位準相關連。因此,程式 電壓之施加之削減與對某位準之寫入之完成係完全一致。換言之,當停止施加某程式電壓時,同時亦停止施加某驗證電壓。 In the example of Fig. 12, a plurality of program voltages can also be applied in one program loop. However, in the case of Figure 12, the program voltages are associated with the write level. Therefore, the program The reduction in voltage application is exactly the same as the completion of a certain level of writing. In other words, when the application of a certain program voltage is stopped, the application of a certain verification voltage is also stopped.
與之相對,根據本實施形態,對程式電壓,不僅與寫入位準相關連,亦與記憶體胞之位置相關連。因此,即使已停止施加例如某程式電壓,卻未必停止施加驗證電壓。 On the other hand, according to the present embodiment, the program voltage is associated not only with the writing level but also with the position of the memory cell. Therefore, even if the application of, for example, a certain program voltage has been stopped, the application of the verification voltage is not necessarily stopped.
接著,對第2實施形態之半導體記憶裝置進行說明。本實施形態係在上述第1實施形態所說明之資料寫入方法中,藉由將程式電壓VPGM1包含於VPGM2內,而將1次程式迴路所使用之編程脈衝數減至2個者。以下,僅對其與第1實施形態不同之點進行說明。 Next, a semiconductor memory device according to a second embodiment will be described. In the data writing method described in the first embodiment, the program voltage VPGM1 is included in the VPGM 2, and the number of programming pulses used in the primary program circuit is reduced to two. Hereinafter, only differences from the first embodiment will be described.
利用圖13及圖14,對本實施形態之資料之寫入動作進行說明。圖13係寫入方法之流程圖,圖14係寫入時之施加至選擇字元線WL之電壓之時序圖。 The data writing operation of the present embodiment will be described with reference to Figs. 13 and 14 . Fig. 13 is a flow chart of the writing method, and Fig. 14 is a timing chart of the voltage applied to the selected word line WL at the time of writing.
首先,列解碼器11響應控制部15之命令而選擇任一條字元線WL,且對選擇字元線WL施加程式電壓VPGM,以對資料進行編程(步驟S20)。 First, the column decoder 11 selects any word line WL in response to a command from the control unit 15, and applies a program voltage VPGM to the selected word line WL to program the material (step S20).
此時,列解碼器11將程式電壓VPGM2a及VPGM3依序施加至選擇字元線WL。電壓VPGM2a係用於第1及第2胞之程式電壓,且存在VPGM2a<VPGM3之關係。又,例如雖為VPGM1≦VPGM2a≦VPGM2,但VPGM2a為例如不會在1次編程中對第1胞過度編程之值。 At this time, the column decoder 11 sequentially applies the program voltages VPGM2a and VPGM3 to the selected word line WL. The voltage VPGM2a is used for the program voltages of the first and second cells, and has a relationship of VPGM2a < VPGM3. Further, for example, although VPGM1≦VPGM2a≦VPGM2, VPGM2a is, for example, a value that does not over-program the first cell in one programming.
於列解碼器11將電壓VPGM2a施加至選擇字元線WL期間,感測放大器模組12對連接有第1及第2胞之位元線BL(在圖9之例中為BL1~BL5)施加0V。藉此,在包含第1及第2胞之NAND串SR中導通選擇電晶體ST1,於第1及第2胞中對資料進行編程。又,列解碼器11對連接有第3胞之位元線BL(在圖9之例中為BL6)施加電壓V1。藉此,禁止對 第3胞之編程。 During the application of the voltage VPGM2a to the selected word line WL by the column decoder 11, the sense amplifier module 12 applies the bit lines BL (BL1 to BL5 in the example of FIG. 9) to which the first and second cells are connected. 0V. Thereby, the selection transistor ST1 is turned on in the NAND string SR including the first and second cells, and the data is programmed in the first and second cells. Further, the column decoder 11 applies a voltage V1 to the bit line BL (BL6 in the example of FIG. 9) to which the third cell is connected. By this, it is forbidden Programming of the third cell.
藉由以上2個步驟,於連接於選擇字元線WL之第1及第2胞、以及第3胞中對資料依序進行編程。 By the above two steps, the data is sequentially programmed in the first and second cells and the third cell connected to the selected word line WL.
接著,控制部15驗證於記憶體胞電晶體MT中所編程之資料(步驟S21)。步驟S21係與第1實施形態所說明之步驟S11相同。 Next, the control unit 15 verifies the data programmed in the memory cell transistor MT (step S21). Step S21 is the same as step S11 described in the first embodiment.
步驟S21之結果,若對第1及第2胞之編程完成(步驟S22:YES),且對第3胞之編程亦完成(步驟S23:YES),則控制部15判斷為對選擇頁面之所需之資料之編程已正常完成,而結束寫入動作。 As a result of the step S21, if the programming of the first and second cells is completed (step S22: YES), and the programming of the third cell is also completed (step S23: YES), the control unit 15 determines that the page is selected. The programming of the required data has been completed normally, and the writing operation is ended.
步驟S21之結果,若對第1及第2胞之編程完成(步驟S22:YES),對第3胞之編程未完成(步驟S23:NO),則控制部15省略施加電壓VPGM2a,且一面將電壓VPGM3升壓(步驟S24),一面重複進行步驟S20之處理。 As a result of the step S21, if the programming of the first and second cells is completed (step S22: YES), the programming of the third cell is not completed (step S23: NO), the control unit 15 omits the application of the voltage VPGM2a, and one side will The voltage VPGM3 is boosted (step S24), and the process of step S20 is repeated.
步驟S21之結果,若對第1及第2胞之至少任一者之編程未完成(步驟S22:NO),對第3胞之編程亦未完成(步驟S25:NO),則控制部15一面將電壓VPGM2a及VPGM3升壓(步驟S26),一面重複進行步驟S20之處理。若對第3胞之編程已完成(步驟S25:YES),則控制部15省略施加電壓VPGM3,且一面將電壓VPGM2a升壓(步驟S27),一面重複進行步驟S20之處理。 As a result of the step S21, if the programming of at least one of the first and second cells is not completed (step S22: NO), and the programming of the third cell is not completed (step S25: NO), the control unit 15 The voltages VPGM2a and VPGM3 are boosted (step S26), and the process of step S20 is repeated. When the programming of the third cell is completed (step S25: YES), the control unit 15 repeats the process of step S20 while omitting the application of the voltage VPGM3 and boosting the voltage VPGM2a (step S27).
根據本實施形態,乃使用程式電壓VPGM2a,對第1及第2胞同時進行編程。因此,可與第1實施形態相同,削減程式迴路次數,並減少程式電壓之種類,從而可簡化電路構成。 According to the present embodiment, the first and second cells are simultaneously programmed using the program voltage VPGM2a. Therefore, as in the first embodiment, the number of program loops can be reduced, and the type of the program voltage can be reduced, so that the circuit configuration can be simplified.
接著,對第3實施形態之半導體記憶裝置進行說明。本實施形態係在上述第1實施形態所說明之資料寫入方法中,藉由將程式電壓VPGM3包含於VPGM2內,而將1次程式迴路所使用之編程脈衝數減至 2個者。以下,僅對其與第1實施形態不同之點進行說明。 Next, a semiconductor memory device according to a third embodiment will be described. In the data writing method described in the first embodiment, the program voltage VPGM3 is included in the VPGM 2, and the number of programming pulses used in the primary circuit is reduced to 2 people. Hereinafter, only differences from the first embodiment will be described.
利用圖15及圖16,對本實施形態之資料之寫入動作進行說明。圖15係寫入方法之流程圖,圖16係寫入時之施加至選擇字元線WL之電壓之時序圖。 The writing operation of the data of this embodiment will be described with reference to Figs. 15 and 16 . Fig. 15 is a flow chart of the writing method, and Fig. 16 is a timing chart of the voltage applied to the selected word line WL at the time of writing.
首先,列解碼器11響應控制部15之命令而選擇任一條字元線WL。且,列解碼器11對選擇字元線WL施加程式電壓VPGM,而對資料進行編程(步驟S30)。 First, the column decoder 11 selects any one of the word lines WL in response to a command from the control unit 15. Further, the column decoder 11 applies the program voltage VPGM to the selected word line WL to program the material (step S30).
此時,列解碼器11將程式電壓VPGM1及VPGM2b依序施加至選擇字元線WL。電壓VPGM2b係用於第2及第3胞之程式電壓,且存在VPGM2b>VPGM1之關係。又,例如為VPGM2≦VPGM2b≦VPGM3。VPGM2a為例如不會在1次編程中對第2胞過度編程之值。於列解碼器11將電壓VPGM2b施加至選擇字元線WL期間,感測放大器模組12對連接有第2及第3胞之位元線BL(在圖9之例中為BL2~BL6)施加0V。藉此,在包含第2及第3胞之NAND串SR中,導通選擇電晶體ST1,於第2及第3胞中對資料進行編程。又,列解碼器11對連接有第1胞之位元線BL(在圖9之例中為BL1)施加電壓V1。藉此,禁止對第1胞之編程。 At this time, the column decoder 11 sequentially applies the program voltages VPGM1 and VPGM2b to the selected word line WL. The voltage VPGM2b is used for the program voltages of the second and third cells, and has a relationship of VPGM2b>VPGM1. Further, for example, it is VPGM2≦VPGM2b≦VPGM3. VPGM2a is, for example, a value that does not over-program the second cell in one programming. During the application of the voltage VPGM2b to the selected word line WL by the column decoder 11, the sense amplifier module 12 applies the bit line BL to which the second and third cells are connected (in the example of FIG. 9 to BL2 to BL6). 0V. Thereby, in the NAND string SR including the second and third cells, the selection transistor ST1 is turned on, and the data is programmed in the second and third cells. Further, the column decoder 11 applies a voltage V1 to the bit line BL (BL1 in the example of FIG. 9) to which the first cell is connected. Thereby, the programming of the first cell is prohibited.
藉由以上2個步驟,於連接於選擇字元線WL之第1胞、以及第2及第3胞中對資料依序進行編程。 By the above two steps, the data is sequentially programmed in the first cell and the second and third cells connected to the selected word line WL.
接著,控制部15驗證於記憶體胞電晶體MT中所編程之資料(步驟S31)。步驟S31係與第1實施形態所說明之步驟S11相同。 Next, the control unit 15 verifies the data programmed in the memory cell transistor MT (step S31). Step S31 is the same as step S11 described in the first embodiment.
步驟S31之結果,若對第1胞之編程完成(步驟S32:YES),對第2及第3胞之編程亦完成(步驟S33:YES),則控制部15判斷為對選擇頁面之所需之資料之編程已正常完成,而結束寫入動作。 As a result of the step S31, if the programming of the first cell is completed (step S32: YES), the programming of the second and third cells is also completed (step S33: YES), the control unit 15 determines that it is necessary for the selection page. The programming of the data has been completed normally, and the writing operation is ended.
步驟S31之結果,若對第1胞之編程完成(步驟S32:YES),對第2 及第3胞之至少任一者之編程未完成(步驟S33:NO),則控制部15省略施加電壓VPGM1,且一面將電壓VPGM2b升壓(步驟S34),一面重複進行步驟S30之處理。 As a result of step S31, if the programming of the first cell is completed (step S32: YES), the second is performed. When the programming of at least one of the third cells is not completed (step S33: NO), the control unit 15 repeats the process of step S30 while omitting the application of the voltage VPGM1 and boosting the voltage VPGM2b (step S34).
步驟S31之結果,若對第1胞之編程未完成(步驟S32:NO),對第2及第3胞之至少任一者之編程亦未完成(步驟S35:NO),則控制部15一面將電壓VPGM1及VPGM2b升壓(步驟S36),一面重複進行步驟S30之處理。若對第2及第3胞之編程已完成(步驟S35:YES),則控制部15省略施加電壓VPGM2b,且一面將電壓VPGM1升壓(步驟S37),一面重複進行步驟S30之處理。 As a result of the step S31, if the programming of the first cell is not completed (step S32: NO), the programming of at least one of the second and third cells is not completed (step S35: NO), the control unit 15 The voltages VPGM1 and VPGM2b are boosted (step S36), and the process of step S30 is repeated. When the programming of the second and third cells is completed (step S35: YES), the control unit 15 omits the application of the voltage VPGM2b and boosts the voltage VPGM1 (step S37), and repeats the process of step S30.
根據本實施形態,乃使用程式電壓VPGM2b,對第2及第3胞同時進行編程。因此,可獲得與第2實施形態相同之效果。 According to the present embodiment, the second and third cells are simultaneously programmed using the program voltage VPGM2b. Therefore, the same effects as those of the second embodiment can be obtained.
接著,對第4實施形態之半導體記憶裝置進行說明。本實施形態係在上述第1實施形態所說明之資料寫入方法中,藉由在施加程式電壓VPGM2時使第1胞之通道電位上升,省略施加VPGM1,而將1次程式迴路所使用之編程脈衝數減至2個者。以下,僅對其與第1實施形態不同之點進行說明。 Next, a semiconductor memory device according to a fourth embodiment will be described. In the data writing method described in the above-described first embodiment, when the program voltage VPGM2 is applied, the channel potential of the first cell is raised, and VPGM1 is omitted, and the programming used for the first-order circuit is programmed. The number of pulses is reduced to two. Hereinafter, only differences from the first embodiment will be described.
利用圖17及圖18,對本實施形態之資料之寫入動作進行說明。圖17係寫入方法之流程圖,圖18係編程時施加至選擇字元線WL及位元線BL之電壓之時序圖。 The data writing operation of the present embodiment will be described with reference to Figs. 17 and 18 . 17 is a flow chart of a writing method, and FIG. 18 is a timing chart of voltages applied to the selected word line WL and the bit line BL at the time of programming.
首先,列解碼器11響應控制部15之命令而選擇任一條字元線WL,且對選擇字元線WL施加程式電壓VPGM,以對資料進行編程(步驟S40)。 First, the column decoder 11 selects one of the word lines WL in response to a command from the control unit 15, and applies a program voltage VPGM to the selected word line WL to program the material (step S40).
此時,列解碼器11將程式電壓VPGM2及VPGM3依序施加至選擇 字元線WL。如第1實施形態所說明般,電壓VPGM2為於對第2胞之編程中最佳化之電壓。不施加電壓VPGM1。 At this time, the column decoder 11 sequentially applies the program voltages VPGM2 and VPGM3 to the selection. Word line WL. As described in the first embodiment, the voltage VPGM2 is a voltage optimized for programming the second cell. Voltage VPGM1 is not applied.
圖19係施加電壓VPGM2時之記憶體胞陣列10之電路圖。在本實施形態中,施加電壓VPGM2時,不僅對第2胞執行編程,且亦對第1胞執行編程。此時,感測放大器模組12對連接有第1胞之位元線BL(在圖19之例中為BL1)施加電壓VQPW。電壓VQPW為較施加至連接有第2胞之位元線BL(在圖19之例中為BL2~BL5)之電壓更大之電壓,例如VQPW>0V。又,VQPW亦為可由閘極中施加有電壓VSG之選擇電晶體ST1傳送之電壓。 Fig. 19 is a circuit diagram of the memory cell array 10 when the voltage VPGM2 is applied. In the present embodiment, when the voltage VPGM2 is applied, not only the programming of the second cell but also the programming of the first cell is performed. At this time, the sense amplifier module 12 applies a voltage V QPW to the bit line BL to which the first cell is connected (in the example of FIG. 19, BL1). The voltage V QPW is a voltage greater than the voltage applied to the bit line BL (BL2 to BL5 in the example of FIG. 19) to which the second cell is connected, for example, V QPW >0V. Further, V QPW is also a voltage that can be transmitted from the selection transistor ST1 to which the voltage VSG is applied in the gate.
因此,於施加有電壓VPGM2期間,第1及第2胞係在對各通道分別施加有VQPW及0V之狀態下編程。 Therefore, during the application of the voltage VPGM2, the first and second cell systems are programmed in a state where V QPW and 0 V are applied to the respective channels.
其後之處理係與在利用第2實施形態之圖13所進行之說明中將VPGM2a表述為VPGM2者相同。且,圖17之步驟S41~S47係與圖13之步驟S21~S27對應。 The subsequent processing is the same as that in the description of FIG. 13 of the second embodiment, in which VPGM2a is expressed as VPGM2. Further, steps S41 to S47 of Fig. 17 correspond to steps S21 to S27 of Fig. 13 .
根據本實施形態,與第2實施形態相同,削減程式迴路次數,並減少程式電壓之種類,從而可簡化構成。又,因可使程式電壓VPGM2之初始值對第2胞最佳化,故較第2實施形態,可使寫入高速化。利用圖20對本效果進行說明。圖20係表示編程時之第1胞及第2胞之閾值電壓之變化之圖表。 According to the present embodiment, as in the second embodiment, the number of program loops is reduced, and the type of the program voltage is reduced, so that the configuration can be simplified. Further, since the initial value of the program voltage VPGM2 can be optimized for the second cell, the writing speed can be increased as compared with the second embodiment. This effect will be described using FIG. Fig. 20 is a graph showing changes in threshold voltages of the first cell and the second cell at the time of programming.
如圖示,由於程式電壓VPGM2於第2胞之編程中最佳化,故第2胞之閾值以所需之步階(⊿Vth1)持續上昇。但,VPGM2對第1胞而言為過大之電壓。因此,若將VPGM2直接應用於第1胞,則其閾值以較所需之步階更大之步階(⊿Vth2)持續上昇。根據情形,存在導致在1次編程中閾值過度上升之虞。 As shown, since the program voltage VPGM2 is optimized in the programming of the second cell, the threshold of the second cell continues to rise in the desired step (⊿Vth1). However, VPGM2 is an excessive voltage for the first cell. Therefore, if VPGM2 is directly applied to the first cell, its threshold value continues to rise in a step (⊿Vth2) larger than the required step. Depending on the situation, there is a flaw that causes the threshold to rise excessively in one programming.
因此,在本實施形態中,對連接有第1胞之位元線BL施加電壓 VQPW。即,藉由施加電壓VQPW而縮小控制閘極與通道之間之電位差。藉此,控制第1胞之閾值變動幅度(縮小變動幅度),而使其以最佳之步階(⊿Vth3)上昇。 Therefore, in the present embodiment, the voltage V QPW is applied to the bit line BL to which the first cell is connected . That is, the potential difference between the control gate and the channel is reduced by applying the voltage V QPW . Thereby, the threshold variation range (reduction in the fluctuation range) of the first cell is controlled to increase in the optimum step (⊿Vth3).
即,可省略施加VPGM1,同時不僅對第2胞執行最佳之編程,亦對第1胞執行最佳之編程,而可實現對該等胞之高速寫入。 That is, application of VPGM1 can be omitted, and not only optimal programming is performed for the second cell, but also optimal programming is performed for the first cell, and high-speed writing of the cells can be realized.
接著,對第5實施形態之半導體記憶裝置進行說明。本實施形態係關於上述第1實施形態之行系周邊電路之構成及動作者。 Next, a semiconductor memory device according to a fifth embodiment will be described. This embodiment relates to the configuration and actor of the peripheral circuit of the line system according to the first embodiment.
圖21係本實施形態之感測放大器模組12、運算模組13、及資料閂鎖模組14之方塊圖。 FIG. 21 is a block diagram of the sense amplifier module 12, the arithmetic module 13, and the data latch module 14 of the embodiment.
如圖示,感測放大器模組12具備與各位元線BL相對應之閂鎖電路SDL。在圖中,“SDL”後所附記之“_B”、“_M”、及“_T”分別表示各閂鎖電路SDL對應於葉片型構造24之最下層之胞、中間層之胞、及最上層之胞。於各閂鎖電路SDL中,表示與哪個胞對應之信號SEL_BOT、SEL_MID、及SEL_TOP係由例如控制部15賦予。即,對閂鎖電路SDL_B賦予SEL_BOT=“H”,對閂鎖電路SDL_M賦予SEL_MID=“H”,對閂鎖電路SDL_T賦予SEL_TOP=“H”。又,同樣地,讀取時用以於每層控制位元線預充電電壓之信號CLAMP_BOT、CLAMP_MID、及CLAMP_TOP係賦予各閂鎖電路SDL。即,對閂鎖電路SDL_B賦予CLAMP_BOT=“H”,對閂鎖電路SDL_M賦予CLAMP_MID=“H”,對閂鎖電路SDL_T賦予CLAMP_TOP=“H”。 As shown, the sense amplifier module 12 includes a latch circuit SDL corresponding to each bit line BL. In the figure, "_B", "_M", and "_T" attached to "SDL" respectively indicate that each latch circuit SDL corresponds to the lowest cell of the blade type structure 24, the cell of the intermediate layer, and the uppermost layer. The cell. In each latch circuit SDL, signals SEL_BOT, SEL_MID, and SEL_TOP corresponding to which cell are indicated are provided by, for example, the control unit 15. That is, SEL_BOT=“H” is given to the latch circuit SDL_B, SEL_MID=“H” is given to the latch circuit SDL_M, and SEL_TOP=“H” is given to the latch circuit SDL_T. Further, similarly, signals CLAMP_BOT, CLAMP_MID, and CLAMP_TOP for controlling the bit line precharge voltage for each layer at the time of reading are applied to the respective latch circuits SDL. That is, CLAMP_BOT=“H” is given to the latch circuit SDL_B, CLAMP_MID=“H” is given to the latch circuit SDL_M, and CLAMP_TOP=“H” is given to the latch circuit SDL_T.
閂鎖電路SDL於資料之寫入時保持自運算模組13傳送之寫入資料。接著,閂鎖電路SDL根據寫入資料,將特定之電壓施加至對應之位元線BL。又,閂鎖電路SDL於資料之讀取時,將位元線BL預充電 為與信號CLAMP_BOT、CLAMP_MID、及CLAMP_TOP相應之電壓。即,閂鎖電路SDL於資料之讀取時,根據讀取對象胞位於哪層,控制施加至位元線BL之預充電電位。 The latch circuit SDL holds the write data transmitted from the computing module 13 when the data is written. Next, the latch circuit SDL applies a specific voltage to the corresponding bit line BL in accordance with the write data. Moreover, the latch circuit SDL precharges the bit line BL during reading of the data. It is a voltage corresponding to the signals CLAMP_BOT, CLAMP_MID, and CLAMP_TOP. That is, the latch circuit SDL controls the precharge potential applied to the bit line BL depending on which layer the read target cell is located at the time of reading the data.
運算模組13具備與各位元線BL相對應之運算電路40。運算電路40亦接收對應之信號SEL(SEL_TOP、SEL_MID、及SEL_BOT)之任一者。且,運算電路40各者於資料之寫入時,藉由使用自資料閂鎖模組14賦予之資料、與對應之信號SEL之運算,而產生寫入資料。接著,將所產生之寫入資料傳送至對應之閂鎖電路SDL。 The arithmetic module 13 includes an arithmetic circuit 40 corresponding to each bit line BL. The arithmetic circuit 40 also receives any of the corresponding signals SEL (SEL_TOP, SEL_MID, and SEL_BOT). Moreover, each of the arithmetic circuit 40 generates a write data by using the data given from the data latch module 14 and the corresponding signal SEL during the writing of the data. Next, the generated write data is transferred to the corresponding latch circuit SDL.
資料閂鎖模組14具備閂鎖電路DL0及DL1之組,該組係與各位元線BL相對應。在資料之寫入時,將例如自主機機器等外部裝置經由資料線DAT所賦予之2位元資料之各位元保持於閂鎖電路DL0及DL1。接著,將該等資料傳送至運算電路13。在讀取時,將自記憶體胞電晶體MT所讀取之2位元資料之各位元保持於閂鎖電路DL0及DL1。接著,閂鎖電路DL0及DL1經由資料線DAT將2位元資料之各位元輸出至外部裝置。 The data latch module 14 is provided with a group of latch circuits DL0 and DL1, and the group corresponds to each bit line BL. At the time of writing the data, the bits of the 2-bit data given from the external device such as the host device via the data line DAT are held in the latch circuits DL0 and DL1. Then, the data is transferred to the arithmetic circuit 13. At the time of reading, the bits of the 2-bit data read from the memory cell MT are held in the latch circuits DL0 and DL1. Next, the latch circuits DL0 and DL1 output the bits of the 2-bit data to the external device via the data line DAT.
接著,利用圖22及圖23,對資料寫入時之上述行系周邊電路之動作進行說明。圖22係表示寫入時之字元線電壓之變化之時序圖,圖23係表示編程時之字元線及位元線電壓之變化之時序圖。 Next, the operation of the above-described line peripheral circuit at the time of data writing will be described with reference to FIGS. 22 and 23. Fig. 22 is a timing chart showing changes in word line voltage at the time of writing, and Fig. 23 is a timing chart showing changes in word line and bit line voltage at the time of programming.
在寫入時,首先,將寫入資料傳送至閂鎖電路DL0及DL1。寫入資料與閂鎖電路DL0及DL1內之資料之關係係如下所述。 At the time of writing, first, the write data is transferred to the latch circuits DL0 and DL1. The relationship between the write data and the data in the latch circuits DL0 and DL1 is as follows.
資料:(DL0、DL1) Information: (DL0, DL1)
“Ep”位準(非寫入):(1、1) “Ep” level (non-write): (1, 1)
“A”位準:(1、0) "A" level: (1, 0)
“B”位準:(0、0) "B" level: (0, 0)
“C”位準:(0、1) “C” level: (0, 1)
又,於閂鎖電路SDL內之資料中存在以下關係。 Moreover, the following relationship exists in the material in the latch circuit SDL.
SDL=1:非寫入胞(BL=V1) SDL=1: Non-written cell (BL=V1)
SDL=0:寫入胞(BL=0V) SDL=0: Write cell (BL=0V)
以下,依序對寫入時之處理步驟進行說明。 Hereinafter, the processing steps at the time of writing will be described in order.
當對閂鎖電路DL0及DL1傳送資料時,運算電路40各者執行用於第1編程之資料組。第1編程係僅對第1胞進行之編程。運算電路40對資料組執行以下邏輯運算。即,/(DL0&/DL1&SEL_BOT)→SDL When data is transferred to the latch circuits DL0 and DL1, each of the arithmetic circuits 40 executes the data group for the first programming. The first programming system only programmed the first cell. The arithmetic circuit 40 performs the following logical operations on the data set. That is, /(DL0&/DL1&SEL_BOT)→SDL
在運算式中,“/”表示反轉,“&”表示邏輯積。根據該運算,僅對DL0=1、DL=0且與最下層之記憶體胞對應之閂鎖電路SDL設定“0”。對其他閂鎖電路SDL設定“1”。其結果,僅對連接有未通過驗證之第1胞之位元線BL施加0V,而對其他之連接有第2胞及第3胞、以及非寫入對象胞及寫入完成胞之位元線BL施加電壓V1。且,對選擇字元線WL施加電壓VPGM1,僅於第1胞中對“A”位準資料進行編程。 In the expression, "/" means reverse and "&" means logical product. According to this calculation, "0" is set only for the latch circuit SDL corresponding to DL0 = 1 and DL = 0 and corresponding to the memory cell of the lowermost layer. "1" is set to the other latch circuit SDL. As a result, only 0 V is applied to the bit line BL to which the unauthenticated first cell is connected, and the second cell and the third cell are connected to the other, and the bit of the non-writing target cell and the write completion cell are connected. Line BL applies a voltage V1. Moreover, the voltage VPGM1 is applied to the selected word line WL, and the "A" level data is programmed only in the first cell.
接著,運算電路40各者執行用於第2編程之資料組。第2編程係僅對第2胞進行之編程。運算電路40對資料組執行以下邏輯運算。即,(DL0&/DL1)|(DL0&/DL1&SEL_BOT)|(/DL0&/DL1&SEL_TOP)→SDL Next, each of the arithmetic circuits 40 executes the data set for the second programming. The second programming system only programs the second cell. The arithmetic circuit 40 performs the following logical operations on the data set. That is, (DL0&/DL1)|(DL0&/DL1&SEL_BOT)|(/DL0&/DL1&SEL_TOP)→SDL
在運算式中,“|”表示邏輯和。根據該運算,對與第1胞、第3胞、及非寫入對象胞對應之閂鎖電路SDL設定“1”。換言之,僅對與第2胞對應之閂鎖電路SDL設定“0”。其結果,僅對連接有未通過驗證之第2胞之位元線BL施加0V,而對其他位元線BL施加電壓V1。且,對選擇字元線WL施加電壓VPGM2,僅於第2胞中對資料進行編 程。 In the expression, "|" represents a logical sum. According to this calculation, "1" is set to the latch circuit SDL corresponding to the first cell, the third cell, and the non-writing target cell. In other words, "0" is set only for the latch circuit SDL corresponding to the second cell. As a result, only 0 V is applied to the bit line BL to which the second cell which has not been verified is connected, and the voltage V1 is applied to the other bit line BL. And, the voltage VPGM2 is applied to the selected word line WL, and the data is only edited in the second cell. Cheng.
接著,運算電路40各者執行用於第3編程之資料組。第3編程係僅對第3胞進行之編程。運算電路40對資料組執行以下邏輯運算。即,/(/DL0&/DL1&SEL_TOP)→SDL Next, each of the arithmetic circuits 40 executes the data set for the third programming. The third programming system only programs the third cell. The arithmetic circuit 40 performs the following logical operations on the data set. That is, /(/DL0&/DL1&SEL_TOP)→SDL
根據該運算,僅對DL0=0、DL=1且與最上層之記憶體胞對應之閂鎖電路SDL設定“0”。對其他閂鎖電路SDL設定“1”。其結果,僅對連接有未通過驗證之第3胞之位元線BL施加0V,而對其他之連接有第1胞及第2胞、以及非寫入對象胞及寫入完成胞之位元線BL施加電壓V1。且,對選擇字元線WL施加電壓VPGM3,而僅於第3胞中對“C”位準資料進行編程。 According to this calculation, "0" is set only for the latch circuit SDL corresponding to DL0 = 0 and DL = 1 and corresponding to the uppermost memory cell. "1" is set to the other latch circuit SDL. As a result, only 0 V is applied to the bit line BL to which the third cell which has not been verified is connected, and the first cell and the second cell are connected to the other, and the bit of the non-writing target cell and the write completion cell are connected. Line BL applies a voltage V1. Moreover, the voltage VPGM3 is applied to the selected word line WL, and the "C" level data is programmed only in the third cell.
接著,對“A”位準執行驗證動作。即,在對選擇字元線WL施加有驗證電壓Vfy_A之狀態下,自記憶體胞電晶體MT讀取資料。且,若記憶體胞電晶體MT斷開,即閾值達到“A”位準,則於閂鎖電路SDL中儲存“1”。另一方面,若記憶體胞電晶體MT導通,即閾值未達到“A”位準,則於閂鎖電路SDL中儲存“0”。 Next, the verification action is performed on the "A" level. That is, in a state where the verification voltage Vfy_A is applied to the selected word line WL, data is read from the memory cell transistor MT. Further, if the memory cell transistor MT is turned off, that is, the threshold reaches the "A" level, "1" is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, the threshold value does not reach the "A" level, "0" is stored in the latch circuit SDL.
接著,運算電路40執行以下邏輯運算。即,(SDL&DL0&/DL1)| DL1→DL1 Next, the arithmetic circuit 40 performs the following logical operation. That is, (SDL&DL0&/DL1)| DL1→DL1
在上式中,(DL0&/DL1)僅於寫入“A”位準之位元線BL中為“1”。因此,(SDL&DL0&/DL1)係僅對寫入資料為“A”位準,且已通過驗證之位元線BL為“1”。其後,進行該運算結果與原本之DL1之邏輯和運算,並將其重設為DL1。其結果,閂鎖電路DL0及DL1之資料成為如下狀態。 In the above formula, (DL0/DL1) is "1" only in the bit line BL to which the "A" level is written. Therefore, (SDL&DL0&/DL1) is only "A" level for the written data, and the verified bit line BL is "1". Thereafter, the logical sum of the operation result and the original DL1 is performed, and is reset to DL1. As a result, the data of the latch circuits DL0 and DL1 are as follows.
“Ep”位準(非寫入):(1、1) “Ep” level (non-write): (1, 1)
“A”位準:(1、0/1) "A" level: (1, 0/1)
“B”位準:(0、0) "B" level: (0, 0)
“C”位準:(0、1) “C” level: (0, 1)
即,藉由最後之邏輯和運算,將不與“A”位準對應之閂鎖電路DL0及DL1之資料設定為初始值。 That is, the data of the latch circuits DL0 and DL1 not corresponding to the "A" level are set as initial values by the last logical sum operation.
接著,運算電路40執行下述(1)式之邏輯運算。即,(DL0&/DL1&SEL_BOT) (1) Next, the arithmetic circuit 40 performs a logical operation of the following formula (1). That is, (DL0&/DL1 & SEL_BOT) (1)
藉此,可獲得與“A”位準對應,且位於最下層之記憶體胞電晶體MT之驗證結果。即,若該運算結果為“0”,則可知與該行對應之第1胞已通過驗證。另一方面,僅與第1胞對應,並與未通過驗證之行對應之運算結果為“1”。 Thereby, the verification result of the memory cell MT in the lowermost layer corresponding to the "A" level can be obtained. That is, if the calculation result is "0", it is understood that the first cell corresponding to the row has passed the verification. On the other hand, the calculation result corresponding to only the first cell and corresponding to the row that has not passed the verification is "1".
因此,例如控制部15計算運算結果為“1”之位元數,若該數為某基準值以下(例如由ECC電路之可訂正錯誤之位元數決定),則判斷為第1胞已通過驗證。該情形時,控制部15發行信號COMP_A_BOT(COMP_A_BOT=“H”),自下一個程式迴路開始不施加電壓VPGM1。 Therefore, for example, the control unit 15 calculates the number of bits in which the calculation result is "1", and if the number is equal to or less than a certain reference value (for example, determined by the number of bits of the correctable error of the ECC circuit), it is determined that the first cell has passed. verification. In this case, the control unit 15 issues the signal COMP_A_BOT (COMP_A_BOT = "H"), and does not apply the voltage VPGM1 from the next program loop.
接著,運算電路40執行下述(2)式之邏輯運算。即,(DL0&/DL1&(SEL_MID|SEL_TOP)) (2) Next, the arithmetic circuit 40 performs a logical operation of the following formula (2). That is, (DL0&/DL1&(SEL_MID|SEL_TOP)) (2)
藉此,可獲得與“A”位準對應,且位於最下層以外之層之記憶體胞電晶體MT之驗證結果。即,若該運算結果為“0”,則可知與該行對應之記憶體胞電晶體已通過驗證。另一方面,僅與“A”位準對應,且與位於最下層以外之層之記憶體胞電晶體MT中未通過驗證者對應之運算結果為“1”。 Thereby, the verification result of the memory cell transistor MT corresponding to the "A" level and located in the layer other than the lowermost layer can be obtained. That is, if the calculation result is "0", it is understood that the memory cell corresponding to the row has been verified. On the other hand, the calculation result corresponding to only the "A" level and corresponding to the verifier in the memory cell MT of the layer located outside the lowermost layer is "1".
因此,例如控制部15計算運算結果為“1”之位元數,若該數為某基準值以下,則判斷為位於最下層以外之層,且應寫入“A”位準之記憶體胞電晶體MT已通過驗證。 Therefore, for example, the control unit 15 calculates the number of bits in which the calculation result is "1", and if the number is below a certain reference value, it is determined that the layer is located outside the lowermost layer, and the memory cell of the "A" level should be written. The transistor MT has been verified.
若基於上述(1)式及(2)式之驗證結果均為通過,則對應寫入“A”位準之所有記憶體胞電晶體MT之編程已完成。因此,控制部15發行信號COMP_A_MIDTOP(COMP_A_MIDTOP=“H”)。且,當控制部15發行信號COMP_A_BOT及COMP_A_MIDTOP兩者時,自下一個程式迴路開始不進行“A”位準之驗證動作。 If the verification results based on the above equations (1) and (2) are all passed, the programming of all the memory cell MTs corresponding to the "A" level is completed. Therefore, the control unit 15 issues the signal COMP_A_MIDTOP (COMP_A_MIDTOP = "H"). Further, when the control unit 15 issues both the signals COMP_A_BOT and COMP_A_MIDTOP, the "A" level verification operation is not performed from the next program loop.
接著,執行對“B”位準之驗證動作。即,在對選擇字元線WL施加有驗證電壓Vfy_B之狀態下,自記憶體胞電晶體MT讀取資料。且,若記憶體胞電晶體MT斷開,即閾值達到“B”位準,則於閂鎖電路SDL中儲存“1”。另一方面,若記憶體胞電晶體MT導通,即閾值未達到“B”位準,則於閂鎖電路SDL中儲存“0”。 Next, the verification action for the "B" level is performed. That is, in a state where the verification voltage Vfy_B is applied to the selected word line WL, data is read from the memory cell transistor MT. Further, if the memory cell transistor MT is turned off, that is, the threshold reaches the "B" level, "1" is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, the threshold value does not reach the "B" level, "0" is stored in the latch circuit SDL.
且,運算電路40同時執行以下邏輯運算。即,(SDL&/DL0&/DL1)| DL0→DL0 Moreover, the arithmetic circuit 40 simultaneously performs the following logical operations. That is, (SDL&/DL0&/DL1)| DL0→DL0
(SDL&/DL0&/DL1)| DL1→DL1 (SDL&/DL0&/DL1)| DL1→DL1
在上式中,(/DL0&/DL1)僅於寫入“B”位準之位元線BL中為“1”。因此,(SDL&/DL0&/DL1)僅對寫入資料為“B”位準,且已通過驗證之位元線BL為“1”。其後,進行該等運算結果與原本之DL0及DL1之邏輯和運算,且將其重設為DL0及DL1。其結果,閂鎖電路DL0及DL1之資料成為如下狀態。 In the above formula, (/DL0&/DL1) is "1" only in the bit line BL to which the "B" level is written. Therefore, (SDL&/DL0&/DL1) is only "B" level for the written data, and the verified bit line BL is "1". Thereafter, the logical operation of the results of the operations with the original DL0 and DL1 is performed, and the DL0 and DL1 are reset. As a result, the data of the latch circuits DL0 and DL1 are as follows.
“Ep”位準(非寫入):(1、1) “Ep” level (non-write): (1, 1)
“A”位準:(1、0/1) "A" level: (1, 0/1)
“B”位準:(0、0/1) "B" level: (0, 0/1)
“C”位準:(0、1) “C” level: (0, 1)
另,與“A”位準對應之閂鎖電路DL0之值在上述步驟(4)中重設為“0”或“1”。 Further, the value of the latch circuit DL0 corresponding to the "A" level is reset to "0" or "1" in the above step (4).
接著,運算電路40執行下述(3)式之邏輯運算。即, (/DL0&/DL1) (3) Next, the arithmetic circuit 40 performs a logical operation of the following formula (3). which is, (/DL0&/DL1) (3)
若該運算結果為“0”,則可知應寫入“B”位準之記憶體胞電晶體MT通過驗證,若為“1”,則未通過驗證。 If the result of the operation is "0", it is understood that the memory cell transistor MT to which the "B" level is to be written is verified, and if it is "1", the verification is not passed.
因此,例如控制部15計算運算結果為“1”之位元數,若該數為某基準值以下,則判斷為“B"位準編程已通過驗證。該情形時,控制電路發行信號COMP_B(COMP_B=“H”),並自下一個程式迴路開始不進行“B”位準之驗證動作。 Therefore, for example, the control unit 15 calculates the number of bits in which the calculation result is "1", and if the number is equal to or less than a certain reference value, it is determined that the "B" level programming has passed the verification. In this case, the control circuit issues the signal COMP_B (COMP_B = "H"), and does not perform the "B" level verification operation from the next program loop.
接著,執行對“C”位準之驗證動作。即,在對選擇字元線WL施加有驗證電壓Vfy_C之狀態下,自記憶體胞電晶體MT讀取資料。且,若記憶體胞電晶體MT斷開,即閾值達到“C”位準,則於閂鎖電路SDL中儲存“1”。另一方面,若記憶體胞電晶體MT導通,即閾值未達到“C”位準,則於閂鎖電路SDL中儲存“0”。步驟6之動作係基本上只是讀取對象資料不同,而與步驟4相同。 Next, the verification action for the "C" level is performed. That is, in a state where the verification voltage Vfy_C is applied to the selected word line WL, data is read from the memory cell transistor MT. Further, if the memory cell transistor MT is turned off, that is, the threshold reaches the "C" level, "1" is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, the threshold value does not reach the "C" level, "0" is stored in the latch circuit SDL. The action of step 6 is basically only the reading of the object data is different, and is the same as step 4.
首先,運算電路40執行以下邏輯運算。即,(SDL&/DL0&/DL1)| DL0→DL0 First, the arithmetic circuit 40 performs the following logical operations. That is, (SDL&/DL0&/DL1)| DL0→DL0
在上式中,(/DL0&DL1)僅於寫入“C”位準之位元線BL中為“1”。因此,(SDL&/DL0&DL1)僅對寫入資料為“C”位準且已通過驗證之位元線BL為“1”。其後,進行該運算結果與原本之DL0及DL1之邏輯和運算,且將其重設為DL0。其結果,閂鎖電路DL0及DL1之資料成為如下狀態。 In the above formula, (/DL0&DL1) is "1" only in the bit line BL to which the "C" level is written. Therefore, (SDL&/DL0&DL1) is only "1" for the bit line BL whose write data is "C" level and which has been verified. Thereafter, the logical sum of the operation result and the original DL0 and DL1 is performed, and is reset to DL0. As a result, the data of the latch circuits DL0 and DL1 are as follows.
“Ep”位準(非寫入):(1、1) “Ep” level (non-write): (1, 1)
“A”位準:(1、0/1) "A" level: (1, 0/1)
“B”位準:(0/1、0/1) "B" level: (0/1, 0/1)
“C”位準:(0/1、1)。 "C" level: (0/1, 1).
接著,運算電路40執行下述(4)式之邏輯運算。即, (/DL0&DL1&SEL_TOP) (4) Next, the arithmetic circuit 40 performs a logical operation of the following formula (4). which is, (/DL0&DL1&SEL_TOP) (4)
藉此,可獲得與“C”位準對應、且位於最上層之記憶體胞電晶體MT(第3胞)之驗證結果。即,若該運算結果為“0”,則可知與該行對應之第3胞已通過驗證。另一方面,僅與第3胞對應,並與未通過驗證之行對應之運算結果為“1”。 Thereby, the verification result of the memory cell transistor MT (the third cell) corresponding to the "C" level and located in the uppermost layer can be obtained. That is, if the calculation result is "0", it is understood that the third cell corresponding to the row has passed the verification. On the other hand, the calculation result corresponding to only the third cell and corresponding to the row that failed the verification is "1".
因此,例如控制部15計算運算結果為“1”之位元數,若該數為某基準值以下,則判斷為第3胞已通過驗證。該情形時,控制電路發行信號COMP_C_TOP(COMP_C_TOP=“H”),自下一個程式迴路開始不施加電壓VPGM3。 Therefore, for example, the control unit 15 calculates the number of bits in which the calculation result is "1", and if the number is equal to or less than a certain reference value, it is determined that the third cell has passed the verification. In this case, the control circuit issues the signal COMP_C_TOP (COMP_C_TOP = "H"), and no voltage VPGM3 is applied from the next program loop.
接著,運算電路40執行下述(5)式之邏輯運算。即,(/DL0&/DL1&(SEL_MID|SEL_BOT)) (5) Next, the arithmetic circuit 40 performs a logical operation of the following formula (5). That is, (/DL0&/DL1&(SEL_MID|SEL_BOT)) (5)
藉此,可獲得與“C”位準對應,且位於最上層以外之層之記憶體胞電晶體MT之驗證結果。即,若該運算結果為“0”,則可知與該行對應之記憶體胞電晶體已通過驗證。另一方面,僅與“C”位準對應,且與位於最上層以外之層之記憶體胞電晶體MT中未通過驗證者對應之運算結果為“1”。 Thereby, the verification result of the memory cell transistor MT corresponding to the "C" level and located in the layer other than the uppermost layer can be obtained. That is, if the calculation result is "0", it is understood that the memory cell corresponding to the row has been verified. On the other hand, the calculation result corresponding to only the "C" level and corresponding to the verifier in the memory cell MT of the layer located outside the uppermost layer is "1".
因此,例如控制部15計算運算結果為“1”之位元數,若該數為某基準值以下,則判斷為位於最上層以外之層之記憶體胞電晶體MT已通過驗證。 Therefore, for example, the control unit 15 calculates the number of bits in which the calculation result is "1", and if the number is equal to or less than a certain reference value, it is determined that the memory cell transistor MT located in the layer other than the uppermost layer has passed the verification.
若基於上述(4)式及(5)式之驗證結果均為通過,則對應寫入“C”位準之所有記憶體胞電晶體MT之編程已完成。因此,控制部15發行信號COMP_C_MIDBOT(COMP_C_MIDBOT=“H”)。且,當控制部15發行信號COMP_C_TOP及COMP_C_MIDBOT兩者時,自下一個程式迴路開始不進行“C”位準之驗證動作。 If the verification results based on the above equations (4) and (5) are all passed, the programming of all the memory cell MTs corresponding to the "C" level is completed. Therefore, the control unit 15 issues the signal COMP_C_MIDBOT (COMP_C_MIDBOT = "H"). Further, when the control unit 15 issues both the signals COMP_C_TOP and COMP_C_MIDBOT, the "C" level verification operation is not performed from the next program loop.
控制部15反復進行以上動作,當5個控制信號COMP_A_BOT、 COMP_A_MIDTOP、COMP_B、COMP_C_TOP、及COMP_C_MIDTOP皆成為“H”位準時,編程已正常完成(編程通過),而完成寫入動作。當任一個控制信號仍為“L”位準而程式迴路數達到最大值時,控制部15將其視為無法正常完成編程(編程失敗),而完成寫入動作。 The control unit 15 repeats the above operations, and when the five control signals COMP_A_BOT, When COMP_A_MIDTOP, COMP_B, COMP_C_TOP, and COMP_C_MIDTOP are all "H" bits, programming is completed normally (programming is passed), and the write operation is completed. When any one of the control signals is still at the "L" level and the number of program loops reaches the maximum value, the control portion 15 regards it as being unable to complete the programming normally (programming failure), and completes the writing operation.
上述第1實施形態所說明之寫入方法可藉由例如本實施形態之構成實現。另,第2至第4實施形態亦相同,藉由使用控制信號SEL_BOT、SEL_MID、SEL_TOP、DL0及DL1之運算,可適當控制位元線BL之電位。 The writing method described in the first embodiment can be realized by, for example, the configuration of the embodiment. Similarly, in the second to fourth embodiments, the potential of the bit line BL can be appropriately controlled by the operations of the control signals SEL_BOT, SEL_MID, SEL_TOP, DL0, and DL1.
接著,對第6實施形態之半導體記憶裝置進行說明。本實施形態係關於具備上述第1至第5實施形態之任一者之半導體記憶裝置1之記憶體系統者。 Next, a semiconductor memory device according to a sixth embodiment will be described. The present embodiment relates to a memory system including the semiconductor memory device 1 of any of the first to fifth embodiments.
圖24係本實施形態之記憶體系統之方塊圖。如圖示,記憶體系統具備第1至第5實施形態所說明之半導體記憶裝置1、及控制半導體記憶裝置1之控制器2。 Figure 24 is a block diagram of the memory system of the embodiment. As shown in the figure, the memory system includes the semiconductor memory device 1 described in the first to fifth embodiments, and the controller 2 that controls the semiconductor memory device 1.
控制器2響應來自未圖示之主機機器之命令,而對NAND型快閃記憶體1命令讀取、寫入及抹除等。再者,管理NAND型快閃記憶體1之記憶空間。控制器2與NAND型快閃記憶體1亦可構成例如同一半導體裝置。又,記憶體系統1亦可為1個裝置,作為其例,可舉出如SDTM卡之記憶卡、或SSD(solid state drive:固態驅動機)等。又,記憶體系統1亦可為將NAND型快閃記憶體1及控制器2內置於個人電腦之構成,只要為搭載有NAND型快閃記憶體1之應用程式,則並非限定者。 The controller 2 commands reading, writing, erasing, and the like to the NAND-type flash memory 1 in response to a command from a host device not shown. Furthermore, the memory space of the NAND type flash memory 1 is managed. The controller 2 and the NAND type flash memory 1 may also constitute, for example, the same semiconductor device. Further, the memory system 1 may also be a device, and examples thereof may include memory cards such as SD TM card, or a SSD (solid state drive: a solid driver) and the like. Further, the memory system 1 may be configured to include the NAND flash memory 1 and the controller 2 in a personal computer, and is not limited to an application in which the NAND flash memory 1 is mounted.
控制器2具備主機介面電路210、內置記憶體(RAM)220、處理器(CPU)230、緩衝記憶體240、NAND介面電路250、及ECC電路260。 The controller 2 includes a host interface circuit 210, a built-in memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, a NAND interface circuit 250, and an ECC circuit 260.
主機介面電路210經由控制器匯流排與主機機器連接,且負責與主機機器之通訊。且,將自主機機器所接收到之命令及資料分別傳送至CPU230及緩衝記憶體240。又,響應CPU230之命令,而將緩衝記憶體240內之資料傳送至主機機器。 The host interface circuit 210 is connected to the host machine via the controller bus and is responsible for communication with the host machine. The commands and data received from the host device are transmitted to the CPU 230 and the buffer memory 240, respectively. Further, in response to a command from the CPU 230, the data in the buffer memory 240 is transferred to the host machine.
NAND介面電路250經由NAND匯流排與NAND型快閃記憶體1連接,且負責與NAND型快閃記憶體1之通訊。且,將自CPU230所接收到之命令傳送至NAND型快閃記憶體1,又在寫入時將緩衝記憶體240內之寫入資料傳送至NAND型快閃記憶體1。再者於讀取時,將自NAND型快閃記憶體1所讀取之資料傳送至緩衝記憶體240。 The NAND interface circuit 250 is connected to the NAND type flash memory 1 via the NAND bus, and is responsible for communication with the NAND type flash memory 1. Further, the command received from the CPU 230 is transferred to the NAND-type flash memory 1, and the write data in the buffer memory 240 is transferred to the NAND-type flash memory 1 at the time of writing. Further, at the time of reading, the data read from the NAND type flash memory 1 is transferred to the buffer memory 240.
CPU230控制控制器2整體之動作。例如,自主機機器接收到寫入讀取命令時,響應其而發行基於NAND介面之寫入命令。讀取及抹除時亦相同。又,CPU230執行平均抹寫等用以管理NAND型快閃記憶體1之各種處理。再者,CPU230執行各種運算。例如,執行資料之加密處理或隨機化處理等。ECC電路260執行資料之錯誤訂正(ECC:Error Checking and Correcting)處理。即,ECC電路260於資料之寫入時,基於寫入資料產生同位,於讀取時自同位產生校驗位而檢測出錯誤,並訂正該錯誤。另,CPU230亦可具有ECC電路260之功能。 The CPU 230 controls the overall operation of the controller 2. For example, when a write read command is received from the host machine, a write command based on the NAND interface is issued in response thereto. The same is true for reading and erasing. Further, the CPU 230 performs an average strobe or the like for managing various processes of the NAND-type flash memory 1. Furthermore, the CPU 230 performs various operations. For example, performing encryption processing or randomization processing of data, and the like. The ECC circuit 260 performs an ECC (Error Checking and Correcting) process. That is, the ECC circuit 260 generates a parity based on the written data when the data is written, generates a parity bit from the same bit at the time of reading, detects an error, and corrects the error. In addition, the CPU 230 may also have the function of the ECC circuit 260.
內置記憶體220為例如DRAM等半導體記憶體,且使用作為CPU230之作業區域。且,內置記憶體220保持用以管理NAND型快閃記憶體1之韌體、或各種管理表格等。 The internal memory 220 is a semiconductor memory such as a DRAM, and is used as a work area of the CPU 230. Further, the built-in memory 220 holds a firmware for managing the NAND flash memory 1, or various management tables and the like.
接著,對本實施形態之控制器2之動作,尤其是對寫入動作進行說明。控制器2對NAND型快閃記憶體1,可以第1模式及第2模式兩種模式之兩種寫入模式寫入資料。 Next, the operation of the controller 2 of the present embodiment, in particular, the writing operation will be described. The controller 2 writes data to the NAND type flash memory 1 in two write modes of the first mode and the second mode.
圖25係以第1模式寫入資料時之在NAND型快閃記憶體1與控制器2之間傳送接收之信號之時序圖。控制器2對NAND型快閃記憶體1發送晶片啟用信號/CE、位址閂鎖啟用信號ALE、指令閂鎖啟用信號CLE、寫入啟用信號/WE、讀取啟用信號/RE。又,NAND型快閃記憶體1對控制器2發送就緒/忙碌信號/R/B。輸入輸出信號I/O1~I/O8係於控制器2與NAND型快閃記憶體之間傳送接收之例如8位元之資料。 Fig. 25 is a timing chart showing signals transmitted and received between the NAND flash memory 1 and the controller 2 when data is written in the first mode. The controller 2 transmits a wafer enable signal /CE, an address latch enable signal ALE, an instruction latch enable signal CLE, a write enable signal /WE, and a read enable signal /RE to the NAND type flash memory 1. Further, the NAND type flash memory 1 transmits a ready/busy signal /R/B to the controller 2. The input/output signals I/O1 to I/O8 are data such as 8-bits transmitted and received between the controller 2 and the NAND-type flash memory.
晶片啟用信號/CE係用於啟用NAND型快閃記憶體1之信號,且固定在低位準。位址閂鎖啟用信號ALE係表示輸入輸出信號I/O1~I/O8為位址之信號,且固定在高位準。指令閂鎖啟用信號CLE係表示輸入輸出信號I/O1~I/O8為指令之信號,且固定在高位準。寫入啟用信號/WE為用於對NAND型快閃記憶體1寫入各資料之信號,且固定在低位準。讀取啟用信號/RE為用於自NAND型快閃記憶體1讀取各資料之信號,且固定在低位準。就緒/忙碌信號/R/B係表示NAND型快閃記憶體1是否為忙碌狀態(是否為可接收信號之狀態)之信號,於忙碌狀態時成為低位準。 The wafer enable signal / CE is used to enable the signal of the NAND type flash memory 1 and is fixed at a low level. The address latch enable signal ALE is a signal indicating that the input/output signals I/O1~I/O8 are address addresses, and is fixed at a high level. The command latch enable signal CLE indicates that the input and output signals I/O1~I/O8 are signals of the command and are fixed at a high level. The write enable signal /WE is a signal for writing each material to the NAND type flash memory 1, and is fixed at a low level. The read enable signal /RE is a signal for reading each material from the NAND type flash memory 1, and is fixed at a low level. The ready/busy signal/R/B indicates whether or not the NAND-type flash memory 1 is in a busy state (whether or not it is in a state in which a signal can be received), and becomes a low level in a busy state.
如圖示,控制器1於以第1模式寫入資料時,發行第1寫入指令80H,並將其寫入於NAND型快閃記憶體1之未圖示之指令暫存器。指令80H為用於通知此後開始執行寫入動作之指令。其後,將行位址(指定位元線之位址)及列位址(指定字元線(頁面)之位址)寫入於位址暫存器。其後,傳送應進行編程之資料D0~D527。最後,控制器2將指令10H寫入於指令暫存器。NAND型快閃記憶體1之控制部15響應該指令,而利用第1至第5實施形態所說明之方法寫入資料。 As shown in the figure, when the controller 1 writes data in the first mode, the first write command 80H is issued and written in the instruction register (not shown) of the NAND flash memory 1. The instruction 80H is an instruction for notifying that the writing operation is started thereafter. Thereafter, the row address (the address of the specified bit line) and the column address (the address of the specified word line (page)) are written to the address register. Thereafter, the data D0~D527 to be programmed are transmitted. Finally, controller 2 writes instruction 10H to the instruction register. In response to the command, the control unit 15 of the NAND flash memory 1 writes data by the methods described in the first to fifth embodiments.
圖26係以第2模式寫入資料時之在NAND型快閃記憶體1與控制器2之間傳送接收之信號之時序圖。與第1模式不同之點為:在第1寫入指令80H之前,控制器2發行前置指令,並將其寫入於指令暫存器。藉由接收前置指令,NAND型快閃記憶體以第2模式寫入資料。第2模 式下之資料之寫入係藉由第1實施形態所說明之圖12之方法執行。 Fig. 26 is a timing chart for transmitting and receiving signals between the NAND flash memory 1 and the controller 2 when data is written in the second mode. The difference from the first mode is that the controller 2 issues a pre-command and writes it to the instruction register before the first write command 80H. By receiving the pre-instruction command, the NAND-type flash memory writes data in the second mode. Second mode The writing of the data under the equation is performed by the method of Fig. 12 described in the first embodiment.
在第2模式中,程式電壓VPGM不根據第1~第3胞分類,而對頁面內應寫入至“A”~“C”位準之所有記憶體胞執行編程。即,VPGM係如圖12所示,僅單純升壓。在圖12之情形時,雖以在1次程式迴路中施加1次VPGM之情形為例進行顯示,但亦可連續施加2次以上。然而,該被施加2次以上之VPGM並非與記憶體胞之位置(位址)或寫入資料相應者,而係使用在於所有寫入對象胞中對資料進行編程。即,當為第2模式時,1次程式迴路之VPGM之施加次數係與驗證電壓之施加次數相同,或少於其。 In the second mode, the program voltage VPGM is not programmed according to the first to third cell classifications, and all memory cells that should be written to the "A" to "C" levels in the page are programmed. That is, as shown in FIG. 12, the VPGM is simply boosted. In the case of FIG. 12, the case where the VPGM is applied once in the primary circuit is taken as an example, but it may be continuously applied twice or more. However, the VPGM applied twice or more does not correspond to the position (address) or data of the memory cell, but is used to program the data in all the cells to be written. That is, in the second mode, the number of times the VPGM of the primary circuit is applied is the same as or less than the number of times the verification voltage is applied.
即,如第1實施形態所說明般,在停止施加某程式電壓之時,同時亦停止施加與其對應之驗證電壓。 That is, as described in the first embodiment, when a certain program voltage is stopped, the verification voltage corresponding thereto is also stopped.
當為本實施形態之構成時,使用者可根據需要而改變寫入速度及消耗電力。 In the configuration of the present embodiment, the user can change the writing speed and power consumption as needed.
即,當為第1模式時,NAND型快閃記憶體1內之升壓電路於產生高電壓VPGM3後產生低電壓VPGM1。因此,在驗證動作中必須使升壓電路放電,且於放電後必須再次自較低之電壓VPGM1進行升壓動作。即,因在升壓電路中反復地進行充放電,故而消耗電流增加。相反,可如第1至第5實施形態所說明般,實現高速之寫入動作。 That is, in the first mode, the booster circuit in the NAND flash memory 1 generates the low voltage VPGM1 after the high voltage VPGM3 is generated. Therefore, the booster circuit must be discharged during the verify operation, and the boosting operation must be performed again from the lower voltage VPGM1 after the discharge. In other words, since the charge and discharge are repeatedly performed in the booster circuit, the current consumption increases. On the contrary, as described in the first to fifth embodiments, the high speed writing operation can be realized.
另一方面,當為第2模式時,升壓電壓單純將VPGM升壓即可,無需進行升壓電壓之放電,在驗證動作中,使電壓配線浮動即可。因此,雖相較於第1模式,寫入速度較差,但可減少消耗電流。 On the other hand, in the second mode, the boosted voltage simply boosts the VPGM, and it is not necessary to discharge the boosted voltage, and the voltage wiring may be floated during the verify operation. Therefore, although the writing speed is inferior compared to the first mode, the current consumption can be reduced.
且,在本實施形態中,可根據來自控制器2之指令,而切換第1模式與第2模式。例如,對出貨為記憶體胞保持2位元以上之資料之(MLC:multi-level cell;多位階胞)製品之NAND型快閃記憶體1,欲使SLC(single-level cell:記憶體胞保持1位元資料)作為暫時緩衝器動 作,或為高可靠性地寫入重要資料而欲使SLC動作之情形等時,較佳為採用第2模式。 Further, in the present embodiment, the first mode and the second mode can be switched in accordance with an instruction from the controller 2. For example, for a NAND-type flash memory 1 that is shipped as a (MLC: multi-level cell) product that retains more than two bits of memory cells, SLC (single-level cell) is required. Cell retains 1 bit data) as a temporary buffer In the case of writing an important material with high reliability and operating the SLC or the like, it is preferable to adopt the second mode.
如此,當為本實施形態時,可切換雖可高速動作但消耗電力相對較高之模式、與雖低速動作但消耗電力低之模式,而使用NAND型快閃記憶體1。 As described above, in the present embodiment, the NAND flash memory 1 can be switched by switching between a mode in which the power consumption is relatively high and a mode in which the power consumption is relatively high and a mode in which the power consumption is low in the low speed operation.
如上所述,實施形態之半導體記憶裝置1具備複數個記憶體胞MT、字元線WL、位元線BL、及列解碼器11。記憶體胞積層於半導體基板上。字元線WL連接於記憶體胞之閘極。位元線BL電性連接於記憶體胞之電流路徑,且可傳送資料。列解碼器11對字元線施加電壓。對記憶體胞MT之資料之寫入係藉由重複複數次包含程式動作與驗證動作之程式迴路而執行(圖11)。在1次程式迴路中,上述列解碼器對選擇字元線依序施加M次(M為1以上之自然數)程式電壓(圖11之t5~t6、及t7~t8),接著,對上述選擇字元線依序施加N次(N大於M,為2以上之自然數)之驗證電壓(圖11之t6~t7、及t7以後)。 As described above, the semiconductor memory device 1 of the embodiment includes a plurality of memory cells MT, word lines WL, bit lines BL, and column decoders 11. The memory cell layer is deposited on the semiconductor substrate. The word line WL is connected to the gate of the memory cell. The bit line BL is electrically connected to the current path of the memory cell, and can transmit data. Column decoder 11 applies a voltage to the word line. The writing of the data of the memory cell MT is performed by repeating the program loop including the program action and the verify action a plurality of times (Fig. 11). In the one-program loop, the column decoder sequentially applies M times (M is a natural number of 1 or more) to the selected word line (t5~t6, and t7~t8 in FIG. 11), and then Select the word line to apply the verification voltage N times (N is greater than M, which is a natural number of 2 or more) (t6~t7 in Fig. 11 and after t7).
換言之,對記憶體胞之資料之寫入係藉由重複複數次包含對選擇字元線施加程式電壓之程式動作、與施加驗證電壓之驗證動作之程式迴路而執行。列解碼器11在連續之2次程式迴路(圖11之t3~t5與t5~t6)期間,一面使驗證電壓之施加次數不變,一面使第2次程式迴路(圖11之t5~t6)之程式電壓之施加次數(3次:VPGM1-VPGM3)較第1次程式迴路(圖11之t3~t5)減少(2次:VPGM2、VPGM3)。 In other words, the writing of the data of the memory cell is performed by repeating the program circuit including the program operation for applying the program voltage to the selected word line and the verification circuit for applying the verification voltage. The column decoder 11 causes the second program loop (t5 to t6 in Fig. 11) while the number of times the verification voltage is applied is constant during the two consecutive program loops (t3 to t5 and t5 to t6 in Fig. 11). The number of times the program voltage is applied (3 times: VPGM1-VPGM3) is reduced from the first program loop (t3 to t5 in Fig. 11) (2 times: VPGM2, VPGM3).
根據本構成,可減少程式迴路次數,從而提高資料之寫入速度。然而,實施形態並非限定於上述所說明之形態,而可進行各種變化。例如,在上述實施形態中,雖以VPGM1及VPGM3之施加較VPGM2之施加先行結束之情形為例進行說明,但,亦可為VPGM2之施加較VPGM1及/或VPGM3之施加先行結束之情形。 According to this configuration, the number of program loops can be reduced, thereby increasing the writing speed of the data. However, the embodiment is not limited to the above-described embodiment, and various changes can be made. For example, in the above-described embodiment, the case where the application of VPGM1 and VPGM3 is terminated earlier than the application of VPGM2 is described as an example. However, the application of VPGM2 may be preceded by the application of VPGM1 and/or VPGM3.
又,在上述實施形態中,將第1胞定義為位於最下層之層且編程為“A”位準之胞。但,第1胞亦可為位於第1層之層至第N層(N為2以上之自然數)之胞。又,於記憶體胞可保持4位元以上之資料(“EP”、“A”、“B”、“C”、“D”、…“O”位準之16值)之情形時,第1胞亦可為於“A”位準至例如“C”位準之範圍內編程之胞。關於第3胞亦相同。即,第3胞可為位於第N+M層(M為4以上之自然數)之層至第L層(L為6以上之自然數)之胞,又,亦可為例如於“L”位準至“O”位準之範圍內編程之胞。 Further, in the above embodiment, the first cell is defined as a cell located at the lowermost layer and programmed to the "A" level. However, the first cell may be a cell located in the first layer to the Nth layer (N is a natural number of 2 or more). In addition, when the memory cell can maintain more than 4 bits of data ("EP", "A", "B", "C", "D", ... "O" level of 16 values), The 1 cell can also be a cell programmed within the range of "A" to, for example, the "C" level. The same is true for the third cell. In other words, the third cell may be a cell located in the N+M layer (M is a natural number of 4 or more) to the Lth layer (L is a natural number of 6 or more), and may be, for example, "L". The cell is programmed to the extent of the "O" level.
再者,在上述第1實施形態中,以將程式脈衝分類為3種之情形為例進行說明(VPGM1~VPGM3)。但,亦可分類為4種以上,且在1次程式迴路中依序施加該4種以上之脈衝。 In the first embodiment, the case where the program pulses are classified into three types will be described as an example (VPGM1 to VPGM3). However, it is also possible to classify into four or more types, and to apply the four or more types of pulses sequentially in a single program loop.
再者,上述第4實施形態之概念亦可應用於第3實施形態。即,在第3實施形態所說明之圖16中,亦可一面取代電壓VPGM2b而施加VPGM3,一面對連接有第2胞之位元線施加VQPW。 Furthermore, the concept of the fourth embodiment described above can also be applied to the third embodiment. That is, in Fig. 16 described in the third embodiment, VPGM3 may be applied instead of voltage VPGM2b, and V QPW may be applied to the bit line to which the second cell is connected .
再者,記憶體胞陣列10之構造不限於圖2至圖6所說明之構成。在上述實施形態中,如圖4所示,以將奇數序號之串組GR1之位元線接觸BC集中配置於記憶體胞陣列10之左側,而將偶數序號之串組GR2之位元線接觸BC集中配置於記憶體胞陣列10之右側之情形為例進行說明。但,該等位元線接觸BC亦可共同集中配置於右側,或共同集中配置於左側。 Furthermore, the configuration of the memory cell array 10 is not limited to the configuration illustrated in FIGS. 2 to 6. In the above embodiment, as shown in FIG. 4, the bit line contact BC of the odd-numbered string group GR1 is collectively disposed on the left side of the memory cell array 10, and the bit line of the even-numbered string group GR2 is contacted. The case where BC is centrally disposed on the right side of the memory cell array 10 will be described as an example. However, the bit line contacts BC may be collectively disposed on the right side or collectively on the left side.
再者,上述實施形態可應用於在資料之寫入時同時所選擇之記憶體胞之集合即頁面內,於資料之寫入速度上具有偏差之構成,不限於NAND型快閃記憶體,而可應用於所有記憶裝置。 Furthermore, the above-described embodiment can be applied to a configuration in which a data is written in a page which is a set of memory cells selected at the same time as data is written, and is not limited to the NAND type flash memory. Can be applied to all memory devices.
雖已說明本發明之幾個實施形態,但該等實施形態係作為例子而提示者,並非意欲限定發明之範圍。該等實施形態可以其他多種形態實施,在不脫離發明主旨之範圍內,可進行多種省略、替代及變 更。該等實施形態或其變化係包含於發明之範圍或主旨內,且同樣包含於申請專利範圍所記載之發明及其均等之範圍內者。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. more. The embodiments and variations thereof are included in the scope of the invention and the scope of the invention as set forth in the appended claims.
t1‧‧‧時刻 Time t1‧‧‧
t2‧‧‧時刻 Time t2‧‧‧
t3‧‧‧時刻 Time t3‧‧‧
t4‧‧‧時刻 Time t4‧‧‧
t5‧‧‧時刻 T5‧‧‧ moment
t6‧‧‧時刻 Time t6‧‧‧
t7‧‧‧時刻 Time t7‧‧‧
t8‧‧‧時刻 T8‧‧‧ moment
Vfy-A‧‧‧驗證電壓 Vfy-A‧‧‧Verification voltage
Vfy-B‧‧‧驗證電壓 Vfy-B‧‧‧Verification voltage
Vfy-C‧‧‧驗證電壓 Vfy-C‧‧‧Verification voltage
VPGM1‧‧‧程式電壓 VPGM1‧‧‧ program voltage
VPGM2‧‧‧程式電壓 VPGM2‧‧‧ program voltage
VPGM3‧‧‧程式電壓 VPGM3‧‧‧ program voltage
Claims (14)
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US11138136B2 (en) | 2016-10-20 | 2021-10-05 | Samsung Electronics Co., Ltd. | System and method for routing bus including buffer |
TWI751189B (en) * | 2016-10-20 | 2022-01-01 | 南韓商三星電子股份有限公司 | Computing system and method for routing bus including buffer routing system |
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