TW201545308A - Three-dimensional multiple chip packages including multiple chip stacks - Google Patents

Abstract

A structure of a multichip package and a method for fabricating the multichip package are described. The multichip package includes multiple chip stacks including chips in multiple chip layers. Each of the chip stacks includes two or more chips, each chip being inside vertical projection of at least another chip in the chip stack and disposed in a respective chip layer. Each of the chip stacks also includes horizontal conductive lines extending to perimeter regions around the chip stacks, the chips in a particular chip layer being electrically connected to horizontal conductive lines disposed in the particular chip layer. Each of the chip stacks also includes vertical conductive lines in the perimeter regions electrically connected to one or more of the horizontal conductive lines in at least two chip layers. The multichip package also includes a controller chip electrically connected to at least one chip in the chip stacks.

Description

3D multi-chip package with multi-wafer stack 【0001】

The present disclosure is directed to a three-dimensional multi-chip package.

【0002】

In a three-dimensional multi-chip package, a plurality of wafers (grains) may have been vertically stacked and interconnected to form a single component. The stacked wafers can be interconnected by electrical connections, such as wire bonding around the edges of the stacked wafer edges. Three-dimensional multi-chip packages can achieve higher storage capacity and/or functionality in a small form factor.

[0003]

Through-Silicon Via (TSV) is a vertical electrical connection through a silicon wafer. Through-via vias provide a shorter electrical connection between stacked wafers than wire bonding. Shorter signal transmission times and lower resistance and parasitic capacitance for shorter electrical connections allow for a wider connection bus and wider connection speeds, as well as lower power consumption.

[0004]

There are many process challenges in wearing through holes. Opening a through-silicon hole and filling the opening with a conductive material, such as copper, can be a challenge. It is another challenge to align the through-via via connections between two wafers made by different manufacturers (with different design rules). Passing through the via may cause stress that changes the circuit characteristics of nearby components. Through-holes generally require looser design rules, which may increase the area and cost.

[0005]

Three-dimensional multi-chip packages can be formed by using through-dielectric Vias (TSVs). For example, U.S. Patent Application Serial No. 13/597,669, filed on Aug. 29, 2012, entitled,,,,,,,,,,,,,,,,,,,,,,,, A stacked chip structure of via holes. A stacked wafer structure has two or more wafers that are individually mounted on different substrates and has a dielectric layer between the substrates. Between the stacked chips is performed using horizontal conductors disposed in the substrates, and vertical conductors passing through the substrate or dielectric layer at positions outside the edges of the stacked wafers. Internal connection. The through dielectric vias provide a denser connection between the stacked wafers. However, similar to wire bonding, the connection distance between stacked wafers is usually determined by the size of the stacked wafers. Therefore, the connection speed and bandwidth between stacked wafers may be limited by the size of the stacked wafer.

[0006]

One of the challenges in making a multi-chip package is that the process yield of a multi-chip package may be less than the process yield of a particular component in a multi-chip package. Furthermore, defective components (eg, defective wafers) in a multi-wafer package can render the overall package non-functional.

【0007】

Accordingly, there is a need to provide a three-dimensional multi-chip package with dielectric vias that provides higher connection speeds and bandwidths between interconnected wafers in a three-dimensional multi-chip package. There is also a need to provide a three-dimensional multi-chip package with built-in redundancy.

[0008]

The present technology provides a multi-chip package and a method of fabricating the multi-chip package. The multi-chip package can include an array of chip stacks. Wherein the wafer stack is separated by an insulator located within a perimeter region of each wafer stack in the array. The vertical connections between the wafers in the wafer stack are made using interlayer connections through the surrounding area. The horizontal connection from the wafer to the interlayer connection can be made using circuitry inside the chip layers in the wafer stack. A control wafer constructed to control the operation of the wafer in the wafer stack array can be included in the multi-chip package.

【0009】

A multi-chip package is described that includes a plurality of wafer stacks including a plurality of chips disposed in a plurality of wafer layers. Each wafer stack contains two or more wafers. Each wafer is located in a vertical projection of at least one other of the wafer stacks and is each disposed within one of the wafer layers. Each wafer stack also includes horizontal wires that extend to the surrounding area of the periphery of the wafer stack. The wafers located in a particular wafer layer are electrically bonded to horizontal wires disposed in a particular wafer layer. Each wafer stack also includes vertical wires that are located in the surrounding area and that are electrically connected to one or more horizontal wires that are located in at least two of the wafer layers.

[0010]

The multi-chip package also includes a control wafer electrically coupled to at least one of the wafer stacks.

[0011]

Other aspects and advantages of the present technology can be found in the following drawings, specifications, and patent claims, which are described in detail below:

[0052]

100‧‧‧Three-dimensional multi-chip package
101‧‧‧Three-dimensional multi-chip package
110‧‧‧ wafer stack
110a‧‧‧ wafer stack
110b‧‧‧ wafer stack
121‧‧‧First Class Wafer
121a‧‧‧ wafer
121b‧‧‧ wafer
122‧‧‧second level wafer
122a‧‧‧ wafer
122b‧‧‧ wafer
123‧‧‧Third-level wafer
123a‧‧‧ wafer
123b‧‧‧ wafer
131‧‧‧Insulation
132‧‧‧Insulation
133‧‧‧Insulation
134‧‧‧Insulation
141‧‧‧Insulation
142‧‧‧Insulation
143‧‧‧Insulation
144‧‧‧Insulation
151‧‧‧ horizontal wire
161‧‧‧Vertical wire
Partial magnification of 164‧‧‧1B
165‧‧‧ Partial enlargement of Figure 1B
190‧‧‧Control chip
301‧‧‧ Ditch
302‧‧‧ Ditch
400‧‧‧Single wafer stack
Partial magnification of 411‧‧‧Fig.
Partial magnification of 412‧‧‧Fig.
1301‧‧‧ Busbar interface unit
1302‧‧‧Alternative Repair Resource/Repair Unit
1303‧‧‧frequency control unit
1304‧‧‧Wafer Stack Status Register
A-A'‧‧‧Dissection wafer stack
Ap‧‧‧ wafer stack
L ₁ ‧‧‧Maximum Wafer Size/2
L ₂ ‧‧‧Width of the surrounding area

[0012]

1A and 1B are side and top views, respectively, of a three-dimensional multi-chip package having a plurality of wafer stacks.
2A and 2B are side and top views, respectively, of a three-dimensional multi-chip package having a plurality of wafer stacks, according to another embodiment.
Figure 3 is a side view showing a more detailed structure of one of the wafer stacks in the three-dimensional multi-chip package of Figure 1A.
4A to 4H are cross-sectional views showing the structure of the process steps of the bottom two layers of the wafer stack of FIG.
Figure 5 is a top view of a single wafer stack.
Figure 6 is a top view of a package having a plurality of wafer stacks.
Figure 7 is a diagram showing the alignment displacements of the single wafer stack of Figure 5.
Figure 8 is a diagram showing the alignment offset of the package having a plurality of wafer stacks of Figure 6.
Figure 9 is a diagram showing the alignment displacement of the single wafer stack of Figure 5.
Figure 10 is a diagram showing the alignment offset of the package having a plurality of wafer stacks of Figure 6.
Figure 11 is a diagram showing the defective through-via and defective wafers in the single wafer stack of Figure 5.
Figure 12 is a diagram showing a through-via via and a defective wafer in a package having a plurality of wafer stacks in Figure 6.
Figure 13 is a block diagram showing an example of a control wafer.

[0013]

The detailed description of the present technology is provided below in conjunction with the drawings.

[0014]

1A and 1B are side and top views, respectively, of a three-dimensional multi-chip package 100 having a plurality of wafer stacks. The three-dimensional multi-chip package 100 includes a plurality of wafer stacks, such as wafer stacks 110a, 110b, and the like.

[0015]

Each wafer stack (e.g., wafer stack 110a) includes two or more wafers stacked in a vertical direction (e.g., wafers 121a, 122a, and 123a). That is, each wafer in a particular wafer stack is located in a vertical projection of at least one other wafer in the particular wafer stack.

[0016]

The wafers in the wafer stack of the three-dimensional multi-chip package 100 may have the same or different sizes. The wafers in the wafer stack of the three-dimensional multi-chip package 100 may be wafers of the same or different types. In some embodiments, the wafer stack (eg, wafer stacks 110a, 110b...) can have the same wafer combination. For example, the first level (top level) wafers (121a, 121b ...) may be logic chips (eg, one or more processors having a bus interface unit and a memory access unit) At the same time, the second level chip (122a, 122b ...) may be a first type of memory chip (for example, a dynamic random-access-memory such as a DRAM chip). The third level wafer (123a, 123b ...) may be a second type of memory wafer (for example, a non-volatile memory wafer such as a flash memory wafer or a phase change memory chip). In another embodiment, the first level of the wafer is a logic wafer, and the second and third level wafers are the first level and the second level of cache memories of the logic chips (eg, second The level and third level wafers may be the same or different types of memory having the same or different speeds). In yet another embodiment, the first level of the wafer is a logic wafer while the second and third level wafers are the memory of the logic wafers. The second level wafer may include peripheral circuits of the memory (for example, an I/O circuit, an error-correcting code or ECC circuits). The third level wafer may comprise a memory cell array of memory. In another embodiment, all of the wafers in all of the wafer stacks may be memory chips of the same type having control wafers constructed as memory controllers for managing access to the memory chips.

[0017]

In some embodiments, multiple layers of wafer stacks having the same pattern (eg, including a logic die, a first memory die, and a second memory die) can be provided in a three-dimensional multi-chip package 100 in. These wafer stack repeating structures of the same type are constructed to provide a higher internal connection bandwidth and alternate repair resources, which will be described in more detail in conjunction with Figures 5 through 12, as described below.

[0018]

The wafers in the wafer stack of the three-dimensional multi-chip package 100 are disposed in a plurality of wafer layers. Each wafer layer includes a plurality of wafers and wires connecting the wafers and includes one or more insulating layers for supporting the wafers and wires in the wafer layer. For example, the first level (top level) wafer layer includes an insulating layer 131 and first level wafers (121a, 121b ...) over the insulating layer 131. The second level wafer layer includes an insulating layer 132 and second level wafers (122a, 122b ...) over the insulating layer 132. The third level (bottom level) wafer layer includes an insulating layer 133 and third level wafers (123a, 123b ...) over the insulating layer 133. Each wafer layer may also include an insulating layer (e.g., insulating layer 141, 142 or 143) overlying the wafer in the wafer layer and supporting the wafer layer above it.

[0019]

The insulating layers 131, 132, 133, 142, and 143 may include ceria, a polymer, or other insulating material suitable for supporting the aforementioned wires and wafers. In addition, the insulating layer may also comprise a plurality of types of materials.

[0020]

The insulating layer 133 at the bottom may be disposed above the substrate layer. For example, the insulating layer at the bottom may be a layer of ruthenium dioxide grown on the surface of the tantalum wafer. In another example, the insulating layer at the bottom may be an insulating layer carried by a printed circuit board or ceramic substrate.

[0021]

The wafers in the wafer layer are electrically connected to horizontal wires in the wafer layer. For example, the first level wafers (121a, 121b ...) in the first level wafer layer are electrically connected to the horizontal lines 151 disposed in the insulating layer 131. The second level wafers (122a, 122b ...) in the second level wafer layer are electrically connected to the horizontal lines 151 disposed in the insulating layer 132. The third level wafers (123a, 123b ...) in the third level wafer layer are electrically connected to the horizontal lines 151 disposed in the insulating layer 133. The horizontal wires 151 located in the two different wafer layers can be connected by the vertical wires 161 (through the dielectric vias) through the insulating layer between the horizontal wires 151. For example, the horizontal wires 151 located in the second level wafer layer (disposed in the insulating layer 132) and the horizontal wires 151 located in the third layer wafer layer (disposed in the insulating layer 133) may pass through the insulating layer 132. Connect with the vertical wire 161 (through the dielectric via) of 143. Thus, wafers located in each wafer stack (e.g., wafer stack 110a) can be electrically interconnected by using horizontal wires 151 and vertical wires 161.

[0022]

In Fig. 1A, only one level of horizontal wires 151 are shown corresponding to each wafer layer. In order to accommodate more complicated wiring, a wafer layer may have more than one layer of horizontal wires to connect the wafers in the three-dimensional multi-chip package 100. For example, the third level wafer layer (including the third level wafers 123a, 123b ...) may include another layer of horizontal wires disposed in the insulating layer 143.

[0023]

Each of the vertical wires 161 in a wafer stack is located in a peripheral region outside the vertical projection of at least one of the wafer stacks and outside the vertical projection of the wafer of another wafer stack of the three-dimensional multi-chip package 100. That is, the vertical wires (through dielectric vias) of a particular wafer stack are located in the surrounding area of the periphery of the wafer of the particular wafer stack, as well as other others in the particular wafer stack and three-dimensional multi-chip package 100. The area between adjacent wafer stacks is illustrated by partial magnifications 164 and 165 in Figure 1B.

[0024]

Each horizontal wire 151 of the wafer stack is located outside of the vertical projection of the wafer of another wafer stack in the three-dimensional multi-chip package 100. That is, the horizontal wires of a wafer stack are located inside the peripheral area of the wafer periphery and are electrically connected to the wafers located in the wafer stack.

[0025]

The three-dimensional multi-chip package 100 also includes a control wafer 190 disposed over the wafer of the top-level wafer layer. As shown in FIG. 1A, the control wafer 190 is disposed over the insulating layer 134. The insulating layer 134 is disposed over the insulating layer 141 on the wafer (wafers 121a, 121b...) covering the insulating layer 131 and the top layer wafer layer. An additional insulating layer 144 can be overlying the control wafer 190 and the insulating layer 134. Control wafer 190 is constructed to provide control signals for controlling the operation or configuration of the wafers in the multi-chip package. In this embodiment, the control wafer 190 includes a controller or is part of a controller, wherein the controller is electrically coupled to at least one of the plurality of wafer stacks. And in some embodiments, the controller is electrically coupled to at least one of each of the plurality of wafer stacks by at least one vertical wire 161 in a through dielectric via located in one of the surrounding regions Wafer. For example, the control wafer 190 may be (wafer) connected by a horizontal wire 151 located in the insulating layer 134 and a vertical wire 161 (through dielectric via) passing through the insulating layers 134 and 141. Control wafer 190 includes circuitry (e.g., by transferring control signals to one or more wafer stacks) that is configured to control wafer stacking in three-dimensional multi-chip package 100 (e.g., control function unit or other) Control logic, bus interface unit). In one embodiment, the control wafer 190 is not part of the three-dimensional multi-chip package 100 (ie, an off-package controller). Such a controller can create an interface with the wafer stack in the three-dimensional multi-chip package 100 via wires and/or other circuitry (eg, I/O circuitry or bridge chip of the three-dimensional multi-chip package 100).

[0026]

2A and 2B are side and top views, respectively, of a three-dimensional multi-chip package (101) having a plurality of wafer stacks, according to another embodiment. The side view is depicted along section line A-A' in the top view. Similar to the three-dimensional multi-chip package 100 illustrated in FIGS. 1A and 1B, the three-dimensional multi-chip package 101 has a plurality (12) of wafer stacks 110 and a plurality of wafers disposed in three wafer layers. The first level (top level) wafer layer includes an insulating layer 131 and a first level (top level) wafer 121 over the insulating layer 131. The second level wafer layer includes insulating layers 132 and 142 and a second level wafer 122 over the insulating layer 132. The third level (bottom level) wafer layer includes insulating layers 133 and 143 and a third level wafer 123 above the insulating layer 133. The wafers in the wafer stack can be connected by vertical wires 161 and horizontal wires 151. The control wafer 190 is disposed above the insulating layer 131 like the other top level wafers 121. That is, the control wafer 190 is disposed in the top layer wafer layer of the three-dimensional multi-chip package 101. In contrast, the control wafer 190 illustrated in FIG. 1A is located above the top level wafers (121a, 121b...) in the top level wafer layer of the three-dimensional multi-chip package 100.

[0027]

In FIGS. 2A and 2B, the control wafer 190 is electrically connected to at least one of the wafer stacks 110 through horizontal wires 151 located in the insulating layer 131. Control wafer 190 includes circuitry that is configured to control the activity of wafer stack 110 in three-dimensional multi-chip package 101. The three-dimensional multi-chip package 101 may also include an insulating layer 144 covering the control wafer 190, the first-level wafer 121, and the insulating layer 131.

[0028]

It is to be noted that the side views in FIGS. 1A and 2A are a simplified view of the wafers in each wafer stack, and the horizontal wires 151 and the vertical wires 161 connecting the control wafer 190 and the wafer stack. Each of the horizontal wires 151 or the vertical wires 161 shown in FIGS. 1A and 2A may include a plurality of wire segments of different lengths or sizes. For details, refer to the following and FIG.

[0029]

3 is a side view showing a more detailed structure of the wafer stack 110b in the three-dimensional multi-chip package 100 of FIG. 1A. As shown in FIG. 1A, the wafer stack 110b includes a third level wafer 123b disposed over the insulating layer 133, a second level wafer 122b disposed over the insulating layer 132, and a first level wafer disposed over the insulating layer 131. 121b. The wafers 121b, 122b, and 123b may be connected to each other by horizontal wires 151 disposed in a specific insulating layer and vertical wires 161 including through dielectric vias through the insulating layers 131, 132, 142, and 143. These through dielectric vias can have different sizes (diameters).

[0030]

4A to 4H are schematic cross-sectional views showing the structure of the bottom two-layer process of the wafer stack 110b of FIG. This process step begins with the insulating layer 133 depicted in FIG. 4A. A horizontal wire 151 is formed in the insulating layer 133 using a damascene process, as shown in FIGS. 4B to 4C. In FIG. 4B, the insulating layer 133 is patterned (eg, using a photoresist) and etched to form a plurality of trenches 301.

[0031]

Next, the trench 301 is filled with a conductive material such as copper or aluminum to form a horizontal wire 151 as shown in FIG. 4C. After the horizontal wires 151 are formed, a planarization method such as Chemical Mechanical Pluishing (CMP) may be used to planarize the upper surface of the structure as depicted in FIG. 4C. Other methods can also be used to make the horizontal wire 151. For example, a blanket metal layer (eg, an aluminum metal layer) is first formed over the insulating layer 133. This metal layer is then patterned and etched (eg, using photoresist and plasma etching) to form horizontal wires 151.

[0032]

The wafer 123b (the third level wafer of the wafer stack 110b) may be flip-chip mounted on the insulating layer 133 as shown in FIG. 4D. The wafers 123b are electrically connected to at least some of the horizontal wires disposed in the insulating layer 133 (for example, by Controlled Collapse Chip Connection or C4 bumps).

[0033]

In another embodiment, the wafer 123b may be attached to the insulating layer 133 face up. For example, a trench having a depth approximately the same as the thickness of the wafer 123b may be formed in the insulating layer 133, and then the wafer 123b may be attached to the trench with the connection pad of the wafer facing upward. A horizontal wire 151 electrically connected to the wafer connection pad is formed in the peripheral region of the wafer 123b and in the periphery of the wafer 123b.

[0034]

Before the wafer 123b is attached to the insulating layer 133, it may be tested and thinned (thickness reduction).

[0035]

As shown in FIG. 4E, after the third-level wafer 123b is disposed on the insulating layer 133, the insulating layer 143 is formed to cover the wafer 123b, the insulating layer 133, and the horizontal wires 151 formed in the insulating layer 133. The insulating layer 143 may be planarized using a planarization method such as chemical mechanical polishing. Next, an insulating layer 132 is formed over the insulating layer 143. In an embodiment, the insulating layers 132 and 143 may be a single insulating layer formed over the wafer 123b and the insulating layer 133.

[0036]

The horizontal wire 151 is formed in the insulating layer 132 by using a damascene process (Figs. 4A to 4C) in which the horizontal wires 151 are formed in the insulating layer 133 as described above.

[0037]

Thereafter, the structure depicted in FIG. 4E is patterned (eg, using photoresist) and etched to form trenches 302, as depicted in FIG. 4F. As depicted in FIG. 4G, the trench 302 is then filled with a conductive material (eg, copper or aluminum) to form a vertical wire 161, thereby causing one of the one or more horizontal wires 151 and the insulating layer 133 in the insulating layer 132. Or a plurality of horizontal wires 151 are electrically connected. It is to be noted that when the vertical wires 161 pass through the insulating layers 132 and 143 in the peripheral region around the periphery of the wafer 123b, they are through a dielectric via. The planarization method, such as chemical mechanical polishing, can be used to planarize the insulating layer 132.

[0038]

Subsequently, the second level wafer 122b is attached to the insulating layer 132 as shown in FIG. 4H. The wafer 122b is electrically connected to one or more horizontal wires 151 located in the insulating layer 132. Therefore, the wafer 122b may pass through one or more horizontal wires 151 in the insulating layer 132, one or more vertical wires 161 (through dielectric vias) in the surrounding area around the wafers 122b and 123b, and the insulating layer 133 One or more horizontal wires 151 are electrically connected to the wafer 123b.

[0039]

Although FIGS. 4A-4H only illustrate the steps of forming a portion of the wafer stack 110b, the overall three-dimensional multi-chip package 100 (or the repeating structure of the three-dimensional multi-chip package 100) can be in accordance with FIGS. 4A-4H. The relevant steps are similar to the description. For example, the process begins with an insulating layer 133, and a horizontal wire may be formed in the insulating layer 133. And, in order to form a repeating structure of the three-dimensional multi-chip package 100, a plurality of third-level wafers (123a, 123b...) may be attached to respective positions on the insulating layer 133. The process continues to form insulating layers 143 and 142, insulating layers 132 and 131, horizontal wires in these insulating layers, and vertical wires (through dielectric vias) through the insulating layers. And, the second-level wafers (122a, 122b, ...), the first-level wafers (121a, 121b, ...), and the control wafer 190 are attached to respective positions. After attaching the repeating structures of the control wafer 190 to their respective positions, an insulating layer 144 is formed to cover the control wafer 190. The entire structure is then cut into a separate structure of the three-dimensional multi-chip package 100.

[0040]

The maximum connection distance between the two wafers in the wafer stack using the aforementioned horizontal and vertical wires is the sum of the wafer size, the width of the surrounding area of the wafer stack, and the vertical connection height in the surrounding area around the wafer stack. The function. For example, the maximum connection distance (D) between the layer wafers shown in the wafer stack of FIG. 3 may be the maximum wafer size 2 × L ₁ , twice the width (2 ×) of the area around the wafer stack L ₂ And the sum of the vertical connection heights H of the top and bottom insulation layers: D = 2 × L ₁ + 2 × L ₂ + H. D is an estimate of the distance of the longest conduction path that the signal can transmit between the two wafers in the stack. The conductive path may include a horizontal wire (L ₁ ) extending from the center of the wafer to the edge of the wafer in the top insulating layer, and a horizontal wire (L ₂ ) in the top insulating layer extending across the width of the surrounding region from the top insulating layer a vertical wire (H) extending from the edge of the wafer to the edge of the wafer stack, extending from the top insulating layer to the underlying insulating layer, and a horizontal wire (L ₂ ) in the underlying insulating layer extending through the width of the surrounding region from the underlying insulating layer The edge of the wafer to the edge of the wafer stack and the horizontal wire (L ₁ ) extending from the center of the wafer to the edge of the wafer in the underlying insulating layer. The wafer size (2 x L ₁ ) can be between about 1 mm (mm) and 20 mm. The thickness of the wafer may be between 10 micrometers (μm) and 25 micrometers after thinning. The overall height (H) of the vertical connection of the wafer stack can range from about 20 micrometers (μm) to about 500 micrometers, depending on the number of layers in the wafer stack. The width (L ₂ ) of the surrounding area of the wafer stack may range from about a few micrometers (μm) to several millimeters depending on the size of the wafer and the number of vertical connections (through dielectric vias) in the surrounding area ( For example, in FIG. 3, if the wafer is less than the wafer 122b 123b, 122b of the wafer may be greater than L ₂ L ₂ of the wafer 123b). The through dielectric vias have a diameter of about 2 microns and the spacing between the other through dielectric vias is also about 2 microns. It should be noted that Figure 3 is not drawn to scale. Since the wafer size can be much larger than the height of the vertical connection and the width of the surrounding area of the wafer stack, the maximum connection distance between the two wafers in the wafer stack is determined by the size of the stacked wafer.

[0041]

The shorter connection between the wafers has a shorter signal transmission time and less resistance and parasitic capacitance than the longer connection distance between the two wafers. Shorter signal transmission times and smaller resistors and parasitic capacitances give higher connection speeds and bandwidths for shorter connections. As previously mentioned, a large proportion of the maximum connection distance between two wafers in a wafer stack is determined by the size of the stacked wafer. Thus, the internal connection speed and bandwidth of the wafer stack can be improved by reducing the size of the wafer in the wafer stack. More specifically, the size of stacked wafers in a three-dimensional multi-chip package can be reduced by having a plurality of wafer stacks in the package and each wafer stack having a smaller size wafer. The multi-wafer stack can be formed and connected to a control wafer as disclosed in the three-dimensional multi-chip package 100 as previously described. For example, a three-dimensional multi-chip package comprising a plurality of wafer stacks and a control wafer may include from 4 to 400 wafer stacks (eg, a 2 by 2 array of wafer stacks to a 20 by 20 array of wafer stacks). Each wafer in the package can have a width dimension, a length dimension, or a width and length dimension of between about 1 mm and 100 mm. The optimal number of wafer stacks and the optimum wafer size can be determined by the design rules for the horizontal and vertical wires connecting the wafers in the wafer stack. The optimal number of wafer stacks and the optimum wafer size can also be determined by the complexity of the wafers in the wafer stack.

[0042]

For example, the three-layer single wafer stack 400 illustrated in FIG. 5 includes a wafer having 16 processor cores in a first level, a 16Mb DRAM wafer in a second level, and a third level. 16Mb NAND chip. The same function as wafer stack 400 can be achieved using 16 identical wafer stacks, each of which includes a wafer with one processor core in the first level and a 1Mb DRAM wafer in the second level. And a 1Mb NAND chip in the third level. The repeating of the 16 smaller wafer stacks and a control wafer can form a single three-dimensional multi-chip package, such as the three-dimensional multi-chip package 100 illustrated in FIGS. 1A and 1B.

[0043]

Figure 5 is a top view of a single wafer stack 400 having a wafer in the first level with 16 processor cores, a 16Mb DRAM wafer in the second level, and a 16Mb in the third level. NAND wafer. Figure 6 is a top view of a three-dimensional multi-chip package 100 having a repeating structure of 16 smaller wafer stacks, each comprising a processor core in a first level, and a 1Mb DRAM chip in a second level. And a smaller wafer stack repeat structure of a 1Mb NAND wafer on the third level. For the sake of simplicity, the control wafer of the three-dimensional multi-chip package 100 is not shown in FIG. It is worth noting that when a single wafer stack is implemented with 16 smaller (and identical) wafer stacks, the maximum wafer size of 2 × L ₁ can generally be reduced. = . At the same time, due to the increase in the total perimeter length (total perimeter length) = 2.5, the number of vertical connections (through dielectric vias) at the edge of each wafer stack can be reduced (calculated by the total number of pre-defined vertical connections). Therefore, the width L ₂ of the surrounding area of the wafer stack can also be reduced, as shown by partial enlargements 411 and 412 of Figs. 5 and 6. The reduction in the maximum wafer size 2 x L ₁ and the width L ₂ of the surrounding area of the wafer stack reduces the maximum connection distance between the wafers in the smaller wafer stack of the three-dimensional multi-chip package 100. Reducing the maximum connection distance between the wafers in the three-dimensional multi-chip package 100 compared to the connection rate and bandwidth between the wafers in the single wafer package 400 enhances the inter-wafer spacing in the smaller wafer stack of the three-dimensional multi-chip package 100. Connection rate and bandwidth.

[0044]

In addition to having a higher connection rate and bandwidth, the three-dimensional multi-chip package 100 has 16 smaller wafer stack repeating structures, each containing a processor core located in a first level and a second level 1Mb DRAM chip and a 1Mb NAND chip in the third level, including a chip with 16 processor cores in the first level, a 16Mb DRAM chip in the second level, and a 16Mb NAND chip in the third level Compared to the single wafer stack 400, there are other differences. For example, a smaller wafer in each three-dimensional multi-chip package 100 can have a higher process yield than a wafer in a single wafer stack 400.

[0045]

Figure 7 is a top plan view of the aforementioned single wafer stack 400. Figure 8 also depicts a top view of the aforementioned three-dimensional multi-chip package 100 having 16 small wafer stacked repeat structures. Figures 7 and 8 also illustrate alignment marks located at opposite corners of the wafer for attaching the wafer to the insulating layer. Because of the shorter distance between the alignment marks, the smaller of the smaller wafer stacks of the three-dimensional multi-chip package 100 can have a greater reasonable misalignment than the larger ones of the single wafer stack 400. (rotational misalignment). The displacement distance of the wafer due to misalignment is the product of the wafer size and the angle at which the wafer is reasonably misaligned. Larger reasonable misalignment for wafers in smaller wafer stacks may not result in larger offset distances due to his smaller wafer size, such as Figure 9 and Figure 10 shows. However, since each of the 16 wafer stacks in the three-dimensional multi-chip package 100 may have different alignment offsets in different directions. In order to attach a larger amount of wafer stack, it may be necessary to increase alignment tolerance.

[0046]

The three-dimensional multi-chip package 100 may require higher attachment costs (and take longer to attach) than a single wafer stack 400 that is less expensive to attach. However, it may be difficult to attach a large wafer in a single wafer stack 400 to a flat surface due to mismatch in curvature between the larger wafer and the surface to which it is to be attached. Thus, the process yield of a single wafer stack 400 using larger wafers may therefore be reduced.

[0047]

A package having a multi-wafer stack and a control wafer, such as the three-dimensional multi-chip package 100 as illustrated in FIGS. 1A and 1B, can provide additional backup repair resources and dynamic control capabilities as compared to a single wafer stack ( Dynamic control capability). For example, the wafer stacks (110a, 110b...) can be operated independently of each other. Control wafers (eg, circuits and logic implemented in control wafer 190) can dynamically adjust the wafer based on work loading and thermal conditions (eg, by transferring control signals to a particular wafer stack) The operating frequency of the stack.

[0048]

FIG. 13 is a block diagram showing an example of a control wafer 190. The control wafer 190 includes a busbar interface unit 1301 for transmitting or receiving signals from the wafer stack in the multi-chip package. The frequency control unit 1303 in the control wafer 190 can (by the bus interface unit) transmit the frequency control signals to a particular wafer stack in the multi-chip package to adjust the operating frequency of the particular wafer stack. The frequency control unit 1303 can also maintain the current operating frequency of a particular wafer stack (or other wafer stack in a multi-chip package) located in the chip stack status registers 1304.

[0049]

Control wafer 190 can also activate or deactivate specific wafers in a particular wafer stack or wafer stack. For example, the alternate repair resource or repair unit 1302 in the control wafer 190 can (by the bus interface unit 10301) transfer the activation/inactivation control signal to a particular wafer stack or a particular wafer. The alternate repair resource or repair unit 1302 can maintain and update the active state of the particular wafer stack associated with the multi-chip package in the wafer stack status register 1304. Control wafer 190 can deactivate a particular wafer stack, such as when the particular wafer stack is no longer functioning. A wafer stack may lose its function due to defective through dielectric vias (vertical leads), defective horizontal leads, or defective wafers in the wafer stack. Figure 11 illustrates a defective through dielectric via and a defective wafer in a single wafer stack 400. As depicted in FIG. 11, a defective single through dielectric via and a defective single wafer may defeat the entire single wafer stack 400. However, as illustrated in FIG. 12, by the multi-wafer stack of the three-dimensional multi-chip package 100, the control wafer can be a wafer stack (eg, a wafer stack) containing defective through-silicon vias or defective wafers. Layer "a") is permanently deactivated while still allowing the entire multi-chip package 100 and other wafer stacks (e.g., wafer stacks "b", "c" ... "p") to perform their functions.

[0050]

With a multi-wafer stack, the three-dimensional multi-chip package 100 can provide built-in spare repair resources or self-repair capabilities. For example, a three-dimensional multi-chip package 100 having 16 processor cores (each of which has a processor core of 16 wafer stacks) can function by 14 processor cores. Control wafer 190 can be constructed to dynamically distribute the workload to 14 of the 16 wafer stacks containing the processor core, freeing up two redundant or spare wafer stacks. For example, the alternate repair resource or repair unit 1302 can assign a workload to the wafer stack "a" by directing the workload directly to the wafer stack "a" through "n" and correspondingly updating the wafer stack status register 1304. "To" n" (as shown in Figure 12). If one or two processor cores (one or two wafer stacks) fail, the control wafer 190 will be in a spare wafer stack (such as the wafer stacks "o" and "p" shown in Figure 12). Replace it. The three-dimensional multi-chip package 100 can also "downgrade" its performance if a failed processor core (wafer stack) is present. For example, if the three-dimensional multi-chip package 100 has only 10 functional processor cores left, the three-dimensional multi-chip package 100 can still function with ten functional processor cores.

[0051]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Three-dimensional multi-chip package

110a‧‧‧ wafer stack

110b‧‧‧ wafer stack

121a‧‧‧ wafer

121b‧‧‧ wafer

122a‧‧‧ wafer

122b‧‧‧ wafer

123a‧‧‧ wafer

123b‧‧‧ wafer

131‧‧‧Insulation

132‧‧‧Insulation

133‧‧‧Insulation

134‧‧‧Insulation

141‧‧‧Insulation

142‧‧‧Insulation

143‧‧‧Insulation

144‧‧‧Insulation

151‧‧‧ horizontal wire

161‧‧‧Vertical wire

190‧‧‧Control chip

Claims (20)

[Item 1] A device comprising:
A multi-chip package comprising a plurality of wafers disposed in a plurality of wafer layers, each of the wafer stacks comprising:
Two or more of the wafers, each of the wafers being located in a vertical projection of at least one other of the wafer stacks, and the wafers are each disposed in one of the wafer layers;
One or more horizontal wires extending into a plurality of peripheral regions of the periphery of the plurality of wafer layers, the plurality of wafers located in a specific wafer layer being electrically connected to the horizontal wires disposed in the specific wafer layer; And one or more vertical wires located in the surrounding area and electrically connected to the one or more of the horizontal wires located in at least two of the plurality of wafer layers; and a controller electrically connected to At least one of the plurality of wafers in the plurality of wafer stacks. [Item 2] The device of claim 1, wherein the controller comprises a wafer disposed on the wafers in a top wafer layer. [Item 3] The device of claim 1, wherein the controller comprises a wafer disposed in a top wafer layer. [Item 4] The device of claim 1, wherein the plurality of wafer stacks each comprise a logic wafer and a memory wafer. [Item 5] The device of claim 1, wherein the wafer stacks each comprise a logic wafer, a volatile memory wafer, and a non-volatile memory wafer. [Item 6] The device of claim 1, wherein the controller comprises a plurality of circuits configured to deactivate one or more of the plurality of wafer stacks. [Item 7] The device of claim 1, wherein the controller comprises a plurality of circuits configured to adjust an operating frequency of one or more of the plurality of wafer stacks. [Item 8] The device of claim 1, wherein the wafers in each of the wafer stacks are flip-chip mounted in the respective wafer layers corresponding thereto. [Item 9] The device of claim 1, wherein the number of the wafer stacks is between 4 and 400. [Item 10] The device of claim 1, wherein at least one of a width or a length of the plurality of wafer stacks is between 1 millimeter and 10 millimeters. [Item 11] A method of fabricating a three-dimensional multichip package, the method comprising:
Forming a plurality of wafer stacks, the plurality of wafers comprising a plurality of wafers disposed in a plurality of wafer layers, each of the wafer stacks comprising:
Providing two or more of the wafers, each of the wafers being located in a vertical projection of at least one other of the wafer stacks, and the wafers are each disposed in an individual one of the wafer layers;
Forming one or more horizontal wires extending into a plurality of surrounding regions of the periphery of the wafer stack, the wafers located in a specific wafer layer being electrically connected to the horizontal wires disposed in the specific wafer layer; And forming one or more vertical wires in the surrounding regions, and electrically connected to one or more of the horizontal wires located in at least two of the plurality of wafer layers; and providing a controller, the controller Optionally connected to at least one of the plurality of wafers located in the plurality of wafer stacks. [Item 12] The method of claim 11, wherein the controller comprises a wafer disposed on the wafers of a top wafer layer. [Item 13] The method of claim 11, wherein the controller comprises a wafer disposed in a top wafer layer. [Item 14] The method of claim 11, wherein the plurality of wafer stacks each comprise a logic wafer and a memory wafer. [Item 15] The method of claim 11, wherein the wafer stacks each comprise a logic wafer, a volatile memory wafer, and a non-volatile memory wafer. [Item 16] The method of claim 11, wherein the controller includes a circuit configured to deactivate one or more of the plurality of wafer stacks. [Item 17] The method of claim 11, wherein the controller includes a circuit configured to adjust an operating frequency of one or more of the plurality of wafer stacks. [Item 18] The method of claim 11, comprising the flip chip attaching the wafers in each of the plurality of wafer stacks. [Item 19] The method of claim 11, wherein the number of the wafer stacks is between 4 and 400. [Item 20] A method of fabricating a three-dimensional multi-chip package, the method comprising:
Forming a first patterned layer composed of a plurality of conductors in a first dielectric layer;
Attaching a plurality of first wafers to the first dielectric layer;
Forming a second patterned layer formed of a plurality of conductors on a second dielectric layer above the first dielectric layer;
Forming through-dielectric vias in a plurality of peripheral regions around the plurality of first wafers to connect the ones of the one or more of the second patterned layers to one or more The plurality of conductors in the first patterned layer; and a plurality of second wafers attached to the second dielectric layer.