TW201543636A - Chip package and method for forming the same - Google Patents

Chip package and method for forming the same Download PDF

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Publication number
TW201543636A
TW201543636A TW103127225A TW103127225A TW201543636A TW 201543636 A TW201543636 A TW 201543636A TW 103127225 A TW103127225 A TW 103127225A TW 103127225 A TW103127225 A TW 103127225A TW 201543636 A TW201543636 A TW 201543636A
Authority
TW
Taiwan
Prior art keywords
bump
device substrate
chip package
insulating layer
electrically connected
Prior art date
Application number
TW103127225A
Other languages
Chinese (zh)
Other versions
TWI529892B (en
Inventor
Chien-Hung Liu
Original Assignee
Xintec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintec Inc filed Critical Xintec Inc
Priority to TW103127225A priority Critical patent/TWI529892B/en
Priority to CN201410461293.3A priority patent/CN105097744A/en
Priority to US14/706,896 priority patent/US9761510B2/en
Publication of TW201543636A publication Critical patent/TW201543636A/en
Application granted granted Critical
Publication of TWI529892B publication Critical patent/TWI529892B/en

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Abstract

A chip package is disclosed. The chip package includes a first device substrate attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also disclosed.

Description

晶片封裝體及其製造方法 Chip package and method of manufacturing same

本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體及其製造方法。 The present invention relates to a chip package technology, and more particularly to a chip package and a method of fabricating the same.

晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。 The wafer packaging process is an important step in the process of forming electronic products. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside.

晶片封裝體通常與其他積體電路晶片各自獨立地設置於電路板上，再透過打線彼此電性連接。 The chip package is usually disposed on the circuit board independently of the other integrated circuit chips, and is electrically connected to each other through the wire.

然而，上述製造方法限制了電路板的尺寸，進而導致電子產品的尺寸難以進一步縮小。 However, the above manufacturing method limits the size of the board, which in turn makes it difficult to further reduce the size of the electronic product.

因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。 Therefore, it is necessary to find a novel chip package and a method of manufacturing the same that can solve or ameliorate the above problems.

本發明實施例係提供一種晶片封裝體，包括一第一裝置基底，貼附於一第二裝置基底的一第一表面上。一第三裝置基底貼附於第二裝置基底相對於第一表面的一第二表面上。一絕緣層覆蓋第一裝置基底、第二裝置基底及第三裝置基底，其中絕緣層內具有至少一開口。至少一凸塊設置於開口的底部下方。一重佈線層設置於絕緣層上，且經由開口電性連接 至凸塊。 Embodiments of the present invention provide a chip package including a first device substrate attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate relative to the first surface. An insulating layer covers the first device substrate, the second device substrate, and the third device substrate, wherein the insulating layer has at least one opening therein. At least one bump is disposed below the bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected via the opening To the bump.

本發明實施例係提供一種晶片封裝體的製造方法，包括將一第一裝置基底貼附於一第二裝置基底的一第一表面上。將一第三裝置基底貼附於第二裝置基底相對於第一表面的一第二表面上。形成至少一凸塊及一絕緣層，其中絕緣層覆蓋第一裝置基底、第二裝置基底及第三裝置基底，且具有至少一開口，使凸塊形成於開口的底部下方。在絕緣層上形成一重佈線層，其經由開口電性連接至凸塊。 Embodiments of the present invention provide a method of fabricating a chip package, comprising attaching a first device substrate to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate relative to the first surface. Forming at least one bump and an insulating layer, wherein the insulating layer covers the first device substrate, the second device substrate, and the third device substrate, and has at least one opening such that the bump is formed under the bottom of the opening. A redistribution layer is formed on the insulating layer, which is electrically connected to the bump via the opening.

100‧‧‧第一裝置基底 100‧‧‧First device substrate

110、210、310‧‧‧元件區 110, 210, 310‧‧‧ component area

120‧‧‧晶片區 120‧‧‧ wafer area

130‧‧‧第一接合墊 130‧‧‧First joint pad

140‧‧‧第一導電墊 140‧‧‧First conductive pad

150、160、250、260、360‧‧‧內連線結構 150, 160, 250, 260, 360‧‧‧ interconnection structure

200‧‧‧第二裝置基底 200‧‧‧Second device substrate

200a‧‧‧第一表面 200a‧‧‧ first surface

200b‧‧‧第二表面 200b‧‧‧ second surface

230‧‧‧第二接合墊 230‧‧‧Second joint pad

240‧‧‧第二導電墊 240‧‧‧Second conductive pad

300‧‧‧第三裝置基底 300‧‧‧ Third device substrate

330‧‧‧第三接合墊 330‧‧‧ third joint pad

340‧‧‧第三導電墊 340‧‧‧ Third conductive pad

370‧‧‧第一凸塊 370‧‧‧First bump

380‧‧‧導電結構 380‧‧‧Electrical structure

400、520‧‧‧絕緣層 400, 520‧‧‧ insulation

420、540‧‧‧開口 420, 540‧‧‧ openings

440、560‧‧‧重佈線層 440, 560‧‧‧Rewiring layer

460‧‧‧鈍化保護層 460‧‧‧passivation protective layer

480‧‧‧開口 480‧‧‧ openings

500‧‧‧第二凸塊 500‧‧‧second bump

510a‧‧‧第三凸塊 510a‧‧‧3rd bump

510b‧‧‧第四凸塊 510b‧‧‧fourth bump

I‧‧‧可見界面 I‧‧‧ visible interface

第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。 1A to 1E are cross-sectional views showing a method of manufacturing a chip package in accordance with an embodiment of the present invention.

第2及3圖係繪示出根據本發明不同實施例之晶片封裝體的剖面示意圖。 2 and 3 are schematic cross-sectional views showing a chip package in accordance with various embodiments of the present invention.

第4A至4F圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。 4A to 4F are cross-sectional views showing a method of manufacturing a chip package in accordance with another embodiment of the present invention.

第5至8圖係繪示出根據本發明其他實施例之晶片封裝體的剖面示意圖。 5 through 8 are schematic cross-sectional views showing a chip package in accordance with other embodiments of the present invention.

以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅 為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。 The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions only For the purpose of simplicity and clarity of the invention, it is not intended to represent any of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。 A chip package in accordance with an embodiment of the present invention can be used to package a microelectromechanical system wafer. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. The electronic components of the integrated circuit are, for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, A physical sensor that measures physical quantities such as capacitance and pressure to measure. In particular, a wafer scale package (WSP) process can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Semiconductor wafers such as accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads Package.

其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體 電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。 The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also suitable for stacking by means of stacking. A plurality of wafers of a circuit to form a chip package of multi-layer integrated circuit devices.

請參照第1E圖，其繪示出根據本發明一實施例之晶片封裝體的剖面示意圖。在本實施例中，晶片封裝體包括一第一裝置基底100、一第二裝置基底200、一第三裝置基底300、一絕緣層400、複數第一凸塊370及一圖案化的重佈線層440。在一實施例中，第一裝置基底100可為一矽基底或其他半導體基底。在本實施例中，第一裝置基底100內包括一個或一個以上的第一接合墊130及第一導電墊140，其可鄰近於第一裝置基底100的上表面。在一實施例中，第一接合墊130及第一導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，且僅繪示出第一裝置基底100內的兩個第一接合墊130及兩個第一導電墊140作為範例說明。 Referring to FIG. 1E, a cross-sectional view of a chip package in accordance with an embodiment of the present invention is shown. In this embodiment, the chip package includes a first device substrate 100, a second device substrate 200, a third device substrate 300, an insulating layer 400, a plurality of first bumps 370, and a patterned redistribution layer. 440. In an embodiment, the first device substrate 100 can be a germanium substrate or other semiconductor substrate. In the present embodiment, the first device substrate 100 includes one or more first bonding pads 130 and first conductive pads 140 that are adjacent to the upper surface of the first device substrate 100. In an embodiment, the first bonding pad 130 and the first conductive pad 140 may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is taken as an example here, and only two first bonding pads 130 and two first conductive pads 140 in the first device substrate 100 are illustrated as an example.

在本實施例中，第一裝置基底100可為包括一元件區110的晶片，且元件區110內包括一電子元件(未繪示)。在一實施例中，元件區110內的電子元件可透過第一裝置基底100內的內連線結構而與第一接合墊130及第一導電墊140電性連接。為簡化圖式，此處僅以虛線150及160分別表示第一接合墊130及第一導電墊140與元件區110之間的內連線結構。 In this embodiment, the first device substrate 100 can be a wafer including an element region 110, and the component region 110 includes an electronic component (not shown). In one embodiment, the electronic components in the component region 110 are electrically connected to the first bonding pad 130 and the first conductive pad 140 through an interconnect structure in the first device substrate 100. To simplify the drawing, only the dashed lines 150 and 160 represent the interconnect structure between the first bonding pad 130 and the first conductive pad 140 and the element region 110, respectively.

第二裝置基底200具有一第一表面200a及與其相對的一第二表面200b，且可透過一黏著層(未繪示)將第二裝置基底200的第一表面200a貼附於第一裝置基底100的上表面。在一實施例中，第二裝置基底200可為一矽基底或其他半導體基 底。在本實施例中，第二裝置基底200內包括一個或一個以上的第二導電墊240，其可鄰近於第二表面200b。再者，第二導電墊240的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第二裝置基底200內由單層導電層所構成的一個第二導電墊240作為範例說明。 The second device substrate 200 has a first surface 200a and a second surface 200b opposite thereto, and the first surface 200a of the second device substrate 200 is attached to the first device substrate through an adhesive layer (not shown). The upper surface of 100. In an embodiment, the second device substrate 200 can be a germanium substrate or other semiconductor substrate. bottom. In the present embodiment, the second device substrate 200 includes one or more second conductive pads 240 that are adjacent to the second surface 200b. Moreover, the structure of the second conductive pad 240 is similar to the structure of the first conductive pad 140. To simplify the drawing, only one second conductive pad 240 composed of a single conductive layer in the second device substrate 200 is illustrated here as an example.

在本實施例中，第二裝置基底200可為包括一元件區210的晶片，且元件區210內包括一電子元件(未繪示)。相似地，元件區210內的電子元件可透過第二裝置基底200的內連線結構(如虛線260所示)而與第二導電墊240電性連接。 In this embodiment, the second device substrate 200 can be a wafer including an element region 210, and the component region 210 includes an electronic component (not shown). Similarly, the electronic components in the component region 210 can be electrically connected to the second conductive pad 240 through the interconnect structure of the second device substrate 200 (as indicated by the dashed line 260).

第三裝置基底300可透過另一黏著層(未繪示)貼附於第二裝置基底200的第二表面200b上。在一實施例中，第三裝置基底300可為一矽基底或其他半導體基底。在本實施例中，第三裝置基底300內包括一個或一個以上的第三導電墊340，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。再者，第三導電墊340的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第三裝置基底300內由單層導電層所構成的一個第三導電墊340作為範例說明。 The third device substrate 300 can be attached to the second surface 200b of the second device substrate 200 through another adhesive layer (not shown). In an embodiment, the third device substrate 300 can be a germanium substrate or other semiconductor substrate. In the present embodiment, the third device substrate 300 includes one or more third conductive pads 340 that are adjacent to the upper surface of the third device substrate 300 (ie, relative to the surface of the second surface 100b). Moreover, the structure of the third conductive pad 340 is similar to the structure of the first conductive pad 140. To simplify the drawing, only one third conductive pad 340 composed of a single conductive layer in the third device substrate 300 is illustrated here as an example.

在本實施例中，第三裝置基底300可為包括一元件區310的晶片，且元件區310內包括一電子元件(未繪示)。相似地，元件區310內的電子元件可透過第三裝置基底300的內連線結構(如虛線360所示)而與第三導電墊340電性連接。 In this embodiment, the third device substrate 300 can be a wafer including an element region 310, and the component region 310 includes an electronic component (not shown). Similarly, the electronic components in the component region 310 can be electrically connected to the third conductive pad 340 through the interconnect structure of the third device substrate 300 (as indicated by the dashed line 360).

在本實施例中，元件區110、210及310內的電子元件可為積體/整合被動元件(Integrated passive device，IPD)、磁性元件、無線射頻(Radio Frequency，RF)元件、振盪器 (oscillator)、微機電系統、感測元件或其他適合的電子元件。 In this embodiment, the electronic components in the component regions 110, 210, and 310 can be integrated passive devices (IPDs), magnetic components, radio frequency (RF) components, and oscillators. (oscillator), MEMS, sensing components or other suitable electronic components.

在本實施例中，第二裝置基底200的尺寸大於第三裝置基底300的尺寸且小於第一裝置基底100的尺寸。再者，當第二裝置基底200的尺寸足夠大時，可在第二裝置基底200的第二表面200b上設置一個以上具有不同積體電路功能的第三裝置基底300。再者，當第一裝置基底100的尺寸足夠大時，可在第一裝置基底100上設置一個以上具有不同積體電路功能的第二裝置基底200。 In the present embodiment, the size of the second device substrate 200 is larger than the size of the third device substrate 300 and smaller than the size of the first device substrate 100. Moreover, when the size of the second device substrate 200 is sufficiently large, one or more third device substrates 300 having different integrated circuit functions can be disposed on the second surface 200b of the second device substrate 200. Moreover, when the size of the first device substrate 100 is sufficiently large, one or more second device substrates 200 having different integrated circuit functions can be disposed on the first device substrate 100.

絕緣層400覆蓋第一裝置基底100、第二裝置基底200及第三裝置基底300，且絕緣層400內具有複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130。在本實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。 The insulating layer 400 covers the first device substrate 100, the second device substrate 200, and the third device substrate 300, and the insulating layer 400 has a plurality of openings 420 therein. In the present embodiment, the opening 420 corresponds to the first bond pad 130 within the first device substrate 100. In the present embodiment, the insulating layer 400 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, acrylates, or other suitable insulating materials .

第一凸塊370設置於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370。。在本實施例中，第一凸塊370對應設置於第一裝置基底100內的第一接合墊130上，並與其電性連接。在本實施例中，第一凸塊370為接合球。在其他實施例中，第一凸塊370也可為導電柱或其他適合的導電結構。在本實施例中，第一凸塊270可包括金或其他適合的導電材料。 The first bump 370 is disposed under the bottom of the opening 420 in the insulating layer 400, and the opening 420 exposes the first bump 370. . In this embodiment, the first bumps 370 are correspondingly disposed on the first bonding pads 130 in the first device substrate 100 and electrically connected thereto. In the embodiment, the first bump 370 is a joint ball. In other embodiments, the first bump 370 can also be a conductive post or other suitable conductive structure. In this embodiment, the first bump 270 can comprise gold or other suitable electrically conductive material.

複數導電結構380設置於絕緣層400內，其分別將第二裝置基底200內的第二導電墊240及第三裝置基底300內的第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140。舉例來說，其中一個導電結構380設置於對應的第一導電墊140及第二導電墊240上，並使元件區110及210內的電子元件彼此電性連接。再者，另一個導電結構380設置於對應的第一導電墊140及第三導電墊340上，並使元件區110及310內的電子元件彼此電性連接。在本實施例中，導電結構380由設置於導電墊上的接合球(bonding ball)及延伸於接合球之間的接線(wire)所構成。再者，導電結構380可包括金或其他適合的導電材料。在一實施例中，第一凸塊370的材料相同於導電結構380的材料。 The plurality of conductive structures 380 are disposed in the insulating layer 400, and electrically connect the second conductive pads 240 in the second device substrate 200 and the third conductive pads 340 in the third device substrate 300 to the first device substrate 100, respectively. The first conductive pad 140. For example, one of the conductive structures 380 is disposed on the corresponding first conductive pad 140 and the second conductive pad 240, and the electronic components in the component regions 110 and 210 are electrically connected to each other. Furthermore, another conductive structure 380 is disposed on the corresponding first conductive pad 140 and third conductive pad 340, and the electronic components in the component regions 110 and 310 are electrically connected to each other. In the present embodiment, the conductive structure 380 is composed of a bonding ball disposed on the conductive pad and a wire extending between the bonding balls. Moreover, the electrically conductive structure 380 can comprise gold or other suitable electrically conductive material. In an embodiment, the material of the first bump 370 is the same as the material of the conductive structure 380.

圖案化的重佈線層440設置於絕緣層400上，且填入絕緣層400的開口420內，以經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，重佈線層440填滿絕緣層400的開口420。在其他實施例中，重佈線層440可順應性設置於開口420的側壁及底部，而未填滿絕緣層400的開口420。在一實施例中，重佈線層440可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。 The patterned redistribution layer 440 is disposed on the insulating layer 400 and filled into the opening 420 of the insulating layer 400 to be electrically connected to the first bump 370 located under the bottom of the opening 420 via the opening 420. In the present embodiment, the redistribution layer 440 fills the opening 420 of the insulating layer 400. In other embodiments, the redistribution layer 440 is compliantly disposed on the sidewalls and bottom of the opening 420 without filling the opening 420 of the insulating layer 400. In an embodiment, the redistribution layer 440 can comprise copper, aluminum, gold, platinum, nickel, tin, combinations of the foregoing, or other suitable electrically conductive materials.

一鈍化保護(passivation)層460設置於重佈線層440及絕緣層400上，且具有複數開口480，暴露出位於絕緣層400上的重佈線層440的一部分。在本實施例中，鈍化保護層460可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子 材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他適合的絕緣材料。 A passivation layer 460 is disposed over the redistribution layer 440 and the insulating layer 400 and has a plurality of openings 480 exposing a portion of the redistribution layer 440 on the insulating layer 400. In this embodiment, the passivation protective layer 460 may include an epoxy resin, a powder mask, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), and organic high. molecule Materials (eg, polyimine resins, benzocyclobutenes, parylenes, naphthalene polymers, fluorocarbons, acrylates), photoresist materials, or other suitable insulating materials.

複數第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層440，而與重佈線層440電性連接。在本實施例中，第二凸塊500可排列為一矩陣(未繪示)，以利於後續能提供穩固的接合。可以理解的是，導電結構380、第一凸塊370及第二凸塊500的位置係取決於設計需求而不限定於此。 The plurality of second bumps 500 are correspondingly disposed in the opening 480 of the passivation protective layer 460 to directly contact the exposed redistribution layer 440 to be electrically connected to the redistribution layer 440. In this embodiment, the second bumps 500 can be arranged in a matrix (not shown) to facilitate subsequent solid bonding. It can be understood that the positions of the conductive structure 380, the first bumps 370, and the second bumps 500 are not limited thereto depending on design requirements.

在本實施例中，第二凸塊500可為凸塊(例如，接合球或導電柱)或其他適合的導電結構，且可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。舉例來說，第二凸塊500可為焊球(solder ball)。在一實施例中，第一凸塊370及第二凸塊500皆為接合球，且第二凸塊500的尺寸大於第一凸塊370的尺寸。在一實施例中，第二凸塊500的材料不同於第一凸塊370的材料。 In this embodiment, the second bump 500 may be a bump (for example, a bonding ball or a conductive pillar) or other suitable conductive structure, and may include tin, lead, copper, gold, nickel, a combination of the foregoing, or other suitable Conductive material. For example, the second bump 500 can be a solder ball. In one embodiment, the first bumps 370 and the second bumps 500 are both bonding balls, and the second bumps 500 are larger in size than the first bumps 370. In an embodiment, the material of the second bump 500 is different from the material of the first bump 370.

請參照第2及3圖，其繪示出根據本發明不同實施例之晶片封裝體的剖面示意圖，其中相同於前述第1E圖的實施例的部件係使用相同的標號並省略其說明。第2圖中的晶片封裝體之結構類似於第1E圖中的晶片封裝體之結構，差異在於第2圖中的第一裝置基底100內不具有第1E圖中的第一接合墊130，而第二裝置基底200內具有兩個第二接合墊230及兩個第二導電墊240，其可分別透過第二裝置基底200內的內連線結構(如虛線250及260所示)而與元件區210內的電子元件電性連接，且第二接合墊230的結構類似於第一接合墊130的結構。再 者，第2圖中的兩個第一凸塊370對應設置於第二裝置基底200內的兩個第二接合墊230上，並與其電性連接。 Referring to FIGS. 2 and 3, there are shown schematic cross-sectional views of a chip package according to various embodiments of the present invention, wherein components that are the same as those of the embodiment of FIG. 1E are given the same reference numerals and the description thereof is omitted. The structure of the chip package in FIG. 2 is similar to the structure of the chip package in FIG. 1E, with the difference that the first device substrate 100 in FIG. 2 does not have the first bonding pad 130 in FIG. The second device substrate 200 has two second bonding pads 230 and two second conductive pads 240 respectively permeable to the interconnect structures (shown by dashed lines 250 and 260) in the second device substrate 200 and the components. The electronic components within the region 210 are electrically connected, and the structure of the second bonding pad 230 is similar to that of the first bonding pad 130. again The two first bumps 370 in FIG. 2 are correspondingly disposed on the second bonding pads 230 in the second device substrate 200 and electrically connected thereto.

第2圖中的第三裝置基底300內具有兩個第三導電墊340透過第三裝置基底300的內連線結構(如虛線360所示)而與元件區310內的電子元件電性連接。再者，絕緣層400內包括三個導電結構380，其分別將第一裝置基底100內的兩個第一導電墊140、第二裝置基底200內的兩個第二導電墊240及第三裝置基底300內的兩個第三導電墊340的其中兩者彼此電性連接。 The third device substrate 300 in FIG. 2 has two third conductive pads 340 electrically connected to the electronic components in the component region 310 through the interconnect structure of the third device substrate 300 (shown by the dashed line 360). Furthermore, the insulating layer 400 includes three conductive structures 380 for respectively disposing two first conductive pads 140 in the first device substrate 100, two second conductive pads 240 in the second device substrate 200, and a third device. Two of the two third conductive pads 340 within the substrate 300 are electrically connected to each other.

再者，第3圖中的晶片封裝體之結構類似於第2圖中的晶片封裝體之結構，差異在於第3圖中的第一裝置基底100內具有一個第一接合墊130，且一個第一凸塊370設置於第一裝置基底100內的第一接合墊130上並與其電性連接，而另一個第一凸塊370設置於第二裝置基底200內的第二接合墊230上並與其電性連接。可以理解的是，上述實施例中接合墊、導電墊及導電結構的位置及數量僅為範例說明，本發明並未侷限於此。 Furthermore, the structure of the chip package in FIG. 3 is similar to the structure of the chip package in FIG. 2, with the difference that the first device substrate 100 in FIG. 3 has a first bonding pad 130, and one A bump 370 is disposed on and electrically connected to the first bonding pad 130 in the first device substrate 100, and the other first bump 370 is disposed on the second bonding pad 230 in the second device substrate 200 and Electrical connection. It can be understood that the positions and numbers of the bonding pads, the conductive pads and the conductive structures in the above embodiments are merely illustrative, and the present invention is not limited thereto.

根據本發明的上述實施例，可將多個不同尺寸的裝置基底/晶片彼此垂直堆疊而將其整合於同一晶片封裝體內，使得單一晶片封裝體具有多種積體電路功能，因此可縮小後續接合的電路板的尺寸，進而能夠進一步縮小電子產品的尺寸。 According to the above embodiments of the present invention, a plurality of device substrates/wafers of different sizes can be vertically stacked on each other to be integrated into the same chip package, so that the single chip package has a plurality of integrated circuit functions, thereby reducing the subsequent bonding. The size of the board can further reduce the size of the electronic product.

以下配合第1A至1E圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。 Hereinafter, a method of manufacturing a chip package according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1E, wherein FIGS. 1A to 1E are schematic cross-sectional views showing a method of manufacturing a chip package according to an embodiment of the present invention.

請參照第1A圖，提供一第一裝置基底100。第一裝 置基底100包括複數晶片區。在一實施例中，第一裝置基底100可為一矽基底或其他半導體基底。舉例來說，第一裝置基底100可為一矽晶圓，以利於進行晶圓級封裝製程。 Referring to FIG. 1A, a first device substrate 100 is provided. First install The substrate 100 includes a plurality of wafer regions. In an embodiment, the first device substrate 100 can be a germanium substrate or other semiconductor substrate. For example, the first device substrate 100 can be a single wafer to facilitate a wafer level packaging process.

在本實施例中，第一裝置基底100的每一晶片區內具有一個或一個以上的第一接合墊及第一導電墊，其可鄰近於第一裝置基底100的上表面。為簡化圖式，此處僅繪示出第一裝置基底100的單一晶片區120以及位於其中的兩個第一接合墊130及兩個第一導電墊140。在一實施例中，第一接合墊130及第一導電墊140可為單層導電層或具有多層之導電層結構。此處，僅以單層導電層作為範例說明。 In the present embodiment, each of the wafer regions of the first device substrate 100 has one or more first bonding pads and first conductive pads that are adjacent to the upper surface of the first device substrate 100. To simplify the drawing, only a single wafer region 120 of the first device substrate 100 and two first bonding pads 130 and two first conductive pads 140 are shown therein. In an embodiment, the first bonding pad 130 and the first conductive pad 140 may be a single conductive layer or a conductive layer structure having multiple layers. Here, only a single conductive layer is exemplified.

在本實施例中，每一晶片區120的第一裝置基底100內包括一元件區110，且元件區110內可包括一電子元件(未繪示)。在一實施例中，元件區110內的電子元件可透過第一裝置基底100內的內連線結構而與第一接合墊130及第一導電墊140電性連接。為簡化圖式，此處僅以虛線150及160分別表示第一接合墊130及第一導電墊140與元件區110之間的內連線結構。 In the present embodiment, the first device substrate 100 of each of the wafer regions 120 includes an element region 110, and the component region 110 may include an electronic component (not shown). In one embodiment, the electronic components in the component region 110 are electrically connected to the first bonding pad 130 and the first conductive pad 140 through an interconnect structure in the first device substrate 100. To simplify the drawing, only the dashed lines 150 and 160 represent the interconnect structure between the first bonding pad 130 and the first conductive pad 140 and the element region 110, respectively.

接著，在每一晶片區120內的第一裝置基底100上提供一第二裝置基底200及一第三裝置基底300。舉例來說，可透過黏著層(未繪示)分別將第二裝置基底200的一第一表面200a貼附於第一裝置基底100的上表面上，且將第三裝置基底300貼附於第二裝置基底200相對於第一表面200a的一第二表面200b上。 Next, a second device substrate 200 and a third device substrate 300 are provided on the first device substrate 100 in each of the wafer regions 120. For example, a first surface 200a of the second device substrate 200 may be attached to the upper surface of the first device substrate 100 through an adhesive layer (not shown), and the third device substrate 300 may be attached to the first device substrate 300. The second device substrate 200 is on a second surface 200b of the first surface 200a.

在一實施例中，第二裝置基底200可為一矽基底或 其他半導體基底。在本實施例中，第二裝置基底200內包括一個或一個以上的第二導電墊240，其可鄰近於第二表面200b。再者，第二導電墊240的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第二裝置基底200內由單層導電層所構成的一個第二導電墊240作為範例說明。 In an embodiment, the second device substrate 200 can be a substrate or Other semiconductor substrates. In the present embodiment, the second device substrate 200 includes one or more second conductive pads 240 that are adjacent to the second surface 200b. Moreover, the structure of the second conductive pad 240 is similar to the structure of the first conductive pad 140. To simplify the drawing, only one second conductive pad 240 composed of a single conductive layer in the second device substrate 200 is illustrated here as an example.

在本實施例中，第二裝置基底200內包括一元件區210，且元件區210內可包括一電子元件(未繪示)。相似地，元件區210內的電子元件可透過第二裝置基底200的內連線結構(如虛線260所示)而與第二導電墊240電性連接。 In the embodiment, the second device substrate 200 includes an element region 210, and the component region 210 may include an electronic component (not shown). Similarly, the electronic components in the component region 210 can be electrically connected to the second conductive pad 240 through the interconnect structure of the second device substrate 200 (as indicated by the dashed line 260).

在其他實施例中，如第2及3圖所示，第二裝置基底200內可更包括一個或一個以上的第二接合墊230，其可透過第二裝置基底200內的內連線結構(如虛線250所示)而與元件區210內的電子元件電性連接。 In other embodiments, as shown in FIGS. 2 and 3, the second device substrate 200 may further include one or more second bonding pads 230 that are transparent to the interconnect structure in the second device substrate 200 ( As shown by the dashed line 250, it is electrically connected to the electronic components in the component region 210.

在一實施例中，第三裝置基底300可為一矽基底或其他半導體基底。在本實施例中，第三裝置基底300內包括一個或一個以上的第三導電墊340，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。再者，第三導電墊340的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第三裝置基底300內由單層導電層所構成的一個第三導電墊340作為範例說明。 In an embodiment, the third device substrate 300 can be a germanium substrate or other semiconductor substrate. In the present embodiment, the third device substrate 300 includes one or more third conductive pads 340 that are adjacent to the upper surface of the third device substrate 300 (ie, relative to the surface of the second surface 100b). Moreover, the structure of the third conductive pad 340 is similar to the structure of the first conductive pad 140. To simplify the drawing, only one third conductive pad 340 composed of a single conductive layer in the third device substrate 300 is illustrated here as an example.

在本實施例中，第三裝置基底300內包括一元件區310，且元件區310內可包括一電子元件(未繪示)。相似地，元件區310內的電子元件可透過第三裝置基底300的內連線結構(如虛線360所示)而與第三導電墊340電性連接。 In the embodiment, the third device substrate 300 includes an element region 310, and the component region 310 can include an electronic component (not shown). Similarly, the electronic components in the component region 310 can be electrically connected to the third conductive pad 340 through the interconnect structure of the third device substrate 300 (as indicated by the dashed line 360).

在本實施例中，元件區110、210及310內的電子元件可為積體/整合被動元件、磁性元件、無線射頻元件、振盪器、微機電系統、感測元件或其他適合的電子元件。 In this embodiment, the electronic components within component regions 110, 210, and 310 can be integrated/integrated passive components, magnetic components, wireless radio frequency components, oscillators, microelectromechanical systems, sensing components, or other suitable electronic components.

在本實施例中，第二裝置基底200的尺寸大於第三裝置基底300的尺寸且小於第一裝置基底100的尺寸。再者，當第二裝置基底200的尺寸足夠大時，可在第二裝置基底200的第二表面200b上形成一個以上具有不同積體電路功能的第三裝置基底300。再者，當第一裝置基底100的尺寸足夠大時，可在第一裝置基底100上形成一個以上具有不同積體電路功能的第二裝置基底200。 In the present embodiment, the size of the second device substrate 200 is larger than the size of the third device substrate 300 and smaller than the size of the first device substrate 100. Moreover, when the size of the second device substrate 200 is sufficiently large, more than one third device substrate 300 having a different integrated circuit function can be formed on the second surface 200b of the second device substrate 200. Moreover, when the size of the first device substrate 100 is sufficiently large, more than one second device substrate 200 having different integrated circuit functions can be formed on the first device substrate 100.

請參照第1B圖，可透過打線接合(Wire Bonding)製程，將複數第一凸塊370形成於第一裝置基底100內對應的第一接合墊130上，並與其電性連接，且形成複數導電結構380，以分別將第二裝置基底200內的第二導電墊240及第三裝置基底300內的第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140。舉例來說，其中一個導電結構380設置於對應的第一導電墊140及第二導電墊240上，並使元件區110及210內的電子元件彼此電性連接。再者，另一個導電結構380設置於對應的第一導電墊140及第三導電墊340上，並使元件區110及310內的電子元件彼此電性連接。在一實施例中，可透過同一打線接合製程，形成第一凸塊370及導電結構380。在其他實施例中，可透過個別的打線接合製程，分別形成第一凸塊370及導電結構380。 Referring to FIG. 1B, a plurality of first bumps 370 can be formed on the corresponding first bonding pads 130 in the first device substrate 100 through a wire bonding process, and electrically connected thereto, and a plurality of conductive layers are formed. The structure 380 is electrically connected to the second conductive pad 240 in the second device substrate 200 and the third conductive pad 340 in the third device substrate 300 to the corresponding first conductive pads 140 in the first device substrate 100, respectively. For example, one of the conductive structures 380 is disposed on the corresponding first conductive pad 140 and the second conductive pad 240, and the electronic components in the component regions 110 and 210 are electrically connected to each other. Furthermore, another conductive structure 380 is disposed on the corresponding first conductive pad 140 and third conductive pad 340, and the electronic components in the component regions 110 and 310 are electrically connected to each other. In one embodiment, the first bump 370 and the conductive structure 380 can be formed through the same wire bonding process. In other embodiments, the first bumps 370 and the conductive structures 380 may be formed through separate wire bonding processes.

在另一實施例中，如第2圖所示，兩個第一凸塊370 可皆形成於第二裝置基底200內對應的第二接合墊230上，並與其電性連接。又另一實施例中，如第3圖所示，可將一個第一凸塊370形成於第一裝置基底100內的第一接合墊130上並與其電性連接，而將另一個第一凸塊370形成於第二裝置基底200內的第二接合墊230上並與其電性連接。 In another embodiment, as shown in FIG. 2, two first bumps 370 The second bonding pads 230 may be formed on the second bonding pad 230 of the second device substrate 200 and electrically connected thereto. In still another embodiment, as shown in FIG. 3, a first bump 370 may be formed on the first bonding pad 130 in the first device substrate 100 and electrically connected thereto, and the other first bump may be formed. Block 370 is formed on and electrically coupled to second bond pad 230 within second device substrate 200.

在第2及3圖的實施例中，第三裝置基底300內包括兩個第三導電墊340，且可在第一裝置基底100上形成三個導電結構380，以分別將第一裝置基底100內的兩個第一導電墊140、第二裝置基底200內的兩個第二導電墊240及第三裝置基底300內的兩個第三導電墊340的其中兩者彼此電性連接。舉例來說，兩個導電結構380分別將第三裝置基底300內的兩個第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140及第二裝置基底200內對應的第二導電墊240，而另一個導電結構380則將第一裝置基底100內的另一個第一導電墊140對應地電性連接至第二裝置基底200內的另一個第二導電墊240。在其他實施例中，可取決於設計需求而選擇性形成導電結構380，本發明並不限定於此。 In the embodiments of FIGS. 2 and 3, the third device substrate 300 includes two third conductive pads 340, and three conductive structures 380 may be formed on the first device substrate 100 to respectively respectively respectively set the first device substrate 100. The two first conductive pads 140, the two second conductive pads 240 in the second device substrate 200, and the two third conductive pads 340 in the third device substrate 300 are electrically connected to each other. For example, the two conductive structures 380 electrically connect the two third conductive pads 340 in the third device substrate 300 to the corresponding first conductive pads 140 and the second device substrate 200 in the first device substrate 100, respectively. The second conductive pad 240, and the other conductive structure 380 electrically connects the other first conductive pad 140 in the first device substrate 100 to the other second conductive pad 240 in the second device substrate 200. In other embodiments, the electrically conductive structure 380 can be selectively formed depending on design requirements, and the invention is not limited thereto.

在本實施例中，第一凸塊370為接合球。在其他實施例中，第一凸塊370也可為導電柱或其他適合的導電結構。在本實施例中，第一凸塊370可包括金或其他適合的導電材料。 In the embodiment, the first bump 370 is a joint ball. In other embodiments, the first bump 370 can also be a conductive post or other suitable conductive structure. In this embodiment, the first bump 370 can comprise gold or other suitable electrically conductive material.

根據本發明實施例，第一凸塊370由能夠與接合墊的材料直接共晶接合的材料(例如，金)所構成，因此第一凸塊370可直接形成於接合墊上，且可採用打線接合製程而非迴焊製程來形成第一凸塊370，因此能夠簡化製程。 According to an embodiment of the invention, the first bump 370 is made of a material (for example, gold) capable of direct eutectic bonding with the material of the bonding pad, so that the first bump 370 can be directly formed on the bonding pad, and wire bonding can be employed. The process, rather than the reflow process, forms the first bumps 370, thus simplifying the process.

在本實施例中，導電結構380由設置於導電墊上的接合球及延伸於接合球之間的接線所構成。再者，導電結構380可包括金或其他適合的導電材料。在一實施例中，第一凸塊370的材料相同於導電結構380的材料。 In the present embodiment, the conductive structure 380 is composed of a bonding ball disposed on the conductive pad and a wire extending between the bonding balls. Moreover, the electrically conductive structure 380 can comprise gold or other suitable electrically conductive material. In an embodiment, the material of the first bump 370 is the same as the material of the conductive structure 380.

請參照第1C圖，可透過模塑成型(molding)製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一裝置基底100上形成一絕緣層400，以覆蓋第一裝置基底100、第二裝置基底200及第三裝置基底300，並使得導電結構380形成於絕緣層400內。在本實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。 Please refer to FIG. 1C, which can be through a molding process or a deposition process (for example, a printing process, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process) in the first device. An insulating layer 400 is formed on the substrate 100 to cover the first device substrate 100, the second device substrate 200, and the third device substrate 300, and the conductive structure 380 is formed in the insulating layer 400. In the present embodiment, the insulating layer 400 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Amine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating material.

接著，可透過雷射鑽孔(laser drilling)製程或微影及蝕刻製程(例如，乾蝕刻製程或濕蝕刻製程)，在絕緣層400內形成複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130，使得第一凸塊370形成於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370。 Next, a plurality of openings 420 may be formed in the insulating layer 400 by a laser drilling process or a lithography and etching process (eg, a dry etch process or a wet etch process). In the present embodiment, the opening 420 corresponds to the first bonding pad 130 in the first device substrate 100 such that the first bump 370 is formed under the bottom of the opening 420 in the insulating layer 400, and the opening 420 exposes the first convex Block 370.

在另一實施例中，如第2圖所示，開口420皆對應於第二裝置基底200內的第二接合墊230。又另一實施例中，如第3圖所示，開口420可分別對應於第一裝置基底100內的第一接合墊130以及第二裝置基底200內的第二接合墊230。 In another embodiment, as shown in FIG. 2, the openings 420 all correspond to the second bond pads 230 in the second device substrate 200. In still another embodiment, as shown in FIG. 3, the openings 420 may correspond to the first bond pads 130 in the first device substrate 100 and the second bond pads 230 in the second device substrate 200, respectively.

在本實施例中，第一接合墊130及第二接合墊230上的第一凸塊370可於形成開口420的製程(例如，雷射鑽孔製 程)中作為緩衝層，以避免上述製程破壞第一接合墊130及第二接合墊230，因此能夠提升晶片封裝體的可靠度或品質。再者，由於第一接合墊130及第二接合墊230上設置有第一凸塊370，因此可降低開口420的深度，進而可降低開口420的深寬比(aspect ratio，AR)而有利於製作開口420。另外，當開口420對應於第二裝置基底200內的第二接合墊230時，可更進一步降低開口420的深度。 In the embodiment, the first bumps 130 on the first bonding pads 130 and the second bonding pads 230 can be formed in the process of forming the openings 420 (for example, laser drilling) As a buffer layer, the first bonding pad 130 and the second bonding pad 230 are destroyed by the above process, so that the reliability or quality of the chip package can be improved. Moreover, since the first bumps 370 and the second bonding pads 230 are provided with the first bumps 370, the depth of the openings 420 can be reduced, and the aspect ratio (AR) of the openings 420 can be reduced to facilitate the aspect ratio (AR). An opening 420 is made. In addition, when the opening 420 corresponds to the second bonding pad 230 in the second device substrate 200, the depth of the opening 420 can be further reduced.

請參照第1D圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層400上形成圖案化的重佈線層440，且填入絕緣層400的開口420內，以經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，重佈線層440填滿絕緣層400的開口420。在其他實施例中，重佈線層440可順應性形成於開口420的側壁及底部，而未填滿絕緣層400的開口420。在一實施例中，重佈線層440可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。 Please refer to FIG. 1D, which can be processed through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless process, or other suitable process), a lithography process, and an etching process. A patterned redistribution layer 440 is formed over the insulating layer 400 and filled into the opening 420 of the insulating layer 400 to be electrically connected to the first bump 370 located below the bottom of the opening 420 via the opening 420. In the present embodiment, the redistribution layer 440 fills the opening 420 of the insulating layer 400. In other embodiments, the redistribution layer 440 is conformally formed on the sidewalls and bottom of the opening 420 without filling the opening 420 of the insulating layer 400. In an embodiment, the redistribution layer 440 can comprise copper, aluminum, gold, platinum, nickel, tin, combinations of the foregoing, or other suitable electrically conductive materials.

接著，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在重佈線層440及絕緣層400上形成一鈍化保護層460。在本實施例中，鈍化保護層460可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在 另一實施例中，鈍化保護層460可包括光阻材料，且可透過微影製程，在鈍化保護層460內形成開口480。 Next, a passivation protective layer 460 is formed on the redistribution layer 440 and the insulating layer 400 through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). In the present embodiment, the passivation protective layer 460 may include an epoxy resin, a green lacquer, an inorganic material (for example, yttrium oxide, lanthanum nitride, lanthanum oxynitride, metal oxide or a combination thereof), an organic polymer material (for example) , polyimine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating materials. in In another embodiment, the passivation protection layer 460 can include a photoresist material and can form an opening 480 in the passivation protection layer 460 through a lithography process.

請參照第1E圖，可透過微影製程及蝕刻製程，在每一晶片區120的鈍化保護層460內形成複數開口480，以暴露出位於絕緣層400上的重佈線層440的一部分。接著，將第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層440，而與重佈線層440電性連接。在本實施例中，第二凸塊500可排列為一矩陣(未繪示)，以利於後續能提供穩固的接合。可以理解的是，導電結構380、第一凸塊370及第二凸塊500的位置係取決於設計需求而不限定於此。 Referring to FIG. 1E, a plurality of openings 480 are formed in the passivation protection layer 460 of each of the wafer regions 120 to expose a portion of the redistribution layer 440 on the insulating layer 400 through a lithography process and an etching process. Next, the second bump 500 is correspondingly disposed in the opening 480 of the passivation protective layer 460 to directly contact the exposed redistribution layer 440 to be electrically connected to the redistribution layer 440. In this embodiment, the second bumps 500 can be arranged in a matrix (not shown) to facilitate subsequent solid bonding. It can be understood that the positions of the conductive structure 380, the first bumps 370, and the second bumps 500 are not limited thereto depending on design requirements.

在本實施例中，第二凸塊500可為凸塊(例如，接合球或導電柱)或其他適合的導電結構。舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在鈍化保護層460的開口480內形成焊料，且進行迴焊製程而形成焊球，以作為第二凸塊500。在本實施例中，第二凸塊500可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。 In this embodiment, the second bump 500 can be a bump (eg, a bonding ball or a conductive pillar) or other suitable conductive structure. For example, solder may be formed in the opening 480 of the passivation protective layer 460 through an electroplating process, a screen printing process, or other suitable process, and a solder reflow process may be performed to form a solder ball as the second bump 500. In this embodiment, the second bumps 500 may comprise tin, lead, copper, gold, nickel, combinations of the foregoing, or other suitable electrically conductive materials.

在一實施例中，第一凸塊370及第二凸塊500皆為接合球，且第二凸塊500的尺寸大於第一凸塊370的尺寸。在一實施例中，第二凸塊500的材料不同於第一凸塊370的材料。在一實施例中，第二凸塊500的形成方法不同於第一凸塊370的形成方法。舉例來說，第二凸塊500透過迴焊製程所形成，而第一凸塊370透過打線接合製程所形成。 In one embodiment, the first bumps 370 and the second bumps 500 are both bonding balls, and the second bumps 500 are larger in size than the first bumps 370. In an embodiment, the material of the second bump 500 is different from the material of the first bump 370. In an embodiment, the method of forming the second bumps 500 is different from the method of forming the first bumps 370. For example, the second bumps 500 are formed by a reflow process, and the first bumps 370 are formed by a wire bonding process.

接著，可沿著相鄰晶片區120之間的切割道(未繪示)，對第一裝置基底100及絕緣層400進行切割製程，以形成 複數獨立的晶片封裝體。在本實施例中，可進一步在獨立的晶片封裝體上提供一電路板(未繪示)，且透過第二凸塊500將第一裝置基底100、第二裝置基底200及第三裝置基底300內的元件區110、210及310內的電子元件電性連接至電路板。 Then, the first device substrate 100 and the insulating layer 400 may be subjected to a cutting process along a scribe line (not shown) between adjacent wafer regions 120 to form A plurality of independent chip packages. In this embodiment, a circuit board (not shown) may be further provided on the independent chip package, and the first device substrate 100, the second device substrate 200, and the third device substrate 300 are transmitted through the second bumps 500. The electronic components within the component regions 110, 210, and 310 are electrically connected to the circuit board.

根據本發明的上述實施例，可將多個不同尺寸的裝置基底/晶片彼此垂直堆疊，進而將其整合於同一晶片封裝體內，使得單一晶片封裝體具有多種積體電路功能，因此可縮小後續接合的電路板的尺寸。如此一來，能夠進一步縮小電子產品的尺寸。再者，由於採用接線(即，導電結構380)將裝置基底內的電子元件彼此電性連接，且透過絕緣層400的開口420內的重佈線層440及第一凸塊370作為晶片封裝體外部電性連接的路徑，而無需於裝置基底內形成矽通孔電極，因此可簡化製程且降低成本。另外，採用晶圓級製程來製作晶片封裝體，可大量生產晶片封裝體，進而降低成本並節省製程時間。 According to the above embodiments of the present invention, a plurality of device substrates/wafers of different sizes can be vertically stacked on each other and integrated into the same chip package, so that the single chip package has various integrated circuit functions, thereby reducing subsequent bonding. The size of the board. In this way, the size of the electronic product can be further reduced. Furthermore, since the electronic components in the device substrate are electrically connected to each other by wires (ie, the conductive structure 380), and the redistribution layer 440 and the first bumps 370 in the opening 420 of the transparent insulating layer 400 are external to the chip package. The path of the electrical connection eliminates the need to form a via via electrode in the device substrate, thereby simplifying the process and reducing the cost. In addition, by using a wafer-level process to fabricate a chip package, the chip package can be mass-produced, thereby reducing cost and saving process time.

以下配合第4A至4F圖說明本發明另一實施例之晶片封裝體的製造方法，其中第4A至4F圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖，且第4A至4F圖中相同於前述第1A至1E圖的實施例的部件係使用相同的標號並省略其說明。 A method for fabricating a chip package according to another embodiment of the present invention is described below with reference to FIGS. 4A to 4F, wherein FIGS. 4A to 4F are schematic cross-sectional views showing a method of fabricating a chip package according to another embodiment of the present invention. The components in the drawings in the same manner as in the above-mentioned first embodiment 1A to 1E are denoted by the same reference numerals and the description thereof will be omitted.

請參照第4A圖，提供垂直堆疊的一第一裝置基底100及一第二裝置基底200。在本實施例中，第二裝置基底200的第一表面200a接合於第一裝置基底100的上表面。在一實施例中，每一晶片區120內的第一裝置基底100與第二裝置基底200之間可具有一接合環(bonding ring，未繪示)以及位於接合 環中的內連線結構(未繪示)，而第一裝置基底100的元件區110與第二裝置基底200的元件區210可透過接合環中的內連線結構彼此電性連接。在一實施例中，第一裝置基底100的元件區110內可包括特定應用積體電路元件(Application-specific integrated circuit，ASIC)或其他適合的電子元件。再者，第二裝置基底200的元件區210內可包括微機電系統(Micro Electro Mechanical System，MEMS)或其他適合的電子元件。 Referring to FIG. 4A, a first device substrate 100 and a second device substrate 200 are vertically stacked. In the present embodiment, the first surface 200a of the second device substrate 200 is bonded to the upper surface of the first device substrate 100. In an embodiment, a bonding ring (not shown) and a bonding device may be disposed between the first device substrate 100 and the second device substrate 200 in each of the wafer regions 120. The interconnect structure (not shown) in the ring, and the component region 110 of the first device substrate 100 and the component region 210 of the second device substrate 200 are electrically connected to each other through an interconnect structure in the bonding ring. In an embodiment, the component area 110 of the first device substrate 100 may include an application-specific integrated circuit (ASIC) or other suitable electronic component. Furthermore, the component area 210 of the second device substrate 200 may include a Micro Electro Mechanical System (MEMS) or other suitable electronic component.

請參照第4B圖，對第二裝置基底200進行切割製程，並暴露出第一裝置基底100內的第一接合墊130。舉例來說，第一裝置基底100及第二裝置基底200皆為半導體晶圓，且第二裝置基底200的晶片區對應於第一裝置基底100的晶片區120。沿著第二裝置基底200的晶片區之間的切割道(未繪示)進行切割製程，去除第二裝置基底200遮蔽第一接合墊130的部分，以暴露出下方的第一接合墊130，且使得第二裝置基底200分離成對應於晶片區120的複數晶片。在一實施例中，分離的晶片仍覆蓋第一裝置基底100與第二裝置基底200之間的接合環(未繪示)。 Referring to FIG. 4B, the second device substrate 200 is subjected to a dicing process, and the first bonding pads 130 in the first device substrate 100 are exposed. For example, the first device substrate 100 and the second device substrate 200 are both semiconductor wafers, and the wafer region of the second device substrate 200 corresponds to the wafer region 120 of the first device substrate 100. Cutting a process along a scribe line (not shown) between the wafer areas of the second device substrate 200 to remove a portion of the second device substrate 200 that shields the first bonding pads 130 to expose the underlying first bonding pads 130, And the second device substrate 200 is separated into a plurality of wafers corresponding to the wafer region 120. In an embodiment, the separated wafer still covers the bond ring (not shown) between the first device substrate 100 and the second device substrate 200.

在其他實施例中，可先將第二裝置基底200分離成複數晶片，再將其分別接合於對應的晶片區120內的第一裝置基底100上。 In other embodiments, the second device substrate 200 can be first separated into a plurality of wafers and then bonded to the first device substrate 100 in the corresponding wafer region 120, respectively.

接著，在每一晶片區120內的第二裝置基底200上提供一第三裝置基底300。舉例來說，可透過黏著層(未繪示)將第三裝置基底300貼附於第二裝置基底200相對於第一表面200a的第二表面200b上。在本實施例中，第三裝置基底300內 包括一個或一個以上的第三接合墊330，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。相似地，第三接合墊330可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，且僅繪示出第三裝置基底300內的四個第三接合墊330作為範例說明。在本實施例中，第三裝置基底300的元件區310內的電子元件(未繪示)可透過第三裝置基底300內的內連線結構(如虛線350所示)而與第三接合墊330電性連接。 Next, a third device substrate 300 is provided on the second device substrate 200 within each wafer region 120. For example, the third device substrate 300 can be attached to the second device substrate 200 relative to the second surface 200b of the first surface 200a through an adhesive layer (not shown). In the embodiment, the third device substrate 300 is inside. One or more third bond pads 330 are included that may be adjacent to the upper surface of the third device substrate 300 (ie, relative to the surface of the second surface 100b). Similarly, the third bonding pad 330 may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only four third bonding pads 330 in the third device substrate 300 are illustrated as an example. In this embodiment, the electronic components (not shown) in the component region 310 of the third device substrate 300 can pass through the interconnect structure (shown by the dashed line 350) in the third device substrate 300 and the third bonding pad. 330 electrical connection.

請參照第4C圖，可透過打線接合製程，將複數第一凸塊370形成於第一裝置基底100內對應的第一接合墊130上，並與其電性連接。再者，可透過打線接合製程，將複數第三凸塊510a及第四凸塊510b形成於第三裝置基底300內對應的第三接合墊330上，並與其電性連接。在本實施例中，第三凸塊510a及第四凸塊510b為接合球。在其他實施例中，第三凸塊510a及第四凸塊510b也可為導電柱或其他適合的導電結構。在本實施例中，第三凸塊510a及第四凸塊510b可包括金或其他適合的導電材料。再者，第三凸塊510a及第四凸塊510b的材料相同於第一凸塊370的材料。 Referring to FIG. 4C, a plurality of first bumps 370 are formed on the first bonding pads 130 in the first device substrate 100 and electrically connected thereto through a wire bonding process. Moreover, the plurality of third bumps 510a and 510b are formed on the third bonding pads 330 of the third device substrate 300 through the wire bonding process, and are electrically connected thereto. In this embodiment, the third bump 510a and the fourth bump 510b are joint balls. In other embodiments, the third bump 510a and the fourth bump 510b may also be conductive pillars or other suitable conductive structures. In this embodiment, the third bump 510a and the fourth bump 510b may comprise gold or other suitable conductive material. Moreover, the materials of the third bump 510a and the fourth bump 510b are the same as the material of the first bump 370.

接著，可透過模塑成型製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一裝置基底100上形成一絕緣層400，以覆蓋第一裝置基底100、第二裝置基底200、第三裝置基底300、第一凸塊370、第三凸塊510a及第四凸塊510b。 Then, an insulating layer can be formed on the first device substrate 100 through a molding process or a deposition process (for example, a printing process, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). 400 to cover the first device substrate 100, the second device substrate 200, the third device substrate 300, the first bump 370, the third bump 510a, and the fourth bump 510b.

請參照第4D圖，對絕緣層400進行機械研磨 (mechanical grinding)製程或化學機械研磨(chemical mechanical polishing)製程，以減少絕緣層400的厚度，並暴露出第三凸塊510a及第四凸塊510b。在本實施例中，上述研磨製程將第三凸塊510a及第四凸塊510b的頂部局部去除，使得第三凸塊510a及第四凸塊510b具有平坦的上表面，且第三凸塊510a及第四凸塊510b的尺寸小於第一凸塊370的尺寸。 Please refer to FIG. 4D for mechanical grinding of the insulating layer 400. A mechanical grinding process or a chemical mechanical polishing process is performed to reduce the thickness of the insulating layer 400 and expose the third bumps 510a and the fourth bumps 510b. In this embodiment, the polishing process partially removes the tops of the third bump 510a and the fourth bump 510b, so that the third bump 510a and the fourth bump 510b have a flat upper surface, and the third bump 510a And the size of the fourth bump 510b is smaller than the size of the first bump 370.

接著，可透過雷射鑽孔製程或微影及蝕刻製程，在絕緣層400內形成複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130，使得第一凸塊370形成於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370的一部份。 Next, a plurality of openings 420 are formed in the insulating layer 400 by a laser drilling process or a lithography and etching process. In the present embodiment, the opening 420 corresponds to the first bonding pad 130 in the first device substrate 100 such that the first bump 370 is formed under the bottom of the opening 420 in the insulating layer 400, and the opening 420 exposes the first convex A portion of block 370.

在本實施例中，上述研磨製程減少了絕緣層400的厚度，使得開口420的深度降低，進而降低了開口420的深寬比，因此有利於製作開口420。 In the present embodiment, the above-described polishing process reduces the thickness of the insulating layer 400, so that the depth of the opening 420 is lowered, thereby reducing the aspect ratio of the opening 420, thereby facilitating the fabrication of the opening 420.

請參照第4E圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層400上形成圖案化的重佈線層440，且填入絕緣層400的開口420內，進而經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，絕緣層400上的重佈線層440延伸至覆蓋至少一部分的第三凸塊510a，並與其電性連接。 Please refer to FIG. 4E, which can be processed through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless process, or other suitable process), a lithography process, and an etching process. A patterned redistribution layer 440 is formed on the insulating layer 400 and filled in the opening 420 of the insulating layer 400, and is electrically connected to the first bump 370 located under the bottom of the opening 420 via the opening 420. In the present embodiment, the redistribution layer 440 on the insulating layer 400 extends to and is electrically connected to at least a portion of the third bumps 510a.

接著，可透過模塑成型製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在絕緣層400上形成另一絕緣層520，以覆 蓋重佈線層440、第三凸塊510a及第四凸塊510b。在本實施例中，絕緣層520可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在一實施例中，絕緣層520的材料不同於絕緣層400的材料，使得絕緣層400與絕緣層520之間具有一可見界面I。在其他實施例中，絕緣層520的材料可相同於絕緣層400的材料。 Next, another insulating layer 520 may be formed on the insulating layer 400 through a molding process or a deposition process (eg, a printing process, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). To cover The wiring layer 440, the third bump 510a, and the fourth bump 510b are covered. In the present embodiment, the insulating layer 520 may include an epoxy resin, an inorganic material (for example, cerium oxide, cerium nitride, cerium oxynitride, metal oxide or a combination thereof), an organic polymer material (for example, poly phthalate) Amine resin, benzocyclobutene, parylene, naphthalene polymer, fluorocarbon, acrylate) or other suitable insulating material. In an embodiment, the material of the insulating layer 520 is different from the material of the insulating layer 400 such that the insulating layer 400 and the insulating layer 520 have a visible interface I. In other embodiments, the material of the insulating layer 520 may be the same as the material of the insulating layer 400.

接著，可透過雷射鑽孔製程或微影及蝕刻製程，在絕緣層520內形成複數開口540。在本實施例中，開口540對應於第三裝置基底300內未與重佈線層440電性接觸的第三接合墊330(即，開口540對應於第四凸塊510b)，使得第四凸塊510b形成於絕緣層520內的開口540的底部下方，且開口540暴露出第四凸塊510b的一部份。在本實施例中，開口540的深度小於開口420的深度。 Next, a plurality of openings 540 are formed in the insulating layer 520 by a laser drilling process or a lithography and etching process. In the present embodiment, the opening 540 corresponds to the third bonding pad 330 in the third device substrate 300 that is not in electrical contact with the redistribution layer 440 (ie, the opening 540 corresponds to the fourth bump 510b), such that the fourth bump 510b is formed below the bottom of the opening 540 in the insulating layer 520, and the opening 540 exposes a portion of the fourth bump 510b. In the present embodiment, the depth of the opening 540 is smaller than the depth of the opening 420.

在本實施例中，第四凸塊510b可於形成開口540的製程(例如，雷射鑽孔製程)中作為緩衝層，以避免上述製程破壞第三接合墊330。再者，由於第三接合墊330上設置有第四凸塊510b，因此可降低開口540的深度，進而降低開口540的深寬比。 In the present embodiment, the fourth bump 510b can serve as a buffer layer in the process of forming the opening 540 (for example, a laser drilling process) to prevent the third bonding pad 330 from being damaged by the above process. Moreover, since the fourth bump 510b is disposed on the third bonding pad 330, the depth of the opening 540 can be reduced, thereby reducing the aspect ratio of the opening 540.

請參照第4F圖，可透過沉積製程、微影製程及蝕刻製程，在絕緣層520上形成圖案化的另一重佈線層560，且填入絕緣層520的開口540內，以經由開口540電性連接至位於開口540底部下方的第四凸塊510b。在本實施例中，重佈線層560 填滿絕緣層520的開口540。在其他實施例中，重佈線層560可順應性形成於開口540的側壁及底部，而未填滿開口540。在一實施例中，重佈線層560可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。 Referring to FIG. 4F, another patterned redistribution layer 560 is formed on the insulating layer 520 through a deposition process, a lithography process, and an etching process, and is filled in the opening 540 of the insulating layer 520 to be electrically connected via the opening 540. Connected to a fourth bump 510b located below the bottom of the opening 540. In the present embodiment, the redistribution layer 560 The opening 540 of the insulating layer 520 is filled. In other embodiments, the redistribution layer 560 is conformally formed on the sidewalls and bottom of the opening 540 without filling the opening 540. In an embodiment, the redistribution layer 560 can comprise copper, aluminum, gold, platinum, nickel, tin, combinations of the foregoing, or other suitable electrically conductive materials.

可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在重佈線層560及絕緣層520上形成一鈍化保護層460，並透過微影製程及蝕刻製程，在每一晶片區120的鈍化保護層460內形成複數開口480，以暴露出位於絕緣層520上的重佈線層560的一部分。 A passivation protective layer 460 may be formed on the redistribution layer 560 and the insulating layer 520 through a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process), and may pass through the lithography. The process and etch process forms a plurality of openings 480 in the passivation protection layer 460 of each wafer region 120 to expose a portion of the redistribution layer 560 on the insulating layer 520.

接著，將第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層560，且與其電性連接。在一實施例中，第二凸塊500、第三凸塊510a及第四凸塊510b皆為接合球，且第二凸塊500的尺寸大於第三凸塊510a及第四凸塊510b的尺寸。在一實施例中，第二凸塊500的材料不同於第三凸塊510a及第四凸塊510b的材料。在一實施例中，第二凸塊500的形成方法不同於第三凸塊510a及第四凸塊510b的形成方法。舉例來說，第二凸塊500透過迴焊製程所形成，而第三凸塊510a及第四凸塊510b透過打線接合製程所形成。 Next, the second bump 500 is correspondingly disposed in the opening 480 of the passivation protective layer 460 to directly contact the exposed redistribution layer 560 and electrically connected thereto. In one embodiment, the second bump 500, the third bump 510a, and the fourth bump 510b are all bonding balls, and the size of the second bump 500 is larger than the size of the third bump 510a and the fourth bump 510b. . In an embodiment, the material of the second bump 500 is different from the material of the third bump 510a and the fourth bump 510b. In an embodiment, the method of forming the second bump 500 is different from the method of forming the third bump 510a and the fourth bump 510b. For example, the second bumps 500 are formed by a reflow process, and the third bumps 510a and the fourth bumps 510b are formed by a wire bonding process.

接著，可沿著相鄰晶片區120之間的切割道(未繪示)，對第一裝置基底100及絕緣層400及520進行切割製程，以形成複數獨立的晶片封裝體。 Then, the first device substrate 100 and the insulating layers 400 and 520 may be subjected to a dicing process along a scribe line (not shown) between adjacent wafer regions 120 to form a plurality of independent chip packages.

當接合於第一裝置基底上的第二或第三裝置基底的數量越多，則將裝置基底中的電子元件彼此電性連接的接線 的數量也越多，造成製造成本及時間大幅增加。再者，過多的接線形成於裝置基底上會導致後續形成的絕緣層難以順利地覆蓋裝置基底。 Wiring for electrically connecting electronic components in the device substrate to each other when the number of second or third device substrates bonded to the first device substrate is increased The greater the number, the greater the cost and time of manufacturing. Furthermore, the formation of excessive wiring on the device substrate can result in the subsequent formation of an insulating layer that is difficult to cover the device substrate smoothly.

在第4A至4F圖的實施例中，採用第一凸塊370、重佈線層440及第三凸塊510a取代接線(例如，第1E、2至3圖中的導電結構380)，能夠在同一製程中同時將所有晶片區120內的裝置基底中的電子元件彼此電性連接，因此有效降低製造成本及時間，且有利於形成絕緣層400，進而降低製程的難度且提升晶片封裝體的可靠度。 In the embodiment of FIGS. 4A to 4F, the first bump 370, the redistribution layer 440, and the third bump 510a are used instead of the wiring (for example, the conductive structure 380 in FIGS. 1E, 2 to 3), and can be in the same In the process, the electronic components in the device substrate in all the wafer regions 120 are electrically connected to each other at the same time, thereby effectively reducing the manufacturing cost and time, and facilitating the formation of the insulating layer 400, thereby reducing the difficulty of the process and improving the reliability of the chip package. .

第5至8圖係繪示出根據本發明其他實施例之晶片封裝體的剖面示意圖，其中相同於前述第1A至1E及4A至4F圖的實施例的部件係使用相同的標號並省略其說明。第5圖中的晶片封裝體之結構類似於第4F圖中的晶片封裝體之結構，差異在於第5圖中的第一凸塊370形成於第二裝置基底200內的第二接合墊230上，而非第一裝置基底100內的第一接合墊130上。如此一來，可降低絕緣層400的開口420的深度，進而降低開口420的深寬比。 5 to 8 are schematic cross-sectional views showing a chip package according to another embodiment of the present invention, wherein components of the embodiment similar to those of the above-mentioned 1A to 1E and 4A to 4F are given the same reference numerals and their description will be omitted. . The structure of the chip package in FIG. 5 is similar to the structure of the chip package in FIG. 4F, with the difference that the first bump 370 in FIG. 5 is formed on the second bonding pad 230 in the second device substrate 200. Instead of the first bonding pad 130 in the first device substrate 100. As a result, the depth of the opening 420 of the insulating layer 400 can be lowered, thereby reducing the aspect ratio of the opening 420.

第6圖中的晶片封裝體之結構類似於第5圖中的晶片封裝體之結構，差異在於第6圖中的第四凸塊510b形成於第一裝置基底100內的第一接合墊130上，而非第三裝置基底300內的第三接合墊330上。再者，可在絕緣層400內形成另一開口420，暴露出第四凸塊510b，且重佈線層560形成於開口420內，使得第二凸塊500經由開口420內的重佈線層560而電性連接至位於第一裝置基底100上的第四凸塊510b。如此一來，可無須 形成絕緣層520，進而簡化製程。 The structure of the chip package in FIG. 6 is similar to the structure of the chip package in FIG. 5, except that the fourth bump 510b in FIG. 6 is formed on the first bonding pad 130 in the first device substrate 100. Instead of the third bond pad 330 in the third device substrate 300. Furthermore, another opening 420 may be formed in the insulating layer 400 to expose the fourth bump 510b, and the redistribution layer 560 is formed in the opening 420 such that the second bump 500 passes through the redistribution layer 560 in the opening 420. Electrically connected to the fourth bump 510b on the first device substrate 100. In this way, it is not necessary The insulating layer 520 is formed, thereby simplifying the process.

第7圖中的晶片封裝體之結構類似於第6圖中的晶片封裝體之結構，差異在於第7圖中的第四凸塊510b形成於第二裝置基底200內的第二接合墊230上，而非第一裝置基底100內的第一接合墊130上。如此一來，可降低暴露出第四凸塊510b的開口420的深度，進而降低其深寬比。再者，還可透過同一製程，同時形成第一凸塊370及第四凸塊510b上方的開口420，且亦可透過同一製程，同時形成重佈線層440及560，因此能夠進一步簡化製程。 The structure of the chip package in FIG. 7 is similar to the structure of the chip package in FIG. 6, except that the fourth bump 510b in FIG. 7 is formed on the second bonding pad 230 in the second device substrate 200. Instead of the first bonding pad 130 in the first device substrate 100. In this way, the depth of the opening 420 exposing the fourth bump 510b can be reduced, thereby reducing the aspect ratio. Moreover, the openings 420 above the first bumps 370 and the fourth bumps 510b can be simultaneously formed through the same process, and the redistribution layers 440 and 560 can be formed simultaneously through the same process, thereby further simplifying the process.

然而在其他實施例中，當第四凸塊510b形成於第二接合墊230上時，也可將第7圖中的第一凸塊370形成於第一裝置基底100內的第一接合墊130上。 In other embodiments, when the fourth bump 510b is formed on the second bonding pad 230, the first bump 370 in FIG. 7 may also be formed on the first bonding pad 130 in the first device substrate 100. on.

第8圖中的晶片封裝體之結構類似於第7圖中的晶片封裝體之結構，差異在於第8圖中的第一凸塊370及第四凸塊510b皆形成於第一裝置基底100內的第一接合墊130上，而非皆形成於第二裝置基底200內的第二接合墊230上。如此一來，同樣可透過同一製程，同時形成第一凸塊370及第四凸塊510b上方的開口420，且亦可透過同一製程，形成重佈線層440及560。 The structure of the chip package in FIG. 8 is similar to the structure of the chip package in FIG. 7 , except that the first bump 370 and the fourth bump 510 b in FIG. 8 are all formed in the first device substrate 100 . The first bonding pads 130 are formed on the second bonding pads 230 in the second device substrate 200, not all of them. In this way, the openings 420 above the first bumps 370 and the fourth bumps 510b can be formed simultaneously through the same process, and the redistribution layers 440 and 560 can also be formed through the same process.

可以理解的是，第4F及5至8圖中的第一凸塊370、第二凸塊500、第三凸塊510a及第四凸塊510b的位置係取決於設計需求而不限定於此。 It can be understood that the positions of the first bump 370, the second bump 500, the third bump 510a, and the fourth bump 510b in FIGS. 4F and 5 to 8 are not limited thereto depending on design requirements.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施 例。 While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100‧‧‧第一裝置基底 100‧‧‧First device substrate

110、210、310‧‧‧元件區 110, 210, 310‧‧‧ component area

120‧‧‧晶片區 120‧‧‧ wafer area

130‧‧‧第一接合墊 130‧‧‧First joint pad

140‧‧‧第一導電墊 140‧‧‧First conductive pad

150、160、260、360‧‧‧內連線結構 150, 160, 260, 360‧‧‧ internal connection structure

200‧‧‧第二裝置基底 200‧‧‧Second device substrate

200a‧‧‧第一表面 200a‧‧‧ first surface

200b‧‧‧第二表面 200b‧‧‧ second surface

240‧‧‧第二導電墊 240‧‧‧Second conductive pad

300‧‧‧第三裝置基底 300‧‧‧ Third device substrate

340‧‧‧第三導電墊 340‧‧‧ Third conductive pad

370‧‧‧第一凸塊 370‧‧‧First bump

380‧‧‧導電結構 380‧‧‧Electrical structure

400‧‧‧絕緣層 400‧‧‧Insulation

420‧‧‧開口 420‧‧‧ openings

440‧‧‧重佈線層 440‧‧‧Rewiring layer

460‧‧‧鈍化保護層 460‧‧‧passivation protective layer

480‧‧‧開口 480‧‧‧ openings

500‧‧‧第二凸塊 500‧‧‧second bump

Claims (34)

一種晶片封裝體，包括：一第一裝置基底，貼附於一第二裝置基底的一第一表面上；一第三裝置基底，貼附於該第二裝置基底相對於該第一表面的一第二表面上；一絕緣層，覆蓋該第一裝置基底、該第二裝置基底及該第三裝置基底，其中該絕緣層內具有至少一開口；至少一第一凸塊，設置於該至少一開口的底部下方；以及一重佈線層，設置於該絕緣層上，且經由該至少一開口電性連接至該至少一第一凸塊。 A chip package comprising: a first device substrate attached to a first surface of a second device substrate; a third device substrate attached to the second device substrate with respect to the first surface a second surface; an insulating layer covering the first device substrate, the second device substrate, and the third device substrate, wherein the insulating layer has at least one opening therein; at least one first bump is disposed on the at least one a bottom portion of the opening; and a redistribution layer disposed on the insulating layer and electrically connected to the at least one first bump via the at least one opening. 如申請專利範圍第1項所述之晶片封裝體，其中該第二裝置基底的尺寸大於該第三裝置基底的尺寸且小於該第一裝置基底的尺寸。 The chip package of claim 1, wherein the second device substrate has a size greater than a size of the third device substrate and smaller than a size of the first device substrate. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一第一凸塊設置於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊。 The chip package of claim 1, wherein the at least one first bump is disposed on the first device substrate and electrically connected to a first bonding pad in the first device substrate. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一第一凸塊設置於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。 The chip package of claim 1, wherein the at least one first bump is disposed on the second device substrate and electrically connected to a second bonding pad in the second device substrate. 如申請專利範圍第1項所述之晶片封裝體，包括複數第一凸塊，且該絕緣層內具有複數開口，其中該等第一凸塊對應設置於該等開口的底部下方，且其中該等第一凸塊的其中一者設置於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊，且該等第一凸塊的其中另一者 設置於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。 The chip package of claim 1, comprising a plurality of first bumps, wherein the insulating layer has a plurality of openings therein, wherein the first bumps are disposed under the bottom of the openings, and wherein the One of the first bumps is disposed on the first device substrate and electrically connected to a first bonding pad in the first device substrate, and the other of the first bumps And disposed on the second device substrate and electrically connected to a second bonding pad in the second device substrate. 如申請專利範圍第1項所述之晶片封裝體，更包括複數導電結構，設置於該絕緣層內，其分別將該第二裝置基底內的一第二導電墊及該第三裝置基底內的一第三導電墊電性連接至該第一裝置基底內對應的一第一導電墊。 The chip package of claim 1, further comprising a plurality of conductive structures disposed in the insulating layer, respectively, respectively, a second conductive pad in the second device substrate and the third device substrate A third conductive pad is electrically connected to a corresponding first conductive pad in the first device substrate. 如申請專利範圍第1項所述之晶片封裝體，更包括複數導電結構，設置於該絕緣層內，其分別將該第一裝置基底內的複數第一導電墊、該第二裝置基底內的複數第二導電墊及該第三裝置基底內的複數第三導電墊的其中兩者彼此電性連接。 The chip package of claim 1, further comprising a plurality of conductive structures disposed in the insulating layer, respectively, the plurality of first conductive pads in the substrate of the first device, and the substrate in the second device The plurality of second conductive pads and two of the plurality of third conductive pads in the third device substrate are electrically connected to each other. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二凸塊，設置於該絕緣層上的該重佈線層上。 The chip package of claim 1, further comprising a second bump disposed on the redistribution layer on the insulating layer. 如申請專利範圍第8項所述之晶片封裝體，其中該第二凸塊的材料不同於該至少一第一凸塊的材料。 The chip package of claim 8, wherein the material of the second bump is different from the material of the at least one first bump. 如申請專利範圍第8項所述之晶片封裝體，其中該至少一第一凸塊及該第二凸塊為接合球，且該第二凸塊的尺寸大於該至少一第一凸塊的尺寸。 The chip package of claim 8, wherein the at least one first bump and the second bump are joint balls, and the size of the second bump is larger than the size of the at least one first bump . 如申請專利範圍第1項所述之晶片封裝體，更包括一第三凸塊，設置於該第三裝置基底上，並電性連接至該第三裝置基底內的一第三接合墊，其中該絕緣層上的該重佈線層覆蓋且電性連接該第三凸塊。 The chip package of claim 1, further comprising a third bump disposed on the third device substrate and electrically connected to a third bonding pad in the third device substrate, wherein The redistribution layer on the insulating layer covers and electrically connects the third bump. 如申請專利範圍第11項所述之晶片封裝體，其中該第三凸塊為接合球，且該第三凸塊具有平坦的上表面。 The chip package of claim 11, wherein the third bump is a bonding ball, and the third bump has a flat upper surface. 如申請專利範圍第11項所述之晶片封裝體，更包括：一第四凸塊，設置於該第一裝置基底與該重佈線層之間；以及一另一重佈線層，設置於該絕緣層上，且電性連接至該第四凸塊。 The chip package of claim 11, further comprising: a fourth bump disposed between the first device substrate and the redistribution layer; and a further redistribution layer disposed on the insulating layer And electrically connected to the fourth bump. 如申請專利範圍第13項所述之晶片封裝體，更包括一第二凸塊，設置於該另一重佈線層上，其中該第二凸塊的材料不同於該第三凸塊及該第四凸塊的材料以及該至少一第一凸塊的材料。 The chip package of claim 13, further comprising a second bump disposed on the other redistribution layer, wherein the material of the second bump is different from the third bump and the fourth a material of the bump and a material of the at least one first bump. 如申請專利範圍第13項所述之晶片封裝體，更包括一第二凸塊，設置於該另一重佈線層上，其中該第二凸塊、該第三凸塊及該第四凸塊為接合球，且該第二凸塊的尺寸大於該第三凸塊及該第四凸塊的尺寸。 The chip package of claim 13 further comprising a second bump disposed on the other redistribution layer, wherein the second bump, the third bump, and the fourth bump are The ball is joined, and the size of the second bump is larger than the size of the third bump and the fourth bump. 如申請專利範圍第13項所述之晶片封裝體，其中該第四凸塊設置於該第三裝置基底上，且電性連接至該第三裝置基底內的一另一第三接合墊，且其中該晶片封裝體更包括一另一絕緣層，覆蓋該絕緣層及該重佈線層，且具有一開口，暴露出該第四凸塊，該另一重佈線層經由該另一絕緣層內的該開口電性連接至該第四凸塊。 The chip package of claim 13, wherein the fourth bump is disposed on the third device substrate and electrically connected to another third bonding pad in the third device substrate, and The chip package further includes a further insulating layer covering the insulating layer and the redistribution layer, and having an opening exposing the fourth bump, the another redistribution layer passing through the other insulating layer The opening is electrically connected to the fourth bump. 如申請專利範圍第16項所述之晶片封裝體，其中該第三凸塊及該第四凸塊為接合球，且該第三凸塊及該第四凸塊具有平坦的上表面。 The chip package of claim 16, wherein the third bump and the fourth bump are bonding balls, and the third bump and the fourth bump have a flat upper surface. 如申請專利範圍第13項所述之晶片封裝體，其中該第四凸塊電性連接至該第一裝置基底內的一第一接合墊或該第二裝置基底內的一第二接合墊，且其中該絕緣層具有複數開 口，該等開口的其中一者暴露出該第四凸塊，且該另一重佈線層經由上述該等開口的其中一者電性連接至該第四凸塊。 The chip package of claim 13, wherein the fourth bump is electrically connected to a first bonding pad in the first device substrate or a second bonding pad in the second device substrate, And wherein the insulating layer has a plurality of openings One of the openings exposing the fourth bump, and the other redistribution layer is electrically connected to the fourth bump via one of the openings. 一種晶片封裝體的製造方法，包括：將一第一裝置基底貼附於一第二裝置基底的一第一表面上；將一第三裝置基底貼附於該第二裝置基底相對於該第一表面的一第二表面上；形成至少一第一凸塊及一絕緣層，其中該絕緣層覆蓋該第一裝置基底、該第二裝置基底及該第三裝置基底，且具有至少一開口，使該至少一第一凸塊形成於該至少一開口的底部下方；以及在該絕緣層上形成一重佈線層，其經由該至少一開口電性連接至該至少一第一凸塊。 A method of fabricating a chip package, comprising: attaching a first device substrate to a first surface of a second device substrate; attaching a third device substrate to the second device substrate relative to the first Forming at least one first bump and an insulating layer, wherein the insulating layer covers the first device substrate, the second device substrate, and the third device substrate, and has at least one opening The at least one first bump is formed under the bottom of the at least one opening; and a redistribution layer is formed on the insulating layer, and the at least one first bump is electrically connected to the at least one opening. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該第二裝置基底的尺寸大於該第三裝置基底的尺寸且小於該第一裝置基底的尺寸。 The method of manufacturing a chip package according to claim 19, wherein the second device substrate has a size larger than a size of the third device substrate and smaller than a size of the first device substrate. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該至少一第一凸塊位於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊。 The method of manufacturing a chip package according to claim 19, wherein the at least one first bump is located on the first device substrate and electrically connected to a first bonding pad in the first device substrate. . 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該至少一第一凸塊位於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。 The method of manufacturing a chip package according to claim 19, wherein the at least one first bump is located on the second device substrate and electrically connected to a second bonding pad in the second device substrate. . 如申請專利範圍第19項所述之晶片封裝體的製造方法，包 括形成複數第一凸塊，且該絕緣層內具有複數開口，使該等第一凸塊對應設置於該等開口的底部下方，其中該等第一凸塊的其中一者位於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊，且該等第一凸塊的其中另一者位於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。 A method of manufacturing a chip package as described in claim 19, comprising Forming a plurality of first bumps, and having a plurality of openings in the insulating layer, such that the first bumps are correspondingly disposed under the bottom of the openings, wherein one of the first bumps is located in the first device a first bonding pad on the substrate and electrically connected to the first device substrate, and the other of the first bumps is located on the second device substrate and electrically connected to the second device a second bond pad within the substrate. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該絕緣層內形成複數導電結構，以分別將該第二裝置基底內的一第二導電墊及該第三裝置基底內的一第三導電墊電性連接至該第一裝置基底內對應的一第一導電墊。 The method for fabricating a chip package according to claim 19, further comprising forming a plurality of conductive structures in the insulating layer to respectively respectively form a second conductive pad and the third device substrate in the second device substrate A third conductive pad is electrically connected to a corresponding first conductive pad in the first device substrate. 如申請專利範圍第19項所述之晶片封裝體的製造方法，在該絕緣層內形成複數導電結構，以分別將該第一裝置基底內的複數第一導電墊、該第二裝置基底內的複數第二導電墊及該第三裝置基底內的複數第三導電墊的其中兩者彼此電性連接。 The method of manufacturing a chip package according to claim 19, wherein a plurality of conductive structures are formed in the insulating layer to respectively form a plurality of first conductive pads in the substrate of the first device and in the substrate of the second device The plurality of second conductive pads and two of the plurality of third conductive pads in the third device substrate are electrically connected to each other. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該絕緣層上的該重佈線層上形成一第二凸塊。 The method of manufacturing a chip package according to claim 19, further comprising forming a second bump on the redistribution layer on the insulating layer. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該第二凸塊的材料不同於該至少一第一凸塊的材料。 The method of manufacturing a chip package according to claim 26, wherein the material of the second bump is different from the material of the at least one first bump. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該至少一第一凸塊及該第二凸塊為接合球，且該第二凸塊的尺寸大於該至少一第一凸塊的尺寸。 The method of manufacturing a chip package according to claim 26, wherein the at least one first bump and the second bump are joint balls, and the second bump has a size larger than the at least one first convex The size of the block. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該第二凸塊的形成方法不同於該至少一第一凸塊的形成 方法。 The method of manufacturing a chip package according to claim 26, wherein the method of forming the second bump is different from the forming of the at least one first bump method. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該第三裝置基底上形成一第三凸塊，其電性連接至該第三裝置基底內的一第三接合墊，其中該絕緣層上的該重佈線層覆蓋且電性連接該第三凸塊。 The method of manufacturing a chip package according to claim 19, further comprising forming a third bump on the third device substrate electrically connected to a third bonding pad in the third device substrate. The redistribution layer on the insulating layer covers and electrically connects the third bump. 如申請專利範圍第30項所述之晶片封裝體的製造方法，更包括：在該第一裝置基底與該重佈線層之間形成一第四凸塊；以及在該絕緣層上形成一另一重佈線層，其電性連接至該第四凸塊。 The method of manufacturing a chip package according to claim 30, further comprising: forming a fourth bump between the first device substrate and the redistribution layer; and forming another weight on the insulating layer a wiring layer electrically connected to the fourth bump. 如申請專利範圍第31項所述之晶片封裝體的製造方法，更包括在該另一重佈線層上形成一第二凸塊，其中該第二凸塊的形成方法不同於該第三凸塊及該第四凸塊的形成方法。 The method of manufacturing a chip package according to claim 31, further comprising forming a second bump on the other redistribution layer, wherein the second bump is formed differently from the third bump and A method of forming the fourth bump. 如申請專利範圍第31項所述之晶片封裝體的製造方法，其中該第四凸塊位於該第三裝置基底上，且電性連接至該第三裝置基底內的一另一第三接合墊，且其中該晶片封裝體的製造方法更包括形成一另一絕緣層，以覆蓋該絕緣層及該重佈線層，該另一絕緣層具有一開口，暴露出該第四凸塊，且該另一重佈線層經由該另一絕緣層內的該開口電性連接至該第四凸塊。 The method of manufacturing a chip package according to claim 31, wherein the fourth bump is located on the third device substrate and electrically connected to another third bonding pad in the third device substrate. And the method of manufacturing the chip package further comprises forming a further insulating layer covering the insulating layer and the redistribution layer, the another insulating layer having an opening exposing the fourth bump, and the other A redistribution layer is electrically connected to the fourth bump via the opening in the other insulating layer. 如申請專利範圍第31項所述之晶片封裝體的製造方法，其中該第四凸塊電性連接至該第一裝置基底內的一第一接合 墊或該第二裝置基底內的一第二接合墊，且其中該絕緣層具有複數開口，該等開口的其中一者暴露出該第四凸塊，且該另一重佈線層經由上述該等開口的其中一者電性連接至該第四凸塊。 The method of manufacturing a chip package according to claim 31, wherein the fourth bump is electrically connected to a first bond in the first device substrate. a second bonding pad in the pad or the second device substrate, and wherein the insulating layer has a plurality of openings, one of the openings exposing the fourth bump, and the other redistribution layer passes through the openings One of the electrical connections is electrically connected to the fourth bump.
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