TW201543495A - Shift register apparatus and voltage regulating device thereof - Google Patents

Abstract

A shift register apparatus including a plurality of serial-connected shift register units is provided. The N<SP>th</SP> shift register unit includes an output driving circuit, a capacitor, a pull-up circuit, a pull-down circuit and an auxiliary pull-down circuit. The pull-up circuit pulls up the voltage level of a driving signal according to a pull-up control signal and an (N-P)<SP>th</SP> output signal. The pull-down circuit regulates the voltage level of the driving signal and the output signal according to a pull-down control signal. The auxiliary pull-down circuit pulls down the driving signal and the voltage level on an output end according to an (N+Z)<SP>th</SP> output signal. At least one of the pull-up circuit, the pull-down circuit and the auxiliary pull-down circuit includes a voltage adjusting unit including a double-gate thin-film transistor, another capacitor and a pre-charging switch. The pre-charging switch turns on or off according to an (N-P)<SP>th</SP> clock signal or the pull-up control signal.

Description

Shift register device and voltage adjusting device thereof

The present invention relates to a shift register device and a voltage adjusting device thereof, and more particularly to a shift register device capable of reducing leakage current and a voltage adjusting device thereof.

At present, the gate driver on array (GOA) display is mostly composed of a thin film transistor (TFT). The gate driving circuit structure is equivalent to a shift register.

Due to the element characteristics of the thin film transistor, when the drain and the source of the thin film transistor are subjected to a large bias voltage VDS, the leakage current will increase correspondingly, which may cause an abnormality in the output of the gate driving circuit structure. In order to improve this phenomenon, the conventional gate driving circuit uses two thin film transistors connected in series in a double-gate thin-film transistor to share a large bias VDS which may be subjected to operation of the circuit. In order to reduce leakage current. Wherein the control ends of the two thin film transistors are connected to each other, and one of the thin film transistors has its source connected to the drain of the other thin film transistor, and the connection point (hereinafter referred to as the third end) is in the double Gate thin film transistor When it is closed, it is floating. However, since the voltage level of the third terminal is often unknown, it can be seen from FIG. 1 that the waveform F1 of the third end is significantly lower than the waveform Q1 of the driving end. In other words, the conventional gate drive circuit has a limited effect of suppressing leakage current.

The invention provides a shift temporary storage device and a voltage adjusting device thereof, which can improve the leakage current problem and have better stability.

The shift register device of the present invention includes a plurality of shift register units, and the shift register units are coupled in series with each other. The shift register unit of the Nth stage includes an output drive circuit, a first capacitor, a pull-up circuit, a pull-down circuit, and an auxiliary pull-down circuit. The output driving circuit is coupled to the output end and the driving end, and the output driving circuit receives the driving signal from the driving end, and generates an output signal according to the driving signal and the timing signal. The first capacitor is coupled between the output end and the driving end. The pull-up circuit has one end coupled to the driving end and the other end receiving the N-P level output signal. The pull-up circuit generates a drive signal according to the pull-up control signal and the N-P stage output signal. The pull-down circuit is coupled between the driving end, the output end and the reference ground end, and is configured to stabilize the driving signal and the voltage level on the output signal according to the pull-down control signal. The auxiliary pull-down circuit is coupled between the driving end, the output end and the reference ground end, and according to the N+Z level output signal, the driving signal and the voltage on the output end are pulled down. Wherein at least one of the pull-up circuit, the pull-down circuit and the auxiliary pull-down circuit comprises a voltage adjusting unit, and the voltage adjusting unit comprises a double gate thin film transistor, a second capacitor and a precharge switch. The double gate thin film transistor has a first control end, a second control end, a first end, a second end, and a third end, and the double gate The first control end and the second control end of the ultra-thin film transistor are coupled to the N+Z-level output signal, the pull-down control signal or the pull-up control signal, and the first end of the double-gate thin film transistor is coupled to the driving end. And the second end thereof is coupled to the reference ground or the NP level output signal. The first end of the second capacitor is coupled to the third end of the dual gate thin film transistor, and the second end of the second capacitor is coupled to the output end. The first end of the pre-charge switch receives the NP-level timing signal, and the second end of the pre-charge switch is coupled to the third end of the dual-gate thin film transistor, and the control end of the pre-charge switch is coupled to the NP-level timing signal or the pull-up control signal To turn on or off. Where N, P, and Z are positive integers and P is less than N.

The shift register device of the present invention further includes a plurality of shift register units, and the shift register units are coupled in series with each other. The shift register unit of the Nth stage includes an output drive circuit, a first capacitor, a pull-up circuit, a pull-down circuit, and an auxiliary pull-down circuit. The output driving circuit is coupled to the output end and the driving end, and the output driving circuit receives the driving signal from the driving end, and generates an output signal according to the driving signal and the timing signal. The first capacitor is coupled between the output end and the driving end. The pull-up circuit has one end coupled to the driving end and the other end receiving the N-P level output signal. The pull-up circuit generates a drive signal according to the pull-up control signal and the N-P stage output signal. The pull-down circuit is coupled between the driving end, the output end and the reference ground end, and is configured to pull down the driving signal and the voltage level on the output signal according to the pull-down control signal. The auxiliary pull-down circuit is coupled between the driving end, the output end and the reference ground end, and according to the N+Z level output signal, the driving signal and the voltage level on the output end are pulled down. Wherein at least one of the pull-up circuit, the pull-down circuit and the auxiliary pull-down circuit comprises a voltage adjustment unit, and the voltage adjustment unit comprises a double gate thin film transistor and a second capacitance. Double gate thin film transistor has the first a control terminal, a second control terminal, a first terminal, a second terminal and a third terminal, the first control terminal and the second control terminal of the dual gate thin film transistor are coupled to the N+Z level output signal and the pull-down control The signal or the pull-up control signal, the first end of the double-gate thin film transistor is coupled to the driving end, and the second end thereof is coupled to the reference ground or the NP-level output signal. The second capacitor is coupled between the first end and the third end of the dual gate thin film transistor. Where N, P, and Z are positive integers and P is less than N.

The voltage adjusting device proposed by the present invention is suitable for a shift register unit of an integrated gate driving circuit. The voltage adjusting device corresponding to the Nth stage shift register unit includes a double gate thin film transistor, a capacitor, and a precharge switch. The dual gate thin film transistor has a first control end, a second control end, a first end, a second end, and a third end. The first control end and the second control end of the dual gate thin film transistor are coupled to the N+Z stage output signal, the pull-down control signal or the pull-up control signal. The first end of the double gate thin film transistor is coupled to the driving end to pull or generate a driving signal, and the second end thereof is coupled to the reference ground or the N-P stage output signal. The first end of the capacitor is coupled to the third end of the dual gate thin film transistor, and the second end of the capacitor is coupled to the output end to generate an output signal. The first end of the precharge switch receives the NP level timing signal, and the second end thereof is coupled to the third end of the double gate thin film transistor, and the control end of the precharge switch is coupled to the precharge control signal or the NP level timing signal . Where N, P, and Z are positive integers and P is less than N.

The voltage adjusting device proposed by the present invention is suitable for the shift register unit of the integrated gate driving circuit. The voltage adjusting device corresponding to the Nth stage shift register unit includes a double gate thin film transistor and a capacitor. The double gate thin film transistor has a first control end, a second control end, a first end, a second end and a third end, and the double gate thin film electro-crystal The first control end of the body and the second control end are coupled to the N+Z stage output signal, the pull-down control signal or a pull-up control signal, and the first end of the double gate thin film transistor is coupled to the driving end, and The second end is coupled to the reference ground or the NP stage output signal. The capacitor is coupled between the first end and the third end of the double gate thin film transistor. Where N, P, and Z are positive integers and P is less than N.

Based on the above, the shift register device and the voltage adjusting device proposed by the embodiments of the present invention use a precharge switch and a capacitive coupling effect to adjust the voltage level of the third terminal of the double gate thin film transistor to a voltage level close to the driving end. The bit can improve the leakage current of the shift register and achieve better stability.

In order to make the above features and advantages of the present invention more comprehensible, the following embodiments are described in detail with reference to the accompanying drawings.

200, 600, 700, 800‧‧‧ shift register unit

210, 610, 710, 810‧‧‧ output drive circuit

220, 620, 720, 820‧‧‧ pull-up circuits

230, 630, 730, 830‧‧‧ pulldown circuits

240, 640, 740, 840‧‧‧Auxiliary pull-down circuit

250, 650, 750, 850‧‧‧ pull-down control circuit

260‧‧‧ Pull-up control circuit

660_1, 660_2, 760_1, 760_2, 860_1, 860_2, 620_1, 620_2‧‧‧ circuits

300, 400, 500‧‧‧ voltage adjustment unit

310, 410, 510, 622, 742, 832‧‧‧ double gate thin film transistors

C, Cx‧‧‧ capacitor

CT1, CT2‧‧‧ control terminal

F‧‧‧ third end

F1, F2, Q1, Q2‧‧‧ waveform

G‧‧‧ output

G(n), G(n-p), G(n-2), G(n+4), G(n+z)‧‧‧ output signals

HC(n), HC(n-p), HC(n-2)‧‧‧ timing signals

K(n)‧‧‧ pulldown control signal

LC‧‧‧Low-frequency clock signal

M1~M3, M11, M21, M31~M32, M41~M42, M51~M54, M61, M62‧‧‧O crystal

Q‧‧‧Driver

Q(n), Q(n-p), Q(n-2)‧‧‧ drive signals

ST(n)‧‧‧ pull-up control signal

SWx‧‧‧Precharge switch

VSS‧‧‧reference ground

1 is a waveform diagram of a conventional shift register unit.

FIG. 2 is a block diagram of a shift register unit according to an embodiment of the invention.

FIG. 3 is a circuit diagram of a voltage adjustment device according to an embodiment of the invention.

4 is a circuit diagram of a voltage regulating device according to an embodiment of the invention.

FIG. 5 is a circuit diagram of a voltage adjusting device according to an embodiment of the invention Figure.

FIG. 6 is a circuit diagram of a shift register unit according to an embodiment of the invention.

FIG. 7 is a circuit diagram of a shift register unit according to an embodiment of the invention.

FIG. 8 is a circuit diagram of a shift register unit according to an embodiment of the invention.

Figure 9 is a waveform diagram of a shift register unit in accordance with an embodiment of the present invention.

The shift register device provided by the embodiment of the invention comprises a plurality of shift register units coupled in series with each other. Referring to FIG. 2, FIG. 2 is a block diagram of an Nth stage shift register unit 200 in a shift register device according to an embodiment of the invention. The shift register unit 200 includes an output drive circuit 210, a capacitor C, a pull-up circuit 220, a pull-down circuit 230, and an auxiliary pull-down circuit 240. The output driving circuit 210 is coupled to the output terminal G and the driving terminal Q. The output driving circuit receives the driving signal Q(n) from the driving terminal Q, and generates an output signal G(n) according to the driving signal Q(n) and the timing signal HC(n) to determine the voltage level on the output terminal G.

The capacitor C is coupled between the output terminal G and the driving terminal Q. One end of the pull-up circuit 220 is coupled to the driving terminal Q, and the other end thereof receives the N-P-level output signal G(n-p). The pull-up circuit 220 generates a driving signal Q(n) according to the pull-up control signal ST(n) and the N-P stage output signal G(n-p) to determine the voltage level of the driving terminal Q.

The pull-down circuit 230 is coupled between the driving terminal Q, the output terminal G and the reference ground terminal VSS, and pulls down the voltage level of the driving terminal Q and the output terminal G according to the pull-down control signal K(n). The auxiliary pull-down circuit 240 is coupled between the driving terminal Q, the output terminal G and the reference ground terminal VSS, and drives the voltage on the driving terminal Q and the output terminal G according to the N+Z-level output signal G(n+z).

In addition, the shift register unit 200 may further include a pull-down control circuit 250 and a pull-up control circuit 260. In detail, the pull-down control circuit 250 is coupled to the driving terminal Q and receives the low-frequency clock signal LC. The pull-down control circuit 250 generates the pull-down control signal K(n) according to the low-frequency clock signal LC and the driving signal Q(n). Thereby, the actuation of the pull-down unit 230 is controlled. The pull-up control circuit 260 receives the NP-level timing signal HC(np) and the NP-level driving signal Q(np), and provides the NP-level timing signal HC(np) as a pull-up according to the NP-level driving signal Q(np). The signal ST(n) is controlled to control the circuit operation of the pull-up circuit 220.

It should be noted that the shift register unit 200 may further include a voltage adjustment unit at least one of the pull-up circuit 220, the pull-down circuit 230, and the auxiliary pull-down circuit 240. Here, the voltage adjustment units 300, 400, and 500 of FIGS. 3 to 5 will be described, and any of the voltage adjustment units 300, 400, and 500 may be used as the pull-up circuit 220, the pull-down circuit 230, or the auxiliary pull-down circuit 240 described above. The voltage adjusting unit of at least one of the electrodes improves the leakage current phenomenon of the shift register unit. It should be noted that, in the following embodiments, the above-mentioned N-P level will be exemplified by the N-2 level, and the N+Z level will be described by taking the N+4 level as an example, but the present invention is not limited thereto.

3 is a circuit diagram of a voltage adjustment unit 300 according to an embodiment of the present invention. It may include a dual gate thin film transistor 310, a capacitor Cx, and a precharge switch SWx. The double gate thin film transistor 310 includes transistors M1 and M2, and the transistors M1 and M2 have control terminals CT1 and CT2, respectively, and the control terminals CT1 and CT2 can be coupled to the N+4 output signal G(n). +4), pull-down control signal K(n) or pull-up control signal ST(n). The first end of the dual gate thin film transistor 310 is coupled to the driving terminal Q to pull or generate the driving signal Q(n), and the second end thereof is coupled to the reference ground VSS or the N-2 output signal G(n). -2), and the second end of the transistor M1 is coupled to the first end of the transistor M2 and serves as the third end F of the double gate thin film transistor. In this embodiment, the precharge switch SWx includes a transistor M3, and the first end of the transistor M3 receives the N-2 stage timing signal HC(n-2), and the control end of the transistor M3 receives the precharge control signal or coupled Connected to the pull-up control signal ST(n), the second end of the transistor M3 is coupled to the third terminal F of the dual-gate thin film transistor 310. In the present embodiment, the precharge switch SWx pulls up the control signal ST(n) as a precharge control signal and turns on or off according to the pull up control signal ST(n). When the pull-up control signal ST(n) is at a high voltage level and the precharge switch SWx is turned on, the N-2 stage timing signal HC(n-2) will be performed on the third terminal F of the double gate thin film transistor 310. Charging. After that, the pull-up control signal ST(n) is turned to the low voltage level, and the output signal G(n) is turned to the high voltage level, so that the voltage level of the third terminal F is raised to be close to the capacitor Cx. The voltage level of the output terminal G, or even higher than the voltage level of the output terminal G. Thereby, the voltage difference between the driving terminal Q and the third terminal F can be effectively reduced, and the voltage difference between the drain and the source of the transistor M1 can be effectively reduced (for example, close to 0 volt (V)). In order to reduce the generation of leakage current.

FIG. 4 illustrates the power of the voltage adjustment unit 400 according to another embodiment of the present invention. Road map. The voltage adjustment unit 400 includes a dual gate thin film transistor 410, a capacitor Cx, and a precharge switch SWx, and the double gate thin film transistor 410 includes transistors M1 and M2. Different from the voltage adjustment unit 300 of FIG. 3, in the pre-charge switch SWx of the voltage adjustment unit 400, the control end of the transistor M3 is coupled to the first end thereof and is commonly coupled to the N-2 timing signal HC ( N-2). Therefore, when the N-2 stage timing signal HC(n-2) is at a high voltage level, the precharge switch SWx can be turned on, and at the same time, the N-2 level timing signal HC(n-2) is applied to the double gate film. The third end F of the transistor 410 is charged to achieve an effect similar to the foregoing embodiment to reduce leakage current.

FIG. 5 is a circuit diagram of a voltage adjustment unit 500 according to another embodiment of the present invention. The voltage adjustment unit 500 includes a dual gate thin film transistor 510 and a capacitor Cx, and the double gate thin film transistor 510 includes transistors M1 and M2. Different from the voltage adjustment unit 300 of FIG. 3 , the voltage adjustment unit 500 of FIG. 5 couples the capacitor Cx between the driving terminal Q and the third terminal F, so that the voltage level change of the driving terminal Q can pass through the capacitor Cx. Directly coupled to the third terminal F, the voltage adjustment unit 500 of this embodiment can also achieve a reduction in the voltage difference between the driving terminal Q and the third terminal F, thereby improving the problem of leakage current. It should be noted that when considering the parasitic capacitance effect, the voltage level of the third terminal F in this embodiment may be lower than the voltage level of the driving terminal Q. However, even if it is affected by the parasitic capacitance, the capacitor Cx can effectively reduce the voltage difference between the driving terminal Q and the third terminal F, thereby reducing leakage current generation.

Thereby, the third terminal F of the double gate thin film transistor is charged by the precharge switch SWx in the voltage adjusting unit of the above embodiment, and the voltage level of the third terminal F is raised by the coupling effect of the capacitor Cx. The voltage level of the third terminal F Adjusting to be close to the driving terminal Q effectively improves the problem of the leakage current phenomenon in the shift register unit 200.

Next, the circuit architecture of the voltage adjustment unit 300 is taken as an example, and the embodiments are used to explain the case where the voltage adjustment unit 300 is applied to the pull-up circuit 220, the pull-down circuit 230, and the auxiliary pull-down circuit 240 of the shift temporary storage unit 200.

FIG. 6 is a circuit diagram of a shift register unit 600 according to an embodiment of the invention. The shift register unit 600 includes an output drive circuit 610, a capacitor C, a pull-up circuit 620, a pull-down circuit 630, an auxiliary pull-down circuit 640, a pull-down control circuit 650, and a pull-up control circuit formed by the circuits 660_1 and 660_2. The output driving circuit 610 includes a transistor M11. The transistor M11 determines the voltage at the output terminal G according to the driving signal Q(n) received by the control terminal thereof and the timing signal HC(n) received by the first terminal thereof. The level is generated to produce an output signal G(n). The capacitor C is coupled between the output terminal G and the driving terminal Q.

The pull-down circuit 630 includes transistors M31 and M32. The first end of the transistor M31 is coupled to the output terminal G, and the control terminal thereof receives the pull-down control signal K(n), and the second end thereof is coupled to the reference ground terminal VSS, so that the pull-down control signal K(n) is When the high voltage level is high, the transistor M31 is turned on, and the voltage level of the output terminal G is pulled down to the voltage level of the reference ground VSS. Similarly, the first end of the transistor M32 is coupled to the driving terminal Q, and the control end thereof receives the pull-down control signal K(n), and the second end thereof is coupled to the reference ground terminal VSS, thereby pulling down the control signal. When K(n) is at a high voltage level, the transistor M32 is turned on, and the voltage level of the driving terminal Q is pulled down to the voltage level of the reference ground VSS.

The auxiliary pull-down circuit 640 includes transistors M41 and M42. The first end of the transistor M41 is coupled to the driving terminal Q, and the control terminal receives the N+4 output signal G(n+4), and the second end thereof is coupled to the reference ground VSS, thereby being at the N+4 level. When the output signal G(n+4) is at the high voltage level, the transistor M41 is turned on, and the voltage level of the driving terminal Q is pulled down to the voltage level of the reference ground VSS. Similarly, the first end of the transistor M42 is coupled to the output terminal G, the control terminal receives the N+4 output signal G(n+4), and the second end thereof is coupled to the reference ground VSS, thereby When the N+4 output signal G(n+4) is at the high voltage level, the transistor M42 is turned on, and the voltage level of the output terminal G is pulled down to the voltage level of the reference ground VSS.

The pull-down control circuit 650 includes transistors M51-M54. The first end and the control end of the transistor M51 receive the low frequency clock signal LC. The first end of the transistor M52 is coupled to the second end of the transistor M51, the control end of the transistor M52 is coupled to the driving terminal Q, and the second end thereof is coupled to the reference ground VSS. The first end of the transistor M53 receives the low frequency clock signal LC, the control end of which is coupled to the second end of the transistor M51, and the second end of the transistor M53 generates the pull-down control signal K(n). The first end of the transistor M54 is coupled to the second end of the transistor M53, the control end of the transistor M54 is coupled to the driving terminal Q, and the second end thereof is coupled to the reference ground VSS. Thereby, the pull-down control signal K(n) generated by the pull-down control circuit 650 can be used to control the pull-down circuit 630 to pull down the voltage levels on the driving terminal Q and the output terminal G.

The pull-up control circuit is composed of circuits 660_1 and 660_2. The pull-up control circuit includes transistors M61 and M62. The first end of the transistor M61 receives the pre-stage timing signal (eg, the N-2 timing signal HC(n-2)), and the control terminal receives the pre-driver a dynamic signal (eg, N-2 stage drive signal Q(n-2)), and a second end thereof generates a pull-up control signal ST(n) to control the pull-up circuit 620 to pull up the drive signal Q(n) Voltage level. The first end of the transistor M62 is coupled to the second end of the transistor M61, the second end of the transistor M62 is coupled to the reference ground GND, and the control end of the transistor M62 receives the pull-down control signal K(n). The transistor M62 pulls down the voltage value of the pull-up control signal ST(n) according to the pull-down control signal K(n).

It should be noted that the pull-up circuit 620 of this embodiment is composed of circuits 620_1 and 620_2. The pull-up circuit 620 includes a voltage adjustment unit, and the voltage adjustment unit is implemented by the circuit architecture of the voltage adjustment unit 300 of FIG. 3, and includes the transistors M1 and M2 of the double gate thin film transistor 622, the capacitor Cx, and the precharge. The transistor M3 of the switch SWx. The control terminals CT1 and CT2 of the dual gate thin film transistor 622 are coupled to the pull-up control signal ST(n), and the first end of the dual-gate thin film transistor 622 is coupled to the driving terminal Q, and the second end thereof Then coupled to the N-2 level output signal G(n-2). In addition, the first end of the capacitor Cx is coupled to the third end F of the dual gate thin film transistor 622, and the second end of the capacitor Cx is coupled to the output end G. The first end of the precharge switch SWx receives the N-2 stage timing signal HC(n-2), and the second end thereof is coupled to the third end F of the double gate thin film transistor 622. The precharge switch SWx is turned on or off according to the pull-up control signal ST(n), and charges the third terminal F with the N-2 timing signal HC(n-2) received at the first end when it is turned on. . After that, when the pull-up control signal ST(n) is turned to the low voltage level and the output signal G(n) is turned to the high voltage level, the voltage level of the third terminal F can be Raised to a voltage level close to the output terminal G, whereby the voltage difference between the driving terminal Q and the third terminal F is greatly reduced, and can be changed The problem of good leakage current.

FIG. 7 is a circuit diagram of a shift register unit 700 according to another embodiment of the invention. The shift register unit 700 includes an output drive circuit 710, a capacitor C, a pull-up circuit 720, a pull-down circuit 730, an auxiliary pull-down circuit 740, a pull-down control circuit 750, and a pull-up control circuit composed of the circuits 760_1 and 760_2. Different from the shift register unit 600 of FIG. 6, the present embodiment applies the circuit architecture of the voltage adjusting unit 300 of FIG. 3 to the auxiliary pull-down circuit 740. The voltage adjustment unit includes transistors M1 and M2 of the double gate thin film transistor 742, a capacitor Cx, and a transistor M3 of the precharge switch SWx. The control terminal CT1 and the CT2 of the dual gate thin film transistor 742 are coupled to the N+4 output signal G(n+4), the first end of which is coupled to the driving end Q, and the second end of the double gate transistor 742 is coupled to the driving end Q. Refer to ground VSS. Similarly, this embodiment adjusts the voltage level of the third terminal F through the voltage adjusting unit in the auxiliary pull-down circuit 740, so that the voltage difference between the driving terminal Q and the third terminal F can be greatly reduced, and the problem of leakage current is improved.

In addition, the pull-up circuit 720 of the present embodiment includes a transistor M21, and one end of the transistor M21 is coupled to the driving terminal Q, and the other end thereof receives the N-2-level output signal G(n-2). The pull-up circuit 720 generates a driving signal Q(n) according to the pull-up control signal ST(n) and the N-2-level output signal G(n-2) to determine the voltage level of the driving terminal Q.

FIG. 8 is a circuit diagram of a shift register unit 800 according to another embodiment of the invention. The shift register unit 800 includes an output drive circuit 810, a capacitor C, a pull-up circuit 820, a voltage stabilization circuit 830, an auxiliary pull-down circuit 840, a pull-down control circuit 850, and a pull-up control circuit composed of the circuits 860_1 and 860_2. Different from the shift register unit 600 of FIG. 6, the present embodiment applies the circuit architecture of the voltage adjusting unit 300 of FIG. 3 to the pull-down circuit 830. The voltage adjustment unit includes transistors M1 and M2 of the double gate thin film transistor 832, a capacitor Cx, and a transistor M3 of the precharge switch SWx. The control terminals CT1 and CT2 of the dual gate thin film transistor 832 are coupled to the pull-down control signal K(n), the first end of which is coupled to the driving terminal Q, and the second end of the double gate transistor 832 is coupled to the reference ground. VSS. Similarly, this embodiment adjusts the voltage level of the third terminal F through the voltage adjusting unit in the pull-down circuit 830, and the voltage difference between the driving terminal Q and the third terminal F can be greatly reduced, thereby improving the generation of leakage current.

Therefore, the voltage adjustment unit can be used as a voltage adjustment unit of at least one of a pull-up circuit, an auxiliary pull-down circuit, and a pull-down circuit in the shift temporary storage unit according to an embodiment of the present invention. By adjusting the voltage level of the third terminal F, the voltage difference between the driving terminal Q and the third terminal F can be greatly reduced, and the problem of leakage current can be improved.

It should be emphasized that the voltage adjusting units 400 and 500 proposed in FIG. 4 and FIG. 5 can also be applied to at least one of the pull-up circuit, the auxiliary pull-down circuit, and the pull-down circuit, respectively, with reference to the above manner, and can also be similar. The above effect of improving leakage current.

FIG. 9 is a waveform diagram of the third terminal F and the driving terminal Q of the shift register device according to the embodiment of the present invention. With respect to FIG. 1, the voltage difference between the waveform F2 of the third terminal F and the waveform Q2 of the driving terminal Q in FIG. 9 can be remarkably suppressed. In other words, the shift register device of the embodiment of the present invention can effectively reduce leakage current.

In summary, the shift register device and the voltage proposed by the embodiment of the present invention The adjusting unit utilizes a pre-charging switch and a capacitive coupling effect to adjust the voltage level of the third terminal of the double-gate thin-film transistor to a voltage level close to the driving end, thereby improving the leakage current of the temporary storage device and achieving better Stability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

200‧‧‧Shift register unit

210‧‧‧Output drive circuit

220‧‧‧ Pull-up circuit

230‧‧‧ Pulldown circuit

240‧‧‧Auxiliary pull-down circuit

250‧‧‧ Pull-down control circuit

260‧‧‧ Pull-up control circuit

C‧‧‧ capacitor

G‧‧‧ output

G(n), G(n-p), G(n+z)‧‧‧ output signals

HC(n), HC(n-p)‧‧‧ timing signals

K(n)‧‧‧ pulldown control signal

LC‧‧‧Low-frequency clock signal

Q‧‧‧Driver

Q(n), Q(n-p)‧‧‧ drive signals

ST(n)‧‧‧ pull-up control signal

VSS‧‧‧reference ground

Claims (11)

A shift register device includes: a plurality of shift register units, wherein the shift register units are coupled in series with each other, wherein the shift stage unit of the Nth stage comprises: an output drive circuit coupled to An output terminal and a driving end, the output driving circuit receives a driving signal from the driving end, and generates an output signal according to the driving signal and a timing signal; a first capacitor coupled to the output end and the driving a pull-up circuit, one end of which is coupled to the driving end, and the other end of which receives an NP-level output signal, the pull-up circuit generates the driving signal according to a pull-up control signal and the NP-level output signal; a pull-up circuit coupled between the driving end, the output end and a reference ground end, according to a pull control signal to pull down the driving signal and the voltage level of the output signal; and an auxiliary pull-down circuit coupled to the Between the driving end, the output end and the reference ground end, according to an N+Z stage output signal to pull down the driving signal and the voltage level of the output end, wherein the pull-up circuit, the pull-down circuit and the At least one of the auxiliary pull-down circuit includes: a voltage adjustment unit comprising: a double gate thin film transistor having a first control end, a second control end, a first end, a second end, and a third end, the a control end and a second control end The first end is coupled to the driving end, and the second end is coupled to the reference ground or the NP-level output. The first end is coupled to the N+Z output signal, the pull-down control signal, or the pull-up control signal. a second capacitor having a first end coupled to the third end of the dual gate thin film transistor, a second end of the second capacitor coupled to the output end, and a precharge switch first The terminal receives an NP-level timing signal, and the second end is coupled to the third end of the dual-gate thin-film transistor, and the control end of the pre-charge switch is coupled to the NP-level timing signal or the pull-up control signal, where , N, P, Z are positive integers and P is less than N. The shift register device of claim 1, wherein the Nth stage shift register unit further comprises: a pull-down control circuit coupled to the drive end and a low frequency clock signal, according to the low frequency The pulse signal and the drive signal to generate the pull down control signal. The shift register device of claim 2, wherein the pull-down control circuit further comprises: a first transistor having a first end, a second end, and a control end, the first of the first transistor The terminal and the control end receive the low frequency clock signal; a second transistor having a first end, a second end, and a control end, the first end of the second transistor being coupled to the second end of the first transistor The control terminal of the second transistor is coupled to the driving end, and the second end of the second transistor is coupled to the reference ground; a third transistor has a first end, a second end, and a control end The third electricity The first end of the crystal receives the low frequency clock signal, the control end of the third transistor is coupled to the second end of the first transistor, and the second end of the third transistor generates the pull down control signal; a fourth transistor having a first end, a second end, and a control end, the first end of the fourth transistor is coupled to the second end of the third transistor, and the control end of the fourth transistor is coupled to The driving end, the second end of the fourth transistor is coupled to the reference ground. The shift register device of claim 1, wherein the Nth stage shift register unit further comprises: a pull-up control circuit, receiving the NP-level timing signal and the NP-level drive signal, and according to the The NP-level drive signal and the NP-level timing signal are used to generate the pull-up control signal. The shift register device of claim 4, wherein the pull-up control circuit comprises: a first transistor having a first end, a second end, and a control end, the first end of the transistor receiving The NP-level timing signal, the control end of the transistor receives the NP-level driving signal, the second end of the transistor generates the pull-up control signal; and a second transistor having a first end, a second end, and a control The first end of the second transistor is coupled to the second end of the first transistor, the second end of the second transistor is coupled to the reference ground, and the control end of the second transistor receives This pull-down control signal. The shift register device according to claim 1, wherein the auxiliary The pull-down circuit further includes: a first transistor having a first end, a second end, and a control end, the first end of the transistor is coupled to the output end, and the control end of the transistor receives the N+Z-level output a signal, the second end of the transistor is coupled to the reference ground; and a second transistor having a first end, a second end, and a control end, the first end of the transistor being coupled to the driving end, The control terminal of the transistor receives the N+Z-level output signal, and the second end of the transistor is coupled to the reference ground. The shift register device of claim 1, wherein the pull-down circuit further comprises: a first transistor having a first end, a second end, and a control end, the first end of the transistor being coupled Up to the output end, the control end of the transistor receives the pull-down control signal, the second end of the transistor is coupled to the reference ground; a second transistor has a first end, a second end, and a control end, The first end of the transistor is coupled to the driving end, and the control end of the transistor receives the pull-down control signal, and the second end of the transistor is coupled to the reference ground. A shift register device includes: a plurality of shift register units, wherein the shift register units are coupled in series with each other, wherein the shift stage unit of the Nth stage comprises: an output drive circuit coupled to An output terminal and a driving end, the output driving circuit receives a driving signal from the driving end, and generates an output signal according to the driving signal and a timing signal; a first capacitor coupled to the output end and the driving End a pull-up circuit, one end of which is coupled to the driving end, and the other end of which receives an NP-level output signal, the pull-up circuit generates the driving signal according to a pull-up control signal and the NP-level output signal; Coupling between the driving end, the output end and a reference ground end, according to the pull control signal to pull down the driving signal and the voltage level of the output signal; and an auxiliary pull-down circuit coupled to the driving end, Between the output terminal and the reference ground terminal, the driving signal and the voltage level on the output terminal are pulled down according to an N+Z-level output signal, wherein the pull-up circuit, the pull-down circuit, and the auxiliary pull-down circuit At least one of the following includes: a voltage adjustment unit comprising: a double gate thin film transistor having a first control end, a second control end, a first end, a second end, and a third end, the first control end thereof The second control terminal is coupled to the N+Z-level output signal, the pull-down control signal, or the pull-up control signal, the first end of which is coupled to the driving end, and the second end of the second control terminal is coupled to the reference ground or The NP level output Number; and a second capacitor coupled between the first terminal and the third terminal of the dual gate thin film transistor, wherein, N, P, Z P is a positive integer less than N. A voltage adjusting device is suitable for a shift temporary storage unit of an integrated gate driving circuit, and the voltage adjusting device corresponding to the Nth stage shifting temporary storage unit comprises: a pair of gate thin film transistors having a first control end, a second control end, a first end, a second end, and a third end, wherein the first control end and the second control end are coupled to an N+Z level The output signal, the pull-down control signal or the pull-up control signal, the first end of which is coupled to a driving end to pull or generate a driving signal, and the second end of which is coupled to a reference ground or an NP-level output signal; a capacitor having a first end coupled to the third end of the dual gate thin film transistor, a second end of the capacitor coupled to an output terminal, and a precharge switch having a first end receiving an NP level timing a second end of the signal is coupled to the third end of the dual gate thin film transistor, and the control end of the precharge switch is coupled to a precharge control signal or the NP level timing signal, wherein, N, P, and Z Is a positive integer and P is less than N. The voltage adjustment device of claim 9, wherein the precharge switch comprises: a transistor having a first end, a second end, and a control end, the first end of the transistor receiving the NP level timing signal The control terminal of the transistor receives the pre-charge control signal or is coupled to the first end of the transistor, and the second end of the transistor is coupled to the third end of the dual-gate thin film transistor. A voltage adjusting device is suitable for a shift temporary storage unit of an integrated gate driving circuit, and the voltage adjusting device corresponding to the Nth stage shifting temporary storage unit comprises: a double gate thin film transistor having a first control end, a second control terminal, a first end, a second end, and a third end, wherein the first control end and the second control end are coupled to an N+Z-level output signal, the pull-down control signal or a pull-up control signal, the first The second end is coupled to the reference ground or an NP-level output signal; and a capacitor is coupled between the first end and the third end of the dual-gate thin film transistor, Where N, P, and Z are positive integers and P is less than N.