TW201541464A - Voltage control circuit and semiconductor storage device - Google Patents

Abstract

According to an embodiment disclosed in the invention, a voltage control circuit comprising a first NMOS transistor, a second NMOS transistor, an operational amplifier, and an adjustment circuit is provided. The drain of the first NMOS transistor connects the first node of an input node side, the source connects the second node of an output node side, and the gate connects the first node as aforementioned through a third node. The drain of the second NMOS transistor connects the third node, and the source connects a first reference potential. The non-inverting input terminal of the operational amplifier connects a reference node that is located between the second node and a second reference potential, the inverting input terminal connects the reference potential, and the output terminal connects the gate of the second NMOS transistor. The adjustment circuit forms a discharge path from a first line towards a second line when the potential of the output node exceeds a target value. The first line is the line connecting between the source of the first NMOS transistor and the second node, and the second line is the line connecting between the third node and the drain of the second NMOS transistor.

Description

Voltage control circuit and semiconductor memory device

Embodiments of the present invention relate to a voltage control circuit and a semiconductor memory device.

The step-down voltage control circuit steps down the voltage input to the input node and outputs the step-down voltage from the output node. At this time, it is preferable to stabilize the level of the voltage to be output from the output node.

The present invention provides a voltage control circuit capable of shortening a discharge time for stabilizing an output voltage level and reducing power consumption, and a semiconductor memory device using the same.

According to one embodiment, a voltage control circuit including a first NMOS transistor, a second NMOS transistor, an operational amplifier, and an adjustment circuit is provided. The first NMOS transistor has a drain connected to the first node on the input node side, a source connected to the second node on the output node side, and a gate connected to the first node via the third node. The second NMOS transistor has a drain connected to the third node and a source connected to the first reference potential. The non-inverting input terminal of the operational amplifier is connected to a reference node between the second node and the second reference potential, the inverting input terminal is connected to the reference potential, and the output terminal is connected to the gate of the second NMOS transistor. The adjustment circuit forms a discharge path from the first line to the second line when the potential of the output node exceeds the target value. The first line is connected to the source of the first NMOS transistor and the line of the second node. The second line connects the third node and the drain of the second NMOS transistor.

1‧‧‧Semiconductor memory device

2‧‧‧ memory cell array

3‧‧‧ column decoder

4‧‧‧Sense Amplifier Block

5‧‧‧ line decoder

6‧‧‧ Controller

7‧‧‧High voltage generator

8‧‧‧CG driver

9‧‧‧ address register

10‧‧‧I/O buffer

40‧‧‧Voltage control circuit

40i‧‧‧ voltage control circuit

40j‧‧‧ voltage control circuit

41‧‧‧NMOS transistor (1st NMOS transistor)

42‧‧‧NMOS transistor (2nd NMOS transistor)

43‧‧‧Operational Amplifier

44i‧‧‧Adjustment circuit

44j‧‧‧Adjustment circuit

71‧‧‧High voltage generating circuit

72‧‧‧High voltage generating circuit

431‧‧‧ Non-inverting input terminal

432‧‧‧Reverse input terminal

433‧‧‧Output terminal

441‧‧‧Rectifying transistor

441j‧‧‧ diode

442‧‧‧Rectification transistor

442j‧‧‧dipole

443‧‧‧Rectifying transistor

443j‧‧‧dipole

444‧‧‧1st line

445‧‧‧2nd line

446‧‧‧discharge path

AT‧‧‧Selected gate

BL‧‧‧ bit line

BL-0~BL-(p-1)‧‧‧ bit line

BLK-0~BLK-(n-1)‧‧‧ Block

BT1‧‧‧bias transistor

BT2‧‧‧bias transistor

BT3‧‧‧bias transistor

C1‧‧‧Capacitive components

CG‧‧‧ voltage

Cout‧‧‧ parasitic capacitance

DT‧‧‧Selected gate

GND‧‧‧ Ground potential

Idis‧‧‧discharge current

Ilim‧‧‧Limit current

MT-0~MT-(k-1)‧‧‧ memory cells

N1‧‧‧ node

N2‧‧‧ node

N3‧‧‧ node

Nf‧‧‧ reference node

Nin‧‧‧ input node

Nout‧‧‧ output node

NS-0~NS-(p-1)‧‧‧NAND string

R1‧‧‧resistive components

R2‧‧‧resistive components

R3‧‧‧resistive components

SGD‧‧‧Selected gate line

SGS‧‧‧Selected gate line

ST‧‧‧Selected gate

T‧‧‧discharge time

T’‧‧· discharge time

T0~t4‧‧‧ Timing

T2i~t4i‧‧‧ timing

Vgate‧‧‧ gate voltage

Vin‧‧‧Input voltage

Vin-2‧‧‧ input voltage

Vout‧‧‧ output voltage

Vout-1‧‧‧1st voltage

Vout-1’‧‧‧1st voltage

Vout-2‧‧‧2nd voltage

Vout-2’‧‧‧2nd voltage

Vpass‧‧‧Transfer potential

Vpgm‧‧‧ program potential

Vr1‧‧‧ reference potential

Vr2‧‧‧ reference potential

Vref‧‧‧ reference potential

Vt‧‧‧ target value

Vt0‧‧‧ target value

WELL‧‧‧ control signal

WL‧‧‧ character line

WL-0~WL-(k-1)‧‧‧ character line

WT1-0~WT1-(k-1)‧‧‧Select gate

WT2-0~WT2-(k-1)‧‧‧Selected gate

Fig. 1 is a view showing the configuration of a voltage control circuit of an embodiment.

Fig. 2 is a view showing the operation of the voltage control circuit of the embodiment.

Fig. 3 is a view showing the configuration of a voltage control circuit in a variation of the embodiment.

Fig. 4 is a view showing the configuration of a voltage control circuit according to another modification of the embodiment.

Fig. 5 is a view showing the configuration of a voltage control circuit according to another modification of the embodiment.

Fig. 6 is a view showing the configuration of a semiconductor memory device to which a voltage control circuit of a basic form is applied.

Fig. 7 is a view showing the configuration of a memory cell array of a semiconductor memory device to which a voltage control circuit of a basic form is applied.

Fig. 8 is a view showing the configuration of a connection between a voltage control circuit and a word line in a basic form.

Fig. 9 is a view showing changes in the potential of the word line of the basic form.

Fig. 10 is a view showing the configuration of a voltage control circuit of a basic form.

Fig. 11 is a view showing the operation of a voltage control circuit of a basic form.

Hereinafter, the voltage control circuit of the embodiment will be described in detail with reference to the additional drawings. Further, the present invention is not limited by the embodiment.

(embodiment)

Before describing the voltage control circuit 40 of the embodiment, the basic form of the voltage control circuit 40 will be described. The basic form voltage control circuit 40 is a step-down type voltage control circuit. For example, it is applied to the semiconductor memory device 1 shown in FIGS. 6 and 7. Fig. 6 is a view showing the configuration of the semiconductor memory device 1 to which the voltage control circuit 40 is applied. Fig. 7 is a view showing the configuration of the memory cell array 2 of the semiconductor memory device 1.

The semiconductor memory device 1 is a non-volatile memory material such as a NAND type flash memory. The semiconductor memory device 1 has a memory cell array 2, a column decoder 3, a sense amplifier (S/A) block 4, a row decoder 5, a controller 6, a high voltage generator (HV GEN) 7, CG The driver 8, the address register 9, and the I/O buffer 10.

The memory cell array 2 has a plurality of memory cells. A plurality of memory cells constitute a complex column and a plurality of rows. The memory cell array 2 includes n (n is a positive integer) blocks BLK-0~BLK-(n-1). In each of the blocks BLK-0 to BLK-(n-1), for example, as shown in FIG. 7, a plurality of NAND strings NS-0 to NS-(p-1) are arranged. The plurality of NAND strings NS-0 to NS-(p-1) are respectively extended, for example, in the column direction. A plurality of NAND strings NS-0~NS-(p-1) are arranged in a row direction. Each of the NAND strings NS-0 to NS-(p-1) includes, for example, a plurality of memory cells MT-0 to MT-(k-1) connected in series to each other and two selection gates connected to one end thereof. The poles ST and DT (refer to Fig. 7).

The plurality of character lines extend in the row direction. A plurality of character line lines are arranged in a column direction. For example, as shown in FIG. 7, a plurality of word line lines WL-0 to WL-(k-1) extend in the row direction, respectively. The plurality of word lines WL-0 to WL-(k-1) are arranged in the column direction. That is, the plurality of word line lines WL-0 to WL-(k-1) intersect with the plurality of NAND strings NS-0 to NS-(p-1). A plurality of word lines WL-0~WL-(k-1) are connected to the control electrodes of the memory cells.

The two selection gate lines SGD and SGS are respectively extended in the row direction. The gate lines SGD and SGS are selected to be disposed at both ends of a plurality of word lines in a column direction. The two selection gate lines SGD and SGS are respectively connected to the control electrodes of the selection gates DT and ST.

A plurality of bit lines extend in a row direction. A plurality of bit lines are arranged in a row direction. For example, as shown in FIG. 7, a plurality of bit lines BL-0 to BL-(p-1) extend in a row direction. The plurality of bit lines BL-0 to BL-(p-1) are arranged in the row direction. That is, the plurality of bit lines BL-0 to BL-(p-1) correspond to a plurality of NAND strings NS-0 to NS-(p-1).

Each NAND string NS is connected to a common source line via a corresponding selection gate ST. Further, each NAND string NS is connected to the corresponding bit line BL via the corresponding selection gate DT.

The high voltage generator 7 boosts the power supply voltage under the control of the controller 6, and supplies a voltage corresponding to the boosted voltage to the CG driver 8. For example, the high voltage generator 7 has high voltage generating circuits 71 and 72 and a voltage control circuit 40 (refer to FIG. 8). The high voltage generating circuit 72 boosts the power supply voltage, and supplies a first voltage Vout-1 for setting the word line potential Vpgm (for example, about 18 V) corresponding to the selected memory cell to the write source. CG drive 8. The high voltage generating circuit 71 boosts the power supply voltage and supplies the boosted voltage to the voltage control circuit 40 and other circuits (not shown). The voltage control circuit 40 is supplied to the second voltage Vout-2 for setting the transfer potential Vpass (for example, about 10 V) to the unselected word line corresponding to the non-selected memory cell by using the boosted voltage during writing. CG drive 8.

Further, the high voltage generator 7 generates a plurality of well regions corresponding to the blocks BLK-0 to BLK-(n-1) according to an operation mode (writing, reading, erasing, etc.) (for example, The control signal WELL including the potential of the double well region of the n well and the p well and the potential of the source line is supplied to the column decoder 3.

The CG driver 8 is controlled by the controller 6 to generate a voltage for driving each word line using the voltage received from the high voltage generator 7. For example, when the CG driver 8 is in writing, the first voltage Vout-1' is generated so as to be substantially equal to the first voltage Vout-1. When the CG driver 8 is in writing, the second voltage Vout-2' is generated so as to be substantially equal to the second voltage Vout-2. The CG driver 8 supplies the generated voltage CG (for example, the first voltage or the second voltage) to the column decoder 3.

The column decoder 3 is connected to each of the word lines WL-0 to WL-(k-1) connected to the control electrodes of the respective memory cells MT in the NAND string NS. The column decoder 3 decodes the column address transmitted from the address register 9 and determines the selected word line and non-selection among the plurality of word lines WL-0~WL-(k-1), respectively. The address of the word line. Further, the column decoder 3 sets the potential of the selected word line to the program potential Vpgm (for example, about 18 V) by applying the first voltage to the selected word line, and applies the second voltage to the unselected word line. Non-selected word The potential of the line is set to the transfer potential Vpass (for example, about 10 V).

The sense amplifier block 4 has a plurality of pairs of sense amplifiers and data latches corresponding to the plurality of bit lines BL-0~BL-(p-1). Each pair of sense amplifiers and data latches are connected to corresponding NAND strings NS and bit lines BL via select gates AT. The read data detected by the sense amplifier is held as a data latch paired with the sense amplifier as, for example, binary data.

The row decoder 5 decodes the row address from the address register 9. Further, based on the result of the decoding, the row decoder 5 determines whether or not to transfer the data held in the data latch circuit to the data bus.

The I/O buffer 10 buffers the address, data, and instructions input from the I/O terminal. In addition, the I/O buffer 10 transfers the address to the address register 9, transfers the instruction to the instruction register, and transfers the data to the data bus.

Next, the relationship between the voltage control circuit 40 and each of the word lines WL-0 to WL-(k-1) will be described with reference to FIGS. 8 and 9. Fig. 8 is a view showing the configuration of the connection of the voltage control circuit 40 and the word lines WL-0 to WL-(k-1). Fig. 9 is a view showing temporal changes in the potentials of the word lines WL-0 to WL-2.

The high voltage generating circuit 72 generates a first voltage Vout-1 corresponding to a voltage for setting a word line setting program potential Vpgm (for example, about 18 V) corresponding to the selected memory cell, and supplies it to the CG driver. 8. The CG driver 8 generates the first voltage Vout-1' so as to be substantially equal to the level of the first voltage Vout-1 generated by the high voltage generating circuit 72. The first voltage Vout-1' is, for example, a voltage for setting a program potential Vpgm (for example, about 18 V) to a selected word line corresponding to the selected memory cell at the time of writing.

The high voltage generating circuit 71 supplies a boosted voltage to the voltage control circuit 40. The voltage control circuit 40 receives the boosted voltage generated by the high voltage generating circuit 71 as the input voltage Vin-2. The voltage control circuit 40 is a step-down voltage control circuit that steps down the input voltage Vin-2 from the input node and outputs the step-down voltage from the output node as an output voltage. (second voltage) Vout-2. The CG driver 8 outputs an output voltage Vout-2' so as to be substantially equal to the second voltage Vout-2. The output voltage Vout-2' is, for example, at the time of writing, for setting a voltage of a transfer potential Vpass (for example, about 10 V) to a non-selected word line corresponding to a non-selected memory cell.

The column decoder 3 has a plurality of selection gates WT1-0~WT1-(k-1), WT2-0~WT2-(k-1). A plurality of selection gates WT1-0~WT1-(k-1) are associated with the high voltage generating circuit 72, and the output node of the voltage control circuit 30 is electrically connected to the selected word line WL according to the decoding result of the column address. A plurality of selection gates WT2-0~WT2-(k-1) are associated with the voltage control circuit 40, and the output node of the voltage control circuit 40 is electrically connected to the non-selected word line WL according to the decoding result of the column address.

That is, during the write operation of the semiconductor memory device 1, the column decoder 3 transmits the first voltage Vout-1' (Vpgm) from the high voltage generating circuit 72 to the selected word line WL, and the voltage control circuit 40 is supplied from the voltage control circuit 40. The second voltage Vout-2' (Vpass) is transmitted to the non-selected word line WL. At this time, since the potential of the unselected word line WL is easily increased by the capacitive coupling of the selected word line WL and the unselected word line WL, the voltage control circuit 40 electrically connected to the unselected word line WL is The waveform of the output voltage is prone to overshoot.

For example, in the case shown in FIG. 9, at the time of the write operation of the semiconductor memory device 1, the selection gates WT1-1, WT2-0, and WT2-2 of the column decoder 3 are turned on. As a result, the first voltage Vout-1' (Vpgm) from the high voltage generating circuit 72 is transmitted to the selected word line WL-1, and the second voltage Vout-2' (Vpass) from the voltage control circuit 40 is transmitted. To the non-selected word lines WL-0, WL-2. At this time, since the potential of the unselected word lines WL-0 and WL-2 is easily increased by selecting the capacitive coupling of the word line WL-1 and the unselected word lines WL-0, WL-2, it is possible that The waveform of the output voltage of the voltage control circuit 40 electrically connected to the non-selected word lines WL-0, WL-2 generates an overshoot.

Further, according to the above, the high voltage generating circuits 71, 72 and the voltage control circuit 40 may generate or generate a voltage for the read operation instead of generating or generating the write operation power. Pressure. In this case, since the potential of the non-selected word lines WL-0 and WL-2 is easily increased by selecting the capacitive coupling of the word line WL-1 and the unselected word lines WL-0, WL-2, It is possible that an overshoot occurs in the waveform of the output voltage of the voltage control circuit 40 electrically connected to the non-selected word lines WL-0, WL-2.

When the waveform of the output voltage of the voltage control circuit 40 produces a significant overshoot, unnecessary stress is applied to the memory cell MT connected to the non-selected word lines WL-0, WL-2, which may result in a memory cell. The deterioration of MT is accelerated. Therefore, it is preferable to suppress the overshoot and suppress the application of unnecessary stress to the memory cell MT.

In the basic form, when an overshoot occurs, the charge of the output node Nout is discharged by the limiting current Ilim of the voltage control circuit 40 shown in FIG. 10, and the output voltage Vout is directed toward the target value. FIG. 10 is a view showing the configuration of the voltage control circuit 40.

Specifically, the voltage control circuit 40 is a step-down type voltage control circuit that steps down the voltage Vin input to the input node Nin substantially in line with the potential of the target value Vt, and self-outputs the step-down voltage Vout. Node Nout output. The voltage control circuit 40 includes an NMOS transistor (first NMOS transistor) 41, an NMOS transistor (second NMOS transistor) 42, an operational amplifier 43, and resistance elements R1 to R3.

The NMOS transistor 41 is disposed between the node N1 on the input node Nin side and the node N2 on the output node Nout side. The NMOS transistor 41 controls the current flowing from the input node Nin to the output node Nout when the voltage control circuit 40 steps down the voltage Vin. The NMOS transistor 41 has its drain connected to the input node Nin via the node N1, the source connected to the output node Nout via the node N2, and the gate connected to the input node Nin via the node N3, the resistive element R3, and the node N1.

The NMOS transistor 42 is disposed between the node N1 on the input node Nin side and the reference potential (first reference potential) Vr1. The NMOS transistor 42 controls the gate voltage Vgate of the NMOS transistor 41 when the voltage control circuit 40 steps down the voltage Vin. That is, the NMOS transistor 42 controls the voltage Vin of the input node Nin by the resistance element R3 by controlling the gate current thereof. The voltage drop amount is thereby controlled, thereby controlling the gate voltage Vgate of the NMOS transistor 41 (the voltage of the node N3). The NMOS transistor 42 has its drain connected to the input node Nin via the node N3, the resistive element R3, and the node N1, the source connected to the reference potential Vr1, and the gate connected to the output terminal 433 of the operational amplifier 43. The reference potential Vr1 is a potential corresponding to the gate voltage Vgate at which the NMOS transistor 41 is turned off when the NMOS transistor 42 is strongly turned on, for example, the ground potential GND.

The operational amplifier 43 adjusts the bias voltage of the gate of the NMOS transistor 42 such that the potential of the output node Nout substantially matches the target value Vt when the voltage control circuit 40 steps down the voltage Vin. In other words, the operational amplifier 43 adjusts the bias voltage of the gate of the NMOS transistor 42 such that the difference between the potential of the reference node Nf and the reference potential Vref substantially coincides with zero. The operational amplifier 43 has its non-inverting input terminal (+) 431 connected to the reference node Nf, the inverting input terminal (-) 432 connected to the reference potential Vref, and the output terminal 433 connected to the gate of the NMOS transistor 42. The node between the node Nf system node N2 and the reference potential Vr2 is referenced. The reference potential Vr2 is a potential lower than the target value Vt and the reference potential Vref, for example, the ground potential GND.

The resistance elements R1 and R2 divide the voltage of the output node Nout by the ratio of the resistance values to the potential of the reference node Nf. The resistance element R1 has one end connected to the reference potential Vr2 and the other end connected to the reference node Nf. The resistance element R2 has one end connected to the reference node Nf and the other end connected to the output node Nout via the node N2.

The resistance element R3 defines the amount of voltage drop of the NMOS transistor 42 and the voltage drop of the node N3 with respect to the voltage Vin of the input node Nin by the resistance value thereof. One end of the resistive element R3 is connected to the gate of the NMOS transistor 41 and the drain of the NMOS transistor 42 via the node N3, and the other end is connected to the drain of the output node Nin and the NMOS transistor 41 via the node N1.

According to the configuration shown in FIG. 10, when the overshoot of the output voltage Vout occurs, the charge of the output node Nout is discharged via the resistance elements R1, R2, and the output voltage is output. Vout is stable when substantially coincident with the target value Vt. Fig. 11 is a waveform diagram showing the operation of the voltage control circuit 40.

At the timing t0 shown in FIG. 11, when, for example, the write operation of the semiconductor memory device 1 is started, the input voltage Vin rises from the reference level (GND level). At the same time, the gate voltage Vgate of the NMOS transistor 41 starts to rise, and the NMOS transistor 41 becomes a half-on state and functions as a resistor equivalently, and the drain current starts to gradually rise.

Since the drain current of the NMOS transistor 41 is shunted at the node N2 and one of the drain currents is partially charged to the output node Nout, the potential of the output node Nout (output voltage Vout) continues to rise.

Further, the other part of the drain current flows as the limiting current Ilim for limiting the potential of the output node Nout to the target value Vt to the reference potential Vr2 via the resistance element R2, the reference node Nf, and the resistance element R1. At this time, the gate current of the NMOS transistor 41 continues to increase as the gate voltage Vgate of the NMOS transistor 41 rises. Therefore, the limiting current Ilim also continues to increase, and the potential Ilim×R1 of the reference node Nf continues to rise from the reference potential Vr2 close to the reference potential Vref. That is, since the potential of the reference node Nf at this time is Ilim × R1 < Vref, the current system Ilim < Vref / (R1) is limited.

When the potential Ilim×R1 of the reference node Nf continues to rise in a manner close to the reference potential Vref, the bias voltage supplied from the output terminal 433 of the operational amplifier 43 to the gate of the NMOS transistor 42 is from the reference level (ground potential). The way to approach the intermediate potential begins to rise. When the bias voltage starts to rise, the NMOS transistor 42 becomes a half-on state and functions as a resistor equivalently, and the drain current starts to gradually rise.

During the period from t0 to t1, the input voltage Vin follows the operation from the reference level (GND level) to the target value Vt0. During the period from t0 to t2, the gate voltage Vgate of the NMOS transistor 41, The output voltage Vout and the limiting current Ilim continue to rise, respectively.

That is, the output terminal 433 of the operational amplifier 43 is supplied to the gate of the NMOS transistor 42. The bias voltage of the pole rises to the intermediate potential, the gate voltage Vgate of the NMOS transistor 41 rises, and the drain current of the NMOS transistor 41 increases. Therefore, the amount of charge charged to the output node Nout increases, the potential of the output node Nout (output voltage Vout) continues to rise to the target value Vt, and the limit current Ilim continues to increase.

At the timing t2, when the overshoot of the potential (output voltage Vout) of the output node Nout exceeds the target value Vt, since the limit current Ilim exceeds the value Vref/(R1), the potential of the reference node Nf becomes Ilim×R1>Vref, so The bias voltage supplied from the output terminal 433 of the operational amplifier 43 to the gate of the NMOS transistor 42 is greatly increased from the intermediate potential. In response to this, the NMOS transistor 42 is in a state of being strongly turned on from the half-on state, and the drain current is greatly increased. As a result, the voltage drop amount due to the resistance element R3 is remarkably increased, and the gate voltage Vgate of the NMOS transistor 41 is suddenly reduced, so that the NMOS transistor 41 is turned off. Accordingly, since the charge charged to the output node Nout is continuously discharged to the reference potential Vr2 via the resistance element R2, the reference node Nf, and the resistance element R1, the limit current Ilim further continues to increase.

At the timing t3, when the discharge of the charge of the output node Nout continues, the amount of voltage drop caused by the discharge exceeds the amount of rise of the voltage caused by the overshoot (refer to FIG. 9), and the potential of the output node Nout (output voltage Vout) Start to gradually reduce. At this time, the NMOS transistor 42 continues to be in a state of being strongly turned on. Although the gate voltage Vgate of the NMOS transistor 41 is maintained near the reference potential Vr1, the limiting current Ilim continues to gradually decrease as the output voltage Vout decreases.

At the timing t4, when the potential of the output node Nout (output voltage Vout) is decreased to the target value Vt, the limit current Ilim is substantially equal to the value Vref/(R1), and the potential of the reference node Nf becomes Ilim × R1 ≒ Vref. Therefore, the bias voltage supplied from the output terminal 433 of the operational amplifier 43 to the gate of the NMOS transistor 42 is greatly reduced to return to the intermediate potential. Correspondingly, the NMOS transistor 42 returns from the state of being strongly turned on to the half-on state, and the drain current thereof returns to the same value as the timing t2. Thereby, the voltage drop caused by the resistance element R3 is returned Returning to the same value as the timing t2, the gate voltage Vgate of the NMOS transistor 41 returns to the same value as the timing t2. Therefore, the NMOS transistor 41 returns to the half-on state. In response to this, the output node Nout is charged with a charge whose potential is the target value Vt, and the remaining charge is continuously discharged to the reference potential Vr2 via the resistance element R2, the reference node Nf, and the resistance element R1. Thereby, the limiting current Ilim is stabilized at a level substantially equal to the value Vref/(R1), and the output voltage Vout is stabilized in a state substantially coincident with the target value Vt.

In the basic form, as shown in FIG. 11, the discharge time T from which the output voltage Vout is stabilized at the target value Vt due to the overshoot from the timing t2 is dependent on the resistance values of the resistance elements R1 and R2 and the output node Nout. Since the time constant of the parasitic capacitance Cout is determined, there is a tendency to become longer. This tendency is remarkable because the resistance value of the resistance elements R1 and R2 is larger as the time constant is larger and the discharge current is smaller.

On the other hand, when the resistance values of the resistance elements R1, R2 are greatly reduced, since the discharge current can be increased by reducing the time constant, the length of the discharge time T can be shortened. However, in the steady operation after the overshoot subsides, since the value of the limiting current Ilim necessary for setting the potential of the output node Nout (output voltage Vout) to the target value Vt is significantly increased, the power consumption of the voltage control circuit 40 The possibility of increase is higher. That is, the shortening of the discharge time and the reduction of the power consumption tend to coexist.

Therefore, in the present embodiment, as shown in FIG. 1, the voltage control circuit 40i is provided with an adjustment circuit that forms a discharge path when the potential of the output node exceeds the target value, and the potential at the output node is less than or equal to the target. In the case of a value, the discharge path is blocked. Therefore, the shortening of the discharge time and the reduction of the power consumption are coexistent. FIG. 1 is a view showing the configuration of the voltage control circuit 40. Hereinafter, a description will be given focusing on a portion different from the basic form.

Specifically, the voltage control circuit 40 further has an adjustment circuit 44i. When the potential of the output node Nout exceeds the target value Vt, the adjustment circuit 44i electrically forms the discharge path 446 from the first line 444 to the second line 445. The first line 444 is connected to the source of the NMOS transistor 41. The line between the pole and the node N2. The second line 445 is a line connecting the node N3 and the drain of the NMOS transistor 42. The adjustment circuit 44i electrically blocks the discharge path 446 from the first line 444 to the second line 445 when the potential of the output node Nout is less than or equal to the target value Vt.

The adjustment circuit 44i has a plurality of rectifier transistors 441 to 443. A plurality of rectifying transistors 441 to 443 are connected in series between the first line 444 and the second line 445. Each of the rectifying transistors 441 to 443 is connected such that the first line 444 side functions as an anode and the second line 445 side functions as a cathode. The rectifier transistor 441 has a drain connected to the gate and the first line 444, and a source connected to the drain of the rectifier transistor 442. The rectifying transistor 442 has its drain connected to the source of the gate and the rectifying transistor 441, and the source connected to the drain of the rectifying transistor 443. The rectifier transistor 443 has its drain connected to the source of the gate and the rectifying transistor 442, and the source connected to the second line 445.

Further, in the present embodiment, as shown in Fig. 2, an operation different from the basic form is performed in the following points.

During the period before the timing t2i, the respective rectifier transistors 441 to 443 of the adjustment circuit 44i are turned off. That is, the adjustment circuit 44i electrically blocks the discharge path 446 from the first line 444 to the second line 445.

At the timing t2i, when the overshoot of the potential (output voltage Vout) of the output node Nout exceeds the target value Vt, since the limit current Ilim exceeds the value Vref/(R1), the potential of the reference node Nf becomes Ilim×R1>Vref, so The bias voltage supplied from the output terminal 433 of the operational amplifier 43 to the gate of the NMOS transistor 42 is greatly increased from the intermediate potential. In response to this, the NMOS transistor 42 is in a state of being strongly turned on from the half-on state, and the drain current is greatly increased. Thereby, the amount of voltage drop caused by the resistance element R3 is remarkably increased, and the gate voltage Vgate of the NMOS transistor 41 is drastically reduced.

At this time, each of the rectifying transistors 441 to 443 of the adjustment circuit 44i is turned on as the gate voltage Vgate of the NMOS transistor 41 is suddenly reduced. That is, the adjustment circuit 44i is electrically formed in the discharge path 446 from the first line 444 to the second line 445. Corresponding to this, charging to output The electric charge of the node Nout is continuously discharged to the reference potential Vr1 as a discharge current Idis via the plurality of rectifying transistors 441 to 443 and the NMOS transistor 42.

Further, since the gate voltage Vgate of the NMOS transistor 41 is suddenly reduced, the NMOS transistor 41 is turned off. In response to this, the charge charged to the output node Nout is continuously discharged to the reference potential Vr2 via the resistance element R2, the reference node Nf, and the resistance element R1 as the limiting current Ilim.

That is, as the discharge path of the charge charged to the output node Nout, in addition to the first discharge path of the output node Nout → the node N2 → the resistance element R2 → the reference node Nf → the resistance element R1 → the reference potential Vr2, the output node Nout is also ensured. → Node N2 → rectification transistor 441 → rectification transistor 442 → rectification transistor 443 → NMOS transistor 42 → second discharge path of reference potential Vr1. The discharge current can be easily increased by securing the first discharge path and the second discharge path.

At the timing t3i, when the discharge of the charge of the output node Nout continues, the amount of voltage drop caused by the discharge exceeds the amount of rise of the voltage caused by the overshoot (refer to FIG. 9), and the potential of the output node Nout (output voltage Vout) Start to gradually reduce. At this time, the NMOS transistor 42 continues to be strongly turned on, and the gate voltage Vgate of the NMOS transistor 41 is maintained near the reference potential Vr1, but each of the discharge current Idis and the limit current Ilim is accompanied by a decrease in the output voltage Vout. And continue to gradually decrease.

At the timing t4i, when the potential of the output node Nout (output voltage Vout) is reduced to the target value Vt, since the limiting current Ilim is substantially equal to the value Vref/(R1), the potential of the reference node Nf becomes Ilim×R1≒Vref, so the self-operation The bias voltage supplied to the gate of the NMOS transistor 42 by the output terminal 433 of the amplifier 43 is greatly reduced to return to the intermediate potential.

In response to this, each of the rectifying transistors 441 to 443 of the adjusting circuit 44i is returned to the off state. That is, the adjustment circuit 44i returns to the state of electrically blocking the discharge path 446 from the first line 444 to the second line 445.

Moreover, the NMOS transistor 42 returns from the state of being strongly turned on to the half-on state, The drain current returns to the same value as the timing t2i. Thereby, the voltage drop amount caused by the resistance element R3 returns to the same value as the timing t2i, and the gate voltage Vgate of the NMOS transistor 41 returns to the same value as the timing t2i, so the NMOS transistor 41 returns to the half-on state. . In response to this, the output node Nout is charged with a charge whose potential is the target value Vt, and the remaining charge is continuously discharged to the reference potential Vr2 via the resistance element R2, the reference node Nf, and the resistance element R1. Thereby, the limiting current Ilim is stabilized at a level substantially equal to the value Vref/(R1), and the output voltage Vout is stabilized in a state substantially coincident with the target value Vt.

As described above, in the present embodiment, in the voltage control circuit 40i, when the potential (output voltage Vout) of the output node Nout exceeds the target value Vt, the adjustment circuit 44i is electrically formed from the first line 444. The discharge path 446 to the second line 445. Therefore, when the output voltage Vout is overshooted, as the discharge path of the charge charged to the output node Nout, a plurality of discharge paths including the discharge path 446 can be ensured except for the discharge path having the same basic configuration. It is easy to increase the discharge current. As a result, the resistance value of the resistance elements R1, R2 is not greatly reduced, and the discharge time T' can be significantly shortened compared with the discharge time T of the basic form.

Further, when the potential (output voltage Vout) of the output node Nout is equal to or lower than the target value Vt, the adjustment circuit 44i electrically blocks the discharge path 446 from the first line 444 to the second line 445. Thereby, the value of the limiting current Ilim necessary for setting the potential (output voltage Vout) of the output node Nout to the target value Vt can be suppressed during the constant operation after the overshoot subsides, so that the voltage control circuit 40 can be reduced. It consumes electricity.

Therefore, according to the present embodiment, the reduction in the discharge time and the reduction in the power consumption can be coexisted.

Further, in the present embodiment, in the adjustment circuit 44i, a plurality of rectifying transistors 441 to 443 are connected in series between the first line 444 and the second line 445. Each of the rectifier transistors 441 to 443 has a function of using the first line 444 side as an anode and the second line 445 side as a second line 445 side. The cathode is connected in a manner that functions as a diode. Thereby, when the potential (output voltage Vout) of the output node Nout exceeds the target value Vt, the discharge path 446 from the first line 444 to the second line 445 is electrically formed, and the potential of the output node Nout (output voltage Vout) When it is less than or equal to the target value Vt, the discharge path 446 from the first line 444 to the second line 445 is electrically blocked, and the adjustment circuit 44i can be configured in this manner.

In FIG. 1, although the number of the rectifier transistors 441 to 443 of the adjustment circuit 44i is exemplarily shown to be three, the number of the rectifier transistors 441 to 443 may be two or less, or may be larger than Equal to 4.

Alternatively, instead of the resistance elements R1, R2, the potential of the reference node Nf may be defined by the capacitance elements C1, C2 as shown in FIG. The capacitive elements C1 and C2 divide the voltage of the output node Nout by the ratio of their capacitance values to the potential of the reference node Nf. The capacitive element C1 has one end connected to the reference potential Vr2 and the other end connected to the reference node Nf. The capacitive element C2 has one end connected to the reference node Nf and the other end connected to the output node Nout via the node N2. In the configuration shown in FIG. 3, by discharging the charge charged to the output node Nout to the capacitive elements C1 and C2, the same operation as in the case where the limiting current Ilim flows through the resistive elements R1 and R2 can be realized equivalently.

Alternatively, instead of the resistance elements R1, R2, the potential of the reference node Nf may be defined by the bias transistors BT1, BT2 as shown in FIG. Further, a bias transistor BT3 may be used instead of the resistance element R3. The bias transistors BT1, BT2, and BT3 supply bias voltages that are adjusted so as to function equivalently as the resistance elements R1, R2, and R3, respectively, to the gate. The bias transistor BT1 has its source connected to the reference potential Vr2 and its drain connected to the reference node Nf. The bias transistor BT2 has its source connected to the reference node Nf and its drain connected to the output node Nout via the node N2. The bias transistor BT3 has its source connected to the node N3 and its drain connected to the node N1.

Alternatively, in the voltage control circuit 40j, the adjustment circuit 44j may have a plurality of diodes 441j to 443j instead of the plurality of rectifier transistors 441 to 443 (see FIG. 1). plural The diodes 441j to 443j are connected in series between the first line 444 and the second line 445. Each of the diodes 441j to 443j has an anode connected to the first line 444 side and a cathode connected to the second line 445 side. The diode 441j has an anode connected to the first line 444 and a cathode connected to the diode 442j. The diode 442j has an anode connected to the diode 441j and a cathode connected to the diode 443j. The diode 443j has an anode connected to the diode 442j and a cathode connected to the second line 445. Thereby, when the potential (output voltage Vout) of the output node Nout exceeds the target value Vt, the discharge path 446 from the first line 444 to the second line 445 is electrically formed, and the potential of the output node Nout (output voltage Vout) When it is less than or equal to the target value Vt, the discharge path 446 from the first line 444 to the second line 445 is electrically blocked, and the adjustment circuit 44j can be configured in this manner.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention or its modifications are intended to be included within the scope of the invention and the scope of the invention disclosed herein.

40i‧‧‧ voltage control circuit

41‧‧‧NMOS transistor

42‧‧‧NMOS transistor

43‧‧‧Operational Amplifier

44i‧‧‧Adjustment circuit

431‧‧‧ Non-inverting input terminal

432‧‧‧Reverse input terminal

433‧‧‧Output terminal

441‧‧‧Rectifying transistor

442‧‧‧Rectification transistor

443‧‧‧Rectifying transistor

444‧‧‧1st line

445‧‧‧2nd line

446‧‧‧discharge path

GND‧‧‧ Ground potential

Idis‧‧‧discharge current

Ilim‧‧‧Limit current

N1‧‧‧ node

N2‧‧‧ node

N3‧‧‧ node

Nf‧‧‧ reference node

Nin‧‧‧ input node

Nout‧‧‧ output node

R1‧‧‧resistive components

R2‧‧‧resistive components

R3‧‧‧resistive components

Vgate‧‧‧ gate voltage

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vr1‧‧‧ reference potential

Vr2‧‧‧ reference potential

Vref‧‧‧ reference potential

Claims (9)

A voltage control circuit comprising: a first NMOS transistor having a drain connected to a first node on an input node side, a source connected to a second node on an output node side, and a gate connected to the first node via a third node a second NMOS transistor having a drain connected to the third node, a source connected to the first reference potential, and an operational amplifier having a non-inverting input terminal connected between the second node and the second reference potential a reference node, wherein the inverting input terminal is connected to the reference potential, the output terminal is connected to the gate of the second NMOS transistor, and the adjusting circuit is formed to be self-connected when the potential of the output node exceeds a target value A source line of the NMOS transistor and a first line of the second node are connected to a discharge path of the second line of the third node and the drain of the second NMOS transistor. The voltage control circuit of claim 1, wherein the first reference potential is associated with a gate potential at which the first NMOS transistor is turned off; the second reference potential is lower than the reference potential; and the reference potential is related to the target The value corresponds. The voltage control circuit of claim 1, wherein the adjustment circuit blocks a discharge path from the first line to the second line when a potential of the output node is less than or equal to the target value. The voltage control circuit of claim 1, wherein the adjustment circuit includes: a rectifying transistor, wherein the first line side functions as an anode, and The diodes are connected such that the second line side functions as a cathode. The voltage control circuit of claim 4, wherein the adjustment circuit comprises: a plurality of the rectifying transistors, wherein the plurality of rectifying transistors are connected in series between the first line and the second line. The voltage control circuit of claim 1, wherein the adjustment circuit includes a diode having an anode connected to the first line side and a cathode connected to the second line side. The voltage control circuit of claim 6, wherein the adjustment circuit comprises: a plurality of the diodes connected in series between the first line and the second line. A semiconductor memory device comprising: a plurality of memory cells connected to a plurality of word line lines; and a voltage control circuit of claim 1 for controlling at least a portion of the word lines of the plurality of word lines The potential. The semiconductor memory device of claim 8, further comprising: a high voltage generator coupled to said input node; and a CG driver coupled between said output node and said word line for generating said word The voltage of the yuan line.