TW201533722A - Phase lock loop based display driver for driving light emitting device and related display apparatus generating internal clock based on external clock - Google Patents

Abstract

Described in example embodiments herein are techniques for reducing requirement of a driver for external high frequency clock signals. In accordance with one example embodiment, a driver for driving a light emitting device includes: a data register and a phase lock loop. The data register is utilized for storing a driving data for driving the light emitting device. The phase lock loop is utilized for generating a second signal according to an input first signal. The operation of the data register is controlled according to one of the input signal and the second signal, while the driving of the light emitting device is controlled according to the other of the input signal and the second signal.

Description

Using an external clock based on a phase-locked loop to generate internal illumination of the drive Component and related display driver and method

The present invention relates to drive technology for displays, and more particularly to a drive and method that reduces the need for external high frequency clock signals, and related displays.

With the advancement of technology, the display technology used in displays has been continuously improved and innovated, from the early cathode ray tube, to the later liquid crystal, plasma and even luminescence. Display technologies such as light emitting diodes (LEDs), the development of these display technologies is nothing more than lower energy consumption, better brightness, contrast, and even color reproduction. In this case, since the light-emitting diode has self-luminous characteristics, it does not need to be illuminated by an additional backlight, and it does not have the problem of aperture ratio of the liquid crystal display technology. Therefore, based on the display technology The designed LED display has a better advantage in terms of brightness and size.

A simplified architectural diagram of a conventional LED display is shown in FIG. As shown in the figure, the LED display 1 includes a plurality of LEDs 11 to MN, which are respectively driven by the LED drivers 10 to M0, and are further illuminated. The LED drivers 10~M0 respectively supply current to each LED and control the length of time that current is supplied to each LED. The LEDs exhibit different brightnesses over time. Since each LED corresponds to a specific primary color (such as R, G or B), by controlling the current supply The length, adjustable and the intensity of the different primary colors allow the LED display 1 to display a full color picture.

Taking the LED driver 10 as an example, it includes LED11~LED1N according to the input terminal DI. The signal DIN of the driving data is generated to generate a pulse time for supplying current to LED11~LED1N. Because the signal DIN is transmitted in sequence, the output of the controller 50 includes the driving data for driving all the LEDs 11~LEDMN, so the LED driver 10 only drives some of the bits in the signal DIN to drive the LEDs 11~LED1N and through the output. The DO transmits the remaining bits in the signal DIN to the next LED driver 20. Thereafter, the LED driver 20 extracts a portion of the bit corresponding to the driving data of the LEDs 21 to 2N from the signal DIN, drives it, and so on.

Please refer to FIG. 2, which is a simple functional side of the LED driver 10 in FIG. Block diagram. As shown, the LED driver 10 includes a drive unit 12, a shift register 13, and a latch 14. The shift register 13 receives and stores the signal DIN provided by the controller 50 bit by bit, and performs a shift operation according to the signal DCLK generated by the controller 50. Finally, only the driving data corresponding to the LEDs 11 to 1N are retained. The bit is transmitted from the output terminal DO by bit by bit in a manner of shifting the driving data corresponding to the other LEDs 21~LEDMN in the signal DIN. Generally, the signal DCLK is a continuous pulse sequence (clock signal), and the data register 13 moves the bit right in the register in the rising edge or the falling edge of each pulse, thereby turning the signal into the DIN. The other bits are transferred to the shift registers in the LED drivers 20~M0.

When the bits stored in the shift register 13 correspond exactly to the LEDs 11~LED1N Drive data, controller 50 will issue a signal LAT, requesting latch 14 to latch the bits stored in shift register 13. Next, the latch 14 transfers these bits to the drive unit 12, causing the drive unit 12 to drive the LEDs 11 - 1 1N based on these bits.

It is assumed that the driver 12 is an N 16-bit pulse width modulation (PWM) driving unit whose function is to generate an average according to the PWM value of 16 bits or the sum is equal to 1 to 65535 (2 ¹⁶ -1). The pulse width per unit time. The driving unit 12 performs brightness control of 65536 steps for each LED according to N 16-bit values (m=N x 16) in the bit latched by the latch 14. The driving unit 12 determines the length of time for supplying current according to the 16-bit value corresponding to each LED, from 1 unit time to a maximum of 65535 unit times. The length of the unit time is determined by the signal GCLK generated by the controller 50. Similar to the signal DCLK, the signal GCLK is also a continuous pulse sequence (clock signal), and the driving unit 12 performs the time interval between the rising edge and the rising edge of the continuous pulse in the signal GCLK or between the falling edge and the falling edge. For a reference time, the actual length of a unit time is determined, and the value of the 16-bit corresponding to each LED is modulated with the unit time to determine the length of time for supplying current to each LED.

However, in such an architecture, each LED driver except the previous LED In addition to the signal DIN outputted by the shift register, the driver must also receive the signal GCLK, the signal DCLK, and the signal LATCH from the controller 50 in order to properly drive each LED. If the display's refresh rate is increased, the frequency of the signal GCLK needs to be higher, so the LED driver's need for an external high frequency signal (GCLK) is necessary.

In order to solve the problem of the high frequency refresh rate display (GCLK and DCLK) of the driver in the conventional architecture, especially for the high refresh rate display, the present invention provides an innovative driver architecture to reduce the high frequency clock signal. Demand. Wherein, the present invention sets a phase-locked loop in the driver and generates another clock signal (such as GCLK) internally based on a clock signal (such as DCLK) generated by the external controller, thereby reducing external high frequency. The need for a clock signal. In this way, the number of signal pins required for the driver to receive the external high-frequency clock signal can be reduced, thereby reducing the manufacturing cost of the display, the circuit complexity, and reducing the transmission of the high-frequency clock signal on the circuit board. Electromagnetic interference (EMI) caused by the electromagnetic interference.

An embodiment of the present invention provides a driver for driving a light emitting element, the package thereof Contains: a data register and a phase-locked loop. The data register is used to store one of the driving materials required to drive the light-emitting element. The phase locked loop is configured to generate a second signal according to an input signal. The operation of the data register is controlled according to one of the input signal and the second signal, and the driving of the light-emitting element is based on the other of the input signal and the second signal. control.

Another embodiment of the present invention provides a driver for driving a light emitting device The method includes a phase locked loop. The method includes: receiving an input signal; and utilizing the phase locked loop to generate a second signal according to the input signal. The operation of the data register is controlled according to one of the input signal and the second signal, and the driving of the light-emitting element is based on the other of the input signal and the second signal. control.

Yet another embodiment of the present invention provides a display including: a plurality of hair An optical component, a plurality of drivers, and a controller. The plurality of drivers are respectively coupled to the plurality of light emitting elements and configured to drive the plurality of light emitting elements. The controller is configured to provide at least one input signal to the plurality of drivers. Each driver includes: a data register and a phase locked loop. The data register is used to store one of the driving materials required to drive the light-emitting element. The phase locked loop is configured to generate a second signal by using a first signal, wherein the first signal is generated according to the input signal. Furthermore, the operation of the data register is controlled according to one of the input signal and the second signal, and the driving of the light emitting element is based on the other of the input signal and the second signal. controlled.

1, 600‧‧‧ display

LED11~LEDMN‧‧‧Light Emitting Diode

10~M0, 100~M00, 100’‧‧‧ drive

50, 500‧‧‧ controller

12, 120‧‧‧ drive unit

13, 130‧‧‧ register

14, 140‧‧‧ Latches

110‧‧‧ phase-locked loop

112, 114‧‧‧ signal processing device

610, 620‧ ‧ steps

Figure 1 is a simplified architectural diagram of a conventional LED display.

Figure 2 is a simplified functional block diagram of the LED driver in Figure 1.

Figure 3 is a simplified functional block diagram of one embodiment of the drive of the present invention.

Figure 4 is a schematic diagram showing the architecture of one of the phase-locked loops and related signal processing devices of the present invention.

Figure 5 is a simplified functional block diagram of another embodiment of the drive of the present invention.

Figure 6 is a block diagram showing another embodiment of the phase locked loop and related signal processing device of the present invention.

Figure 7 is a block diagram showing an embodiment of a display of the present invention.

Figure 8 is a flow chart of one embodiment of the method of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

Figure 3 is a block diagram showing the simplified function of an embodiment of the driver of the present invention. Compared with the conventional driver shown in FIG. 2, the driver 100 of the present invention only needs to receive the signal DCLK, the signal LATCH, and the signal DIN from the controller 500 without receiving the signal GCLK, thereby reducing the external high frequency clock. Signal demand. The driver 100 includes a phase locked loop 110, a driving unit 120, The data register 130 and the latch 140 are used to drive the LEDs 11 to 1 1N according to the signal DIN. It should be noted that the number of LEDs in the drawings is for illustrative purposes only and is not a limitation of the invention. For example, in other embodiments of the present invention, the LEDs driven by the driver 100 may be arranged in an array, for example, one LED array includes a plurality of parallel LED strings, and each LED string includes multiple LEDs in series.

The data register 130 receives the signal DIN provided by the controller 500, and performs a shift operation according to the signal DCLK generated by the controller 500, and receives each bit in the signal DIN one by one, and the reserved signal DIN corresponds to The LEDs of the driving data of the LEDs 11 to 1N are transmitted, and the driving data of the LEDs corresponding to the driving of other drivers (not shown) in the signal DIN are transmitted. In an embodiment of the invention, the data register 130 can be a shift register. However, this is not a limitation of the present invention, and any circuit that is equivalent in function and can retain part of the signal DIN to transfer the rest to other drivers is also an implementation scope of the present invention.

When the bit stored in the data register 130 corresponds to the driving data of the LED 11~LED1N, the controller 500 generates a signal LAT to the driver 100, and stores the data stored in the data register 130 through the latch 140. The bits are latched to transfer these bits to the drive unit 120. The driving unit 120 controls the brightness of each LED according to the bit value of each LED in the bit latched by the latch 140. And, according to the period of the signal GCLK or the time interval between the rising edge and the rising edge of the continuous pulse or between the falling edge and the falling edge (that is, the frequency of the signal GCLK), a reference time is determined, and the reference time is used. It is used as the unit time to supply current to the LED, where the length of the reference time may be equal to the length of the unit time, or there is a proportional relationship. The final determined unit time will be further modulated with the corresponding bit value for each LED, and the driver 100 will thereby be able to control the length of time that current is supplied to each LED.

In this embodiment, the signal GCLK is provided by the phase-locked loop 110. The phase-locked loop 110 uses the signal DCLK as a reference signal to perform a phase-locked operation to generate the signal GCLK. With the proper design of the phase-locked loop 110 (eg, fractional-N PLL), the frequency of the signal GCLK generated by the phase-locked loop 110 can be an integer multiple of the signal DCLK, or a non-integer multiple. In this way, although the driver 100 does not receive the signal GCLK from the external controller, the frequency of the generated signal GCLK can be sufficient to cover all possible frequencies by the integer multiple or non-integer multiple of the frequency adjustment capability of the phase-locked loop 110. Meet the needs of different applications (such as refresh rate). This is because in different applications, the driver 100 may need to provide brightness control of different PWM orders, so the length of the unit time for supplying current to the LED will also be different, through the non-integer multiple of the frequency adjustment capability of the phase locked loop 110. The driver 100 can determine a plurality of different lengths of unit time according to different needs.

In the embodiment shown in FIG. 3, the phase-locked loop 110 directly generates the signal GCLK according to the signal DCLK provided by the controller 500, and supplies the signal GCLK to the driving unit 120 for LED driving. However, in order to further improve the frequency coverage capability of the phase-locked loop 110, in other embodiments of the present invention, it may be additionally adjusted by other signal processing devices (usually a frequency divider that performs a power-off of 2). The frequency of the signal DCLK, and the frequency-adjusted signal is sent to the phase-locked loop 110 to generate the signal GCLK, or the frequency of the signal generated by the phase-locked loop 110 is adjusted, and then the frequency is adjusted (usually the power of 2) The signal of the frequency division is used as the signal GCLK, or both of them are parallel. Please refer to the example shown in Figure 4 for such an embodiment. In this example, the input end of the phase-locked loop 110 is coupled to the first signal processing device 112. The first signal processing device 112 first adjusts the frequency of the signal DCLK to generate the first signal CLK1. Then, the phase locked loop 110 uses the first signal CLK1 as a reference signal, performs a phase lock operation, and generates a second signal CLK2. The second signal processing device 114 further adjusts the frequency of the second signal CLK2 to generate the signal GCLK. Although the above embodiment uses two signal processing devices 112 and 114 to process the signal input to the phase-locked loop 110 and the signal output by the phase-locked loop 110, this is not a limitation of the present invention. In other embodiments, only the first signal processing device 112 and the second message may be included. One of the number of processing devices 114, but not both.

In addition, in an embodiment of the present invention, the first signal processing device 112 and the second signal processing device 114 may be a frequency divider (but not limited) that performs a power-off of 2, and divides the individual input signals. frequency. Therefore, the signal shown in Fig. 4 may have the following relationship in frequency: fCLK2 = (fDCLK/2 ^K ) × Q; fGCLK = fCLK2 / 2 ^L ; fCLK2 = fCLK1 × Q; (where K, L are positive An integer, Q is an integer greater than or equal to one, or a non-integer greater than one, fCLK1 is the frequency of signal CLK1, fCLK2 is the frequency of signal CLK2, fDCLK is the frequency of signal DCLK, and fGCLK is the frequency of signal GCLK. It can be seen from the above relationship that the phase-locked loop 100 of the present invention can provide more kinds of frequency selections through the assistance of the first signal processing device 112 and/or the second signal processing device 114 under appropriate parameter selection, and more The frequency required for the signal GCLK in different applications is completely covered, enabling the driver 100 to more precisely control the unit time required to drive the light-emitting elements.

In addition, although in the above description, the phase-locked loop 110 or the first signal processing device 112 and the second signal processing device 114 generate the signal GCLK based on the signal DCLK, in other embodiments of the present invention, Signal GCLK is used to generate signal DCLK. Please refer to the embodiments shown in Figures 5 and 6. In this embodiment, the phase locked loop 110 in the driver 100' generates the signal DCLK according to the signal GCLK provided by the controller 500. At this time, the driving unit 120 performs LED driving based on the signal GCLK provided by the controller 500, and the data register 130 receives the signal DCLK generated by the phase locked loop 110 to perform a shift operation on the signal DIN. The phase-locked loop 110 can also pre-adjust the frequency of the signal GCLK through the assistance of an additional signal processing device, and the frequency-adjusted signal is sent to the phase-locked loop 110 to generate the signal DCLK, or the adjustment is generated by the phase-locked loop 110. The frequency of the signal, and then adjust the frequency (usually the second power of 2) The frequency signal is used as the signal DCLK, or both.

As shown in Fig. 6, in this embodiment, the frequency of the signal will have the following relationship: fCLK2 = (fGCLK/2 ^K ) × Q; fDCLK = fCLK2 / 2 ^L ; fCLK2 = fCLK1 × Q; (where K L is a positive integer, Q is an integer greater than one or equal to one, or a non-integer greater than one, fCLK1 is the frequency of signal CLK1, fCLK2 is the frequency of signal CLK2, fDCLK is the frequency of signal DCLK, and fGCLK is signal GCLK Frequency of).

Fig. 7 is a diagram showing an LED display 600 implemented on the basis of the driver 100 shown in Fig. 3 or Fig. 5 or the driver 100'. As shown, the display 600 includes a plurality of light-emitting elements LED11-LEDMN and is driven by drivers 100-M00, respectively. The controller 500 is configured to provide at least the signal DIN, the signal LAT, and the signal DCLK (or the signal GCLK) to the drivers 100~M00. The internal architecture of each of the drivers 100 to M00 may be the same as the driver 100 or the driver 100' shown in FIG. Each driver further includes at least a data buffer and a phase-locked loop to drive the LEDs 11 to MN respectively. Since the operation principle and details of each driver are as described above, no repetitive description will be made here. It should be noted that the number of LEDs in the drawings and the number of drivers are not limitations of the display of the present invention. In addition, the kind and number of control signals provided by the controller 500 are not limited by the present invention. In other embodiments of the invention, controller 500 may also provide additional control signals to provide additional control over the operation of drivers 100-M00.

One embodiment of the present invention provides a method for driving a light emitting component in a driver, the driver including a phase locked loop, the method including step 610 and step 620 as shown in FIG. In step 610, the method of the present invention first receives a first signal, the first In addition to the input signal provided by the external controller, the signal may also be generated by frequency adjustment of the input signal provided by the external controller. In step 620, the phase locked loop is utilized to generate a second signal according to the first signal. The phase locked loop uses the first signal as a reference signal and performs a phase lock operation to generate the second signal. One of the first signal and the second signal can be used to control the operation of one of the data registers of the driver, wherein the data register is used to store one of the driving data required to drive the light-emitting component; The other of the first signal and the second signal is used to determine one of the required unit time for driving the light-emitting element. In addition, when determining the unit time, the unit time can be directly determined according to the frequency of the second signal; or after adjusting the frequency of the second signal by using an additional frequency adjustment, an output signal is generated, and the output signal is used to determine The unit time. The first signal and the second signal are pulse sequence/clock signals. The rising edge or falling edge of the pulse of one of the first signal and the second signal may be used to trigger a shift operation of one of the data registers, and the rising edge and the rising edge of the continuous pulse of the other The time interval or time interval between the falling edge and the falling edge can be used as a reference time, which may be the same as the reference time or proportional to the reference time. The unit time is finally modulated with the drive data in the data register to determine the time during which the current is supplied to the light-emitting element.

Note that although the above description uses the driver to drive the LED as an example, and the LED is used as a display unit in the display, this is not a limitation of the present invention. In fact, the driver of the present invention can also be applied to other types of light-emitting elements, and the display of the present invention may also use other types of light-emitting elements as display units, and such variations are also within the scope of the present invention.

The "an embodiment" referred to above means that a particular feature, structure or characteristic described for the embodiment is included in at least one embodiment of the invention. Furthermore, "an embodiment" as used in the different paragraphs herein does not represent the same embodiment. Therefore, although the above descriptions of different embodiments refer to different structural features or methodological actions, respectively, It is to be noted that these various features can be implemented in the same specific embodiment at the same time through appropriate modifications.

In summary, the present invention effectively reduces the need for external high frequency clock signals by the application of the phase-locked loop, and also provides different frequency adjustment mechanisms to effectively cover the frequency coverage of the signal, accurately Controlling the driving of the light-emitting elements and the operation of the data registers in the drive.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

LED11~LED1N‧‧‧Light Emitter

100‧‧‧ drive

500‧‧‧ controller

110‧‧‧ phase-locked loop

120‧‧‧ drive unit

130‧‧‧data register

140‧‧‧Latch

Claims (24)

A driver for driving a light-emitting component, comprising: a data buffer for storing driving data required to drive the light-emitting component; and a phase-locked loop for generating a second signal according to an input signal The operation of the data register is controlled according to one of the input signal and the second signal, and the driving of the light emitting element is based on the other of the input signal and the second signal. controlled. The driver of claim 1, wherein the frequency of the second signal is greater than or equal to the frequency of the first signal. The driver of claim 1, further comprising: a first signal processing device coupled to one of the input terminals of the phase-locked loop for adjusting a frequency of the input signal to generate a first signal, and The first signal is provided to the phase locked loop to generate the second signal. The driver of claim 3, wherein the first signal processing device is a frequency divider, and the frequency of the first signal is a fraction of a frequency of the input signal. The driver of claim 3, wherein one of the input signal and the second signal is used to control a displacement operation of the data register, and the other of the input signal and the second signal It is used to control one of the reference times required to drive the light-emitting element. The driver of claim 1, further comprising: a second signal processing device coupled to an output end of the phase-locked loop for adjusting a frequency of the second signal output by the phase-locked loop, Generate an output signal. The driver of claim 6, wherein the second signal processing device is a frequency divider, and the frequency of the output signal is a fraction of a frequency of the second signal. The driver of claim 6, wherein one of the first signal and the output signal is used to control a displacement operation of the data register, and the first signal and the output signal are The other is used to control one of the reference times required to drive the light-emitting element. A method for driving a light-emitting component in a driver, the driver comprising a phase-locked loop, the method comprising: receiving an input signal; and using the phase-locked loop to generate a second signal according to the input signal The operation of one of the data registers in the drive is controlled according to one of the input signal and the second signal, and the driving of the light-emitting component is based on the input signal and the second signal. The other is controlled; the data register is used to store one of the driving materials required to drive the light-emitting element. The method of claim 9, wherein the frequency of the second signal is greater than or equal to the frequency of the first signal. The method of claim 9, further comprising: adjusting a frequency of the input signal to generate a first signal. The method of claim 11, wherein the step of adjusting the input signal comprises: performing a frequency division operation on the input signal to generate the first signal, wherein the frequency of the first signal is the frequency of the input signal The score is multiple. The method of claim 11, further comprising: controlling one of the data registers by using one of the input signal and the second signal; and using the input signal and the second signal The other of them controls one of the reference times required to drive the light-emitting element. The method of claim 9, further comprising: adjusting a frequency of the second signal to generate an output signal. The method of claim 14, wherein the step of adjusting the second signal comprises: performing a frequency division operation on the second signal to generate the output signal, wherein the frequency of the output signal is the second signal The fractional frequency of the frequency. The method of claim 14, further comprising: controlling one of the data registers by using one of the first signal and the output signal; and using the first signal and the output signal The other of them controls one of the reference times required to drive the light-emitting element. A display comprising: a plurality of light-emitting elements; a plurality of drivers coupled to the plurality of light-emitting elements for driving the plurality of light-emitting elements; and a controller for providing at least one input signal to the plurality of drivers Where each drive contains: a data buffer for storing one of driving data required to drive the light-emitting element; and a phase-locked loop for generating a second signal by using a first signal, wherein the first signal is based on the input signal The operation of the data register is controlled according to one of the input signal and the second signal, and the driving of the light-emitting element is based on the other of the input signal and the second signal And being controlled. The display of claim 17, wherein the frequency of the second signal is greater than or equal to an integer multiple or a non-integer multiple of the frequency of the first signal. The display device of claim 17, wherein each of the drivers further includes: a first signal processing device coupled to one of the input terminals of the phase-locked loop for adjusting the frequency of the input signal to generate the first a signal, and the first signal is provided to the phase locked loop to generate the second signal. The display device of claim 19, wherein the first signal processing device is a frequency divider, and the frequency of the first signal is a fraction of a frequency of the input signal. The display of claim 19, wherein one of the input signal and the second signal is used to control a displacement operation of the data register, and another one of the input signal and the second signal One is used to control one of the reference times required to drive the light-emitting element. The display device of claim 17, wherein the input signal is the first signal, the phase locked loop uses the first signal to generate the second signal, wherein each driver further comprises: a second signal a processing device coupled to an output end of the phase locked loop for adjusting the phase lock The frequency of the second signal generated by the loop generates an output signal. The display device of claim 22, wherein the second signal processing device is a frequency divider, and the frequency of the output signal is a fraction of a frequency of the second signal. The display of claim 22, wherein one of the first signal and the output signal is used to control a displacement operation of the data register, and the first signal and the output signal The other is used to control one of the reference times required to drive the light-emitting element.