TW201530318A - Storage device for transmitting multiple forms of data, and socket for inserting the same - Google Patents
Storage device for transmitting multiple forms of data, and socket for inserting the same Download PDFInfo
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本發明有關於一種可傳輸多形式資料之儲存裝置及其插設之連接座，尤指一種符合於CFast硬體標準規範並可以傳輸多種形式資料之儲存裝置及連接座。
The invention relates to a storage device capable of transmitting multi-form data and a connector for inserting the same, in particular to a storage device and a connection seat which conform to the CFast hardware standard specification and can transmit various forms of data.
隨著資料的存取需求，一般電子設備都會設置有可供儲存器(如記憶卡或隨身碟)插設之連接端，以使電子設備可以對於插入的儲存器進行資料的存取。
目前市面上的快閃儲存器之硬體標準規範眾多，如SD、MMC、MS、CF、CFast等等硬體標準規範之記憶卡或USB硬體標準規範之隨身碟，且每一硬體標準規範之儲存器對於資料的存取都會制定有單一特定的傳輸協定規範，如SD、MMC、MS、SATA或USB。此外，以往每一儲存器都會各自製作成一單體結構，其擁有自己的包裝殼體並配置一連接器，致使以透過各自的連接器插接於電子設備之中而與電子設備進行資料的傳輸。
再者，以往電子設備為了可以存取不同傳輸協定規範的儲存器，於電子設備的電路板上設置有各式各樣的硬體標準規範之連接座，以供各個儲存器的連接器進行插設。然而，於電子設備之中設置多種硬體標準規範之連接座，不僅會增加連接座的設置成本，電子設備若為一可攜式電子設備(如平板電腦或通訊裝置)時，此多數量之連接端將會讓可攜式電子設備無法達到薄型化外觀之目的。
With the access requirements of the data, the general electronic device is provided with a connection port for the storage device (such as a memory card or a flash drive), so that the electronic device can access the data of the inserted storage device.
At present, there are many standard hardware standards for flash memory on the market, such as SD, MMC, MS, CF, CFast, etc., hardware standard specifications of the memory card or USB hardware standard specification of the flash drive, and each hardware standard The specification of the memory access to the data will be developed with a single specific transport protocol specification, such as SD, MMC, MS, SATA or USB. In addition, in the past, each of the storage devices was individually fabricated into a single structure, which has its own packaging casing and is equipped with a connector, so that data is transmitted to and from the electronic device through the respective connectors inserted into the electronic device. .
Furthermore, in the past, in order to access the memory of different transmission protocol specifications, the electronic device is provided with a variety of hardware standard specification connectors on the circuit board of the electronic device for inserting the connectors of the respective storage devices. Assume. However, setting a plurality of hardware standard specification connectors in an electronic device not only increases the installation cost of the connector, but when the electronic device is a portable electronic device (such as a tablet or a communication device), the number is The connection will make the portable electronic device unable to achieve a thin appearance.
本發明之一目的，在於提供一種多形式資料之儲存裝置及其插設之連接座，儲存裝置及連接器皆符合於CFast卡硬體標準規範，其中儲存裝置包括有一可以插接在連接座上的連接器，連接器及連接座被定義可以傳輸一第一形式資料及至少一第二形式資料，當儲存裝置透過連接器插設在電子設備的連接座時，電子設備與儲存裝置之間將可以傳輸第一形式及第二形式的資料，如此，儲存裝置與電子設備只要採用單一連接器及連接座相互插接，即可傳輸多種傳輸協定規範形式之資料，藉以降低連接器及連接座的設置數量及安裝空間。
為了達到上述目的，本發明提供一種可傳輸多形式資料之儲存裝置，其外觀尺寸符合於CFast硬體標準規範，包括：一控制器；一儲存單元，連接控制器，用以儲存資料；及一連接器，其連接控制器，包括：一第一連接埠及一第二連接埠，利用第一連接埠以傳輸一第一形式資料，以及利用第二連接埠以傳輸至少一第二形式資料。
本發明一實施例中，其中第一形式資料或第二形式資料為符合於SATA、USB、PCI-E、SD、MMC、MS或eMMC傳輸協定規範之資料。
本發明一實施例中，其中第一形式資料及第二形式資料分別為不同傳輸協定規範之資料。
本發明一實施例中，其中第一形式資料及第二形式資料為相同傳輸協定規範之資料。
本發明一實施例中，其中連接器為一CFA(Compact Flash Association)協會所定義的CFast硬體標準規範之連接器，第一連接埠之腳位數量為七，而第二連接埠之腳位數量為十七。
本發明一實施例中，其中儲存單元包括一第一儲存器及至少一第二儲存器，控制器對於第一儲存器存取第一形式資料及對於第二儲存器存取第二形式資料。
本發明一實施例中，其中第一連接埠及第二連接埠分別包括複數個腳位，從第一連接埠之腳位中定義出複數個用以傳輸第一形式資料之資料腳位，從第二連接埠之腳位中定義出複數個用以傳輸第二形式資料之資料腳位。
本發明又提供一種連接座，用以插設一符合於CFast硬體標準規範之儲存裝置，儲存裝置包括一連接器，連接器包括一第一連接埠及一第二連接埠，連接座包括：一第一連接端；及一第二連接端，連接器之第一連接埠插接在連接座之第一連接端上，利用第一連接埠與第一連接端以傳輸一第一形式資料，連接器之第二連接埠插接在連接座之第二連接端上，利用第二連接埠與第二連接端以傳輸一第二形式資料。
本發明一實施例中，其中連接座為一CFA(Compact Flash Association)協會所定義的CFast硬體標準規範之連接座，第一連接端之腳位數量為七，而第二連接端之腳位數量為十七。
本發明一實施例中，其中第一連接端及第二連接端分別包括複數個腳位，從第一連接端之腳位中定義出複數個用以傳輸第一形式資料之資料腳位，從第二連接端之腳位中定義出複數個用以傳輸第二形式資料之資料腳位。
An object of the present invention is to provide a multi-form data storage device and a plug-in connector thereof. The storage device and the connector are all conformed to the CFast card hardware standard specification, wherein the storage device includes a plug-in connector. The connector, the connector and the connector are defined to transmit a first form of data and at least a second form of data. When the storage device is inserted into the connector of the electronic device through the connector, the electronic device and the storage device are The first form and the second form of data can be transmitted. Thus, the storage device and the electronic device can transmit data of various transmission protocol specifications by using a single connector and a connector, thereby reducing the connector and the connector. Set the number and installation space.
In order to achieve the above object, the present invention provides a storage device capable of transmitting multiple forms of data, the size of which conforms to the CFast hardware standard specification, including: a controller; a storage unit connected to the controller for storing data; And a connector, comprising: a first port and a second port, the first port is used to transmit a first form of data, and the second port is used to transmit at least one second form of data.
In an embodiment of the invention, the first form of data or the second form of data is data conforming to a SATA, USB, PCI-E, SD, MMC, MS or eMMC transmission protocol specification.
In an embodiment of the invention, the first form of data and the second form of data are respectively data of different transmission agreement specifications.
In an embodiment of the invention, the first form of data and the second form of data are materials of the same transfer protocol specification.
In an embodiment of the invention, wherein the connector is a connector of the CFast hardware standard specification defined by the CFA (Compact Flash Association) Association, the number of pins of the first port is seven, and the pin of the second port is The number is seventeen.
In an embodiment of the invention, the storage unit includes a first storage unit and at least one second storage unit, and the controller accesses the first form of data for the first storage and the second form of data for the second storage.
In an embodiment of the invention, the first port and the second port respectively comprise a plurality of pins, and a plurality of data pins for transmitting the first form of data are defined from the pin of the first port. A plurality of data pins for transmitting the second form of data are defined in the pin of the second port.
The present invention further provides a connector for inserting a storage device conforming to the CFast hardware standard specification. The storage device includes a connector. The connector includes a first connector and a second connector. The connector includes: a first connecting end; and a second connecting end, the first connecting end of the connector is inserted on the first connecting end of the connecting base, and the first connecting end and the first connecting end are used to transmit a first form of data, The second connection port of the connector is inserted on the second connection end of the connection base, and the second connection port and the second connection end are used to transmit a second form of data.
In an embodiment of the invention, the connection base is a connector of the CFast hardware standard specification defined by the CFA (Compact Flash Association) Association, and the number of pins of the first connection end is seven, and the position of the second connection end is The number is seventeen.
In an embodiment of the invention, the first connection end and the second connection end respectively comprise a plurality of pin positions, and a plurality of data pin positions for transmitting the first form data are defined from the pin positions of the first connection end, A plurality of data pins for transmitting the second form of data are defined in the pin of the second connection end.
10‧‧‧儲存裝置
11‧‧‧控制器
13‧‧‧儲存單元
131‧‧‧第一儲存器
133‧‧‧第二儲存器
20‧‧‧連接器
205‧‧‧定位件
21‧‧‧第一連接埠
211‧‧‧腳位
23‧‧‧第二連接埠
231‧‧‧腳位
30‧‧‧連接座
301‧‧‧基部
302‧‧‧卡體容置區
303‧‧‧臂部
305‧‧‧導槽部
31‧‧‧第一連接端
311‧‧‧腳位
33‧‧‧第二連接端
331‧‧‧腳位
41‧‧‧第一耦合電容
43‧‧‧第二耦合電容
50‧‧‧主機板
51‧‧‧微處理器10‧‧‧Storage device
11‧‧‧ Controller
13‧‧‧ storage unit
131‧‧‧First storage
133‧‧‧Second storage
20‧‧‧Connector
205‧‧‧ positioning parts
21‧‧‧ First connection埠
211‧‧‧ feet
23‧‧‧Second connection埠
231‧‧‧ feet
30‧‧‧Connecting seat
301‧‧‧ base
302‧‧‧ card body storage area
303‧‧‧ Arms
305‧‧‧ Guide groove
31‧‧‧First connection
311‧‧‧ feet
33‧‧‧second connection
331‧‧‧ feet
41‧‧‧First coupling capacitor
43‧‧‧Second coupling capacitor
50‧‧‧ motherboard
51‧‧‧Microprocessor
第１圖：本發明儲存裝置及其插設之連接座一較佳實施例之平面構造示意圖。
第２圖：本發明電子設備與儲存裝置一較佳實施例之電路結構示意圖。
第３圖：本發明連接器及連接座一實施例之腳位定義圖表。
第４圖：本發明在控制器與連接器間及在微處理器及連接座間設置耦合電容之電路結構示意圖。
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view showing a preferred embodiment of a storage device of the present invention and its interposed connector.
2 is a schematic diagram showing the circuit structure of a preferred embodiment of the electronic device and storage device of the present invention.
Fig. 3 is a diagram showing the definition of the position of the connector and the connector of the present invention.
Fig. 4 is a schematic view showing the circuit structure of the coupling capacitor between the controller and the connector and between the microprocessor and the connector.
請同時參閱第１圖及第２圖，分別為本發明儲存裝置及其插設之連接座一較佳實施例之平面構造示意圖及電子設備與儲存裝置一較佳實施例之電路結構示意圖。如圖所示，本發明儲存裝置10及連接座30之外觀尺寸符合於CFast 2.0硬體標準規範。
其中，儲存裝置10包括一控制器11、一儲存單元13及一連接器20。控制器11分別電性連接儲存單元13及連接器20。儲存單元13係以快閃記憶體作為基本的組成元件，用以儲存資料。控制器11利用連接器20以傳輸儲存單元13所儲存之資料。
連接器20為CFA(Compact Flash Association)協會所定義的CFast 2.0硬體標準規範之連接器，其包括一第一連接埠21及一第二連接埠23。第一連接埠21包括有七個腳位211，而第二連接埠23包括有十七個腳位231。第一連接埠21被定義用以傳輸一第一形式資料，而第二連接埠23被定義用以傳輸至少一第二形式資料。
同樣的，連接座30也為CFA(Compact Flash Association)協會所定義的CFast 2.0硬體標準規範之連接座，其包括一第一連接端31及一第二連接端33。第一連接端31包括有七個腳位311，而第二連接端33包括有十七個腳位331。當連接器20之第一連接埠21及第二連接埠23分別插接在連接座30之第一連接端31及第二連接端33時，第一連接埠21及第一連接端31間將可以傳輸第一形式資料，而第二連接埠23及第二連接埠33間將可以傳輸第二形式資料。
進一步參閱第３圖，為本發明連接器及連接座一實施例之腳位定義圖表。如圖表所示，連接器20之第一連接埠21之腳位211及連接座30之第一連接端31之腳位311包括有S1~S7，而連接器20之第二連接埠23之腳位231及連接座30之第二連接端33之腳位331包括有PC1~PC17。
本發明連接器20及連接座30為符合CFast 2.0 標準規範之連接器及連接座，因此，在連接器20及連接座30中絕大部分的腳位211、231、311、331仍依照原本CFast 2.0 的標準規範進行相對的定義，例如：S1、S4、S7、PC2、PC7、PC15~PC16定義為接地腳位，S13、S14定義為電源腳位，PC8、PC9定義為LED輸出訊號腳位，PC1、PC17定義為檢測腳位，而S2、S3、S5、S6定義為資料腳位。
在本發明中，第一連接埠21及第一連接端31之S2、S3、S5、S6腳位211、311將被定義作為傳輸第一形式資料(A1+、A1-、A2-、A2+)之資料腳位。此外，第二連接埠23及第二連接端33之中尚包括有複數個閒置腳位231、331，例如：PC3~PC6、PC10~12腳位，部分的閒置腳位231、331將被定義作為傳輸第二形式資料(B1+、B1-、B2-、B2+)之資料腳位，例如：PC4、PC5、PC10、PC11腳位。則，連接器20及連接座30將可以透過第一連接埠21及第一連接端31之資料腳位(S2、S3、S5、S6)211、311傳輸第一形式資料以及透過第二連接埠23及第二連接端33之資料腳位(PC4、PC5、PC10、PC11)231、331傳輸第二形式資料。
接續，本發明一實施例中，連接器20與連接座30所傳輸的第一形式資料及第二形式資料分別為不同傳輸協定規範之資料，例如：第一形式資料為符合於SATA傳輸協定規範之資料，而第二形式資料為符合於USB、PCI-E、SD、MMC、MS或eMMC傳輸協定規範之資料。
或者，本發明又一實施例中，連接器20與連接座30所傳輸的第一形式資料及第二形式資料可以為相同傳輸協定規範之資料，例如：第一形式資料及第二形式資料皆符合於SATA、USB、PCI-E、SD、MMC、MS或eMMC傳輸協定規範之資料。
再度參閱第２圖，本發明連接座30將會設置在一電子設備之主機板50之上。主機板50包括有一微處理器51，該連接座30電性連接微處理器51。當儲存裝置10之連接器20插接在連接座30時，主機板50之微處理器51即可對於儲存裝置10存取第一形式資料及/或第二形式資料。在此，電子設備與儲存裝置10之間只要採用單一個連接器20及連接座30進行插接，電子設備即可對於儲存裝置10存取多種傳輸協定規範形式之資料，以降低連接器10及連接座30的設置數量及安裝空間。
又，本發明儲存裝置10之儲存單元13包括有一第一儲存器131及一第二儲存器133。連接器20之資料腳位(S2、S3、S5、S6)211將作為第一儲存器131專屬的資料腳位，其用以傳輸第一儲存器131所存取的第一形式資料(A1+、A1-、A2-、A2+)。另外，連接器20之資料腳位(PC4、PC5、PC10、PC11)231將作為第二儲存器133專屬的資料腳位，其用以傳輸第二儲存器133所存取的第二形式資料(B1+、B1-、B2-、B2+)。在此，本發明將多個不同傳輸協定規範或相同傳輸協定規範之儲存器131、133整合至儲存裝置10之中，其相較於以往各自包裝的單體構件形式，可以有效降低整體的單位體積。
本發明上述實施例中，第一連接埠21及其插設的第一連接端31與第二連接埠23及其插設的第二連接端33皆被設定為可以傳輸資料的介面，例如：第一連接埠21及第一連接端31之S2、S3、S5、S6腳位被設定為傳輸資料之腳位，第二連接埠23及第二連接端33之PC4、PC5、PC10、PC11腳位也被設定為傳輸資料之腳位。當然，本發明又一實施例中，也可以只選擇將第二連接埠23及其插設的第二連接端33設定為可以傳輸資料之介面，而第一連接埠21及其插設的第一連接端31未被設定有傳輸資料之功效，例如：第一連接埠21及第一連接端31之S2、S3、S5、S6腳位未設定成資料腳位而是改作為其他用途。請參閱第４圖為本發明在控制器與連接器間及在微處理器及連接座間設置耦合電容之電路結構示意圖。如圖所示，本發明一實施例中，在控制器11與連接器20間尚設置有一對第一耦合電容41及在微處理器51與連接座30間尚設置有一對第二耦合電容43。
以往為了降低資料在傳輸途徑中受到電磁干擾(EMI)之影響，因此，一般都會採用差動訊號方式進行儲存裝置10與電子設備之間的資料傳輸。然而，控制器11或微處理器51內部電路中所形成的直流偏壓(VDC
)仍會反應在所傳輸的差動資料訊號之上，以致該傳輸的差動資料訊號往往包含有直流偏壓(VDC
)成分。該包含有直流偏壓成分的差動資料訊號不僅會影響到資料存取上之正確性，且亦可能超出控制器11或微處理器51可容許的電壓範圍而造成儲存裝置10或電子設備之內部電路的損壞。
本發明藉由第一耦合電容41及第二耦合電容43的設置，將可有效隔離控制器11或微處理器51內部電路中所形成的直流偏壓(VDC
)雜訊，避免直流偏壓(VDC
)雜訊跟隨著差動資料訊號從連接器20及連接座30傳輸至微處理器51或從連接座30及連接器20傳輸至控制器11而影響到資料的存取或電路的運作。
此外，當儲存裝置10之連接器20誤插於不同資料傳輸協定規範的電子設備之連接座30時(例如：連接器20之第二連接埠23被定義符合於USB資料傳輸協定規範，然而，其對應插設的連接座30之第二連接端32另被定義符合於PCI-E資料傳輸協定規範)，該第一耦合電容41及該第二耦合電容43也可以產生防插錯的保護作用，避免不同資料傳輸規範之訊號壓差造成電子設備或儲存裝置10的電路損壞。
承上所述，本發明連接器20及連接座30為符合於CFast標準規範之連接元件，因此，在連接器20及連接座30之中定義有多個檢測腳位PC1、PC17 (CDI、CDO)，這些檢測腳位PC1、PC17 (CDI、CDO)將用以檢測連接器20是否正確電性插接在連接座30之中，如第３圖表所示。
又，再度參閱第１圖，本發明符合CFast 2.0標準規範之連接座30之座體構造包括一基部301及兩臂部303。兩臂部303分別設置在基部301之兩側，基部301與兩臂部303間形成有一卡體容置區302，第一連接端31及第二連接端32固定在基部301之上且突設在卡體容置區302之中，而第一連接端31及第二連接端32與兩側的臂部303之間的空隙分別形成為一導槽部305。
另，本發明儲存裝置10之前緣中央處分別設置第一連接埠21及第二連接埠23，第一連接埠21及第二連接埠23之兩側分別設置有一定位件205。在此，第一連接埠21、第二連接埠23及兩側的定位件205將構成為該符合CFast 2.0標準規範之連接器20。
當儲存裝置10從卡體容置區302進入連接座30內部時，連接器20之第一連接埠21及第二連接埠23係可以電性插接於連接座30之第一連接端31及第二連接端33之上，且連接器20之定位件205也會同時嵌固在導槽部305之中。則，透過導槽部305與定位件205間的定位嵌合，將使得連接器20可以更穩固地電性插接在連接座30之上。
在此，藉由CFast 2.0標準所制定的檢測腳位(CDI、CDO)及導槽定位結構等等兩項規範，將可以確保本發明連接器20可以穩固正確地插設在連接座30之中，其相較於採用其他標準規範(如SD、MMC、MS或USB)將具有更高的可靠度連接，致使以提高電子設備與儲存裝置10間資料存取上的穩定性。
以上所述者，僅為本發明之一較佳實施例而已，並非用來限定本發明實施之範圍，即凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
Please refer to FIG. 1 and FIG. 2, which are schematic diagrams showing a planar structure of a preferred embodiment of the storage device and the inserted connector of the present invention, and a circuit structure of a preferred embodiment of the electronic device and the storage device. As shown, the apparent dimensions of the storage device 10 and connector 30 of the present invention conform to the CFast 2.0 hardware standard specification.
The storage device 10 includes a controller 11 , a storage unit 13 , and a connector 20 . The controller 11 is electrically connected to the storage unit 13 and the connector 20 respectively. The storage unit 13 uses flash memory as a basic component for storing data. The controller 11 utilizes the connector 20 to transfer the data stored by the storage unit 13.
The connector 20 is a connector of the CFast 2.0 hardware standard specification defined by the CFA (Compact Flash Association) Association, and includes a first port 21 and a second port 23. The first port 21 includes seven pins 211 and the second port 23 includes seventeen pins 231. The first port 21 is defined to transmit a first form of data, and the second port 23 is defined to transmit at least a second form of material.
Similarly, the connector 30 is also a connector of the CFast 2.0 hardware standard defined by the CFA (Compact Flash Association) Association, and includes a first connection end 31 and a second connection end 33. The first connection end 31 includes seven foot positions 311, and the second connection end 33 includes seventeen foot positions 331. When the first connection port 21 and the second connection port 23 of the connector 20 are respectively inserted into the first connection end 31 and the second connection end 33 of the connection base 30, the first connection port 21 and the first connection end 31 will be The first form of data may be transmitted, and the second form of data may be transmitted between the second port 23 and the second port 33.
Further referring to Fig. 3, there is shown a diagram of the pin definition of an embodiment of the connector and the connector of the present invention. As shown in the figure, the pin 211 of the first port 21 of the connector 20 and the pin 311 of the first terminal 31 of the connector 30 include S1~S7, and the second port 23 of the connector 20 is connected. The bit 331 of the bit 231 and the second connection end 33 of the connector block 30 includes PC1~PC17.
The connector 20 and the connector 30 of the present invention are connectors and connectors that conform to the CFast 2.0 standard specification. Therefore, most of the pins 211, 231, 311, and 331 in the connector 20 and the connector 30 are still in accordance with the original CFast. The standard specification of 2.0 is relatively defined. For example, S1, S4, S7, PC2, PC7, PC15~PC16 are defined as ground pins, S13 and S14 are defined as power pins, and PC8 and PC9 are defined as LED output signals. PC1 and PC17 are defined as detection pins, and S2, S3, S5, and S6 are defined as data pins.
In the present invention, the first connection port 21 and the S2, S3, S5, and S6 pins 211, 311 of the first connection terminal 31 are defined as the first form data (A1+, A1-, A2-, A2+). Information pin. In addition, the second connection port 23 and the second connection end 33 further include a plurality of idle pins 231, 331, for example, PC3~PC6, PC10~12 pins, and some idle pins 231, 331 will be defined. As the data pin for transmitting the second form data (B1+, B1-, B2-, B2+), for example, PC4, PC5, PC10, PC11 pin. Then, the connector 20 and the connector 30 can transmit the first form data and the second port through the first port 21 and the first pin 31 (S2, S3, S5, S6) 211, 311. 23 and the data pin (PC4, PC5, PC10, PC11) 231, 331 of the second connection terminal 33 transmit the second form of data.
In the embodiment of the present invention, the first form data and the second form data transmitted by the connector 20 and the connector 30 are respectively different data of the transmission protocol specification, for example, the first form of data is in accordance with the SATA transmission protocol specification. The second form of information is material that conforms to the USB, PCI-E, SD, MMC, MS or eMMC transport protocol specifications.
Alternatively, in another embodiment of the present invention, the first form data and the second form data transmitted by the connector 20 and the connector 30 may be the same transmission protocol specification, for example, the first form data and the second form data. Compliance with SATA, USB, PCI-E, SD, MMC, MS or eMMC transport protocol specifications.
Referring again to Figure 2, the connector 30 of the present invention will be placed over the motherboard 50 of an electronic device. The motherboard 50 includes a microprocessor 51 electrically connected to the microprocessor 51. When the connector 20 of the storage device 10 is plugged into the connector 30, the microprocessor 51 of the motherboard 50 can access the first form of data and/or the second form of data for the storage device 10. Here, the electronic device and the storage device 10 can be connected by using a single connector 20 and the connector 30, and the electronic device can access the data of the plurality of transmission protocol specifications for the storage device 10 to lower the connector 10 and The number of installation seats 30 and the installation space.
Moreover, the storage unit 13 of the storage device 10 of the present invention includes a first storage unit 131 and a second storage unit 133. The data pin (S2, S3, S5, S6) 211 of the connector 20 will serve as a data pin specific to the first memory 131 for transmitting the first form data accessed by the first memory 131 (A1+, A1-, A2-, A2+). In addition, the data pin (PC4, PC5, PC10, PC11) 231 of the connector 20 will serve as a data pin exclusive to the second storage 133 for transmitting the second form of data accessed by the second storage 133 ( B1+, B1-, B2-, B2+). Here, the present invention integrates a plurality of different transport protocol specifications or the same transport protocol specification storages 131, 133 into the storage device 10, which can effectively reduce the overall unit compared to the conventionally packaged single component forms. volume.
In the above embodiment of the present invention, the first connection port 21 and the first connection end 31 and the second connection port 23 and the second connection end 33 inserted therein are all set as interfaces for transmitting data, for example: The first connection port 21 and the first connection end 31 of the S2, S3, S5, and S6 pins are set to transmit data pins, and the second connection port 23 and the second connection terminal 33 are PC4, PC5, PC10, and PC11 pins. The bit is also set to the pin of the transmitted data. Of course, in another embodiment of the present invention, only the second connection port 23 and the second connection end 33 inserted therein may be selected as an interface capable of transmitting data, and the first connection port 21 and the inserted portion thereof A connection end 31 is not configured to transmit data. For example, the first connection port 21 and the S2, S3, S5, and S6 pins of the first connection end 31 are not set to the data pin position but are used for other purposes. Please refer to FIG. 4, which is a schematic structural diagram of a circuit in which a coupling capacitor is disposed between a controller and a connector and between a microprocessor and a connector. As shown in the figure, in the embodiment of the present invention, a pair of first coupling capacitors 41 are disposed between the controller 11 and the connector 20, and a pair of second coupling capacitors 43 are disposed between the microprocessor 51 and the connector 30. .
In the past, in order to reduce the influence of electromagnetic interference (EMI) in the transmission path, data transmission between the storage device 10 and the electronic device is generally performed by using a differential signal method. However, the DC bias voltage (V DC ) formed in the internal circuit of the controller 11 or the microprocessor 51 still reflects on the transmitted differential data signal, so that the transmitted differential data signal often contains DC bias. Pressure (V DC ) component. The differential data signal including the DC bias component not only affects the correctness of data access, but may also exceed the voltage range that can be tolerated by the controller 11 or the microprocessor 51 to cause the storage device 10 or the electronic device. Damage to internal circuits.
The present invention can effectively isolate the DC bias (V DC ) noise formed in the internal circuit of the controller 11 or the microprocessor 51 by the arrangement of the first coupling capacitor 41 and the second coupling capacitor 43 to avoid the DC bias. (V DC ) noise is transmitted from the connector 20 and the connector 30 to the microprocessor 51 or from the connector 30 and the connector 20 to the controller 11 to affect the access or circuitry of the data. Operation.
In addition, when the connector 20 of the storage device 10 is mistakenly inserted into the connector 30 of the electronic device of different data transmission protocol specifications (for example, the second port 23 of the connector 20 is defined to comply with the USB data transfer protocol specification, however, The second connection end 32 of the corresponding connection socket 30 is further defined to comply with the PCI-E data transmission protocol specification, and the first coupling capacitor 41 and the second coupling capacitor 43 can also provide protection against insertion errors. The signal voltage difference of different data transmission specifications is prevented from causing circuit damage of the electronic device or the storage device 10.
As described above, the connector 20 and the connector 30 of the present invention are connected components conforming to the CFast standard specification. Therefore, a plurality of detection pins PC1 and PC17 (CDI, CDO) are defined in the connector 20 and the connector 30. The detection pins PC1, PC17 (CDI, CDO) will be used to detect whether the connector 20 is properly electrically inserted into the connector 30, as shown in the third diagram.
Moreover, referring again to FIG. 1, the seat structure of the connector 30 conforming to the CFast 2.0 standard specification of the present invention includes a base portion 301 and two arm portions 303. The two arm portions 303 are respectively disposed on two sides of the base portion 301, and a card body receiving portion 302 is formed between the base portion 301 and the two arm portions 303. The first connecting end 31 and the second connecting end 32 are fixed on the base portion 301 and protruded. In the card body accommodating area 302, the gap between the first connection end 31 and the second connection end 32 and the arm portions 303 on both sides is formed as a guide groove portion 305, respectively.
In addition, a first connecting port 21 and a second connecting port 23 are respectively disposed at the center of the front edge of the storage device 10 of the present invention, and a positioning member 205 is disposed on each of two sides of the first connecting port 21 and the second connecting port 23 respectively. Here, the first port 21, the second port 23 and the positioning members 205 on both sides will be constructed as the connector 20 conforming to the CFast 2.0 standard.
When the storage device 10 enters the interior of the connector 30 from the card housing area 302, the first connector 21 and the second connector 23 of the connector 20 can be electrically connected to the first connector 31 of the connector 30 and Above the second connecting end 33, the positioning member 205 of the connector 20 is also embedded in the guiding groove portion 305 at the same time. Then, through the positioning and fitting between the guide groove portion 305 and the positioning member 205, the connector 20 can be electrically connected to the connecting seat 30 more stably.
Here, by the two specifications of the detection foot position (CDI, CDO) and the guide groove positioning structure developed by the CFast 2.0 standard, it can be ensured that the connector 20 of the present invention can be stably and correctly inserted in the connection base 30. It will have a higher reliability connection than other standard specifications (such as SD, MMC, MS or USB), so as to improve the stability of data access between the electronic device and the storage device 10.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, which is equivalent to the changes in shape, structure, features and spirit of the present invention. Modifications are intended to be included in the scope of the patent application of the present invention.
10‧‧‧儲存裝置 10‧‧‧Storage device
11‧‧‧控制器 11‧‧‧ Controller
13‧‧‧儲存單元 13‧‧‧ storage unit
131‧‧‧第一儲存器 131‧‧‧First storage
133‧‧‧第二儲存器 133‧‧‧Second storage
20‧‧‧連接器 20‧‧‧Connector
21‧‧‧第一連接埠 21‧‧‧ First connection埠
23‧‧‧第二連接埠 23‧‧‧Second connection埠
30‧‧‧連接座 30‧‧‧Connecting seat
31‧‧‧第一連接端 31‧‧‧First connection
33‧‧‧第二連接端 33‧‧‧second connection
50‧‧‧主機板 50‧‧‧ motherboard
51‧‧‧微處理器 51‧‧‧Microprocessor
Claims (1)
2.如申請專利範圍第1項所述之儲存裝置，其中該第一形式資料或該第二形式資料為符合於SATA、USB、PCI-E、SD、MMC、MS或eMMC傳輸協定規範之資料。
3.如申請專利範圍第1項所述之儲存裝置，其中該第一形式資料及該第二形式資料分別為不同傳輸協定規範之資料。
4.如申請專利範圍第1項所述之儲存裝置，其中該第一形式資料及該第二形式資料為相同傳輸協定規範之資料。
5.如申請專利範圍第1項所述之儲存裝置，其中該連接器為一CFA(Compact Flash Association)協會所定義的CFast硬體標準規範之連接器，該第一連接埠之腳位數量為七，而該第二連接埠之腳位數量為十七。
6.如申請專利範圍第1項所述之儲存裝置，其中該儲存單元包括一第一儲存器及至少一第二儲存器，該控制器對於該第一儲存器存取該第一形式資料及對於該第二儲存器存取該第二形式資料。
7.如申請專利範圍第1項所述之儲存裝置，其中該第一連接埠及該第二連接埠分別包括複數個腳位，從該第一連接埠之腳位中定義出複數個用以傳輸該第一形式資料之資料腳位，從該第二連接埠之腳位中定義出複數個用以傳輸該第二形式資料之資料腳位。
8.一種連接座，用以插設一符合於CFast硬體標準規範之儲存裝置，儲存裝置包括一連接器，連接器包括一第一連接埠及一第二連接埠，連接座包括：一第一連接端；及一第二連接端，連接器之第一連接埠插接在連接座之第一連接端之上，利用第一連接埠與第一連接端以傳輸一第一形式資料，連接器之第二連接埠插接在連接座之第二連接端之上，利用第二連接埠與第二連接端以傳輸一第二形式資料。
9.如申請專利範圍第8項所述之連接座，其中該第一形式資料或該第二形式資料為符合於SATA、USB、PCI-E、SD、MMC、MS或eMMC傳輸協定規範之資料。
10.如申請專利範圍第8項所述之連接座，其中該第一形式資料及該第二形式資料分別為不同傳輸協定規範之資料。
11.如申請專利範圍第8項所述之連接座，其中該第一形式資料及該第二形式資料為相同傳輸協定規範之資料。
12.如申請專利範圍第8項所述之連接座，其中該連接座為一CFA(Compact Flash Association)協會所定義的CFast硬體標準規範之連接座，該第一連接端之腳位數量為七，而該第二連接端之腳位數量為十七。
13.如申請專利範圍第8項所述之連接座，其中該第一連接端及該第二連接端分別包括複數個腳位，從該第一連接端之腳位中定義出複數個用以傳輸該第一形式資料之資料腳位，從該第二連接端之腳位中定義出複數個用以傳輸該第二形式資料之資料腳位。A storage device capable of transmitting multiple forms of data, the size of which conforms to the CFast hardware standard specification, comprising: a controller; a storage unit connected to the controller for storing data; and a connector connected to the controller, The method includes: a first port and a second port, the first port is used to transmit a first form of data, and the second port is used to transmit at least one second form of data.
2. The storage device of claim 1, wherein the first form of data or the second form of data is data conforming to SATA, USB, PCI-E, SD, MMC, MS or eMMC transmission protocol specifications. .
3. The storage device of claim 1, wherein the first form of information and the second form of data are data of different transmission agreement specifications.
4. The storage device of claim 1, wherein the first form of information and the second form of data are materials of the same transmission agreement specification.
5. The storage device of claim 1, wherein the connector is a connector of the CFast hardware standard specification defined by the CFA (Compact Flash Association) Association, and the number of pins of the first connection port is Seven, and the number of pins of the second port is seventeen.
6. The storage device of claim 1, wherein the storage unit comprises a first storage device and at least a second storage device, the controller accessing the first form of data for the first storage device and Accessing the second form of material for the second storage.
7. The storage device of claim 1, wherein the first port and the second port respectively comprise a plurality of pins, and a plurality of pins are defined from the pins of the first port. Transmitting the data pin of the first form of data, and defining a plurality of data pins for transmitting the second form of data from the pin of the second port.
8. A connector for inserting a storage device conforming to the CFast hardware standard specification, the storage device comprising a connector, the connector comprising a first connection port and a second connection port, the connection block comprising: a first a connecting end; and a second connecting end, the first connecting end of the connector is inserted on the first connecting end of the connecting base, and the first connecting end is used to transmit a first form of data, and the first connecting end is connected The second connection port of the device is inserted on the second connection end of the connection base, and the second connection port and the second connection end are used to transmit a second form of data.
9. The connector of claim 8, wherein the first form of information or the second form of data is data conforming to SATA, USB, PCI-E, SD, MMC, MS or eMMC transmission protocol specifications. .
10. The connector of claim 8, wherein the first form of information and the second form of data are data of different transmission agreement specifications.
11. The connector of claim 8, wherein the first form of information and the second form of data are materials of the same transmission agreement specification.
12. The connector of claim 8, wherein the connector is a connector of a CFast hardware standard specification defined by a CFA (Compact Flash Association) Association, and the number of pins of the first connector is Seven, and the number of pins of the second connection is seventeen.
13. The connector of claim 8, wherein the first connection end and the second connection end respectively comprise a plurality of pins, and a plurality of pins are defined from the first connection end Transmitting the data pin of the first form of data, and defining a plurality of data pins for transmitting the second form of data from the pin of the second connection end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103102179A TW201530318A (en) | 2014-01-21 | 2014-01-21 | Storage device for transmitting multiple forms of data, and socket for inserting the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103102179A TW201530318A (en) | 2014-01-21 | 2014-01-21 | Storage device for transmitting multiple forms of data, and socket for inserting the same |
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| Publication Number | Publication Date |
|---|---|
| TW201530318A true TW201530318A (en) | 2015-08-01 |
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| TW103102179A TW201530318A (en) | 2014-01-21 | 2014-01-21 | Storage device for transmitting multiple forms of data, and socket for inserting the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI602127B (en) * | 2016-10-21 | 2017-10-11 | 宇瞻科技股份有限公司 | Electronic card and detecting method thereof |
| TWI671618B (en) * | 2017-06-05 | 2019-09-11 | 日商東芝記憶體股份有限公司 | Memory card, host device, memory card connector, and memory card adapter |
-
2014
- 2014-01-21 TW TW103102179A patent/TW201530318A/en unknown
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI602127B (en) * | 2016-10-21 | 2017-10-11 | 宇瞻科技股份有限公司 | Electronic card and detecting method thereof |
| US10162723B2 (en) | 2016-10-21 | 2018-12-25 | Apacer Technology Inc. | Electronic card and detecting method thereof |
| TWI671618B (en) * | 2017-06-05 | 2019-09-11 | 日商東芝記憶體股份有限公司 | Memory card, host device, memory card connector, and memory card adapter |
| TWI717792B (en) * | 2017-06-05 | 2021-02-01 | 日商東芝記憶體股份有限公司 | Memory card |
| US11093811B2 (en) | 2017-06-05 | 2021-08-17 | Kioxia Corporation | Memory card with multiple modes, and host device corresponding to the memory card |
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