TW201530316A - Co-support system and microelectronic assembly - Google Patents

Co-support system and microelectronic assembly Download PDF

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Publication number
TW201530316A
TW201530316A TW104114389A TW104114389A TW201530316A TW 201530316 A TW201530316 A TW 201530316A TW 104114389 A TW104114389 A TW 104114389A TW 104114389 A TW104114389 A TW 104114389A TW 201530316 A TW201530316 A TW 201530316A
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TW
Taiwan
Prior art keywords
contacts
microelectronic
type
module
microelectronic component
Prior art date
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TW104114389A
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Chinese (zh)
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TWI541651B (en
Inventor
Richard Dewitt Crisp
Belgacem Haba
Wael Zohni
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Invensas Corp
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Priority claimed from US13/839,402 external-priority patent/US8787034B2/en
Priority claimed from US13/840,353 external-priority patent/US8848391B2/en
Priority claimed from US13/840,542 external-priority patent/US8848392B2/en
Application filed by Invensas Corp filed Critical Invensas Corp
Publication of TW201530316A publication Critical patent/TW201530316A/en
Application granted granted Critical
Publication of TWI541651B publication Critical patent/TWI541651B/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract

A system may include a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component may include a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Description

共支撐系統和微電子組件 Co-support system and microelectronic components

本申請案的主要內容和微電子結構有關，舉例來說，併入主動式電路元件的結構，例如，但是並不受限於，包含至少一半導體晶片或至少一半導體晶片之部分的結構，以及併入微電子結構的組件。 The main content of the present application relates to a microelectronic structure, for example, a structure incorporating an active circuit component, such as, but not limited to, a structure including at least one semiconductor wafer or a portion of at least one semiconductor wafer, and A component that incorporates a microelectronic structure.

相關申請案交叉參考 Related application cross reference

本申請案為2013年3月15日提申的美國專利申請案第13/840,353號、第13/839,402號、以及第13/840,542號的接續案，前述每一案皆係2012年8月27日提申的美國專利申請案第13/595,486號的部分接續案，本文以引用的方式將它們的揭示內容併入。因此，本文以引用的方式將下面共同擁有及共同待審的美國專利申請案併入：2013年3月15日提申的美國專利申請案第13/841,052號。 This application is a continuation of U.S. Patent Application Serial Nos. 13/840,353, 13/839,402, and 13/840,542, filed on March 15, 2013, each of which is assigned to Part of the continuation of U.S. Patent Application Serial No. 13/595,486, the disclosure of which is incorporated herein by reference. The U.S. Patent Application Serial No. 13/841,052, filed on March 15, 2013, is hereby incorporated by reference.

半導體晶片通常被當作單獨、事先封裝的單元。標準的晶片具有扁平、矩形的主體，其具有龐大的正面，該正面具有被連接至該晶片之內部電路系統的多個接點。每一個單獨的晶片通常容納於一封裝中，該封裝具有被連接至該晶片之該等接點的多個外部終端。接著，該等終端(也就是，該封裝的外部連接點)會被配置成用以電性連接至一電路板，例如， 印刷電路板。於許多習知的設計中，該晶片封裝佔用該電路板的面積明顯大於該晶片本身的面積。如本揭示內容中參考具有一正面的扁平晶片的用法，「晶片的面積」應該被理解為表示該正面的面積。 Semiconductor wafers are typically treated as separate, pre-packaged units. A standard wafer has a flat, rectangular body with a bulky front surface with a plurality of contacts that are connected to the internal circuitry of the wafer. Each individual wafer is typically housed in a package having a plurality of external terminations connected to the contacts of the wafer. The terminals (ie, the external connection points of the package) are then configured to be electrically connected to a circuit board, for example, A printed circuit board. In many conventional designs, the chip package occupies an area of the board that is significantly larger than the area of the wafer itself. As used in this disclosure with reference to the use of a flat wafer having a front side, the "area of the wafer" should be understood to mean the area of the front side.

在晶片的任何實體排列中，尺寸都是重要的考量。隨著可攜式電子裝置的快速發展，對於晶片之更小型實體排列的需求已經愈加強烈。舉例來說，通常稱為「智慧型電話(smart phone)」的裝置會整合蜂巢式電話的功能以及功能強大的資料處理器、記憶體、以及附屬裝置(例如，全球定位系統接收器、電子相機、區域網路連接、以及高解析度顯示器和相關聯的影像處理晶片)。此等裝置提供多項功能，例如，完整的網際網路連接能力、包含完全解析度視訊的娛樂、導航、電子銀行、以及更多功能，全部在口袋尺寸的裝置中。複雜的可攜式裝置需要將眾多晶片封裝至一小型的空間中。又，某些該等晶片有許多輸入和輸出連接，通常稱為「I/O」。此等I/O必須和其它晶片的I/O互連。構成該等互連的器件不應該大幅增加該組件的尺寸。其它應用中有雷同的需求，舉例來說，資料伺服器，例如，需要高效能並且縮減尺寸的網際網路搜尋引擎中所使用的資料伺服器。 Size is an important consideration in any physical arrangement of the wafer. With the rapid development of portable electronic devices, the demand for smaller physical arrangements of wafers has become stronger. For example, a device commonly referred to as a "smart phone" integrates the functionality of a cellular phone with a powerful data processor, memory, and attached devices (eg, GPS receivers, electronic cameras). , regional network connections, and high-resolution displays and associated image processing wafers). These devices offer a variety of features such as full Internet connectivity, entertainment with full resolution video, navigation, e-banking, and more, all in pocket-sized devices. Complex portable devices require a large number of chips to be packaged into a small space. Also, some of these wafers have many input and output connections, commonly referred to as "I/O." These I/Os must be interconnected with the I/O of other wafers. The devices that make up these interconnects should not significantly increase the size of the component. There are similar needs in other applications, for example, data servers, for example, data servers used in high performance and reduced size Internet search engines.

微電子元件(例如，含有記憶體儲存陣列的半導體晶片，尤其是動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶片和快閃記憶體晶片)通常被封裝在單晶片或多晶片封裝與組件中。每一個封裝皆有許多電性連接線，用以在終端和該等微電子元件(舉例來說，位於其中的晶片)之間攜載訊號、電力、以及接地。該等電性連接線可以包含不同種類的導體，例如：，水平導體，舉例來說，線路、樑形導線(beam lead)、…等，它們延伸在相對於一晶片之接點承載表面為水平的方向中；垂直導體，例 如，穿孔，它們延伸在相對於該晶片之該表面為垂直的方向中；以及焊線(wire bond)，它們延伸在相對於該晶片之該表面為水平和垂直的方向中。 Microelectronic components (eg, semiconductor wafers containing memory storage arrays, particularly dynamic random access memory (DRAM) wafers and flash memory wafers) are typically packaged in single or multi-chip packages. In the component. Each package has a plurality of electrical connections for carrying signals, power, and ground between the terminals and the microelectronic components (for example, the wafers located therein). The electrical connection lines may comprise different types of conductors, such as: horizontal conductors, for example, lines, beam leads, etc., which extend horizontally relative to the bearing surface of a wafer. In the direction of the vertical conductor For example, the perforations extend in a direction perpendicular to the surface of the wafer; and wire bonds extend in a horizontal and vertical direction relative to the surface of the wafer.

習知的微電子封裝可能會併入一具有用以定義記憶體儲存陣列的主動式元件的微電子元件。因此，於某些習知的微電子元件中，電晶體或其它主動式元件會構成一有或沒有額外元件的記憶體儲存陣列。於此某些情況中，微電子元件會被配置成以提供記憶體儲存陣列功能為主，也就是，於此情況中，微電子元件為提供記憶體儲存陣列功能而具現的主動式元件的數量可能大於任何其它功能。於某些情況中，一微電子元件可以係或包含一DRAM晶片，或者，可以係或包含一由此等半導體晶片組成的堆疊電性互連組件。一般來說，此封裝的所有終端被放置在相鄰於一鑲嵌著該微電子元件的封裝基板之一或更多個周圍邊緣的多組直行中。 Conventional microelectronic packages may incorporate a microelectronic component having active components for defining a memory storage array. Thus, in some conventional microelectronic components, a transistor or other active component will constitute a memory storage array with or without additional components. In some cases, the microelectronic component will be configured to provide memory storage array functionality, that is, in this case, the number of active components of the microelectronic component that provide memory storage array functionality. May be larger than any other feature. In some cases, a microelectronic component can be or include a DRAM wafer, or can be or include a stacked electrical interconnect assembly of such semiconductor wafers. In general, all of the terminals of the package are placed in groups of straight rows adjacent to one or more surrounding edges of a package substrate inlaid with the microelectronic component.

習知的電路板或其它微電子器件通常會被配置成用以耦合至一於其中具有一或更多個第一類型微電子元件的微電子封裝。此等電路板或其它微電子器件通常無法被耦合至一於其中具有一或更多個不同類型或第二類型微電子元件的微電子封裝。 Conventional circuit boards or other microelectronic devices are typically configured to be coupled to a microelectronic package having one or more first type of microelectronic components therein. Such boards or other microelectronic devices typically cannot be coupled to a microelectronic package having one or more different types or types of microelectronic components therein.

依照前述，可以對電路板或其它微電子器件的設計進行特定改良，以便改良它們的功能靈活性，尤其是在多個封裝會被鑲嵌並且彼此電性互連的電路板或其它微電子器件中。 In accordance with the foregoing, specific modifications can be made to the design of circuit boards or other microelectronic devices to improve their functional flexibility, particularly in circuit boards or other microelectronic devices where multiple packages are embedded and electrically interconnected to each other. .

根據本發明的一項觀點，一種器件會被配置成用於連接一微電子組件，該微電子組件包含一組終端以及一微電子元件，該微電子元件具有一具有給定數量儲存位置的記憶體儲存陣列，該組件的該微電子元件 有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊。該器件可以包含：一支撐結構，其承載被配置成用以攜載該命令與位址資訊的一組導體；以及複數個接點，它們被耦合至該組導體，該等接點被配置成用以連接該微電子組件之該等終端中的對應終端。 According to one aspect of the invention, a device can be configured for connection to a microelectronic assembly comprising a set of terminals and a microelectronic component having a memory having a given number of storage locations Body storage array, the microelectronic component of the assembly There are multiple inputs that connect to the terminals to receive command and address information that explicitly specifies one of the storage locations. The device can include: a support structure carrying a set of conductors configured to carry the command and address information; and a plurality of contacts coupled to the set of conductors, the contacts being configured to Corresponding terminals in the terminals for connecting the microelectronic components.

該等接點可以具有根據用於連接第一類型微電子組件的第一預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成以第一取樣率來取樣經由該等接點(該等接點具有第一數量的接點)與其耦合的命令與位址資訊。該等接點可以具有根據用於連接第二類型微電子組件的第二預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成以大於該第一取樣率的第二取樣率來取樣經由該等接點中的一子集(其包含第二數量的接點)與其耦合的命令與位址資訊，該子集包含佔據和被指派至該第一預設排列方式之接點相同位置的某些接點，該第二數量少於該第一數量。 The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein the microelectronic elements are configured to sample at a first sampling rate Command and address information coupled thereto via the contacts (the contacts have a first number of contacts). The contacts may have address and command information assignments arranged according to a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic component is configured to be greater than the first sampling rate a second sampling rate to sample command and address information coupled thereto via a subset of the contacts (which includes a second number of contacts), the subset including occupancy and assignment to the first preset Some contacts of the same position in the arrangement of the contacts, the second number being less than the first number.

於其中一範例中，根據該第二預設排列方式排列的接點子集中的所有接點會佔據和被指派至該第一預設排列方式的接點相同的位置。於其中一實施例中，該第二取樣率可以係該第一取樣率的整數倍。於一特殊的範例中，該器件可以還包含一被耦合至該組導體的裝置，該裝置可操作用以將該命令與位址資訊驅動至該等接點。於一示範性實施例中，該裝置可以係一微處理器。於其中一範例中，該裝置可以係一緩衝元件。於一特殊的實施例中，該裝置會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過該第一排列方式來連接該器件和第一類型微電子 組件以及透過該第二排列方式來連接該器件和第二類型微電子組件。 In one example, all of the contacts in the subset of contacts arranged according to the second predetermined arrangement occupy the same position as the contacts assigned to the first predetermined arrangement. In one embodiment, the second sampling rate may be an integer multiple of the first sampling rate. In a particular example, the device can further include a device coupled to the set of conductors, the device being operative to drive the command and address information to the contacts. In an exemplary embodiment, the device can be a microprocessor. In one example, the device can be a cushioning element. In a particular embodiment, the apparatus is configured to operate in each of the first mode and the second mode to connect the device and the first type of microelectronics through the first arrangement, respectively And connecting the device and the second type of microelectronic assembly through the second arrangement.

於一特殊的範例中，該器件可以還包含該第一類型微電子組件，其中，該等接點會電性連接該等終端。於其中一實施例中，該器件可以還包含該第二類型微電子組件，其中，該等接點會電性連接該等終端。於一示範性實施例中，該器件可以係一電路板，而且該等接點會曝露在該電路板的一表面處。於其中一範例中，該微電子組件可以係一微電子封裝，且其中，該等終端可以係表面鑲嵌終端並且會曝露在該微電子封裝的一表面處。於一特殊的實施例中，該器件可以係一電路板，而且該等接點會被設置在一電性連接該電路板的插槽中。 In a particular example, the device can further include the first type of microelectronic assembly, wherein the contacts are electrically connected to the terminals. In one embodiment, the device may further include the second type of microelectronic assembly, wherein the contacts are electrically connected to the terminals. In an exemplary embodiment, the device can be a circuit board and the contacts are exposed at a surface of the circuit board. In one example, the microelectronic assembly can be a microelectronic package, and wherein the terminals can be surface mount terminals and exposed at a surface of the microelectronic package. In a particular embodiment, the device can be a circuit board and the contacts can be placed in a socket that is electrically connected to the circuit board.

於一示範性實施例中，該微電子組件可以包含一模組卡，其具有第一和第二反向的表面。該等終端可以係該等第一表面和第二表面中至少其中一者處的複數個平行曝露終端，用以在該模組被插入該插槽中時配接該插槽的接點。於其中一實施例中，該器件可以係一電路板，而且該等接點會被設置在一電性連接該電路板的連接器中。該微電子組件可以包含一模組卡，其具有第一和第二反向的表面。該等終端可以係曝露在該等第一表面和第二表面中其中一者處的複數個終端，用以在該模組被附接至該連接器時配接該連接器的接點。 In an exemplary embodiment, the microelectronic assembly can include a module card having first and second opposing surfaces. The terminals may be a plurality of parallel exposure terminals at at least one of the first surface and the second surface for mating the contacts of the socket when the module is inserted into the socket. In one embodiment, the device can be a circuit board and the contacts are disposed in a connector that is electrically connected to the circuit board. The microelectronic assembly can include a module card having first and second opposing surfaces. The terminals may be a plurality of terminals exposed at one of the first and second surfaces for mating the contacts of the connector when the module is attached to the connector.

於一特殊的範例中，該微電子組件可以係一第一微電子組件而該器件可以係一第二微電子組件，而且該等接點可以係該第二微電子組件的終端。於其中一範例中，該第二微電子組件可能會被耦合至該支撐結構並且可以包含一於其中具有主動式裝置的微電子元件。該第二微電子組件的終端會藉由僅延伸在該第二微電子組件裡面的電性連接線來耦合該第 二微電子組件的微電子元件。 In a particular example, the microelectronic assembly can be a first microelectronic assembly and the device can be a second microelectronic assembly, and the contacts can be the terminals of the second microelectronic assembly. In one example, the second microelectronic component may be coupled to the support structure and may include a microelectronic component having an active device therein. The terminal of the second microelectronic component is coupled to the first by an electrical connection line extending only within the second microelectronic component Microelectronic components of two microelectronic components.

於一特殊的實施例中，介於該第二微電子組件之該等終端和該第二微電子組件之該微電子元件之間的該等電性連接線可以包含延伸在一垂直於該第二微電子組件之表面(該第二微電子組件的該等終端曝露在該表面處)的方向中的互連元件。該等互連元件會被配置成用於進行封裝上封裝堆疊。於其中一實施例中，介於該第二微電子組件之該等終端和該第二微電子組件之該微電子元件之間的該等電性連接線可以包含一焊接穿孔陣列，從該第二微電子組件的該等終端處延伸至曝露在該第二微電子組件的一基板的表面處的接點。 In a special embodiment, the electrical connection lines between the terminals of the second microelectronic component and the microelectronic component of the second microelectronic component may comprise extending perpendicular to the first An interconnecting element in the direction of the surface of the two microelectronic assembly that is exposed at the surface of the second microelectronic assembly. The interconnecting elements will be configured for package-on-package stacking. In one embodiment, the electrical connection lines between the terminals of the second microelectronic component and the microelectronic component of the second microelectronic component may comprise a solder via array from the The terminals of the two microelectronic assemblies extend to contacts that are exposed at the surface of a substrate of the second microelectronic assembly.

於一特殊的範例中，該第二微電子組件可能會被耦合至該支撐結構並且可以包含一於其中具有主動式裝置的微電子元件。該第二微電子組件的終端會延伸在該第二微電子組件之該微電子元件的表面處。於一示範性實施例中，該第二微電子組件之該微電子元件可以係一第一微電子元件。該第二微電子組件可以還包含各自於其中具有主動式裝置的至少一第二微電子元件。該等第一微電子元件與第二微電子元件會以堆疊配置的方式被排列。於其中一範例中，該第二微電子組件的終端會藉由延伸穿過該至少一第二微電子元件的直通矽穿孔來電性連接該等支撐結構的該組導體。 In a particular example, the second microelectronic component may be coupled to the support structure and may include a microelectronic component having an active device therein. A terminal of the second microelectronic assembly extends at a surface of the microelectronic component of the second microelectronic component. In an exemplary embodiment, the microelectronic component of the second microelectronic component can be a first microelectronic component. The second microelectronic assembly can further include at least one second microelectronic component each having an active device therein. The first microelectronic component and the second microelectronic component are arranged in a stacked configuration. In one example, the terminals of the second microelectronic assembly are electrically connected to the set of conductors of the support structures by through-through turns extending through the at least one second microelectronic component.

於一特殊的實施例中，該第二微電子組件的微電子元件可以包含一邏輯功能。於其中一實施例中，該等接點可以係第一接點，而該等導體可以係第一組導體。該器件可以還包含被耦合至一第二組導體的複數個第二接點。該等第二接點會被配置成用以連接該微電子組件的對應終 端。該等第二接點會被配置成用以攜載該命令與位址資訊以外的資訊。於一特殊的範例中，該等接點可以係第一接點，而該等導體可以係第一組導體。該器件可以還包含被耦合至一第二組導體的複數個電力接點和接地接點。該等電力接點和接地接點會被配置成用以連接該微電子組件的對應終端。該等電力接點和接地接點會被配置成用以分別攜載一電力電位和一參考電位。 In a particular embodiment, the microelectronic component of the second microelectronic component can include a logic function. In one embodiment, the contacts may be first contacts and the conductors may be a first set of conductors. The device can also include a plurality of second contacts coupled to a second set of conductors. The second contacts are configured to connect to the corresponding end of the microelectronic component end. The second contacts are configured to carry information other than the command and address information. In a particular example, the contacts can be first contacts and the conductors can be a first set of conductors. The device can also include a plurality of power contacts and ground contacts coupled to a second set of conductors. The power contacts and ground contacts are configured to connect to corresponding terminals of the microelectronic assembly. The power contacts and ground contacts are configured to carry a power potential and a reference potential, respectively.

於一示範性實施例中，當該等第一接點具有根據第二預設排列方式被排列的指派時，該第二類型微電子組件的微電子元件會被配置成用以連接該等電力接點和接地接點，該等電力接點和接地接點具有第三數量的接點。當該等第一接點具有根據第一預設排列方式被排列的指派時，該第一類型微電子組件的微電子元件會被配置成用以連接該等電力接點和接地接點中的一子集，該子集包含第四數量的電力接點和接地接點，該第四數量少於該第三數量。 In an exemplary embodiment, when the first contacts have an assignment arranged according to a second predetermined arrangement, the microelectronic components of the second type of microelectronic components are configured to connect the power Contact and ground contacts, the power contacts and ground contacts having a third number of contacts. When the first contacts have an assignment arranged according to a first predetermined arrangement, the microelectronic components of the first type of microelectronic components are configured to connect the power contacts and the ground contacts A subset comprising a fourth number of power contacts and ground contacts, the fourth number being less than the third number.

於其中一範例中，該第一類型微電子組件中的微電子元件可以為DDRx型。於一特殊的實施例中，該第二類型微電子組件中的微電子元件可以為LPDDRx型。於其中一實施例中，該第一類型微電子組件中的微電子元件可以為GDDRx型。於一特殊的實施例中，一種系統可以包含一如上面所述的器件以及被電性連接至該器件的一或更多個其它電子器件。於一示範性實施例中，該系統可以還包含一殼體，該器件以及該等一或更多個其它電子器件會和該殼體組裝在一起。 In one example, the microelectronic component of the first type of microelectronic component can be of the DDRx type. In a particular embodiment, the microelectronic component of the second type of microelectronic component can be of the LPDDRx type. In one embodiment, the microelectronic component of the first type of microelectronic component can be of the GDDRx type. In a particular embodiment, a system can include a device as described above and one or more other electronic devices electrically coupled to the device. In an exemplary embodiment, the system can further include a housing with the device and the one or more other electronic components assembled with the housing.

根據本發明的另一項觀點，一種器件會被配置成用以連接一微電子組件，該微電子組件包含一組終端以及一具有一具有給定數量儲存 位置之記憶體儲存陣列的微電子元件，該組件的該微電子元件有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊。該器件可以包含：一支撐結構，其承載被配置成用以攜載該命令與位址資訊的一組導體；以及複數個接點，它們被耦合至該組導體，該等接點被配置成用以連接該微電子組件之該等終端中的對應終端。 According to another aspect of the present invention, a device is configured to connect to a microelectronic component, the microelectronic component comprising a set of terminals and a having a given number of stores The microelectronic component of the memory storage array of the location, the microelectronic component of the component having a plurality of inputs that are coupled to the terminals for receiving command and address information that explicitly specifies one of the storage locations. The device can include: a support structure carrying a set of conductors configured to carry the command and address information; and a plurality of contacts coupled to the set of conductors, the contacts being configured to Corresponding terminals in the terminals for connecting the microelectronic components.

該等接點可以具有根據用於連接第一類型微電子組件的第一預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等接點中的第一子集(其包含第一數量的接點)與其耦合的命令與位址資訊。該等接點可以具有根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等接點中的第二子集(其包含第二數量的接點)與其耦合的命令與位址資訊，該等第一子集與第二子集包含佔據相同位置的某些接點，該第二數量少於該第一數量。 The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein the microelectronic components are configured to sample via the The first subset of points (which contain the first number of contacts) are coupled with command and address information. The contacts may have address and command information assignments arranged according to a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic components are configured to sample via the a second subset of points (which includes a second number of contacts) with command and address information coupled thereto, the first subset and the second subset including certain contacts occupying the same location, the second The number is less than the first quantity.

於其中一範例中，第一類型微電子組件的命令與位址資訊可以包含同位元資訊，該第一類型微電子組件中的微電子元件會被配置成用以取樣該同位元資訊，而用於連接第二類型微電子組件的該等接點中的第二子集不會被配置成用以取樣該同位元資訊。於一示範性實施例中，該第二類型微電子組件中的微電子元件可以係DDR3型，而該第一類型微電子組件中的微電子元件可以係DDR4型。 In one example, the command and address information of the first type of microelectronic component may include the same bit information, and the microelectronic component of the first type of microelectronic component is configured to sample the same bit information, and The second subset of the contacts connecting the second type of microelectronic components is not configured to sample the peer information. In an exemplary embodiment, the microelectronic component of the second type of microelectronic component may be of the DDR3 type, and the microelectronic component of the first type of microelectronic component may be of the DDR4 type.

於其中一實施例中，具有DDR4型微電子元件之該第一類型微電子組件中的命令與位址資訊可以包含同位元資訊，而且該第一類型微電子組件中的該DDR4型微電子元件會被配置成用以取樣該同位元資訊。 於一特殊的範例中，該第二類型微電子組件中的微電子元件可以係DDRx型，而該第一類型微電子組件中的微電子元件可以係DDR(x+1)型。 In one embodiment, the command and address information in the first type of microelectronic component having the DDR4 type microelectronic component may include the parity information, and the DDR4 type microelectronic component in the first type of microelectronic component It will be configured to sample the same bit information. In a particular example, the microelectronic component of the second type of microelectronic component can be of the DDRx type, and the microelectronic component of the first type of microelectronic component can be of the DDR(x+1) type.

根據本發明的一項觀點，一種模組會被配置成用以連接至少一微電子組件，每一個微電子組件皆包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊。該模組可以包含一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊；以及至少一組共支撐接點，它們會被耦合至該組導體。每一組共支撐接點皆會曝露在該第一表面或是該第二表面處。每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電子組件的該終端組。 According to one aspect of the invention, a module is configured to connect at least one microelectronic component, each microelectronic component comprising a set of terminals and a memory storage array having a given number of storage locations. The microelectronic component, the microelectronic component of each microelectronic component has a plurality of inputs that are coupled to the terminals to receive command and address information that explicitly specifies one of the storage locations. The module can include a circuit board having first and second opposing surfaces and carrying a set of conductors configured to carry the command and address information; and at least one set of co-supporting Points, they will be coupled to the set of conductors. Each set of co-supporting contacts is exposed to the first surface or the second surface. Each set of co-supporting contacts is configured to connect to the set of terminals of a single microelectronic assembly of the at least one microelectronic component.

該模組可以還包含複數個模組接點，它們會被耦合至該組導體。該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊。該等模組接點會被配置成用以連接位於該模組外部的一器件。該至少一組共支撐接點中的每一者皆可以包含多個第一接點，它們具有根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成以第一取樣率來取樣經由該等第一接點(該等第一接點具有第一數量的接點)與其耦合的命令與位址資訊。 The module can also include a plurality of module contacts that are coupled to the set of conductors. The module contacts are configured to carry information transmitted to and from the at least one set of co-support contacts. The module contacts are configured to connect a device external to the module. Each of the at least one set of co-supporting contacts may include a plurality of first contacts having address and command information arranged according to a first predetermined arrangement for connecting the first type of microelectronic components Assignment, wherein the microelectronic component is configured to sample command and address information coupled thereto via the first contacts (the first contacts having a first number of contacts) at a first sampling rate.

該至少一組共支撐接點中的每一者皆可以包含多個第一接點，它們具有根據用於連接第二類型微電子組件的第二預設排列方式所排 列的位址與命令資訊指派，其中，該微電子元件會被配置成以大於第一取樣率的第二取樣率來取樣經由該等第一接點中的一子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該子集包含佔據和被指派至該第一預設排列方式之第一接點相同位置的某些第一接點，該第二數量少於該第一數量。 Each of the at least one set of co-supporting contacts may include a plurality of first contacts that are arranged in accordance with a second predetermined arrangement for connecting the second type of microelectronic components The address of the column is assigned with a command information, wherein the microelectronic component is configured to sample at a second sampling rate greater than the first sampling rate via a subset of the first contacts (which includes the second number a first contact) with command and address information coupled thereto, the subset including certain first contacts occupying the same location as the first contact of the first predetermined arrangement, the second number Less than the first quantity.

於其中一範例中，根據該第二預設排列方式排列的第一接點的子集中的所有接點會佔據和被指派至該第一預設排列方式的第一接點相同的位置。於其中一實施例中，該第二取樣率可以係該第一取樣率的整數倍。於一特殊的範例中，每一組共支撐接點中的該等第一接點可以包含被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊的接點。於一示範性實施例中，該模組可以包含一被耦合至該組導體的裝置，該裝置可操作用以將該命令與位址資訊驅動至該等第一接點。於其中一範例中，該裝置可以係一緩衝元件。於一特殊的實施例中，該裝置會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過該第一排列方式來連接該模組和第一類型微電子組件以及透過該第二排列方式來連接該模組和第二類型微電子組件。 In one example, all of the contacts in the subset of the first contacts arranged according to the second predetermined arrangement occupy the same position as the first contacts assigned to the first predetermined arrangement. In one embodiment, the second sampling rate may be an integer multiple of the first sampling rate. In a particular example, the first contacts in each set of co-supporting contacts may include interfaces that are assigned to carry address information that can be used to explicitly specify a location within the memory storage array. point. In an exemplary embodiment, the module can include a device coupled to the set of conductors, the device being operative to drive the command and address information to the first contacts. In one example, the device can be a cushioning element. In a particular embodiment, the apparatus is configured to operate in each of the first mode and the second mode to connect the module and the first type of micro through the first arrangement The electronic component and the second arrangement are connected to the module and the second type of microelectronic assembly.

於一特殊的範例中，該模組可以包含該第一類型微電子組件。該至少一組共支撐接點中的一組會電性連接該第一類型微電子組件的該等終端。於其中一實施例中，該模組可以包含該第二類型微電子組件。該至少一組共支撐接點中的一組會電性連接該第二類型微電子組件的該等終端。於一示範性實施例中，該微電子組件可以係一微電子封裝。該等終端可以係表面鑲嵌終端並且會曝露在該微電子封裝的一表面處。於其中一 範例中，該電路板可以係一模組卡。該等模組接點可以係該等第一表面和第二表面中至少其中一者處的複數個平行曝露接點，用以在該模組被插入一第二電路板的插槽中時配接該插槽的接點。 In a particular example, the module can include the first type of microelectronic assembly. One of the at least one set of co-supporting contacts electrically connects the terminals of the first type of microelectronic assembly. In one embodiment, the module can include the second type of microelectronic assembly. One of the at least one set of co-supporting contacts electrically connects the terminals of the second type of microelectronic assembly. In an exemplary embodiment, the microelectronic assembly can be a microelectronic package. The terminals may be surface mount terminals and may be exposed at a surface of the microelectronic package. One of them In the example, the board can be a module card. The module contacts may be a plurality of parallel exposed contacts at at least one of the first surface and the second surface for use when the module is inserted into a slot of a second circuit board Connect the contacts of the slot.

於一特殊的實施例中，該電路板可以係一模組卡。該等模組接點可以係該等第一表面和第二表面中其中一者處的複數個接點，用以在該模組被附接至一第二電路板的連接器時配接該連接器的接點。於其中一實施例中，該等模組接點可以係曝露在該等第一表面和第二表面中其中一者處的表面鑲嵌接點，用以在該模組接合一第二電路板時面向並且電性連接該第二電路板的接點。於一特殊的範例中，該至少一組共支撐接點中的每一者可以皆包含被配置成用以攜載該命令與位址資訊以外之資訊的第二接點。 In a particular embodiment, the circuit board can be a module card. The module contacts may be a plurality of contacts at one of the first surface and the second surface for mating the module when attached to a connector of a second circuit board The connector's contacts. In one embodiment, the module contacts may be surface inlaid contacts exposed to one of the first surface and the second surface for engaging a second circuit board in the module. A contact that faces and electrically connects the second circuit board. In a particular example, each of the at least one set of co-supported contacts can include a second contact configured to carry information other than the command and address information.

於一示範性實施例中，該至少一組共支撐接點中的每一者會曝露在該電路板之第一表面的一對應區域中。該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的一周圍的至少第一與第二反向邊緣相鄰的第一區域與第二區域中。該個別共支撐接點組的所有第一接點會被設置在該個別共支撐接點組的該等第一區域與第二區域之間。 In an exemplary embodiment, each of the at least one set of co-supporting contacts is exposed in a corresponding region of the first surface of the circuit board. At least some of the second contacts of each of the at least one set of co-supporting contacts are disposed at least with the first and second reverse edges of a region of the region of the individual co-supporting contact groups Adjacent first and second regions. All of the first contacts of the individual co-supporting contact sets are disposed between the first and second regions of the individual co-supporting contact sets.

於其中一範例中，該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的該周圍的至少第三與第四反向邊緣相鄰的第三區域與第四區域中。該等第三邊緣與第四邊緣中的每一者可以延伸在一位於該等第一邊緣與第二邊緣之間的方向中。該個別共支撐接點組的所有第一接點會被設置在該個別共支撐接點 組的該等第三區域與第四區域之間。 In one example, at least some of the second contacts of each of the at least one set of co-supporting contacts are disposed at least a third of the circumference of the region of the individual co-supporting contact sets In the third area and the fourth area adjacent to the fourth reverse edge. Each of the third and fourth edges may extend in a direction between the first and second edges. All of the first contacts of the individual co-supporting contact group are disposed at the individual co-supporting contacts Between the third and fourth regions of the group.

於一特殊的實施例中，該第一類型微電子組件中的微電子元件可以係DDRx型。於其中一實施例中，該第二類型微電子組件中的微電子元件可以係LPDDRx型。於一特殊的範例中，該第一類型微電子組件中的微電子元件可以係GDDRx型。於一示範性實施例中，該至少一組共支撐接點可以在該第一表面處包含一第一組並且在該第一表面處包含一第二組，該第二組在一平行於該第一表面的方向中與該第一組隔開。於其中一範例中，該至少一組共支撐接點可以在該第一表面處包含一第一組並且在該第二表面處包含一第二組。 In a particular embodiment, the microelectronic components of the first type of microelectronic assembly can be of the DDRx type. In one embodiment, the microelectronic components in the second type of microelectronic assembly can be of the LPDDRx type. In a particular example, the microelectronic components of the first type of microelectronic assembly can be of the GDDRx type. In an exemplary embodiment, the at least one set of co-supporting contacts may include a first group at the first surface and a second group at the first surface, the second group being parallel to the The first surface is spaced apart from the first set. In one example, the at least one set of co-supporting joints can include a first set at the first surface and a second set at the second surface.

於其中一實施例中，每一組共支撐接點中的第一接點可以包含第一群第一接點和第二群第一接點，每一群第一接點會被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊。於一特殊的實施例中，在每一組共支撐接點裡面，該第一群的該等第一接點中的每一者的訊號指派會以一理論軸為基礎對稱於該第二群的一對應第一接點的訊號指派。於一特殊的範例中，當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該微電子元件會被配置成用以連接該等第一群和第二群中每一群中的第一接點。 In one embodiment, the first contact of each set of common support contacts may include a first group of first contacts and a second group of first contacts, each group of first contacts being assigned to carry The payload can be used to explicitly specify address information for a location within the memory storage array. In a special embodiment, in each set of co-supporting contacts, the signal assignment of each of the first contacts of the first group is symmetric to the second group based on a theoretical axis. A signal assignment corresponding to the first contact. In a particular example, when each set of co-supporting contacts has an assignment arranged according to the first predetermined arrangement, the microelectronic component of the first type of microelectronic assembly is configured to connect to the Waiting for the first junction in each of the first group and the second group.

於一示範性實施例中，該第一類型微電子組件可以包含複數個微電子元件。當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該等複數個微電子元件中的每一者會被配置成用以連接該等第一群和第二群中每一群中的第一接點。於其中一範例中，當每一組共支撐接點具有根據該第二預設排列方式所排列的指派 時，該第二類型微電子組件的該微電子元件會被配置成用以連接該第一群的第一接點而不連接該第二群的第一接點。 In an exemplary embodiment, the first type of microelectronic assembly can include a plurality of microelectronic components. Each of the plurality of microelectronic components of the first type of microelectronic assembly is configured to connect when each set of co-supporting contacts has an assignment arranged according to the first predetermined arrangement The first contact in each of the first group and the second group. In one example, when each set of co-supporting contacts has an assignment arranged according to the second predetermined arrangement The microelectronic component of the second type of microelectronic assembly is configured to connect the first contact of the first group without connecting the first contact of the second group.

於一特殊的實施例中，該第二類型微電子組件可以包含複數個微電子元件，其包括前半部微電子元件和後半部微電子元件。當每一組共支撐接點具有根據該第二預設排列方式所排列的指派時，該第二類型微電子組件的前半部微電子元件中的每一者會被配置成用以連接該第一群第一接點而不連接該第二群第一接點，而該第二類型微電子組件的後半部微電子元件中的每一者會被配置成用以連接該第二群第一接點而不連接該第一群第一接點。於一特殊的範例中，一種系統可以包含：一如上所述的模組；以及一或更多個其它電子器件，被電性連接至該模組。於一示範性實施例中，該系統可以還包含一外殼，該模組及該等一或更多個其它電子器件會與該外殼組裝在一起。 In a particular embodiment, the second type of microelectronic assembly can include a plurality of microelectronic components including a front half microelectronic component and a second half microelectronic component. Each of the first half of the microelectronic components of the second type of microelectronic component is configured to connect to each of the first set of microelectronic components when the set of common support contacts has an assignment according to the second predetermined arrangement a group of first contacts that are not connected to the second group of first contacts, and each of the second half of the second type of microelectronic components is configured to connect to the second group first The junction is not connected to the first group of first contacts. In a particular example, a system can include: a module as described above; and one or more other electronic devices electrically coupled to the module. In an exemplary embodiment, the system can further include a housing that can be assembled with the housing and the one or more other electronic components.

根據本發明的另一項觀點，一種模組會被配置成用以連接至少一微電子組件，每一個微電子組件皆包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊。該模組可以包含一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊。 According to another aspect of the present invention, a module is configured to connect at least one microelectronic component, each microelectronic component comprising a set of terminals and a memory storage array having a given number of storage locations The microelectronic component, the microelectronic component of each microelectronic component has a plurality of inputs that are coupled to the terminals to receive command and address information that explicitly specifies one of the storage locations. The module can include a circuit board having first and second opposing surfaces and carrying a set of conductors configured to carry the command and address information.

該模組可以還包含至少一組共支撐接點，它們會被耦合至該組導體，每一組共支撐接點皆會曝露在該第一表面或是該第二表面處，每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電 子組件的該終端組。該模組可以還包含複數個模組接點，它們會被耦合至該組導體，該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊，該等模組接點會被配置成用以連接位於該模組外部的一器件。 The module may further comprise at least one set of co-supporting contacts that are coupled to the set of conductors, each set of common support contacts being exposed to the first surface or the second surface, each set of The support contacts are all configured to be connected to the single micro-electricity of the at least one microelectronic component The terminal group of the subcomponent. The module can further include a plurality of module contacts that are coupled to the set of conductors, the module contacts being configured to carry and transmit to and from the at least one set of co-supporting contacts Information, the module contacts are configured to connect a device external to the module.

該至少一組共支撐接點中的每一者皆可以包含具有根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派的多個第一接點，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第一子集(其包含第一數量的第一接點)與其耦合的命令與位址資訊。該至少一組共支撐接點中的每一者皆可以包含具有根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派的多個第一接點，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第二子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該等第一子集與第二子集包含佔據相同位置的某些第一接點，該第二數量少於該第一數量。 Each of the at least one set of co-supporting contacts may include a plurality of first contacts having address and command information assignments according to a first predetermined arrangement for connecting the first type of microelectronic components The microelectronic component is configured to sample command and address information coupled thereto via a first subset of the first contacts (which includes a first number of first contacts). Each of the at least one set of co-supporting contacts may include a plurality of first contacts having address and command information assignments according to a second predetermined arrangement for connecting the second type of microelectronic components The microelectronic component is configured to sample command and address information coupled thereto via a second subset of the first contacts (which includes a second number of first contacts) The first subset and the second subset comprise certain first contacts occupying the same location, the second number being less than the first number.

於其中一範例中，第一類型微電子組件的命令與位址資訊可以包含同位元資訊，該第一類型微電子組件中的微電子元件會被配置成用以取樣該同位元資訊，而用於連接第二類型微電子組件的該等第一接點中的第二子集不會被配置成用以取樣該同位元資訊。於一示範性實施例中，該第二類型微電子組件中的微電子元件可以係DDR3型，而該第一類型微電子組件中的微電子元件可以係DDR4型。 In one example, the command and address information of the first type of microelectronic component may include the same bit information, and the microelectronic component of the first type of microelectronic component is configured to sample the same bit information, and The second subset of the first contacts connecting the second type of microelectronic components are not configured to sample the parity information. In an exemplary embodiment, the microelectronic component of the second type of microelectronic component may be of the DDR3 type, and the microelectronic component of the first type of microelectronic component may be of the DDR4 type.

於其中一實施例中，具有DDR4型微電子元件之該第一類型微電子組件中的命令與位址資訊可以包含同位元資訊，而且該第一類型微 電子組件中的該DDR4型微電子元件會被配置成用以取樣該同位元資訊。於一特殊的範例中，該第二類型微電子組件中的微電子元件可以係DDRx型，而該第一類型微電子組件中的微電子元件可以係DDR(x+1)型。 In one embodiment, the command and address information in the first type of microelectronic component having the DDR4 type microelectronic component may include the same bit information, and the first type of micro The DDR4 type microelectronic component in the electronic component is configured to sample the parity information. In a particular example, the microelectronic component of the second type of microelectronic component can be of the DDRx type, and the microelectronic component of the first type of microelectronic component can be of the DDR(x+1) type.

根據本發明的一項觀點，一種系統可以包含：一微電子組件，該微電子組件包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，該組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊；以及一器件，用於連接該微電子組件。該器件可以包含：一承載一組導體的支撐結構，該組導體被配置成用以攜載該命令與位址資訊；以及複數個接點，它們會被耦合至該組導體，該等接點會電性連接該微電子組件的該等終端中的對應終端。 According to one aspect of the invention, a system can include: a microelectronic assembly comprising a set of terminals and a microelectronic component having a memory storage array having a given number of storage locations, the component of the component The microelectronic components each have a plurality of inputs that connect to the terminals to receive command and address information that explicitly designate one of the storage locations; and a device for connecting the microelectronic components. The device can include: a support structure carrying a set of conductors configured to carry the command and address information; and a plurality of contacts that are coupled to the set of conductors, the contacts A corresponding terminal in the terminals of the microelectronic component is electrically connected.

該等接點可以具有根據用於連接第一類型微電子組件的第一預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成以第一取樣率來取樣經由該等接點(該等接點具有第一數量的接點)與其耦合的命令與位址資訊。該等接點可以具有根據用於連接第二類型微電子組件的第二預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成以大於該第一取樣率的第二取樣率來取樣經由該等接點中的一子集(其包含第二數量的接點)與其耦合的命令與位址資訊，該子集包含佔據和被指派至該第一預設排列方式之接點相同位置的某些接點，該第二數量少於該第一數量。 The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein the microelectronic elements are configured to sample at a first sampling rate Command and address information coupled thereto via the contacts (the contacts have a first number of contacts). The contacts may have address and command information assignments arranged according to a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic component is configured to be greater than the first sampling rate a second sampling rate to sample command and address information coupled thereto via a subset of the contacts (which includes a second number of contacts), the subset including occupancy and assignment to the first preset Some contacts of the same position in the arrangement of the contacts, the second number being less than the first number.

於其中一範例中，根據該第二預設排列方式排列的接點子集中的所有接點會佔據和被指派至該第一預設排列方式的接點相同的位置。 於其中一實施例中，該第二取樣率可以係該第一取樣率的整數倍。於一特殊的範例中，該系統可以還包含一被耦合至該組導體的裝置，該裝置可操作用以將該命令與位址資訊驅動至該等接點。於一示範性實施例中，該裝置可以係一微處理器。於其中一範例中，該裝置會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過該第一排列方式來連接該器件和第一類型微電子組件以及透過該第二排列方式來連接該器件和第二類型微電子組件。於一特殊的實施例中，該系統可以還包含至少一中央處理單元(Central Processing Unit，CPU)。該CPU會被配置成用以控制該系統中複數個器件的操作，其包含向該微電子組件進行的讀取操作以及寫入至該微電子組件的寫入操作。 In one example, all of the contacts in the subset of contacts arranged according to the second predetermined arrangement occupy the same position as the contacts assigned to the first predetermined arrangement. In one embodiment, the second sampling rate may be an integer multiple of the first sampling rate. In a particular example, the system can further include a device coupled to the set of conductors, the device being operative to drive the command and address information to the contacts. In an exemplary embodiment, the device can be a microprocessor. In one example, the apparatus is configured to operate in each of the first mode and the second mode to respectively connect the device and the first type of microelectronic component through the first arrangement and The device and the second type of microelectronic assembly are connected by the second arrangement. In a particular embodiment, the system can further include at least one Central Processing Unit (CPU). The CPU is configured to control the operation of a plurality of devices in the system, including read operations to the microelectronic assembly and write operations to the microelectronic assembly.

於一特殊的範例中，該系統可以還包含一電源供應器，其被配置成用以供應讓該器件和該微電子組件使用的電力。於其中一實施例中，該微電子組件可以係第一類型微電子組件。於一示範性實施例中，該微電子組件可以係第二類型微電子組件。於其中一範例中，該器件可以係一電路板，而且該等接點會曝露在該電路板的一表面處。於一特殊的實施例中，該微電子組件可以係一微電子封裝。該等終端可以係曝露在該微電子封裝的一表面處的表面鑲嵌終端。 In a particular example, the system can further include a power supply configured to supply power for use by the device and the microelectronic assembly. In one embodiment, the microelectronic assembly can be a first type of microelectronic assembly. In an exemplary embodiment, the microelectronic assembly can be a second type of microelectronic assembly. In one example, the device can be a circuit board and the contacts are exposed at a surface of the board. In a particular embodiment, the microelectronic assembly can be a microelectronic package. The terminals may be surface mount terminals exposed at a surface of the microelectronic package.

於一示範性實施例中，該電路板可以係一主機線路板(motherboard)。於其中一實施例中，該電路板可以係一模組卡，該模組卡包含一或更多列曝露的模組接點，該等模組接點列中的至少其中一者被設置在該等第一表面或第二表面的一邊緣旁邊，用以在該模組被插入一第二電路板的插槽中時配接該插槽的接點。於一特殊的範例中，該器件可以係一 電路板，而且該等接點會被設置在一電性連接該電路板的插槽中。於其中一範例中，該微電子組件可以包含一模組卡，其具有第一和第二反向的表面。該等終端可以係在該等第一表面和第二表面中至少其中一者的一邊緣旁邊的複數個平行曝露終端，用以在該模組被插入該插槽中時配接該插槽的接點。 In an exemplary embodiment, the circuit board can be a motherboard. In one embodiment, the circuit board can be a module card, the module card includes one or more columns of exposed module contacts, and at least one of the module contact columns is disposed at Adjacent to an edge of the first surface or the second surface, the contact of the slot is mated when the module is inserted into a slot of a second circuit board. In a special case, the device can be tied to one A circuit board, and the contacts are disposed in a slot electrically connected to the circuit board. In one example, the microelectronic assembly can include a module card having first and second opposing surfaces. The terminals may be a plurality of parallel exposure terminals beside an edge of at least one of the first surface and the second surface for mating the socket when the module is inserted into the slot contact.

於一特殊的實施例中，該器件可以係一電路板，而且該等接點會被設置在一電性連接該電路板的連接器中。該微電子組件可以包含一模組卡，其具有第一和第二反向的表面。該等終端可以係曝露在該等第一表面和第二表面中其中一者處的複數個平行終端，用以在該模組被附接至該連接器時配接該連接器的接點。於其中一實施例中，該微電子組件可以係一第一微電子組件，而該器件可以係一第二微電子組件，而且該等接點可以係該第二微電子組件的終端。 In a particular embodiment, the device can be a circuit board and the contacts can be placed in a connector that is electrically connected to the circuit board. The microelectronic assembly can include a module card having first and second opposing surfaces. The terminals may be a plurality of parallel terminals exposed at one of the first and second surfaces for mating the contacts of the connector when the module is attached to the connector. In one embodiment, the microelectronic assembly can be a first microelectronic assembly, and the device can be a second microelectronic assembly, and the contacts can be terminals of the second microelectronic assembly.

於一特殊的範例中，該第二微電子組件可能會被耦合至該支撐結構並且包含一於其中具有主動式裝置的微電子元件。該第一微電子組件的該微電子元件會藉由僅延伸在該等第一微電子組件和第二微電子組件裡面的電性連接線來耦合該第二微電子組件的微電子元件。於一示範性實施例中，介於該第一微電子組件之該微電子元件和該第二微電子組件之該微電子元件之間的該等電性連接線可以包含延伸在一垂直於該第二微電子組件之表面(該第二微電子組件的該等終端曝露在該表面處)的方向中的互連元件。該等互連元件會被配置成用於進行封裝上封裝堆疊。 In a particular example, the second microelectronic component may be coupled to the support structure and include a microelectronic component having an active device therein. The microelectronic component of the first microelectronic component couples the microelectronic component of the second microelectronic component by an electrical connection extending only within the first microelectronic component and the second microelectronic component. In an exemplary embodiment, the electrical connection lines between the microelectronic component of the first microelectronic component and the microelectronic component of the second microelectronic component may comprise extending perpendicular to the An interconnecting element in the direction of the surface of the second microelectronic component that is exposed at the surface of the second microelectronic component. The interconnecting elements will be configured for package-on-package stacking.

於其中一範例中，介於該第一微電子組件之該微電子元件和該第二微電子組件之該微電子元件之間的該等電性連接線可以包含一焊接 穿孔陣列，從該第二微電子組件的該等終端處延伸至曝露在該第二微電子組件的一基板的表面處的接點。於一特殊的實施例中，該第二微電子組件會被耦合至該支撐結構並且包含一於其中具有主動式裝置的微電子元件，該第二微電子組件的終端會曝露在該第二微電子組件的微電子元件的一表面處。 In one example, the electrical connection between the microelectronic component of the first microelectronic component and the microelectronic component of the second microelectronic component can comprise a solder A perforated array extends from the terminals of the second microelectronic assembly to contacts that are exposed at a surface of a substrate of the second microelectronic assembly. In a particular embodiment, the second microelectronic component is coupled to the support structure and includes a microelectronic component having an active device therein, the terminal of the second microelectronic component being exposed to the second micro A surface of a microelectronic component of an electronic component.

於其中一實施例中，該第二微電子組件的微電子元件可以係一第一微電子元件。該第二微電子組件可以還包含至少一第二微電子元件，每一個第二微電子元件中皆有主動式裝置。該等第一微電子元件與第二微電子元件會被排列成堆疊配置。於一特殊的範例中，該第二微電子組件的終端會藉由延伸穿過該至少一第二微電子元件的直通矽穿孔來電性連接該等支撐結構的該組導體。 In one embodiment, the microelectronic component of the second microelectronic component can be a first microelectronic component. The second microelectronic assembly can further include at least one second microelectronic component, each of which has an active device. The first microelectronic component and the second microelectronic component are arranged in a stacked configuration. In a particular example, the terminals of the second microelectronic assembly are electrically connected to the set of conductors of the support structures by through-through turns extending through the at least one second microelectronic component.

於一示範性實施例中，該第二微電子組件的微電子元件可以包含一邏輯功能。於其中一範例中，該等接點可以係第一接點，而該等導體可以係第一組導體。該器件可以還包含被耦合至一第二組導體的複數個第二接點。該等第二接點會被配置成用以連接該微電子組件的對應終端。該等第二接點會被配置成用以攜載該命令與位址資訊以外的資訊。 In an exemplary embodiment, the microelectronic component of the second microelectronic component can include a logic function. In one example, the contacts can be first contacts and the conductors can be a first set of conductors. The device can also include a plurality of second contacts coupled to a second set of conductors. The second contacts are configured to connect to corresponding terminals of the microelectronic assembly. The second contacts are configured to carry information other than the command and address information.

於一特殊的實施例中，該第一類型微電子組件中的微電子元件可以為DDRx型。於其中一實施例中，該第二類型微電子組件中的微電子元件可以為LPDDRx型。於一特殊的範例中，該第一類型微電子組件中的微電子元件可以為GDDRx型。於一示範性實施例中，一種如上面所述的系統可以包含被電性連接至該器件的一或更多個其它電子器件。於其中一範例中，該系統可以包含一殼體，該器件以及該等一或更多個其它電子器 件會和該殼體組裝在一起。 In a particular embodiment, the microelectronic components of the first type of microelectronic assembly can be of the DDRx type. In one embodiment, the microelectronic component in the second type of microelectronic component can be of the LPDDRx type. In a particular example, the microelectronic component of the first type of microelectronic component can be of the GDDRx type. In an exemplary embodiment, a system as described above can include one or more other electronic devices that are electrically coupled to the device. In one example, the system can include a housing, the device, and one or more other electronic devices The piece will be assembled with the housing.

根據本發明的另一項觀點，一種系統可以包含：一微電子組件，該微電子組件包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，該組件的該微電子元件有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊；以及一器件，用以連接該微電子組件。該器件可以包含：一支撐結構，其承載被配置成用以攜載該命令與位址資訊的一組導體；以及複數個接點，它們被耦合至該組導體，該等接點會電性連接該微電子組件之該等終端中的對應終端。 In accordance with another aspect of the present invention, a system can include: a microelectronic assembly including a set of terminals and a microelectronic component having a memory storage array having a given number of storage locations, the component The microelectronic component has a plurality of inputs that connect to the terminals to receive command and address information that explicitly designate one of the storage locations; and a device to connect the microelectronic components. The device can include: a support structure carrying a set of conductors configured to carry the command and address information; and a plurality of contacts coupled to the set of conductors, the contacts being electrically Corresponding terminals in the terminals that connect the microelectronic components.

該等接點可以具有根據用於連接第一類型微電子組件的第一預設排列方式被排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等接點中的第一子集(其包含第一數量的接點)與其耦合的命令與位址資訊。該等接點可以具有根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等接點中的第二子集(其包含第二數量的接點)與其耦合的命令與位址資訊，該等第一子集與第二子集包含佔據相同位置的某些接點，該第二數量少於該第一數量。 The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein the microelectronic components are configured to sample via the The first subset of points (which contain the first number of contacts) are coupled with command and address information. The contacts may have address and command information assignments arranged according to a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic components are configured to sample via the a second subset of points (which includes a second number of contacts) with command and address information coupled thereto, the first subset and the second subset including certain contacts occupying the same location, the second The number is less than the first quantity.

於其中一範例中，第一類型微電子組件的命令與位址資訊可以包含同位元資訊，該第一類型微電子組件中的微電子元件會被配置成用以取樣該同位元資訊，而用於連接第二類型微電子組件的該等接點中的第二子集不會被配置成用以取樣該同位元資訊。於一示範性實施例中，該第二類型微電子組件中的微電子元件可以係DDR3型，而該第一類型微電子 組件中的微電子元件可以係DDR4型。 In one example, the command and address information of the first type of microelectronic component may include the same bit information, and the microelectronic component of the first type of microelectronic component is configured to sample the same bit information, and The second subset of the contacts connecting the second type of microelectronic components is not configured to sample the peer information. In an exemplary embodiment, the microelectronic component in the second type of microelectronic component can be of the DDR3 type, and the first type of microelectronics The microelectronic components in the assembly can be of the DDR4 type.

於其中一實施例中，具有DDR4型微電子元件之該第一類型微電子組件中的命令與位址資訊可以包含同位元資訊，而且該第一類型微電子組件中的該DDR4型微電子元件會被配置成用以取樣該同位元資訊。於一特殊的範例中，該第二類型微電子組件中的微電子元件可以係DDRx型，而該第一類型微電子組件中的微電子元件可以係DDR(x+1)型。 In one embodiment, the command and address information in the first type of microelectronic component having the DDR4 type microelectronic component may include the parity information, and the DDR4 type microelectronic component in the first type of microelectronic component It will be configured to sample the same bit information. In a particular example, the microelectronic component of the second type of microelectronic component can be of the DDRx type, and the microelectronic component of the first type of microelectronic component can be of the DDR(x+1) type.

5‧‧‧器件 5‧‧‧Device

10‧‧‧微電子組件 10‧‧‧Microelectronic components

25a‧‧‧終端 25a‧‧‧ Terminal

25b‧‧‧終端 25b‧‧‧ Terminal

30‧‧‧微電子元件 30‧‧‧Microelectronic components

35a‧‧‧元件接點 35a‧‧‧Component contacts

35b‧‧‧元件接點 35b‧‧‧Component contacts

36‧‧‧匯流排 36‧‧‧ busbar

60‧‧‧支撐結構 60‧‧‧Support structure

65‧‧‧第一接點 65‧‧‧First contact

67‧‧‧第二接點 67‧‧‧second junction

70‧‧‧第一導體組 70‧‧‧First Conductor Group

71‧‧‧第二導體組 71‧‧‧Second conductor set

80‧‧‧裝置 80‧‧‧ device

105‧‧‧器件 105‧‧‧Devices

105b‧‧‧器件 105b‧‧‧Device

105c‧‧‧器件 105c‧‧‧Device

110‧‧‧微電子封裝 110‧‧‧Microelectronics package

110c‧‧‧微電子封裝 110c‧‧‧Microelectronics package

110d‧‧‧微電子封裝 110d‧‧‧Microelectronics package

111‧‧‧導電接合單元 111‧‧‧Electrical joint unit

112‧‧‧微電子封裝的第一表面 112‧‧‧ First surface of the microelectronic package

120‧‧‧封裝基板 120‧‧‧Package substrate

121‧‧‧封裝基板的第一表面 121‧‧‧ First surface of the package substrate

122‧‧‧封裝基板的第二表面 122‧‧‧The second surface of the package substrate

124‧‧‧基板接點 124‧‧‧Substrate contacts

125‧‧‧終端 125‧‧‧ Terminal

125a‧‧‧表面鑲嵌終端 125a‧‧‧ surface mosaic terminal

125b‧‧‧表面鑲嵌終端 125b‧‧‧ surface mosaic terminal

127a‧‧‧表面鑲嵌終端 127a‧‧‧ surface mosaic terminal

127b‧‧‧表面鑲嵌終端 127b‧‧‧ surface mosaic terminal

130‧‧‧微電子元件 130‧‧‧Microelectronic components

131a‧‧‧微電子元件 131a‧‧‧Microelectronic components

131b‧‧‧微電子元件 131b‧‧‧Microelectronic components

131c‧‧‧微電子元件 131c‧‧‧Microelectronic components

131d‧‧‧微電子元件 131d‧‧‧Microelectronic components

132a‧‧‧微電子元件 132a‧‧‧Microelectronic components

132b‧‧‧微電子元件 132b‧‧‧Microelectronic components

132c‧‧‧微電子元件 132c‧‧‧Microelectronic components

132d‧‧‧微電子元件 132d‧‧‧Microelectronic components

135‧‧‧位址輸入 135‧‧‧ address input

160‧‧‧電路板 160‧‧‧ boards

160b‧‧‧電路板 160b‧‧‧Board

160c‧‧‧電路板 160c‧‧‧PCB

161‧‧‧電路板的第一表面 161‧‧‧ first surface of the board

162‧‧‧電路板的第二表面 162‧‧‧ second surface of the board

163‧‧‧電路板邊緣 163‧‧‧Circuit edge

164‧‧‧接點 164‧‧‧Contacts

165‧‧‧接點 165‧‧‧Contacts

165a‧‧‧接點 165a‧‧‧Contacts

165b‧‧‧接點 165b‧‧‧Contacts

167a‧‧‧接點 167a‧‧‧Contact

167b‧‧‧接點 167b‧‧‧Contacts

168‧‧‧接點組 168‧‧‧Contact Group

168a‧‧‧邊緣 168a‧‧‧ edge

168b‧‧‧邊緣 168b‧‧‧ edge

170‧‧‧導體組 170‧‧‧Conductor group

171‧‧‧導體組 171‧‧‧Conductor group

180‧‧‧裝置 180‧‧‧ device

180a‧‧‧裝置 180a‧‧‧ device

180b‧‧‧裝置 180b‧‧‧ device

190‧‧‧第二電路板 190‧‧‧second board

193‧‧‧插槽 193‧‧‧ slots

195‧‧‧導體組 195‧‧‧Conductor group

205a‧‧‧器件 205a‧‧‧Device

205b‧‧‧器件 205b‧‧‧Device

210a‧‧‧模組 210a‧‧‧ module

210b‧‧‧模組 210b‧‧‧Module

220a‧‧‧模組卡 220a‧‧‧Module Card

220b‧‧‧模組卡 220b‧‧‧ module card

221‧‧‧模組卡的第一表面 221‧‧‧ first surface of the module card

222‧‧‧模組卡的第二表面 222‧‧‧ second surface of the module card

223‧‧‧邊緣 223‧‧‧ edge

225a‧‧‧終端 225a‧‧‧ Terminal

225b‧‧‧終端 225b‧‧‧ Terminal

226a‧‧‧終端 226a‧‧‧ Terminal

226b‧‧‧終端 226b‧‧‧ Terminal

227a‧‧‧終端 227a‧‧‧ Terminal

227b‧‧‧終端 227b‧‧‧ Terminal

227c‧‧‧終端 227c‧‧‧ Terminal

228‧‧‧槽口 228‧‧‧ notch

230‧‧‧微電子元件 230‧‧‧Microelectronic components

235‧‧‧位址輸入 235‧‧‧ address input

260a‧‧‧電路板 260a‧‧‧PCB

260b‧‧‧電路板 260b‧‧‧ boards

261‧‧‧電路板的第一表面 261‧‧‧ first surface of the board

262‧‧‧電路板的第二表面 262‧‧‧ second surface of the board

265a‧‧‧接點 265a‧‧‧Contacts

265b‧‧‧接點 265b‧‧‧Contacts

266a‧‧‧插槽 266a‧‧ slots

266b‧‧‧連接器 266b‧‧‧Connector

270‧‧‧導體組 270‧‧‧Conductor group

305‧‧‧器件 305‧‧‧Device

305b‧‧‧器件 305b‧‧‧Device

305c‧‧‧器件 305c‧‧‧Device

310‧‧‧第一微電子組件 310‧‧‧First microelectronic components

320‧‧‧封裝基板 320‧‧‧Package substrate

321‧‧‧封裝基板的第一表面 321‧‧‧ The first surface of the package substrate

322‧‧‧封裝基板的第二表面 322‧‧‧The second surface of the package substrate

325‧‧‧終端 325‧‧‧ Terminal

330‧‧‧微電子元件 330‧‧‧Microelectronic components

335‧‧‧位址輸入 335‧‧‧ address input

340‧‧‧第二微電子組件 340‧‧‧Second microelectronic components

340c‧‧‧第二微電子組件 340c‧‧‧Second microelectronic components

341‧‧‧微電子元件 341‧‧‧Microelectronic components

342‧‧‧互連基板 342‧‧‧Interconnect substrate

343‧‧‧基板的表面 343‧‧‧ Surface of the substrate

344‧‧‧第二微電子組件的下表面 344‧‧‧The lower surface of the second microelectronic component

345‧‧‧下終端 345‧‧‧ Terminal

347‧‧‧第二微電子組件的第一表面 347‧‧‧ First surface of the second microelectronic component

348‧‧‧模造區 348‧‧·Molding area

349‧‧‧元件接點 349‧‧‧Component contacts

360‧‧‧電路板 360‧‧‧PCB

361‧‧‧電路板的第一表面 361‧‧‧ first surface of the board

365‧‧‧上終端 365‧‧‧Upper terminal

370‧‧‧導體組 370‧‧‧Conductor group

370b‧‧‧導體組 370b‧‧‧Conductor group

370c‧‧‧導體組 370c‧‧‧Conductor group

375‧‧‧接點 375‧‧‧Contacts

405‧‧‧器件 405‧‧‧Device

405b‧‧‧器件 405b‧‧‧Device

410‧‧‧第一微電子組件 410‧‧‧First microelectronic components

420‧‧‧封裝基板 420‧‧‧Package substrate

421‧‧‧封裝基板的第一表面 421‧‧‧ First surface of the package substrate

422‧‧‧封裝基板的第二表面 422‧‧‧The second surface of the package substrate

425‧‧‧終端 425‧‧‧ Terminal

430‧‧‧微電子元件 430‧‧‧Microelectronic components

435‧‧‧位址輸入 435‧‧‧ address input

440‧‧‧第二微電子組件 440‧‧‧Second microelectronic components

444‧‧‧第二微電子組件的第二表面 444‧‧‧Second surface of the second microelectronic component

445‧‧‧下終端 445‧‧‧Next terminal

446‧‧‧直通矽穿孔 446‧‧‧through through hole piercing

447‧‧‧第二微電子組件的第一表面 447‧‧‧ First surface of the second microelectronic component

460‧‧‧電路板 460‧‧‧ circuit board

461‧‧‧電路板的第一表面 461‧‧‧ first surface of the board

465‧‧‧上終端 465‧‧‧Upper terminal

470‧‧‧導體組 470‧‧‧Conductor group

470b‧‧‧導體組 470b‧‧‧Conductor group

475‧‧‧接點 475‧‧‧Contacts

500‧‧‧系統 500‧‧‧ system

501‧‧‧殼體 501‧‧‧shell

502‧‧‧電路板 502‧‧‧ circuit board

504‧‧‧導體 504‧‧‧Conductor

506‧‧‧模組或器件 506‧‧‧Modules or devices

508‧‧‧電子器件 508‧‧‧Electronic devices

510‧‧‧電子器件 510‧‧‧Electronic devices

511‧‧‧電子器件 511‧‧‧Electronic devices

600‧‧‧系統 600‧‧‧ system

602‧‧‧第二電路板 602‧‧‧second circuit board

604‧‧‧導體 604‧‧‧Conductor

605‧‧‧插槽 605‧‧‧Slot

606‧‧‧器件 606‧‧‧Device

607‧‧‧接點 607‧‧‧Contacts

圖1所示的係根據本發明一實施例的器件的略圖。 1 is a schematic view of a device in accordance with an embodiment of the present invention.

圖2A所示的係根據本發明一實施例的器件的側視圖，其具有一微電子封裝以及一電路板。 2A is a side elevational view of a device in accordance with an embodiment of the present invention having a microelectronic package and a circuit board.

圖2B所示的係根據本發明一實施例的器件的側視圖，其具有一微電子封裝以及一模組卡。 2B is a side elevational view of a device in accordance with an embodiment of the present invention having a microelectronic package and a module card.

圖2C所示的係根據本發明一實施例的器件的側視圖，其具有一第一類型微電子封裝以及一電路板。 2C is a side elevational view of a device in accordance with an embodiment of the present invention having a first type of microelectronic package and a circuit board.

圖2D所示的係根據本發明一實施例的器件的側視圖，其具有一第二類型微電子封裝以及一電路板。 2D is a side elevational view of a device in accordance with an embodiment of the present invention having a second type of microelectronic package and a circuit board.

圖3A所示的係根據本發明一實施例的器件的側視圖，其具有一模組以及一電路板。 3A is a side elevational view of a device in accordance with an embodiment of the present invention having a module and a circuit board.

圖3B所示的係根據在圖3A中看見之本發明實施例的變化例的器件的側視圖，其具有一模組以及一電路板。 Figure 3B is a side elevational view of the device according to a variation of the embodiment of the invention as seen in Figure 3A, having a module and a circuit board.

圖3C所示的係圖3A的模組卡的立體圖，其具有各種可以的終端配置。 3C is a perspective view of the module card of FIG. 3A with various possible terminal configurations.

圖4A所示的係根據本發明一實施例的器件的側視圖，其具有一封裝上封裝結構以及一電路板。 4A is a side elevational view of a device in accordance with an embodiment of the present invention having a package-on-package structure and a circuit board.

圖4B所示的係根據本發明一實施例的器件的側視圖，其具有一封裝上封裝結構。 4B is a side elevational view of a device in accordance with an embodiment of the present invention having a package-on-package structure.

圖4C所示的係根據本發明一實施例的器件的側視圖，其具有一封裝上封裝結構。 4C is a side elevational view of a device in accordance with an embodiment of the present invention having a package-on-package structure.

圖5A所示的係根據本發明一實施例的器件的側視圖，其具有一微電子封裝、一TSV堆疊、以及一電路板。 Figure 5A is a side elevational view of a device in accordance with an embodiment of the present invention having a microelectronic package, a TSV stack, and a circuit board.

圖5B所示的係根據本發明一實施例的器件的側視圖，其具有一微電子封裝以及一TSV堆疊。 Figure 5B is a side elevational view of a device in accordance with an embodiment of the present invention having a microelectronic package and a TSV stack.

圖6所示的係根據本發明一實施例的系統的概略剖視圖。 Figure 6 is a schematic cross-sectional view of a system in accordance with an embodiment of the present invention.

圖7所示的係根據本發明一實施例的系統的概略剖視圖。 Figure 7 is a schematic cross-sectional view of a system in accordance with an embodiment of the present invention.

圖1中圖解的係根據本發明一實施例的器件5。如圖1中所見，器件5被配置成用以連接一微電子組件10。 Illustrated in Figure 1 is a device 5 in accordance with an embodiment of the present invention. As seen in FIG. 1, device 5 is configured to connect a microelectronic assembly 10.

微電子組件10包含一組終端25以及一微電子元件30，該微電子元件30具有一具有給定數量儲存位置的記憶體儲存陣列。該微電子元件30有多個元件接點35，其包含：輸入35a，用以連接該等終端25，以便接收命令以及明確指定該等儲存位置中其中一者的位址資訊；以及其它元件接點35b，用以發送與接收命令和位址資訊以外的資訊(舉例來說，資料資訊)。微電子組件10可以具有各種外形，舉例來說，如下面參考圖2至5所述。 Microelectronic assembly 10 includes a set of terminals 25 and a microelectronic component 30 having a memory storage array having a given number of storage locations. The microelectronic component 30 has a plurality of component contacts 35 including: an input 35a for connecting the terminals 25 for receiving commands and explicitly specifying address information of one of the storage locations; and other components Point 35b is used to send and receive information other than command and address information (for example, data information). The microelectronic assembly 10 can have a variety of configurations, for example, as described below with reference to Figures 2 through 5.

微電子組件10可以包含多個主動式元件(舉例來說，主動式裝置，例如，電晶體)或是其上的其它主動式元件，它們會配合或不配合額外的元件來定義一記憶體儲存陣列。於其中一範例中，該等主動式元件以及由該等主動式元件定義的記憶體儲存陣列會被併入一微電子元件30的一部分之中，或是被併入微電子組件10的一或更多個微電子元件(舉例來說，一或更多個半導體晶片)之中，或者，可被併入該微電子組件的一或更多個微電子封裝之中。 The microelectronic assembly 10 can include a plurality of active components (eg, active devices, such as transistors) or other active components thereon that define a memory storage with or without additional components. Array. In one example, the active components and the memory storage array defined by the active components may be incorporated into a portion of a microelectronic component 30 or incorporated into one or more of the microelectronic components 10. Among a plurality of microelectronic components (for example, one or more semiconductor wafers), or incorporated into one or more microelectronic packages of the microelectronic assembly.

沒有任何限制，於其中一範例中，舉例來說，微電子組件10可能係一微電子封裝或是其一部分，其中，該等終端25曝露在該微電子封裝的一表面處。於另一範例中，該微電子組件可能包含複數個電性連接的微電子封裝；或者，可能包含一結構，其包含電性連接的微電子元件、半導體晶片、或是微電子元件或半導體晶片的一部分、或是微電子封裝的一部分。 Without any limitation, in one example, for example, the microelectronic assembly 10 may be a microelectronic package or a portion thereof, wherein the terminals 25 are exposed at a surface of the microelectronic package. In another example, the microelectronic component may comprise a plurality of electrically connected microelectronic packages; or, possibly, a structure comprising electrically connected microelectronic components, semiconductor wafers, or microelectronic components or semiconductor wafers Part of it, or part of a microelectronic package.

如本文中的用法，「曝露在」一結構的一表面處所指的係該導電元件可用於接觸一在垂直於該表面的方向中從該結構外面朝該表面移動的理論點。因此，曝露在一結構的一表面處的終端或其它導體元件可能會從此表面處突出；可能會齊平於此表面；或者，相對於此表面可能為凹陷並且經由該結構中的孔洞或凹部露出。 As used herein, "exposed to" a surface of a structure means that the conductive element can be used to contact a theoretical point of movement from the outside of the structure toward the surface in a direction perpendicular to the surface. Thus, terminals or other conductor elements exposed at a surface of a structure may protrude from the surface; may be flush with the surface; or may be recessed relative to the surface and exposed through holes or recesses in the structure .

於其中一範例中，該等一或更多個微電子元件30的記憶體儲存陣列包括該微電子組件10的一功能部，其角色可充當該微電子組件10的另一功能部。舉例來說，微電子組件10可能包含一邏輯功能部(舉例來說，處理器)以及一記憶體功能部，而且該記憶體功能部可協助或幫助充當 該邏輯功能部的一功能。然而，於一特殊的範例中，該微電子組件10可能會被配置成以提供記憶體儲存陣列功能為主。於後面的情況中，該微電子組件10中被配置成用以提供記憶體儲存陣列功能的主動式元件(舉例來說，主動式裝置，例如，電晶體)的數量可能大於該微電子組件中被配置成用以提供記憶體儲存陣列功能以外之功能的其它器件中的主動式元件的數量。 In one example, the memory storage array of the one or more microelectronic components 30 includes a functional portion of the microelectronic assembly 10 that functions as another functional portion of the microelectronic assembly 10. For example, the microelectronic component 10 may include a logic function (for example, a processor) and a memory function, and the memory function may assist or help A function of the logic function. However, in a particular example, the microelectronic assembly 10 may be configured to provide memory storage array functionality. In the latter case, the number of active components (eg, active devices, eg, transistors) configured to provide memory storage array functionality in the microelectronic assembly 10 may be greater than in the microelectronic assembly. The number of active components in other devices configured to provide functionality beyond the memory storage array functionality.

於其中一範例中，微電子組件10可能於其中含有繞線，其會利用微電子元件30的對應位址輸入35a直接電性耦合一組終端25，舉例來說，「第一終端」25a。如本文中的用法，每一個「第一終端」25a在該微電子組件10上皆有一訊號指派，包含該等位址輸入35a中的一或更多者。於另一範例中，如下面的進一步說明，微電子組件10可能包含一緩衝元件，例如，其上具有複數個主動式元件的半導體晶片，此半導體晶片會被配置成用以進行下面至少其中一者：再生或者部分或完整解碼在該等終端25處收到的位址或命令資訊中至少其中一者，以便讓該微電子結構傳輸至該等位址輸入。命令資訊可能係控制該微電子組件10裡面的一記憶體儲存陣列或其一部分之操作模式的資訊。 In one example, the microelectronic assembly 10 may have a winding therein that directly couples a set of terminals 25, for example, a "first terminal" 25a, using a corresponding address input 35a of the microelectronic component 30. As used herein, each "first terminal" 25a has a signal assignment on the microelectronic component 10, including one or more of the address inputs 35a. In another example, as further explained below, the microelectronic assembly 10 may include a buffer component, such as a semiconductor wafer having a plurality of active components thereon, the semiconductor wafer being configured to perform at least one of the following Retrieving or partially or completely decoding at least one of the address or command information received at the terminals 25 for transmission of the microelectronic structure to the address inputs. The command information may be information that controls the mode of operation of a memory storage array or a portion thereof within the microelectronic assembly 10.

微電子組件10會被配置成用以提供在該等第一終端25a處收到的位址資訊給該等一或更多個微電子元件30的位址輸入35a。如本文中的用法，在位址資訊或是命令位址匯流排資訊或訊號以及一微電子元件或其一部分的位址輸入的背景中，終端上的位址資訊「被提供至位址輸入」的意義為該等終端上的位址資訊會透過與其相連的電性連接線或是經由一緩衝元件被傳輸至該等位址輸入，該緩衝元件可實施下面至少其中一者： 再生、部分解碼或解碼在該等終端處收到的位址資訊。 The microelectronic assembly 10 is configured to provide address information received at the first terminals 25a to the address inputs 35a of the one or more microelectronic components 30. As used herein, in the context of address information or command address bus information or signals and address input of a microelectronic component or a portion thereof, the address information on the terminal is "provided to address input". The meaning is that the address information on the terminals is transmitted to the address input through the electrical connection line connected thereto or via a buffer component, and the buffer component can implement at least one of the following: Retrieving, partially decoding, or decoding address information received at the terminals.

於此微電子元件30的其中一種類型中，該等位址輸入35a中的某些接點中的每一個接點可能會被配置成用以接收被供應至該微電子元件的位址資訊中的特殊位址資訊。於一特殊的實施例中，此等接點中的每一者可能係一被配置成用以接收從微電子元件30外面被供應至該微電子元件的位址資訊的位址輸入35a，也就是，經由微電子封裝10的繞線(例如，焊線)以及經由該等第一終端25a。該等微電子元件30的接點可能還會被配置成用以接收來自該微電子元件外面的其它資訊或訊號。 In one of the types of microelectronic components 30, each of the contacts in the address inputs 35a may be configured to receive address information that is supplied to the microelectronic component. Special address information. In a particular embodiment, each of the contacts may be an address input 35a configured to receive address information supplied from outside the microelectronic component 30 to the microelectronic component. That is, windings (eg, wire bonds) through the microelectronic package 10 and via the first terminals 25a. The contacts of the microelectronic elements 30 may also be configured to receive other information or signals from outside the microelectronic elements.

舉例來說，當微電子元件30包含或者係一DRAM半導體晶片時，該等第一終端25a會被配置成用以攜載傳輸至該微電子組件10的位址資訊，其可讓該微電子組件裡面的電路系統使用，舉例來說，列位址解碼器和行位址解碼器以及組選擇電路系統(若存在的話)，用以從該微電子組件中的一微電子元件裡面的一記憶體儲存陣列的所有可用之可定址的記憶體位置中決定一可定址的記憶體位置。於一特殊的實施例中，該等第一終端25a會被配置成用以攜載讓該微電子組件10裡面的此電路系統用來決定此記憶體儲存陣列裡面的一可定址的記憶體位置的所有位址資訊。該等第一終端25a中的每一者會被配置成用以攜載足以明確指定該微電子組件10之記憶體儲存陣列裡面的一位置的位址資訊。 For example, when the microelectronic component 30 includes or is a DRAM semiconductor wafer, the first terminals 25a are configured to carry address information transmitted to the microelectronic component 10, which allows the microelectronics The circuitry within the component uses, for example, a column address decoder and a row address decoder and a group selection circuitry (if present) for a memory from a microelectronic component in the microelectronic component A addressable memory location is determined among all available addressable memory locations of the bulk storage array. In a particular embodiment, the first terminals 25a are configured to carry the circuitry within the microelectronic assembly 10 for determining an addressable memory location within the memory storage array. All address information. Each of the first terminals 25a is configured to carry address information sufficient to explicitly designate a location within the memory storage array of the microelectronic assembly 10.

一般來說，當該微電子組件10中的微電子元件30係或者包含一DRAM晶片時，於其中一實施例中，該位址資訊可能包含從該微電子結構外部的一器件(舉例來說，器件5)處傳輸至該微電子組件的所有位址資訊，其被用於決定該微電子組件裡面的一隨機存取可定址的記憶體位置， 以便對其進行讀取存取或者對其進行讀取或寫入存取。 In general, when the microelectronic component 30 in the microelectronic component 10 is or includes a DRAM die, in one embodiment, the address information may include a device external to the microelectronic structure (for example, All of the address information transmitted to the microelectronic component at device 5) is used to determine a random access addressable memory location within the microelectronic component, In order to read access or read or write access to it.

於一特殊的實施例中，該等第一終端25a會被配置成用以攜載控制該等微電子元件30中一或更多者之操作模式的資訊。更明確地說，該等第一終端25a會被配置成用以攜載傳輸至該微電子組件10的一特殊命令訊號組及/或時脈訊號組之全部。於其中一實施例中，該等第一終端25a會被配置成用以攜載從一外部器件(舉例來說，器件5)處傳輸至該組件10的命令訊號、位址訊號、組位址訊號、以及時脈訊號之全部，其中，該等命令訊號包含列位址選通、行位址選通、以及寫入致能。 In a particular embodiment, the first terminals 25a are configured to carry information that controls the mode of operation of one or more of the microelectronic components 30. More specifically, the first terminals 25a are configured to carry all of a special command signal group and/or a clock signal group transmitted to the microelectronic assembly 10. In one embodiment, the first terminals 25a are configured to carry command signals, address signals, group addresses transmitted from an external device (for example, device 5) to the component 10. All of the signal and the clock signal, wherein the command signals include a column address strobe, a row address strobe, and a write enable.

於該等微電子元件30中的一或更多者被配置成用以提供動態記憶體儲存陣列功能的實施例中，例如，由動態隨機存取記憶體(DRAM)半導體晶片或是多個DRAM晶片組成的組件所提供，該等命令訊號可能係寫入致能訊號、列位址選通訊號、以及行位址選通訊號。該等第一終端25a可能攜載或不攜載其它訊號，例如，ODT(晶粒上終止，On Die Termination)、晶片選擇、時脈致能。該等時脈訊號可能係被該等微電子元件中一或更多者用來取樣該等位址訊號的時脈。 In embodiments in which one or more of the microelectronic components 30 are configured to provide dynamic memory storage array functionality, for example, by a dynamic random access memory (DRAM) semiconductor wafer or a plurality of DRAMs Provided by the components of the chip, the command signals may be written into the enable signal, the column address selection communication number, and the row address selection communication number. The first terminals 25a may or may not carry other signals, such as ODT (On Die Termination), wafer selection, and clock enable. The clock signals may be used by one or more of the microelectronic components to sample the clocks of the address signals.

除了該等第一終端25a之外，終端25(或者本文中所述之任何其它實施例中的終端)可能還包含第二終端25b，它們被配置成用以攜載(發送及/或接收)命令和位址資訊以外的資訊，例如，資料訊號。該等第二終端25b中的至少一部分會被配置成用以攜載該等第一終端25a所攜載之位址訊號以外的訊號。於特殊的範例中，該等第二終端25b可能攜載下面之中的一或更多者：資料、資料選通訊號、或者其它訊號或參考電位(例如，晶片選擇、重置、電源供應器電壓(舉例來說，Vdd、Vddq、以及接地(舉例來 說，Vss與Vssq)))。該等第二終端25b可以電性連接其它元件接點35b，用以發送與接收命令和位址資訊以外的資訊。 In addition to the first terminals 25a, the terminal 25 (or the terminal in any other embodiment described herein) may also include a second terminal 25b configured to carry (transmit and/or receive) Information other than commands and address information, such as data signals. At least a portion of the second terminals 25b are configured to carry signals other than the address signals carried by the first terminals 25a. In a particular example, the second terminal 25b may carry one or more of the following: data, data selection communication number, or other signal or reference potential (eg, wafer selection, reset, power supply) Voltage (for example, Vdd, Vddq, and ground (for example Said, Vss and Vssq))). The second terminals 25b can be electrically connected to other component contacts 35b for transmitting and receiving information other than commands and address information.

於其中一範例中，該等第二終端25b可能包含用於攜載下面訊號的終端：送往及/或來自該等微電子元件30的單向或雙向資料訊號、資料選通訊號、資料遮罩訊號、以及用於啟動或關閉終端電阻器之平行終止的ODT或「晶粒上終止」訊號。於特殊的範例中，該等第二終端25b可能攜載諸如下面的訊號：重置；以及參考電位，例如，電源供應器電壓(舉例來說，Vdd、Vddq、或是接地(舉例來說，Vss與Vssq))。 In one example, the second terminals 25b may include terminals for carrying signals: one-way or two-way data signals, data selection numbers, and data masks sent to and/or from the microelectronic components 30. The cover signal, and the ODT or "die termination" signal used to activate or deactivate the parallel termination of the terminating resistor. In a particular example, the second terminals 25b may carry signals such as: reset; and reference potentials, such as power supply voltages (eg, Vdd, Vddq, or ground (for example, Vss and Vssq)).

於此微電子元件30的其中一特殊範例中，出現在該等元件接點35a處的命令和位址資訊會以個別微電子元件所使用之時脈的訊號緣為基準(也就是，該時脈在第一與第二不同的電壓狀態之間進行轉變時)被取樣。也就是，每一個命令和位址訊號會在該時脈的一較低電壓狀態和一較高電壓狀態之間的上升轉變時被取樣，或者，在該時脈的一較高電壓狀態和一較低電壓狀態之間的下降轉變時被取樣。因此，該等複數個命令和位址訊號可能全部會在該時脈的上升轉變時被取樣；或者，此等命令和位址訊號可能全部會在該時脈的下降轉變時被取樣；或者，於另一範例中，該等元件接點35a中其中一者處的命令或位址訊號會在該時脈的上升轉變時被取樣，而另一個外部接點處的命令或位址訊號會在該時脈的下降轉變時被取樣。 In one particular example of the microelectronic component 30, the command and address information present at the component contacts 35a is referenced to the signal edge of the clock used by the individual microelectronic component (ie, at that time) The pulse is sampled as it transitions between the first and second different voltage states. That is, each command and address signal is sampled at a rising transition between a lower voltage state and a higher voltage state of the clock, or a higher voltage state of the clock and a The falling transition between the lower voltage states is sampled. Therefore, the plurality of command and address signals may all be sampled at the rising transition of the clock; or, the command and address signals may all be sampled during the falling transition of the clock; or, In another example, the command or address signal at one of the component contacts 35a will be sampled during the rising transition of the clock, and the command or address signal at the other external contact will be The time-lapse of the clock is sampled.

於另一種類型的微電子元件30中，其可能會被配置成以提供記憶體儲存陣列功能為主，其上的該等命令或位址位址接點35a中的一或更多者會以多工的方式被使用。於此範例中，個別微電子元件30的一特殊 元件接點35a可能會接收從外面被供應至該微電子元件的二或更多個不同訊號。因此，一第一命令或位址位址訊號會在該時脈於該等第一與第二不同的電壓狀態之間進行第一轉變時(舉例來說，上升轉變)在該特殊接點35a處被取樣，而一該第一命令或位址位址訊號以外的訊號則會在該時脈於該等第一與第二不同的電壓狀態之間進行和該第一轉變反向的第二轉變時(舉例來說，下降轉變)在該特殊接點處被取樣。 In another type of microelectronic component 30, which may be configured to provide memory storage array functionality, one or more of the commands or address address contacts 35a thereon may The multiplexed way is used. In this example, a special of the individual microelectronic components 30 Component contact 35a may receive two or more different signals that are supplied to the microelectronic component from the outside. Therefore, a first command or address address signal will be at the special contact 35a when the clock undergoes a first transition between the first and second different voltage states (for example, a rising transition). Sampling, and a signal other than the first command or the address bit signal is in the second phase opposite to the first transition between the first and second different voltage states At the time of the transition (for example, a falling transition), it is sampled at the special joint.

依照此種多工方式，兩個不同的訊號會在個別微電子元件30的相同元件接點35a上於該時脈的相同週期裡面被接收。於一特殊的情況中，依此方式進行多工能夠讓一第一位址命令或位址訊號以及一不同的訊號在個別微電子元件30的相同元件接點35a上於相同時脈週期中被接收。於又一範例中，依此方式進行多工能夠讓一第一命令或位址訊號以及一第二不同的命令或位址訊號在個別微電子元件30的相同元件接點35a上於相同時脈週期中被接收。 In accordance with this multiplex mode, two different signals are received on the same component contact 35a of the individual microelectronic component 30 during the same cycle of the clock. In a particular case, multiplexing in this manner enables a first address command or address signal and a different signal to be on the same component contact 35a of the individual microelectronic component 30 in the same clock cycle. receive. In yet another example, multiplexing in this manner enables a first command or address signal and a second different command or address signal to be on the same component contact 35a of the individual microelectronic component 30 at the same clock. Received during the cycle.

於其中一範例中，操作參數可能和時序有關，例如，列位址選通訊號在已致能狀態中被微電子組件10的電路系統偵測到之後的等待時間(latency)(下文中稱為「RAS等待時間」)的時脈週期的數量；或者，可能和行位址選通訊號在已致能狀態中被微電子組件的電路系統偵測到之後的等待時間的時脈週期的數量有關；或者，可能和微電子組件的容量有關，舉例來說，十億位元(1Gb)、二十億位元(2Gb)、…等；或者，可能和微電子組件的組織有關，例如，「單面(single-rank)」、「2面(2-rank)」、「4面(4-rank)」、或是其它結構、…等；或者，其它操作參數；或者，前面操作參數或其它操作參數之組合。於其中一範例中，非揮發性記憶體可能儲存前述參數中 單一參數的資訊，或者，可能儲存該等操作參數之任何組合的資訊，沒有任何限制。於一特殊的範例中，非揮發性記憶體可能含有一由微電子組件10之記憶體儲存陣列裡面的已知不良記憶體位置組成的表格，該等位置應該在讀取存取或寫入存取該記憶體儲存陣列期間被避開。 In one example, the operational parameters may be related to timing, for example, the latency after the column address selection communication number is detected by the circuitry of the microelectronic assembly 10 in the enabled state (hereinafter referred to as The number of clock cycles of the "RAS wait time"; or, possibly, the number of clock cycles of the wait time after the row address selection communication number is detected in the enabled state by the circuitry of the microelectronic component Or, may be related to the capacity of microelectronic components, for example, one billion bits (1Gb), two billion bits (2Gb), etc.; or, may be related to the organization of microelectronic components, for example, " Single-rank, 2-rank, 4-rank, or other structures, etc.; or other operational parameters; or, previous operational parameters or other A combination of operating parameters. In one example, non-volatile memory may store the aforementioned parameters. There is no restriction on the information of a single parameter, or the information that may store any combination of these operational parameters. In a particular example, the non-volatile memory may contain a table of known bad memory locations in the memory storage array of the microelectronic assembly 10, which locations should be read or written. It is avoided during the memory storage array.

器件5包含一支撐結構60(舉例來說，一電路板)，其承載一第一導體組70，該等導體70被配置成用以攜載命令與位址資訊。支撐結構60可能有許多不同的形式，就此而言，例如，電路板160(圖2A)、模組卡160b(圖2B)、互連基板342(圖4B)、模造區348(圖4C)、微電子元件440(圖5B)、或是疊置在一微電子元件上面的介電層(圖中並未顯示)。 Device 5 includes a support structure 60 (e.g., a circuit board) that carries a first set of conductors 70 that are configured to carry command and address information. The support structure 60 may have many different forms, for example, a circuit board 160 (FIG. 2A), a module card 160b (FIG. 2B), an interconnect substrate 342 (FIG. 4B), a molding region 348 (FIG. 4C), Microelectronic component 440 (Fig. 5B), or a dielectric layer (not shown) overlying a microelectronic component.

器件5還包含複數個第一接點65，它們被耦合至導體組70並且被配置成用於連接微電子組件10之該等終端25中的對應終端。該第一導體組70可能包含具有複數條訊號線的至少一匯流排，該等訊號線被配置成用以攜載傳輸至該等第一接點65的所有位址資訊。該等第一接點65會電性連接該第一導體組70的該至少一匯流排。 The device 5 also includes a plurality of first contacts 65 that are coupled to the conductor set 70 and configured to connect corresponding terminals in the terminals 25 of the microelectronic assembly 10. The first conductor set 70 may include at least one bus bar having a plurality of signal lines configured to carry all of the address information transmitted to the first contacts 65. The first contacts 65 are electrically connected to the at least one bus bar of the first conductor set 70.

器件5的該等接點65和微電子組件10的該等終端25之間的連接會採取各種形式，舉例來說，如下面參考圖2至5所述。該等接點65具有由位址和命令資訊指派所組成的複數個預設排列方式，俾使得該等接點會連接一具有複數種類型(舉例來說，DDRx、GDDRx、LPDDRx、…等)之一或更多個微電子元件30的微電子組件10的終端25。 The connections between the contacts 65 of the device 5 and the terminals 25 of the microelectronic assembly 10 may take various forms, for example, as described below with reference to Figures 2 through 5. The contacts 65 have a plurality of preset arrangements consisting of address and command information assignments, such that the contacts are connected to a plurality of types (for example, DDRx, GDDRx, LPDDRx, ..., etc.) Terminal 25 of microelectronic assembly 10 of one or more microelectronic elements 30.

該等接點65會根據用於連接第一類型微電子組件10的第一預設排列方式被排列，其中，該等一或更多個微電子元件30會被配置成以第一取樣率(舉例來說，DDR3或DDR4)來取樣經由該等接點中的第一子集 (其包含第一數量的接點，其可能為該等接點中的一部分或全部)與其耦合的命令與位址資訊。相同的接點65會根據用於連接第二類型微電子組件10的第二預設排列方式被排列，其中，該等一或更多個微電子元件30會被配置成以大於該第一取樣率的第二取樣率(舉例來說，LPDDR3)來取樣經由該等接點中的第二子集(其包含少於第一數量的第二數量接點)與其耦合的命令與位址資訊。該等接點65中的第一子集和第二子集包含佔據相同的位置的某些接點。根據用於連接兩種不同類型微電子組件10的兩種不同預設排列方式被排列的該等接點65在本文中亦稱為「共支撐接點」。 The contacts 65 are arranged according to a first predetermined arrangement for connecting the first type of microelectronic assemblies 10, wherein the one or more microelectronic elements 30 are configured to have a first sampling rate ( For example, DDR3 or DDR4) to sample through the first subset of the contacts (It contains a first number of contacts, which may be some or all of the contacts) command and address information coupled thereto. The same contacts 65 are arranged according to a second predetermined arrangement for connecting the second type of microelectronic assemblies 10, wherein the one or more microelectronic elements 30 are configured to be larger than the first sampling A second sampling rate of the rate (for example, LPDDR3) is used to sample command and address information coupled thereto via a second subset of the contacts (which includes less than the first number of second number of contacts). The first subset and the second subset of the contacts 65 contain certain contacts occupying the same location. The contacts 65 that are arranged according to two different preset arrangements for connecting the two different types of microelectronic assemblies 10 are also referred to herein as "co-supporting contacts."

於一特殊的實施例中，該第二取樣率可能係第一取樣率的整數倍數。舉例來說，器件5可能會被配置成使得當其中具有DDR3或DDR4記憶體的第一類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以第一取樣率(例如，每個時脈週期一次，舉例來說，在該時脈週期的上升訊號緣)來取樣經由第一數量的接點65與其耦合的命令與位址資訊。於此相同的範例中，器件5可能會被配置成使得當其中具有LPDDR3記憶體的第二類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以第二取樣率(例如，每個時脈週期兩次，舉例來說，在該時脈週期的上升訊號緣和下降訊號緣各一次)來取樣經由第二數量的接點65與其耦合的命令與位址資訊。所以，於此範例中，第二取樣率係第一取樣率的整數倍數(2倍)。 In a particular embodiment, the second sampling rate may be an integer multiple of the first sampling rate. For example, device 5 may be configured such that when a first type of microelectronic component 10 having DDR3 or DDR4 memory therein is attached to the device, microelectronic component 30 in the microelectronic component will be configured to The command and address information coupled thereto via the first number of contacts 65 is sampled at a first sampling rate (e.g., once per clock cycle, for example, at the rising edge of the clock cycle). In this same example, device 5 may be configured such that when a second type of microelectronic component 10 having LPDDR3 memory therein is attached to the device, microelectronic component 30 in the microelectronic component is configured Sampling is coupled to the second number of contacts 65 by a second sampling rate (e.g., two clock cycles per cycle, for example, one time each of the rising and falling signal edges of the clock cycle) Command and address information. Therefore, in this example, the second sampling rate is an integer multiple (2 times) of the first sampling rate.

於第二取樣率係第一取樣率之整數倍數的另一實施例中，器件5可能會被配置成使得當其中具有DDR3或DDR4記憶體的第一類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成 以每個時脈週期一次的第一取樣率來取樣經由第一數量的接點65與其耦合的命令與位址資訊。於此相同的範例中，器件5可能會被配置成使得當其中具有不同類型記憶體的第二類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以每個時脈週期四次(舉例來說，在該時脈週期的每隔四分之一週期處各一次)的第二取樣率來取樣經由第二數量的接點65與其耦合的命令與位址資訊。所以，於此範例中，第二取樣率同樣係第一取樣率的整數倍數(4倍)。 In another embodiment where the second sampling rate is an integer multiple of the first sampling rate, device 5 may be configured such that when a first type of microelectronic assembly 10 having DDR3 or DDR4 memory therein is attached to the device The microelectronic component 30 in the microelectronic assembly is configured to The command and address information coupled thereto via the first number of contacts 65 is sampled at a first sampling rate once per clock cycle. In this same example, device 5 may be configured such that when a second type of microelectronic component 10 having a different type of memory therein is attached to the device, the microelectronic component 30 in the microelectronic component will be Sampling is coupled to be coupled via a second number of contacts 65 at a second sampling rate of four times per clock cycle (for example, once every quarter cycle of the clock cycle) Command and address information. Therefore, in this example, the second sampling rate is also an integer multiple (4 times) of the first sampling rate.

於又一實施例中，第二取樣率可能係第一取樣率的非整數倍數。舉例來說，器件5可能會被配置成使得當其中具有記憶體的第一類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以每個時脈週期四次(舉例來說，在該時脈週期的每隔四分之一週期處各一次)的第一取樣率來取樣經由第一數量的接點65與其耦合的命令與位址資訊。於此相同的範例中，器件5可能會被配置成使得當其中具有記憶體的第二類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以每個時脈週期六次(舉例來說，在該時脈週期的每隔六分之一週期處各一次)的第二取樣率來取樣經由第二數量的接點65與其耦合的命令與位址資訊。所以，於此範例中，第二取樣率係第一取樣率的非整數倍數(1.5倍)。 In yet another embodiment, the second sampling rate may be a non-integer multiple of the first sampling rate. For example, device 5 may be configured such that when a first type of microelectronic assembly 10 having a memory therein is attached to the device, microelectronic elements 30 in the microelectronic assembly will be configured to each The first sampling rate of the clock cycle four times (for example, once every quarter cycle of the clock cycle) to sample command and address information coupled thereto via the first number of contacts 65 . In this same example, device 5 may be configured such that when a second type of microelectronic assembly 10 having memory therein is attached to the device, microelectronic element 30 in the microelectronic assembly will be configured to The command and the coupling with the second number of contacts 65 are sampled at a second sampling rate of six times per clock cycle (for example, once every one-sixth cycle of the clock cycle). Address information. Therefore, in this example, the second sampling rate is a non-integer multiple of the first sampling rate (1.5 times).

於第二取樣率係第一取樣率之非整數倍數的另一實施例中，當該等微電子元件30所進行之命令與位址資訊的取樣僅在某些時脈週期期間實施但卻不在其它時脈週期期間實施時，該等第一取樣率和第二取樣率之間的非整數關係便會出現。舉例來說，器件5可能會被配置成使得 當其中具有DDR3或DDR4記憶體的第一類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以每隔一個時脈週期一次的第一取樣率來取樣經由第一數量的接點65與其耦合的命令與位址資訊。於此相同的範例中，器件5可能會被配置成使得當其中具有另一類型記憶體的第二類型微電子組件10被附接至該器件時，該微電子組件中的微電子元件30會被配置成以每隔兩個時脈週期兩次(舉例來說，每隔兩個時脈週期的上升訊號緣和下降訊號緣各一次)的第二取樣率來取樣經由第二數量的接點65與其耦合的命令與位址資訊。所以，於此範例中，第二取樣率係第一取樣率的非整數倍數(1.5倍)。 In another embodiment where the second sampling rate is a non-integer multiple of the first sampling rate, the sampling of the command and address information performed by the microelectronic components 30 is performed only during certain clock cycles but not A non-integer relationship between the first sampling rate and the second sampling rate occurs when implemented during other clock cycles. For example, device 5 may be configured such that When a first type of microelectronic assembly 10 having DDR3 or DDR4 memory therein is attached to the device, the microelectronic component 30 in the microelectronic assembly is configured to be first sampled once every other clock cycle Rate to sample command and address information coupled thereto via a first number of contacts 65. In this same example, device 5 may be configured such that when a second type of microelectronic component 10 having another type of memory therein is attached to the device, microelectronic component 30 in the microelectronic component will Measured to sample via a second number of contacts at a second sampling rate twice every two clock cycles (for example, every two rising and falling signal edges of every two clock cycles) 65 Command and address information coupled to it. Therefore, in this example, the second sampling rate is a non-integer multiple of the first sampling rate (1.5 times).

除了上面所述的特定範例之外，於該等微電子元件30所進行之命令與位址資訊的取樣在每一個時脈週期期間被實施的範例中，以及於該等微電子元件所進行之命令與位址資訊的取樣僅在某些時脈週期期間實施但卻不在其它時脈週期期間實施的範例中，本發明還涵蓋該第二取樣率和該第一取樣率之間的許多其它整數倍數及非整數倍數關係。 In addition to the specific examples described above, the sampling of the command and address information performed by the microelectronic components 30 is performed during each clock cycle, and by the microelectronic components. The sampling of the command and address information is only performed during certain clock cycles but is not implemented during other clock cycles, and the invention also covers many other integers between the second sampling rate and the first sampling rate. Multiple and non-integer multiples.

於其中一範例中，器件5之接點65的相同預設排列會被用來連接包含根據工業標準DDR3或DDR4規格來操作之微電子元件的第一類型微電子組件10，或是，用來連接包含相容於工業標準LPDDR3規格之微電子元件的第二類型微電子結構。 In one example, the same predetermined arrangement of contacts 65 of device 5 can be used to connect a first type of microelectronic assembly 10 comprising microelectronic components that operate according to industry standard DDR3 or DDR4 specifications, or A second type of microelectronic structure comprising microelectronic components compatible with the industry standard LPDDR3 specification is connected.

於本文中所示的範例中，在第二類型微電子組件10中(其利用少於第一類型的接點65來取樣命令與位址資訊)，某些該等終端25可能係不需要用於傳輸位址資訊給微電子組件10中一或更多個記憶體儲存陣列之位址輸入35a的無連接終端。 In the example shown herein, in the second type of microelectronic assembly 10 (which utilizes fewer than the first type of contacts 65 to sample command and address information), some of the terminals 25 may not be required for The address information is transmitted to the connectionless terminal of the address input 35a of one or more memory storage arrays in the microelectronic assembly 10.

如本文中的用法，一微電子組件的「無連接終端」的意義為沒有在任何電性路徑(舉例來說，用於傳導資訊給微電子組件10裡面之任何微電子元件30(舉例來說，半導體晶片)的路徑)中被連接的終端，不論在此無連接終端上是否存在任何資訊。因此，即使資訊可能出現在一無連接終端上，例如，可能從被連接至該無連接終端的器件5處被耦合至此，出現在該無連接終端上的資訊仍不會在被提供至微電子組件10裡面之任何微電子元件30的任何路徑中。 As used herein, the term "connectionless termination" of a microelectronic component is not in any electrical path (for example, any microelectronic component 30 used to conduct information into the microelectronic assembly 10 (for example, , the terminal connected in the path of the semiconductor wafer), whether or not there is any information on the connectionless terminal. Thus, even if information may appear on a connectionless terminal, for example, possibly coupled to the device 5 connected to the connectionless terminal, information appearing on the connectionless terminal will not be provided to the microelectronics. In any path of any of the microelectronic components 30 within the assembly 10.

於本文中的任何實施例中，除了該等第一接點65之外，器件5可能還包含複數個第二接點67，它們被耦合至第二導體組71並且被配置成用於連接微電子組件10之該等第二終端25b中的對應終端。該等第二接點67會被配置成用於連接微電子組件10的對應第二終端25b，該等第二接點被配置成用以攜載命令與位址資訊以外的資訊，例如，資料訊號。該第二導體組71可能具有至少一第二匯流排，其會電性連接該等第二接點67中的至少某些接點。此第二匯流排可能具有複數條訊號線，它們會被配置成用以攜載位址與命令資訊以外的資訊。 In any of the embodiments herein, in addition to the first contacts 65, the device 5 may also include a plurality of second contacts 67 that are coupled to the second conductor set 71 and configured to connect to the micro Corresponding terminals in the second terminals 25b of the electronic component 10. The second contacts 67 are configured to connect to the corresponding second terminals 25b of the microelectronic assembly 10, the second contacts being configured to carry information other than command and address information, for example, data. Signal. The second conductor set 71 may have at least one second bus bar electrically connected to at least some of the second contacts 67. This second bus may have a plurality of signal lines that are configured to carry information other than the address and command information.

器件5可能還包含一被耦合至該導體組的裝置80，該裝置可操作用以將該命令與位址資訊驅動至該等接點。於其中一範例中，該裝置80可能係一被電性連接至導體組70的驅動元件。舉例來說，裝置80可能係一微處理器或是一直接記憶體存取控制器(DMA(Direct Memory Access)控制器)。於一特殊的實施例中，裝置80可能係一緩衝元件；或是一協定轉換器，其會被配置成用以將能夠被器件5使用之具有第一協定的位址資訊轉換成能夠被微電子組件10中特殊類型微電子元件30使用的第二協定。裝 置80會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過位址和命令資訊指派所組成的第一排列方式來連接器件5和第一類型微電子組件10以及透過位址和命令資訊指派所組成的第二排列方式來連接器件5和第二類型微電子組件。 Device 5 may also include a device 80 coupled to the conductor set, the device being operative to drive the command and address information to the contacts. In one example, the device 80 may be a drive element that is electrically connected to the conductor set 70. For example, device 80 may be a microprocessor or a direct memory access controller (DMA). In a particular embodiment, device 80 may be a buffer component; or a protocol converter configured to convert address information having a first agreement that can be used by device 5 to be capable of being micro A second agreement for the use of special types of microelectronic components 30 in electronic component 10. Loading The set 80 is configured to operate in each of the first mode and the second mode to connect the device 5 and the first type of microelectronics by a first arrangement consisting of an address and a command information assignment, respectively. The component 10 and the second arrangement formed by the address and command information assignments connect the device 5 and the second type of microelectronic assembly.

於一特殊的範例中，裝置80可能係至少一中央處理單元(CPU)，該CPU被配置成用以控制該系統中複數個器件的操作，其包含向微電子組件10進行的讀取操作以及寫入至該微電子組件的寫入操作。器件5可能包含一個以上的裝置80，舉例來說，其包含一直接記憶體存取控制器以及一CPU。於其中一實施例中，器件5可能進一步包含一電源供應器，其被配置成用以供應讓該器件和該微電子組件10使用的電力。 In a particular example, device 80 may be at least a central processing unit (CPU) configured to control the operation of a plurality of devices in the system, including read operations to microelectronic assembly 10 and Write operation to the microelectronic component. Device 5 may include more than one device 80, for example, including a direct memory access controller and a CPU. In one embodiment, device 5 may further include a power supply configured to supply power for use by the device and the microelectronic assembly 10.

圖1中雖然僅顯示單一個微電子組件10電性連接器件5；不過，於其它實施例中，複數個微電子組件會電性連接該器件。 Although only a single microelectronic assembly 10 is electrically connected to the device 5 in FIG. 1, in other embodiments, a plurality of microelectronic components are electrically connected to the device.

圖2A所示的係根據圖1中所示之本發明一特殊範例的器件105。如圖2A中所見，器件105包含一電路板160，而且接點165曝露在該電路板的第一表面161處。電路板160(以及本文中所述其它實施例中的電路板)可能為各種類型，就此而言，例如，雙排記憶體模組(Dual-Inline Memory Module，DIMM)模組中所使用的印刷電路板、要連接一系統中其它器件的電路線路板(circuit board)或電路板、或是主機線路板(motherboard)。 Figure 2A shows a device 105 according to a particular example of the invention shown in Figure 1. As seen in Figure 2A, device 105 includes a circuit board 160 and contacts 165 are exposed at first surface 161 of the circuit board. The circuit board 160 (and the circuit boards in other embodiments described herein) may be of various types, for example, for printing in a dual-in-line memory module (DIMM) module. A circuit board, a circuit board or circuit board to which other devices in a system are to be connected, or a mother board.

接合至電路板160的微電子組件具有微電子封裝110的形式。微電子封裝110中有一或更多個微電子元件130，它們具有一面向一封裝基板120之第一表面121的表面。微電子元件130具有多個位址輸入135，它們被電性連接至曝露在基板120中和該第一表面121反向之第二表面122 處的終端125。第二表面122係微電子封裝110的一曝露表面。該等終端125可能係表面鑲嵌終端(舉例來說，BGA、LGA、PGA、…等類型)。 The microelectronic assembly bonded to the circuit board 160 is in the form of a microelectronic package 110. One or more microelectronic components 130 in the microelectronic package 110 have a surface that faces a first surface 121 of a package substrate 120. The microelectronic component 130 has a plurality of address inputs 135 that are electrically coupled to a second surface 122 that is exposed in the substrate 120 and that is opposite the first surface 121. Terminal 125 at the location. The second surface 122 is an exposed surface of the microelectronic package 110. The terminals 125 may be surface mount terminals (for example, BGA, LGA, PGA, ..., etc.).

圖2A中雖然僅顯示單一個微電子封裝110電性連接器件105；不過，於其它實施例中，複數個微電子封裝會電性連接該器件。於此等實施例中，所有該等微電子封裝110會被附接至電路板160的第一表面161；所有該等微電子封裝會被附接至該電路板的第二表面162；或者，一或更多個微電子封裝會被附接至該電路板的第一表面且一或更多個微電子封裝會被附接至該第二表面。 Although only a single microelectronic package 110 is electrically connected to the device 105 in FIG. 2A; however, in other embodiments, a plurality of microelectronic packages may be electrically connected to the device. In such embodiments, all of the microelectronic packages 110 will be attached to the first surface 161 of the circuit board 160; all of the microelectronic packages will be attached to the second surface 162 of the circuit board; or, One or more microelectronic packages may be attached to the first surface of the circuit board and one or more microelectronic packages may be attached to the second surface.

微電子封裝110可能具有複數個位址輸入135，用以接收明確指定該記憶體儲存陣列裡面之位置的位址資訊。因此，該等位址輸入135可能係曝露在的如上面所述的一微電子元件130的一表面處的接點。微電子封裝110會被配置成用以將在該微電子結構的特殊終端125處收到的位址資訊傳輸給該等位址輸入135。舉例來說，微電子封裝110可以將在該結構的特殊終端125處收到的訊號耦合至對應的特殊位址輸入135。 Microelectronic package 110 may have a plurality of address inputs 135 for receiving address information that explicitly specifies the location within the memory storage array. Thus, the address inputs 135 may be exposed at a junction of a surface of a microelectronic component 130 as described above. The microelectronic package 110 is configured to transmit address information received at the special terminal 125 of the microelectronic structure to the address inputs 135. For example, microelectronic package 110 can couple signals received at special terminal 125 of the fabric to corresponding special address inputs 135.

於一特殊的範例中，該等位址輸入135會曝露在一微電子元件130(舉例來說，一半導體晶片)的某一面處，其中，該面面向基板120的第一表面121。於另一範例中，該等位址輸入135會曝露在一微電子元件130中背向該第一表面121的另一面處。於某些情況中，當該等位址輸入135曝露在微電子元件130中背向該第一表面121的另一面處時，一晶粒附接黏著劑可能會被設置在該微電子元件的一背面和基板120的第一表面121之間，其可以機械性增強該微電子元件和該基板之間的連接。 In a particular example, the address inputs 135 are exposed at a face of a microelectronic component 130 (eg, a semiconductor wafer) that faces the first surface 121 of the substrate 120. In another example, the address inputs 135 are exposed at the other side of the microelectronic component 130 that faces away from the first surface 121. In some cases, when the address inputs 135 are exposed at the other side of the microelectronic component 130 facing away from the first surface 121, a die attach adhesive may be disposed on the microelectronic component. A back surface and the first surface 121 of the substrate 120 can mechanically enhance the connection between the microelectronic element and the substrate.

如在圖2A中的特殊範例中進一步所見，一被併入微電子組 件110之中的微電子元件130可能在其某一面處具有多個元件接點135，它們會被電性連接至基板120的第一表面121或第二表面122處的個別基板接點124。於其中一範例中，微電子元件130可能會透過延伸在該微電子元件的元件接點135和基板120的第一表面121處的對應基板接點124之間的導體接合元件被覆晶黏接至基板120。 As further seen in the particular example in Figure 2A, one is incorporated into the microelectronics group. The microelectronic component 130 of the device 110 may have a plurality of component contacts 135 at one of its faces that are electrically connected to the first substrate 121 of the substrate 120 or the individual substrate contacts 124 at the second surface 122. In one example, the microelectronic component 130 may be crystallized by a conductor bonding component extending between the component contact 135 of the microelectronic component and the corresponding substrate contact 124 at the first surface 121 of the substrate 120 to Substrate 120.

於另一範例中，多條焊線可能會延伸穿過基板120中的開口並且可以利用該基板的第二表面122處的基板接點電性連接該等元件接點135。或者，可以使用其它類型的導體(舉例來說，導線框架的一部分、撓性帶狀焊線、…等)來電性連接該等元件接點135和該等個別的基板接點124，於某些情況中，其可能會連接該等元件接點和被設置在從正表面121處算起的高度大於微電子元件130之正面處的其它導體元件。 In another example, a plurality of bonding wires may extend through openings in the substrate 120 and may be electrically connected to the component contacts 135 using substrate contacts at the second surface 122 of the substrate. Alternatively, other types of conductors (for example, a portion of a leadframe, a flexible ribbon bond wire, etc.) may be used to electrically connect the component contacts 135 and the individual substrate contacts 124 to certain In this case, it may be connected to the component contacts and to other conductor elements disposed at a height from the front surface 121 that is greater than the front surface of the microelectronic component 130.

於某些實施例中，該等接點135可能會於某些情況中經由該半導體的後段生產線(Back End Of Line，BEOL)繞線來連接半導體晶片130的主動式裝置，該半導體可能包含穿孔或是其它導電結構並且可能於某些情況中被設置在該等接點135底下。 In some embodiments, the contacts 135 may be connected to the active device of the semiconductor wafer 130 via a back end of line (BEOL) winding of the semiconductor in some cases, the semiconductor may include perforations. Or other conductive structures and may be placed under the contacts 135 in some cases.

該等終端125(以及本文中所述的任何其它終端)可能為導電終端，舉例來說，接點、觸墊、短柱、接針、插槽、繞線、或是曝露在微電子封裝110的第一表面112處的其它導電結構，於圖2A中所示的範例中，該第一表面112係和基板120的第二表面122相同的表面。 The terminals 125 (and any other terminals described herein) may be conductive terminals, for example, contacts, pads, stubs, pins, slots, wires, or exposed to the microelectronic package 110 The other conductive structures at the first surface 112 are the same surface as the second surface 122 of the substrate 120 in the example shown in FIG. 2A.

於某些情況中，該等終端125會被配置成用以導體焊接至另一元件(例如，電路板160)的對應接點165，例如，利用導體接合元件111。導體接合元件111可能包含一由可熔導體材料製成的焊接金屬，就此而言， 例如，焊劑、錫、銦、金、共熔合金材料、含有金屬的導電基質材料、以及聚合材料、或是其它導體焊接材料；而且於某些情況中可能還包含額外的結構，例如，被附接至基板120之導體結構的導體凸塊，例如，導體觸墊或短柱。於其它情況中，該等終端125會被配置成用以機械性和電性扣接電路板160的對應特徵元件，例如，藉由每一個器件的對應導體元件之間的壓力或干涉配接，於某些情況中，器件可能會相對於它們扣接的對應導體表面滑動或塗擦。舉例來說，該等終端125可能會經由基板120上的導電結構(例如，線路和穿孔)來電性連接該等基板接點124。 In some cases, the terminals 125 may be configured to be soldered to corresponding contacts 165 of another component (eg, circuit board 160), for example, using conductor bonding elements 111. The conductor engaging element 111 may comprise a weld metal made of a fusible conductor material, in this regard, For example, flux, tin, indium, gold, eutectic alloy materials, conductive matrix materials containing metals, and polymeric materials, or other conductor soldering materials; and in some cases may also include additional structures, for example, attached Conductor bumps that are connected to the conductor structure of the substrate 120, such as conductor pads or stubs. In other cases, the terminals 125 may be configured to mechanically and electrically engage corresponding features of the circuit board 160, for example, by pressure or interference between corresponding conductor elements of each device, In some cases, the device may slip or rub against the corresponding conductor surface to which they are snapped. For example, the terminals 125 may electrically connect the substrate contacts 124 via conductive structures (eg, lines and vias) on the substrate 120.

如圖2A中所示，導電接合單元111(舉例來說，焊球)會延伸在該微電子組件的所有終端125以及對應的電路板接點165之間。然而，於微電子組件110的某些終端125係無連接終端的實施例中(舉例來說，當該微電子元件為第二類型時，例如，LPDDR3)，此等無連接終端可能會被連接至對應的電路板接點165而沒有於用以傳導資訊給該微電子組件裡面的一微電子元件130的任何電性路徑中被連接在該微電子組件110裡面。 As shown in FIG. 2A, conductive bonding unit 111 (for example, solder balls) extends between all terminals 125 of the microelectronic assembly and corresponding board contacts 165. However, in some embodiments where some of the terminals 125 of the microelectronic component 110 are connectionless terminals (for example, when the microelectronic component is of the second type, eg, LPDDR3), such connectionless terminals may be connected. The corresponding circuit board contacts 165 are not connected to the microelectronic assembly 110 in any electrical path for conducting information to a microelectronic component 130 within the microelectronic assembly.

於某些實施例中，圖2A中所示的基板120(或是本文中所述的任何其它封裝基板)及/或電路板160(或是本文中所述的任何其它電路板)可能包含類薄片或類板狀的介電元件，其基本上可能係由聚合材料(就此而言，舉例來說，樹脂或聚亞醯胺)所組成。或者，基板120及/或電路板160可能包含一具有複合構造的介電元件，例如，玻璃強化環氧樹脂(舉例來說，BT樹脂)或FR-4構造。於某些範例中，基板120及/或電路板160的介電元件在該介電元件的平面中(也就是，在平行於其第一表面110的方向中)可能具有高達每攝氏度數百萬分(下文中稱為ppm/℃)之30的熱膨脹係數。 In some embodiments, the substrate 120 (or any other package substrate described herein) and/or the circuit board 160 (or any other circuit board described herein) shown in FIG. 2A may contain classes. A sheet or plate-like dielectric element, which may consist essentially of a polymeric material (for example, a resin or a polyamidamide). Alternatively, substrate 120 and/or circuit board 160 may comprise a dielectric component having a composite construction, such as a glass reinforced epoxy (for example, BT resin) or FR-4 construction. In some examples, the dielectric elements of substrate 120 and/or circuit board 160 may have up to millions per degree Celsius in the plane of the dielectric element (ie, in a direction parallel to its first surface 110). The coefficient of thermal expansion of 30 (hereinafter referred to as ppm/°C).

於另一範例中，基板120可能包含一由熱膨脹係數(Coefficient of Thermal Expansion，CTE)小於每攝氏度數百萬分之12的材料製成的支撐元件，其上可能設置著該等終端125和其它導體結構。舉例來說，此低CTE的元件基本上可能係由下面所組成：玻璃、陶瓷、或是半導體材料或液晶聚合物材料、或是此等材料的組合。 In another example, the substrate 120 may comprise a support member made of a material having a coefficient of thermal expansion (CTE) of less than 12 parts per million degrees Celsius, on which the terminals 125 and others may be disposed. Conductor structure. For example, the low CTE component may consist essentially of glass, ceramic, or a semiconductor material or a liquid crystal polymer material, or a combination of such materials.

於其中一範例中，導體組170可能包含延伸在平行於電路板160之第一表面161的第一方向X中的至少一匯流排。於一特殊的範例中，導體組170的該至少一匯流排可能會延伸在平行於電路板160之第一表面161的第二方向Y中，該第二方向橫越該第一方向。於某些實施例中，導體組170之該等匯流排的該等訊號線可能位於彼此相同的平面中，而且每一條獨特的訊號線皆可能包含延伸在複數個平面中和延伸在複數個方向中的多個導體部。 In one example, conductor set 170 may include at least one bus bar that extends in a first direction X that is parallel to first surface 161 of circuit board 160. In a particular example, the at least one busbar of conductor set 170 may extend in a second direction Y parallel to first surface 161 of circuit board 160, the second direction traversing the first direction. In some embodiments, the signal lines of the bus bars of the conductor set 170 may be in the same plane as each other, and each unique signal line may include extending in a plurality of planes and extending in a plurality of directions. Multiple conductor sections in the middle.

導體組170之該至少一匯流排可能有複數條訊號線，被配置成用以攜載傳輸至電路板160之該等接點165的所有位址資訊。該等接點165會電性連接導體組170的該至少一匯流排。於其中一範例中，導體組170的該至少一匯流排會被配置成用以攜載傳輸至該等接點165的所有命令訊號，該等命令訊號包含寫入致能訊號、列位址選通訊號、以及行位址選通訊號。 The at least one bus bar of the conductor set 170 may have a plurality of signal lines configured to carry all of the address information transmitted to the contacts 165 of the circuit board 160. The contacts 165 are electrically connected to the at least one bus bar of the conductor set 170. In one example, the at least one bus bar of the conductor set 170 is configured to carry all command signals transmitted to the contacts 165, the command signals including write enable signals, column address selection The communication number and the line address are selected as the communication number.

電路板160可能視情況包含一或更多個終端電阻器，它們會被連接至一終端電壓源。導體組170之該等匯流排中一或更多者的該等複數條訊號線中的一或更多條訊號線會視情況被電性連接至一終端電阻器。 Circuit board 160 may optionally include one or more terminating resistors that are connected to a terminal voltage source. One or more of the plurality of signal lines of one or more of the bus bars of the conductor set 170 are electrically connected to a terminating resistor as appropriate.

圖2A中所示的該等接點165會根據一預設的排列方式被排 列，該預設的排列方式定義電路板160之第一表面161上用於攜載位址與命令資訊及資料的接點的相對位置。 The contacts 165 shown in Figure 2A are arranged according to a predetermined arrangement. The arrangement of the presets defines the relative position of the contacts on the first surface 161 of the circuit board 160 for carrying the address and command information and data.

電路板160不需要在第一模式與第二模式中進行改變便能使用，當該等接點165中的一給定接點組連接一對應類型微電子封裝110的終端時便會啟動某一種模式。舉例來說，器件105可能包含一電路板160以及一第一類型微電子封裝110，該第一類型微電子封裝110的第一終端125會被接合至該電路板的第一接點165。於另一範例中，一器件5可能包含一電路板160以及一第二類型微電子封裝110，該第二類型微電子封裝110的第一終端125會被接合至該電路板的第一接點165。 The circuit board 160 can be used without changing in the first mode and the second mode. When a given contact group of the contacts 165 is connected to the terminal of a corresponding type microelectronic package 110, a certain type is activated. mode. For example, device 105 may include a circuit board 160 and a first type of microelectronic package 110, the first terminal 125 of which is bonded to the first contact 165 of the circuit board. In another example, a device 5 may include a circuit board 160 and a second type of microelectronic package 110. The first terminal 125 of the second type of microelectronic package 110 is bonded to the first contact of the circuit board. 165.

舉例來說，在第一模式中，電路板160會被耦合至一第一類型微電子封裝110，該第一類型微電子封裝110可操作用於以每個時脈週期一次的方式取樣該等第一接點165所攜載的位址與命令資訊。此等微電子封裝可能為DDR3或DDR4型，或者，可能為GDDR3、GDDR4、或GDDR5型。 For example, in the first mode, the circuit board 160 can be coupled to a first type of microelectronic package 110 that is operable to sample the clocks once per clock cycle. The address and command information carried by the first contact 165. These microelectronic packages may be of the DDR3 or DDR4 type, or may be of the GDDR3, GDDR4, or GDDR5 type.

和雙倍資料速率DRAM記憶體與低功率雙倍資料速率DRAM記憶體以及預期不久的未來會實現的圖形式雙倍資料速率DRAM記憶體有關的標準不斷地在發展。目前及未來的標準皆始於DDR3標準，而LPDDR3標準及GDDR3標準在本文中分別統稱為「DDRx」、「LPDDRx」、以及「GDDRx」。 Standards related to double data rate DRAM memory and low power double data rate DRAM memory and graphical double data rate DRAM memory that is expected to be realized in the near future are constantly evolving. Current and future standards begin with the DDR3 standard, and the LPDDR3 standard and the GDDR3 standard are collectively referred to herein as "DDRx", "LPDDRx", and "GDDRx".

於一特殊的範例中，在第二模式中，電路板160會被耦合至一第二類型微電子封裝110，該第二類型微電子封裝110可操作用於以每個時脈週期兩次的方式取樣該等第一接點165所攜載的位址與命令資訊。此 等微電子封裝110可能為LPDDRX型，舉例來說，就既有和計劃的標準來說，LPDDR3或LPDDR4。 In a particular example, in the second mode, the circuit board 160 is coupled to a second type of microelectronic package 110 that is operable for two cycles per clock cycle. The method samples the address and command information carried by the first contacts 165. this The microelectronic package 110 may be of the LPDDRX type, for example, LPDDR3 or LPDDR4, both in terms of planned and planned standards.

於其中一實施例中，電路板160會利用該等第一接點165中的第一子集被耦合至一第一類型微電子封裝110，而且相同的電路板會利用該等第一接點中的第二子集被耦合至一第二類型微電子封裝，該第二子集的接點的數量少於該第一子集。於此實施例中，第一類型微電子封裝110可操作用於以和第二類型微電子封裝110可操作用以取樣該等第一接點中的第二子集所攜載的位址與命令資訊之每個時脈週期中相同次數的方式(舉例來說，每個時脈週期一次)來取樣該等第一接點中的第一子集所攜載的位址與命令資訊。 In one embodiment, the circuit board 160 is coupled to a first type of microelectronic package 110 using a first subset of the first contacts 165, and the same circuit board utilizes the first contacts. The second subset is coupled to a second type of microelectronic package, the second subset having fewer contacts than the first subset. In this embodiment, the first type of microelectronic package 110 is operable to operate with the second type of microelectronic package 110 to sample the address carried by the second subset of the first contacts. The same number of times in each clock cycle of the command information (for example, once per clock cycle) is used to sample the address and command information carried by the first subset of the first contacts.

於此實施例中，第一類型微電子封裝110可能具有DDR4型的微電子元件，而第二類型微電子封裝可能具有DDR3型的微電子元件。該等第一接點165中的第一子集可能包含被配置成用以攜載沒有被該等第一接點中的第二子集攜載的命令與位址資訊(例如，舉例來說，ALERT_N(其係一I/O訊號，可能係被用來發訊通知同位元錯誤的輸出)；BG(組群訊號)；被輸入至晶片PAR的同位元位元，其會如同任何其它命令-位址訊號、ACT輸入、以及DRAM般地被取樣，其會以該晶片收到的資訊(其包含位址資訊、PAR位元、以及已收到的命令資訊(也就是，RAS、CAS、ACT(啟動主動低位準訊號)))為基礎來檢查同位元)的某些接點。再者，該等第一接點165中的第二子集的接點的數量雖然少於該第一子集；不過，該等第一接點中的第二子集可能包含三組位址資訊(用於DDR3微電子元件)，而該等第一接點中的第一子集可能包含兩組位址資訊(用於DDR4微電子元件)。 In this embodiment, the first type of microelectronic package 110 may have a DDR4 type microelectronic component, and the second type of microelectronic package may have a DDR3 type of microelectronic component. The first subset of the first contacts 165 may include command and address information configured to carry not being carried by the second subset of the first contacts (eg, for example, , ALERT_N (which is an I/O signal, may be used to signal the output of the same bit error); BG (group signal); the same bit that is input to the chip PAR, which would be like any other command - Address signal, ACT input, and DRAM-like sampling, which will receive information from the chip (which contains address information, PAR bits, and command information received (ie, RAS, CAS, Some contacts of the ACT (starting the active low-level signal))) to check the same bits). Moreover, the number of contacts of the second subset of the first contacts 165 is less than the first subset; however, the second subset of the first contacts may contain three sets of addresses Information (for DDR3 microelectronic components), and the first subset of these first contacts may contain two sets of address information (for DDR4 microelectronic components).

於一特殊的實施例中，第一類型微電子封裝中的該等一或更多個微電子元件130可能併入一和該第二類型微電子封裝中的該等一或更多個微電子元件不同類型的記憶體儲存陣列。於另一範例中，電路板160會被耦合至另一類型的微電子封裝110，其可操作用於以每個時脈週期四次的方式取樣該等第一接點165所攜載的位址與命令資訊。 In a particular embodiment, the one or more microelectronic components 130 in the first type of microelectronic package may incorporate the one or more microelectronics in the second type of microelectronic package. Different types of memory storage arrays for components. In another example, the circuit board 160 can be coupled to another type of microelectronic package 110 that is operable to sample the bits carried by the first contacts 165 four times per clock cycle. Address and command information.

於圖2A的實施例中，於其中一範例中，例如，當第一類型微電子封裝110包含複數個微電子元件130時，該第一類型微電子封裝中的所有微電子元件會被配置成用以連接被配置成用以攜載單一組命令-位址訊號的相同導體組170。於此實施例中，器件105可能會被配置成使得當於其中具有DDR3或DDR4記憶體的第一類型微電子封裝100被附接至該器件時，該微電子封裝中的該等微電子元件會被配置成用於以第一取樣率(例如，每個時脈週期一次，舉例來說，在該時脈週期的上升訊號緣)來取樣經由第一數量的接點165與其耦合的命令與位址資訊。 In the embodiment of FIG. 2A, in one example, for example, when the first type of microelectronic package 110 includes a plurality of microelectronic components 130, all of the microelectronic components in the first type of microelectronic package are configured to Used to connect the same set of conductors 170 that are configured to carry a single set of command-address signals. In this embodiment, device 105 may be configured such that when a first type of microelectronic package 100 having DDR3 or DDR4 memory therein is attached to the device, the microelectronic components in the microelectronic package Will be configured to sample a command coupled thereto via a first number of contacts 165 at a first sampling rate (e.g., once per clock cycle, for example, at the rising edge of the clock cycle) Address information.

於圖2A的實施例中，於另一範例中，例如，當第二類型微電子封裝110包含複數個微電子元件130時，該等第一接點165中的第一群接點會被連接至該導體組170的一第一命令-位址訊號匯流排，其會被連接至該等微電子元件中的前半部微電子元件，而第二群接點165會被連接至該導體組的一第二命令-位址訊號匯流排，其會被連接至該等微電子元件中的後半部微電子元件。器件105可能會被配置成使得當於其中具有LPDDR3記憶體的第二類型微電子封裝100被附接至該器件時，該微電子封裝中的該等微電子元件30會被配置成用於以第二取樣率(例如，每個時脈週期兩次，舉例來說，在該時脈週期的上升訊號緣和下降訊號緣各一次)來取樣經 由第二數量的接點165與其耦合的命令與位址資訊。 In the embodiment of FIG. 2A, in another example, for example, when the second type microelectronic package 110 includes a plurality of microelectronic components 130, the first group of contacts in the first contacts 165 are connected. a first command-address signal bus to the conductor set 170 that is connected to the first half of the microelectronic components, and the second set of contacts 165 is connected to the conductor set A second command-address signal bus that is connected to the second half of the microelectronic components. Device 105 may be configured such that when a second type of microelectronic package 100 having LPDDR3 memory therein is attached to the device, the microelectronic components 30 in the microelectronic package may be configured to The second sampling rate (for example, twice per clock cycle, for example, one time at the rising edge and the falling edge of the clock cycle) Command and address information coupled thereto by a second number of contacts 165.

舉例來說，一第二類型微電子封裝110可能包含複數個微電子元件130，該等微電子元件中的前半部微電子元件會被配置成用以連接第一群第一接點中的第一接點165而不會連接第二群第一接點；而該等微電子元件中的後半部微電子元件則會被配置成用以連接第二群第一接點中的第一接點而不會連接第一群第一接點。於此實施例中，該導體組170會被配置成用以攜載兩組相同的命令-位址訊號，俾使得該等微電子元件130中的每一個半部會被連接至該導體組的該等兩組命令-位址訊號中的其中一組。本發明的優點係，不論與其電性連接的微電子封裝110的類型為何，該等導體170的實體排列方式都不會改變。 For example, a second type of microelectronic package 110 may include a plurality of microelectronic elements 130, and the first half of the microelectronic elements may be configured to connect the first of the first group of first contacts a contact 165 is not connected to the second group of first contacts; and the second half of the microelectronic components are configured to connect the first contact of the second group of first contacts It will not connect the first group of first contacts. In this embodiment, the conductor set 170 is configured to carry two sets of identical command-address signals such that each of the microelectronic components 130 is connected to the conductor set. One of the two sets of command-address signals. An advantage of the present invention is that the physical arrangement of the conductors 170 does not change regardless of the type of microelectronic package 110 to which it is electrically connected.

並不需要使用全部的導體組170來攜載訊號。舉例來說，於該導體組170被配置成用以攜載兩組相同的命令-位址訊號的其中一實施例中，當該等導體被電性連接至一微電子封裝110時，並不需要所有該等導體攜載訊號給該微電子封裝。即使當該導體組170被配置成用以攜載兩組相同的命令-位址訊號，該微電子組件仍可能不使用被配置成用以攜載完全相同之命令-位址訊號的導體中的一部分或全部，以便減少該導體組170所攜載的切換訊號的數量，以便降低功率消耗。 It is not necessary to use all of the conductor sets 170 to carry the signals. For example, in one embodiment in which the conductor set 170 is configured to carry two sets of identical command-address signals, when the conductors are electrically connected to a microelectronic package 110, All of these conductors are required to carry signals to the microelectronic package. Even when the conductor set 170 is configured to carry two sets of identical command-address signals, the microelectronic component may not use a conductor configured to carry the exact same command-address signal. Part or all, in order to reduce the number of switching signals carried by the conductor set 170 in order to reduce power consumption.

於一特殊的範例中，一第二類型微電子封裝110可能包含單一個微電子元件，其會連接第一群第一接點中的第一接點165而不會連接第二群第一接點，俾使得該單一微電子元件會連接該導體組170的一第一命令-位址訊號匯流排，而不會連接該導體組的一第二命令-位址訊號匯流排。 In a particular example, a second type of microelectronic package 110 may include a single microelectronic component that connects the first contact 165 of the first group of first contacts without connecting the second group of first connections. The point 俾 causes the single microelectronic component to connect to a first command-address signal bus of the conductor set 170 without connecting a second command-address signal bus of the conductor set.

器件105可能還包含一被耦合至該導體組170的裝置180，該裝置可操作用以將該命令與位址資訊驅動至該等接點165。裝置180會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過位址和命令資訊指派所組成的第一排列方式來連接器件105和第一類型微電子組件110以及透過位址和命令資訊指派所組成的第二排列方式來連接器件105和第二類型微電子組件，而不需要改變該等導體170的實體配置。 Device 105 may also include a device 180 coupled to the conductor set 170 that is operable to drive the command and address information to the contacts 165. The device 180 is configured to operate in each of the first mode and the second mode to connect the device 105 and the first type of microelectronics by a first arrangement consisting of an address and a command information assignment, respectively. The component 110 and the second arrangement of address and command information assignments connect the device 105 and the second type of microelectronic assembly without changing the physical configuration of the conductors 170.

圖2B圖解根據圖2A中所示之本發明變化例的器件105b。如圖2B中所見，器件105b包含一電路板160b，其具有相鄰於該電路板之邊緣163的至少一列曝露接點164。舉例來說，該等曝露接點164會被配置在一或更多個平行列之中，而且該等曝露接點會依照下面參考圖3A至3C所述的任何方式被配置。器件105b會藉由將邊緣163插入在第二電路板190的對應插槽193之中而被耦合至該第二電路板。器件105b會依照下面參考圖3A至3C所述的任何方式被耦合至電路板190。 Figure 2B illustrates a device 105b in accordance with a variation of the invention illustrated in Figure 2A. As seen in Figure 2B, device 105b includes a circuit board 160b having at least one column of exposed contacts 164 adjacent to edge 163 of the circuit board. For example, the exposed contacts 164 will be configured in one or more parallel columns, and the exposed contacts will be configured in any manner as described below with reference to Figures 3A through 3C. Device 105b is coupled to the second circuit board by inserting edge 163 into corresponding slot 193 of second circuit board 190. Device 105b will be coupled to circuit board 190 in any manner described below with respect to Figures 3A-3C.

第二電路板190可能包含一被耦合至該第二電路板的一導體組195的裝置180a，該裝置可操作用以將該命令與位址資訊驅動至電路板160b的接點165。器件105b可能包含一被耦合至該導體組的裝置180b。於其中一範例中，裝置180n可能係一緩衝元件；或是一協定轉換器，其會被配置成用以將能夠被器件5或電路板190使用之具有第一協定的位址資訊轉換成能夠被微電子組件110中特殊類型微電子元件130使用的第二協定。 The second circuit board 190 may include a device 180a coupled to a conductor set 195 of the second circuit board, the device being operative to drive the command and address information to the contacts 165 of the circuit board 160b. Device 105b may include a device 180b coupled to the conductor set. In one example, device 180n may be a buffer component; or a protocol converter configured to convert address information having a first agreement that can be used by device 5 or circuit board 190 to enable A second protocol used by the special type of microelectronic component 130 in the microelectronic assembly 110.

裝置180a與180b中的一或兩者會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過位址和命令資訊指派所組成的第一排列方式來連接器件105和第一類型微電子組件110以及透過位址和 命令資訊指派所組成的第二排列方式來連接器件105和第二類型微電子組件。 One or both of the devices 180a and 180b are configured to operate in each of the first mode and the second mode to connect by a first arrangement consisting of an address and a command information assignment, respectively. Device 105 and first type of microelectronic assembly 110 and through address and A second arrangement of command information assignments is used to connect the device 105 to the second type of microelectronic assembly.

本文中所述之任何實施例中所示的電路板(舉例來說，圖2C與2D的電路板160c)可能係一第一電路板，例如，具有一連接器介面用以電性連接一第二電路板(例如，電路板190)的電路板160b，該連接器介面被配置成用以攜載資訊，以便傳輸至該等接點165以及從該等接點165處傳輸出來。此排列方式的一特殊範例顯示在圖7中，圖中顯示複數個器件606(每一個器件可能包含一電路板160b)透過一個別的連接器介面被耦合至一第二電路板602。 The circuit board shown in any of the embodiments described herein (for example, the circuit board 160c of FIGS. 2C and 2D) may be a first circuit board, for example, having a connector interface for electrically connecting a first A circuit board 160b of a second circuit board (e.g., circuit board 190) that is configured to carry information for transmission to and from the contacts 165. A particular example of this arrangement is shown in FIG. 7, which shows a plurality of devices 606 (each of which may include a circuit board 160b) coupled to a second circuit board 602 through a different connector interface.

於圖7中所示的範例中，該連接器介面可能包含一插槽605，其在該插槽的一或兩側處具有複數個接點607，該插槽會被配置成用以接收一電路板，例如，電路板160b，其具有被設置在該電路板的至少一邊緣163處的對應曝露邊緣接點。於其它實施例中，介於電路板160c和該第二電路板190之間的連接器介面可能係圖3A與3B中所示的類型，或者，可能係表面鑲嵌連接類型(舉例來說，BGA、LGA、PGA、…等)。 In the example shown in FIG. 7, the connector interface may include a slot 605 having a plurality of contacts 607 at one or both sides of the slot, the slot being configured to receive a slot A circuit board, such as circuit board 160b, has corresponding exposed edge contacts disposed at at least one edge 163 of the circuit board. In other embodiments, the connector interface between the circuit board 160c and the second circuit board 190 may be of the type shown in Figures 3A and 3B, or may be a surface damascene connection type (for example, BGA) , LGA, PGA, ..., etc.).

圖2C圖解一器件105c，其包含一電路板160c，該電路板160c被配置成用於耦合至一或更多個微電子封裝110c。圖2C和2D中所示的電路板160c為相同的電路板，而且圖2C和2D中的每一者皆顯示一器件105c，其包含被耦合至一不同的個別微電子組件110c或110d的電路板160c。 2C illustrates a device 105c that includes a circuit board 160c that is configured for coupling to one or more microelectronic packages 110c. The circuit board 160c shown in Figures 2C and 2D is the same circuit board, and each of Figures 2C and 2D shows a device 105c that includes circuitry coupled to a different individual microelectronic assembly 110c or 110d. Plate 160c.

如在圖2C中所見，電路板160c會定義第一表面161和第二表面162。電路板160c會有至少一接點組168，曝露在第一表面161處，用於連接一併入具有記憶體儲存陣列之一或更多個微電子元件131的微電子 封裝110c的對應表面鑲嵌終端125與127(舉例來說，BGA、LGA、…等類型)。 As seen in Figure 2C, the circuit board 160c defines a first surface 161 and a second surface 162. The circuit board 160c has at least one contact set 168 exposed at the first surface 161 for connecting a microelectronic having one or more microelectronic components 131 having a memory storage array. The corresponding surface of package 110c is inlaid with terminals 125 and 127 (for example, BGA, LGA, ..., etc.).

電路板160c可能具有複數組接點165與167，由接點165、167組成的每一個接點組168會被配置成用以連接至單一個微電子封裝110c。每一個接點組168中的接點可能包含：多個第一接點165，用以攜載位址與命令資訊；以及多個第二接點167，用以攜載位址與命令資訊以外的資訊(舉例來說，資料輸入/輸出資訊)。 Circuit board 160c may have complex array contacts 165 and 167, each of which is configured to be connected to a single microelectronic package 110c. The contacts in each of the contact groups 168 may include: a plurality of first contacts 165 for carrying address and command information; and a plurality of second contacts 167 for carrying address and command information. Information (for example, data input/output information).

雷同於圖2A，該等接點組成的每一個接點組168會有一預設的排列方式，其定義第一表面161(或是第二表面162，倘若該接點組曝露在第二表面的話)上用於攜載位址與命令資訊及資料的接點的相對位置。每一個接點組168中的接點會根據該預設的排列方式被排列。根據分別用於連接兩種不同類型微電子組件110的兩種不同預設排列方式來排列之該等接點組成的接點組168在本文中亦稱為一組「共支撐接點」。 Similarly to FIG. 2A, each of the contact sets 168 of the contacts has a predetermined arrangement that defines a first surface 161 (or a second surface 162 if the contact set is exposed on the second surface). The relative position of the joint used to carry the address and command information and data. The contacts in each of the contact groups 168 are arranged according to the preset arrangement. The set of contacts 168 of the contacts arranged in accordance with two different preset arrangements for connecting the two different types of microelectronic assemblies 110 are also referred to herein as a set of "co-supported contacts."

電路板160c不需要在第一模式與第二模式中進行改變便能使用，當由接點組成的一給定接點組168連接一對應類型微電子封裝110c或110d的終端時便會啟動某一種模式。舉例來說，器件105c可能會接合一第一類型微電子封裝110c(圖2C)，該第一類型微電子封裝110c的第一終端125會被接合至該電路板的第一接點165。於另一範例中，相同的器件105c可能接合一第二類型微電子封裝110d(圖2D)，該第二類型微電子封裝110d的第一終端125會被接合至該電路板的第一接點165。 The circuit board 160c can be used without changing in the first mode and the second mode. When a given contact group 168 composed of contacts is connected to a terminal of a corresponding type microelectronic package 110c or 110d, a certain A pattern. For example, device 105c may engage a first type of microelectronic package 110c (FIG. 2C), and first terminal 125 of first type microelectronic package 110c will be bonded to first contact 165 of the circuit board. In another example, the same device 105c may be coupled to a second type of microelectronic package 110d (FIG. 2D), the first terminal 125 of the second type of microelectronic package 110d being bonded to the first contact of the circuit board 165.

舉例來說，在第一模式中，電路板160c會被耦合至一第一類型微電子封裝110c，該第一類型微電子封裝110c可操作用於以每個時脈 週期一次的方式取樣該等第一接點165所攜載的位址與命令資訊。此等第一類型微電子封裝的範例包含具有四個微電子元件131a、131b、131c、以及131d的微電子封裝110c，如圖2C中所示，或者包含具有其它數量(下文將作說明)微電子元件的微電子封裝110c。此微電子封裝110c可能包含DDR3或DDR4型(一般稱為DDRx)或是GDDR3或GDDR4型(一般稱為GDDRx)的微電子元件131。 For example, in the first mode, the circuit board 160c will be coupled to a first type of microelectronic package 110c that is operable for each clock. The address and command information carried by the first contacts 165 are sampled in a periodic manner. Examples of such first type microelectronic packages include a microelectronic package 110c having four microelectronic elements 131a, 131b, 131c, and 131d, as shown in Figure 2C, or containing other quantities (described below) Microelectronic package 110c of electronic components. The microelectronic package 110c may comprise a microelectronic component 131 of the DDR3 or DDR4 type (generally referred to as DDRx) or GDDR3 or GDDR4 type (generally referred to as GDDRx).

於一特殊的範例中，在第二模式中，電路板160c會被耦合至一第二類型微電子封裝110d，該第二類型微電子封裝110d可操作用於以每個時脈週期兩次的方式取樣該等第一接點165所攜載的位址與命令資訊。此種第二類型微電子封裝的範例包含具有四個微電子元件132a、132b、132c、以及132d的微電子封裝110d，如圖2D中所示，或者包含具有其它數量(下文將作說明)微電子元件的微電子封裝110d。此微電子封裝110d可能包含LPDDR3或LPDDR4型(一般稱為LPDDRx)的微電子元件132。 In a particular example, in the second mode, the circuit board 160c is coupled to a second type of microelectronic package 110d that is operable for two cycles per clock cycle. The method samples the address and command information carried by the first contacts 165. An example of such a second type of microelectronic package includes a microelectronic package 110d having four microelectronic elements 132a, 132b, 132c, and 132d, as shown in Figure 2D, or including other quantities (described below) Microelectronic package 110d for electronic components. This microelectronic package 110d may comprise a microelectronic component 132 of the LPDDR3 or LPDDR4 type (generally referred to as LPDDRx).

於一特殊的範例中，該第一類型微電子封裝(舉例來說，圖2C中所示的微電子封裝110c)中的該等一或更多個微電子元件131會併入一和該第二類型微電子封裝(舉例來說，圖2D中所示的微電子封裝110d)中的該等一或更多個微電子元件不同類型的記憶體儲存陣列。 In a particular example, the one or more microelectronic components 131 in the first type of microelectronic package (for example, the microelectronic package 110c shown in FIG. 2C) will incorporate one and the first Different types of memory storage arrays of the one or more microelectronic components in a two type of microelectronic package (for example, microelectronic package 110d shown in Figure 2D).

如能夠在圖2C中所見，電路板160c可能在每一個接點組168中包含多個第一接點165，其可能包含第一群第一接點165a和第二群第一接點165b。每一群第一接點165a和165b會被指派用以攜載可用於明確指定該等一或更多個微電子元件131組成的記憶體儲存陣列裡面的一位置的位址資訊。 As can be seen in FIG. 2C, the circuit board 160c may include a plurality of first contacts 165 in each of the contact sets 168, which may include a first group of first contacts 165a and a second group of first contacts 165b. Each group of first contacts 165a and 165b is assigned to carry address information that can be used to explicitly designate a location within the memory storage array of one or more of the one or more microelectronic components 131.

當電路板160c被連接至一第一類型微電子封裝(例如，圖2C中所示的微電子封裝110c)時，該等第一群第一接點165a和第二群第一接點165b會被用來一起明確指定該等一或更多個微電子元件131組成的記憶體儲存陣列裡面的一位置。 When the circuit board 160c is connected to a first type of microelectronic package (eg, the microelectronic package 110c shown in FIG. 2C), the first group of first contacts 165a and the second group of first contacts 165b A location within the memory storage array that is used to explicitly designate one or more of the one or more microelectronic components 131.

於此範例中，該第一群第一接點165a會被連接至導體組170中的一第一命令-位址訊號匯流排F0(其會被連接至每一個微電子元件131)，而該第二群接點165b會被連接至該導體組中的一第二命令-位址訊號匯流排F1(其會被連接至每一個微電子元件131)。於特殊的實施例中，一第一類型微電子封裝可能包含一或兩個微電子元件131，每一個微電子元件會被配置成用以連接該等第一群第一接點165a和第二群第一接點165b中每一群中的第一接點165。於其它實施例中，一第一類型微電子封裝可能包含兩個以上的微電子元件131，每一個微電子元件會被配置成用以連接該等第一群第一接點165a和第二群第一接點165b中每一群中的第一接點165。 In this example, the first group of first contacts 165a are connected to a first command-address signal bus F0 (which will be connected to each of the microelectronic components 131) in the conductor set 170. The second group of contacts 165b will be connected to a second command-address signal bus F1 (which will be connected to each of the microelectronic elements 131) in the conductor set. In a particular embodiment, a first type of microelectronic package may include one or two microelectronic components 131, each of which may be configured to connect the first plurality of first contacts 165a and second The first contact 165 in each of the group first contacts 165b. In other embodiments, a first type of microelectronic package may include more than two microelectronic components 131, each of which may be configured to connect the first plurality of first contacts 165a and the second group The first contact 165 in each of the first contacts 165b.

於圖2C中所示的範例中，該微電子封裝110c具有四個微電子元件131，而且此等微電子元件中的每一者會被連接至導體組170的第一命令-位址訊號匯流排F0和第二命令-位址訊號匯流排F1兩者。於圖2C中所示的範例中，每一個微電子元件131a、131b、131c、以及131d會接收16位位元的命令-位址訊號資訊：8位位元來自訊號匯流排F0，而8位位元來自訊號匯流排F1。訊號匯流排F0與F1以及該等微電子元件131之間的連接概略地顯示在圖2C中，導體G0會連接訊號匯流排F0，而導體G1會連接訊號匯流排F1。 In the example shown in FIG. 2C, the microelectronic package 110c has four microelectronic components 131, and each of the microelectronic components is connected to the first command-address signal sink of the conductor set 170. Row F0 and second command - address signal bus F1 both. In the example shown in FIG. 2C, each of the microelectronic components 131a, 131b, 131c, and 131d receives a command-bit address information of a 16-bit bit: the 8-bit bit comes from the signal bus F0, and the 8-bit The bit is from the signal bus F1. The connection between the signal bus bars F0 and F1 and the microelectronic components 131 is schematically shown in Fig. 2C, the conductor G0 is connected to the signal bus F0, and the conductor G1 is connected to the signal bus F1.

於圖2C中所示之實施例的變化例中，該第一類型微電子封 裝110c可能具有八個微電子元件131，而且此等微電子元件中的每一者會被連接至導體組170的第一命令-位址訊號匯流排F0和第二命令-位址訊號匯流排F1兩者。於此範例中，每一個微電子元件131會接收16位位元的命令-位址訊號資訊：8位位元來自訊號匯流排F0，而8位位元來自訊號匯流排F1。 In a variation of the embodiment shown in FIG. 2C, the first type of microelectronic seal The package 110c may have eight microelectronic components 131, and each of the microelectronic components will be connected to the first command-address signal bus F0 and the second command-address bus of the conductor set 170. Both F1. In this example, each microelectronic component 131 receives a command-bit address information of 16 bits: the 8-bit bit comes from the signal bus F0, and the 8-bit bit comes from the signal bus F1.

或者，當電路板160c被連接至一第二類型微電子封裝(例如，圖2D中所示的微電子封裝110d)時，該等第一群第一接點165a和第二群第一接點165b會被分開使用，以便各自明確指定該等一或更多個微電子元件132a、132b、132c、以及132d組成的記憶體儲存陣列裡面的一位置。 Alternatively, when the circuit board 160c is connected to a second type of microelectronic package (eg, the microelectronic package 110d shown in FIG. 2D), the first group of first contacts 165a and the second group of first contacts 165b will be used separately to individually specify a location within the memory storage array of one or more of the one or more microelectronic elements 132a, 132b, 132c, and 132d.

於此範例中，該第一群第一接點165a會被連接至導體組170中的一第一命令-位址訊號匯流排F0(其會被連接至該等微電子元件132中的前半部微電子元件)，而該第二群接點165b會被連接至該導體組中的一第二命令-位址訊號匯流排F1(其會被連接至該等微電子元件132中的後半部微電子元件)。舉例來說，一第二類型微電子封裝可能包含複數個微電子元件132，該等微電子元件中的前半部微電子元件會被配置成用以連接該第一群第一接點165a中的第一接點165而不連接該第二群第一接點165b，而該等微電子元件中的後半部微電子元件則會被配置成用以連接該第二群第一接點165b中的第一接點而不連接該第一群第一接點165a。 In this example, the first group of first contacts 165a will be connected to a first command-address signal bus F0 in the conductor set 170 (which will be connected to the first half of the microelectronic components 132). Microelectronic component), and the second group of contacts 165b is coupled to a second command-address signal bus F1 in the conductor set (which is connected to the second half of the microelectronic components 132) Electronic component). For example, a second type of microelectronic package may include a plurality of microelectronic elements 132, and the first half of the microelectronic elements may be configured to connect to the first group of first contacts 165a. The first contact 165 is not connected to the second group of first contacts 165b, and the second half of the microelectronic components are configured to be connected to the second group of first contacts 165b The first contact is not connected to the first group first contact 165a.

於一特殊的範例中，一第二類型微電子封裝可能包含單一個微電子元件132，其會連接該第一群第一接點165a中的第一接點165而不連接該第二群第一接點165b，俾使得該單一個微電子元件會連接該第一命令-位址訊號匯流排F0而不連接該第二命令-位址訊號匯流排F1。 In a particular example, a second type of microelectronic package may include a single microelectronic component 132 that connects the first contact 165 of the first plurality of first contacts 165a without connecting the second group. A contact 165b causes the single microelectronic component to connect to the first command-address signal bus F0 without connecting the second command-address signal bus F1.

在圖2D中，微電子封裝110d有四個微電子元件132a、132b、132c、以及132d。此等微電子元件中的其中兩個132a與132b會連接該第一群第一接點165a而不連接該第二群第一接點165b，俾使得微電子元件132a與132b會連接導體組170的第一命令-位址訊號匯流排F0而不連接該第二命令-位址訊號匯流排F1。此等微電子元件中的另外兩個132c與132d則會連接該第二群第一接點165b而不連接該第一群第一接點165a，俾使得微電子元件132c與132d會被連接至第二命令-位址訊號匯流排F1而不連接至該第一命令-位址訊號匯流排F0。 In FIG. 2D, microelectronic package 110d has four microelectronic components 132a, 132b, 132c, and 132d. Two of the microelectronic components 132a and 132b are connected to the first group of first contacts 165a without connecting the second group of first contacts 165b, such that the microelectronic components 132a and 132b are connected to the conductor set 170. The first command - the address signal bus F0 is not connected to the second command - the address signal bus F1. The other two of the microelectronic components 132c and 132d are connected to the second group of first contacts 165b without connecting the first group of first contacts 165a, such that the microelectronic components 132c and 132d are connected to The second command-address signal bus F1 is not connected to the first command-address signal bus F0.

於此實施例中，每一條訊號匯流排F0與F1會被配置成用以攜載兩組命令-位址訊號，俾使得該等四個微電子元件132中的每一者會被連接至一特殊訊號匯流排F0或F1中的該等兩組命令-位址訊號中的其中一者。 In this embodiment, each of the signal bus bars F0 and F1 is configured to carry two sets of command-address signals, so that each of the four microelectronic components 132 is connected to one. One of the two sets of command-address signals in the special signal bus F0 or F1.

於圖2D中所示之實施例的其中一範例中，該等微電子元件中的其中兩個132a與132b會從第一命令-位址訊號匯流排F0處接收32位位元的命令-位址訊號資訊，而此等微電子元件中的另外兩個132c與132d則會從第二命令-位址訊號匯流排F1處接收32位位元的命令-位址訊號資訊。於圖2D中所示之實施例的另一範例中，該等微電子元件中的其中兩個132a與132b會從第一命令-位址訊號匯流排F0處接收16位位元的命令-位址訊號資訊，而此等微電子元件中的另外兩個132c與132d則會從第二命令-位址訊號匯流排F1處接收16位位元的命令-位址訊號資訊。訊號匯流排F0與F1以及該等微電子元件132之間的連接概略地顯示在圖2D中，導體G0會連接訊號匯流排F0，而導體G1會連接訊號匯流排F1。 In one example of the embodiment shown in FIG. 2D, two of the microelectronic components 132a and 132b receive a 32-bit command-bit from the first command-address signal bus F0. The address signal information, and the other two of the microelectronic components 132c and 132d receive the 32-bit command-address information from the second command-address signal bus F1. In another example of the embodiment shown in FIG. 2D, two of the microelectronic components 132a and 132b receive a 16-bit command-bit from the first command-address signal bus F0. The address signal information, and the other two of the microelectronic components 132c and 132d receive the 16-bit command-address information from the second command-address signal bus F1. The connection between the signal bus bars F0 and F1 and the microelectronic components 132 is schematically shown in Fig. 2D, the conductor G0 is connected to the signal bus F0, and the conductor G1 is connected to the signal bus F1.

於圖2D中所示之實施例的變化例中，該第二類型微電子封裝110d可能具有兩個微電子元件132。該等微電子元件132中的第一微電子元件會連接該第一群第一接點165a而不連接該第二群第一接點165b，俾使得該第一微電子元件會連接第一命令-位址訊號匯流排F0而不連接該第二命令-位址訊號匯流排F1。該等微電子元件132中的第二微電子元件會連接該第二群第一接點165b而不連接該第一群第一接點165a，俾使得該第二微電子元件會被連接第二命令-位址訊號匯流排F1而不連接該第一命令-位址訊號匯流排F0。於此範例中，每一個微電子元件132會從第一訊號匯流排F0或第二訊號匯流排F1處接收32位位元的命令-位址訊號資訊。 In a variation of the embodiment shown in FIG. 2D, the second type of microelectronic package 110d may have two microelectronic elements 132. The first microelectronic component of the microelectronic components 132 is connected to the first group of first contacts 165a without connecting the second group of first contacts 165b, such that the first microelectronic component will connect to the first command. - Address signal bus F0 is not connected to the second command - address signal bus F1. The second microelectronic component of the microelectronic components 132 is connected to the second group of first contacts 165b without connecting the first group of first contacts 165a, such that the second microelectronic component is connected to the second The command-address signal bus F1 is not connected to the first command-address signal bus F0. In this example, each microelectronic component 132 receives command-bit address information of 32 bits from the first signal bus F0 or the second signal bus F1.

於圖2C中所示之電路板160c的特殊實施例中，第一群165a的第一接點中的每一個接點的訊號指派會以一理論軸174為基準對稱於第二群165b的對應第一接點的訊號指派。一具有以理論軸174為基準而對稱之訊號指派的第一類型微電子封裝(例如，微電子封裝110c)或是一具有以一理論軸為基準而對稱(舉例來說，位址資訊和無連接對稱性)之訊號指派的第二類型微電子封裝(例如，微電子封裝110d)會被鑲嵌至相同的電路板160c。 In a particular embodiment of the circuit board 160c shown in FIG. 2C, the signal assignment for each of the first contacts of the first group 165a is symmetric with respect to the second group 165b with respect to a theoretical axis 174. The signal assignment of the first contact. A first type of microelectronic package (e.g., microelectronic package 110c) having a signal assignment symmetrically based on a theoretical axis 174 or having a symmetry based on a theoretical axis (for example, address information and none) The signal-assigned second type of microelectronic package (eg, microelectronic package 110d) of the connection symmetry) is embedded to the same circuit board 160c.

本文中所示之電路板160c的實施例中的第一群165a的第一接點的訊號指派雖然以一理論軸174(圖2C)為基準對稱於第二群165b的對應第一接點的訊號指派；但是，情況未必是如此。本文中所述和主張的發明涵蓋的電路板160c亦可能讓第一群165a的第一接點的訊號指派沒有以一理論軸為基準對稱於第二群165b的對應第一接點的訊號指派。 The signal assignment of the first contact of the first group 165a in the embodiment of the circuit board 160c shown herein is symmetric with respect to the corresponding first contact of the second group 165b, with reference to a theoretical axis 174 (Fig. 2C). Signal assignment; however, this may not be the case. The circuit board 160c covered by the invention described and claimed herein may also allow the signal assignment of the first contact of the first group 165a to be symmetrical to the corresponding first contact of the second group 165b with reference to a theoretical axis. .

如能夠在圖2C中所見，電路板160c可能進一步包含每一個接點組168中的第二接點167，而且每一個接點組中的此等第二接點可能包 含第一群第二接點167a和第二群第二接點167b。該等第二接點167會被指派用以攜載位址與命令資訊以外的資訊。該電路板160c可能具有導體組171的至少一第二匯流排F2、F3，其會電性連接至少某些該等第二接點167。此第二匯流排F2、F3可能具有複數條訊號線，它們被配置成用以攜載位址與命令資訊以外的資訊。 As can be seen in Figure 2C, the circuit board 160c may further include a second contact 167 in each of the contact sets 168, and such second contacts in each of the contact sets may include The first group of second contacts 167a and the second group of second contacts 167b are included. The second contacts 167 are assigned to carry information other than the address and command information. The circuit board 160c may have at least one second bus bar F2, F3 of the conductor set 171, which is electrically connected to at least some of the second contacts 167. The second busbars F2, F3 may have a plurality of signal lines configured to carry information other than the address and command information.

於其中一範例中，該等四個微電子元件131中的每一者會電性連接該導體組171裡面不同的訊號線。舉例來說，微電子元件131a會從訊號匯流排F2的前半部導體處接收16位位元的資料訊號資訊，微電子元件131b會從訊號匯流排F2的後半部導體處接收16位位元的資料訊號資訊，微電子元件131c會從訊號匯流排F3的前半部導體處接收16位位元的資料訊號資訊，而微電子元件131d會從訊號匯流排F3的後半部導體處接收16位位元的資料訊號資訊。訊號匯流排F2與F3以及該等微電子元件之間的連接概略地顯示在圖2C與2D中，導體G2會連接訊號匯流排F2，而導體G3會連接訊號匯流排F3。 In one example, each of the four microelectronic components 131 is electrically connected to a different signal line within the conductor set 171. For example, the microelectronic component 131a receives the 16-bit data signal information from the first half conductor of the signal bus F2, and the microelectronic component 131b receives the 16-bit bit from the rear half conductor of the signal bus F2. For information signal information, the microelectronic component 131c receives the 16-bit data signal information from the first half conductor of the signal bus F3, and the microelectronic component 131d receives the 16-bit bit from the rear half conductor of the signal bus F3. Information signal information. The connections between the signal busbars F2 and F3 and the microelectronic components are shown schematically in Figures 2C and 2D. The conductor G2 is connected to the signal busbar F2 and the conductor G3 is connected to the signal busbar F3.

於其中一範例中，如能夠在圖2D中所見，該至少一接點組168中每一者的至少某些該等第二接點167會被設置在第一區167a與第二區167b中，相鄰於該個別接點組之預設周圍的至少第一與第二反向邊緣168a、168b，俾使得該個別接點組中的所有第一接點165會被設置在該個別接點組的該等第一區與第二區之間。 In one example, as can be seen in FIG. 2D, at least some of the second contacts 167 of each of the at least one set of contacts 168 are disposed in the first region 167a and the second region 167b, At least first and second reverse edges 168a, 168b adjacent to a preset circumference of the individual contact group, such that all of the first contacts 165 in the individual contact group are disposed in the individual contact group Between the first zone and the second zone.

另外，於此範例中，該至少一接點組168中每一者的至少某些該等第二接點167會被設置在第三區與第四區中，相鄰於該個別接點組之預設周圍的至少第三與第四反向邊緣，該等第三與第四邊緣延伸在該等 第一與第二邊緣168a、168b之間的方向中，俾使得該個別接點組中的所有第一接點165會被設置在該個別接點組的該等第三區與第四區之間。 In addition, in this example, at least some of the second contacts 167 of each of the at least one contact group 168 are disposed in the third region and the fourth region adjacent to the individual contact group. Presetting at least third and fourth reverse edges around, the third and fourth edges extending at the same In the direction between the first and second edges 168a, 168b, 俾 causes all of the first contacts 165 in the individual contact group to be disposed in the third and fourth regions of the individual contact group between.

圖2C與2D之任何實施例中所示的電路板160c在第一表面161處會有一第一接點組168並且在第二表面162處會有一第二接點組168，每一個接點組168中的該等第一接點165和第二接點167中的每一者會根據相同的預設排列方式來排列。圖2C與2D之任何實施例中所示的電路板160c在第一表面161處會有一第一接點組168並且在該第一表面處會有一第二接點組168，該第二接點組168在平行於該第一表面的方向中和該第一接點組隔開，每一個接點組168中的該等第一接點165和第二接點167中的每一者會根據相同的預設排列方式來排列。 The circuit board 160c shown in any of the embodiments of Figures 2C and 2D will have a first set of contacts 168 at the first surface 161 and a second set of contacts 168 at the second surface 162, each contact set Each of the first and second contacts 165 and 167 in 168 are arranged according to the same predetermined arrangement. The circuit board 160c shown in any of the embodiments of Figures 2C and 2D will have a first contact set 168 at the first surface 161 and a second contact set 168 at the first surface, the second contact The set 168 is spaced apart from the first set of contacts in a direction parallel to the first surface, each of the first and second contacts 165 and 167 of each of the contact sets 168 being Arrange the same preset arrangement.

於某些實施例中，具有一個以上接點組168的電路板160c會使用相同的導體通道170來攜載命令與位址資訊給該等接點組中的每一者。於其它實施例中，具有一個以上接點組168的電路板160c會使用不同的導體通道170，每一條導體通道被配置成用以攜載命令與位址資訊給該等接點組中不同的接點組。 In some embodiments, circuit board 160c having more than one set of contacts 168 will use the same conductor path 170 to carry command and address information to each of the set of contacts. In other embodiments, the circuit board 160c having more than one contact set 168 will use different conductor channels 170, each of which is configured to carry command and address information to different ones of the set of contacts. Contact group.

圖3A所示的係根據圖1中所示之發明的特殊範例的器件205a。如在圖3A中所見，器件205a包含一電路板260a，而該等接點265a被設置在一插槽266a中，該插槽266a被附接至該電路板的第一表面261並且電性連接導體組270。 The device 205a according to the specific example of the invention shown in Fig. 1 is shown in Fig. 3A. As seen in FIG. 3A, device 205a includes a circuit board 260a that is disposed in a socket 266a that is attached to the first surface 261 of the circuit board and that is electrically connected Conductor set 270.

被接合至電路板260a的微電子組件係一模組210a，其包含一模組卡220a以及被附接至此的一或更多個微電子元件230，每一個微電子元件皆有一面向該模組卡之第一表面221的表面。該微電子元件230具有 多個位址輸入235，被電性連接至模組卡220a的終端225a。於一特殊的實施例中，模組210a可能包含複數個微電子元件230，它們會以和參考圖2C或圖2D所示及所述相同的方式來連接導體組270的匯流排F0、F1、F2、以及F3，端視該等微電子元件究竟係第一類型或第二類型而定。 The microelectronic component bonded to the circuit board 260a is a module 210a comprising a module card 220a and one or more microelectronic components 230 attached thereto, each of the microelectronic components having a module facing the module The surface of the first surface 221 of the card. The microelectronic component 230 has A plurality of address inputs 235 are electrically coupled to terminal 225a of module card 220a. In a particular embodiment, module 210a may include a plurality of microelectronic components 230 that connect busbars F0, F1 of conductor set 270 in the same manner as described and described with respect to FIG. 2C or FIG. 2D. F2, and F3, depending on whether the microelectronic components are of the first type or the second type.

如能夠在圖3A中所見，該等終端225a為複數個平行曝露的邊緣終端，相鄰於模組卡220a之第一表面221和第二表面222中至少其中一者的一邊緣223，用以在該模組被插入插槽266a中時配接該插槽的接點265a。圖3A中所示的終端225a雖然曝露在模組卡220a之第一表面221和第二表面222兩者處；不過，終端225a亦可能僅曝露在第一表面處、僅曝露在第二表面處、或者曝露在該模組卡的該等第一表面和第二表面兩者處。 As can be seen in FIG. 3A, the terminals 225a are a plurality of parallel exposed edge terminations adjacent to an edge 223 of at least one of the first surface 221 and the second surface 222 of the module card 220a. The contact 265a of the slot is mated when the module is inserted into the slot 266a. The terminal 225a shown in FIG. 3A is exposed at both the first surface 221 and the second surface 222 of the module card 220a; however, the terminal 225a may only be exposed at the first surface and exposed only at the second surface. Or exposed at both the first surface and the second surface of the module card.

如能夠在圖3C中所見，模組卡220a可能有一列平行曝露的邊緣終端225a，相鄰於邊緣223；一第一列平行曝露的邊緣終端226a和一相鄰於該第一列終端的第二列平行曝露的終端226b；或者，一第一列平行曝露的邊緣終端227a以及複數列平行曝露的終端227b、227c(圖3C中雖然顯示兩個額外列227，不過，該模組卡可能包含兩個以上的額外列)，第二列終端227b相鄰於該第一列終端227a，且第三列終端227c相鄰於該第二列終端227b。模組卡220a可能有延伸自邊緣223的槽口228，此等槽口有助於卡接該模組卡和一被配置成用以接收該模組卡的多部件插槽266a。圖3C中所示的終端225、226、以及227雖然曝露在模組卡220a的第一表面221處；不過，終端225、226、以及227可能僅曝露在該第一表面處、僅曝露在第二表面222處、或者曝露在該模組卡的該等第一表面和第二表面兩者處。 As can be seen in Figure 3C, the module card 220a may have a series of parallel exposed edge terminations 225a adjacent to the edge 223; a first column of parallel exposed edge terminations 226a and a first adjacent to the first column of terminations Two columns of parallel exposed terminals 226b; or a first column of parallel exposed edge terminals 227a and a plurality of columns of parallel exposed terminals 227b, 227c ( although two additional columns 227 are shown in FIG. 3C, however, the module card may contain Two or more additional columns), the second column terminal 227b is adjacent to the first column terminal 227a, and the third column terminal 227c is adjacent to the second column terminal 227b. The module card 220a may have slots 228 extending from the edge 223 that facilitate snapping into the module card and a multi-component slot 266a configured to receive the module card. The terminals 225, 226, and 227 shown in FIG. 3C are exposed at the first surface 221 of the module card 220a; however, the terminals 225, 226, and 227 may only be exposed at the first surface, only exposed to the first The two surfaces 222 are either exposed to both the first and second surfaces of the module card.

圖3B所示的係根據在圖3A中所示之本發明的變化例的器件205b。如在圖3B中所見，器件205b包含一電路板260b，而該等接點265b被設置在一連接器266b中，該連接器266b被附接至該電路板的第一表面261並且電性連接導體組270。模組210b的終端225b為曝露在模組卡220b之第一表面221和第二表面222處的複數個平行終端，用以在該模組被附接至連接器266b時配接該連接器的接點265b。於一特殊的實施例中，模組210b可能包含複數個微電子元件230，它們會以和參考圖2C或圖2D所示及所述相同的方式來連接導體組270的匯流排F0、F1、F2、以及F3，端視該等微電子元件究竟係第一類型或第二類型而定。 Figure 3B shows a device 205b according to a variation of the invention shown in Figure 3A. As seen in Figure 3B, device 205b includes a circuit board 260b that is disposed in a connector 266b that is attached to the first surface 261 of the circuit board and that is electrically connected Conductor set 270. The terminal 225b of the module 210b is a plurality of parallel terminals exposed at the first surface 221 and the second surface 222 of the module card 220b for mating the connector when the module is attached to the connector 266b. Contact 265b. In a particular embodiment, module 210b may include a plurality of microelectronic components 230 that connect busbars F0, F1 of conductor set 270 in the same manner as described and described with respect to FIG. 2C or FIG. 2D. F2, and F3, depending on whether the microelectronic components are of the first type or the second type.

雷同於上述圖3A的實施例，模組卡220b可能有兩列平行曝露的邊緣終端225b，曝露在該模組卡的一表面處；四個平行的曝露終端列(舉例來說，一額外的平行終端列會被設置為相鄰於每一列終端225b)；或者，六或更多個平行的曝露終端列(舉例來說，二或更多個額外的平行終端列會被設置為相鄰於每一列終端225b)。同樣雷同於圖3A的實施例，模組卡220b可能有一或更多個槽口，被配置成用以幫助卡接該模組卡和一被配置成用以接收該模組卡的多部件插槽266b。 Similar to the embodiment of FIG. 3A above, the module card 220b may have two columns of parallel exposed edge terminals 225b exposed at a surface of the module card; four parallel exposed terminal columns (for example, an additional Parallel terminal columns will be placed adjacent to each column terminal 225b); or, six or more parallel exposed terminal columns (for example, two or more additional parallel terminal columns will be placed adjacent to each other) Each column of terminals 225b). Also similar to the embodiment of FIG. 3A, the module card 220b may have one or more slots configured to facilitate snapping the module card and a multi-part plug configured to receive the module card. Slot 266b.

於此實施例中，插槽266b、該等接點265b、以及模組210b的該等終端225b會被配置成當該模組被附接至該插槽時，模組卡220b的第二表面222會被配向成實質上平行於電路板260b的第一表面261。 In this embodiment, the slots 266b, the contacts 265b, and the terminals 225b of the module 210b are configured to be the second surface of the module card 220b when the module is attached to the slot. 222 will be oriented substantially parallel to first surface 261 of circuit board 260b.

圖3A和3B中的每一圖雖然僅顯示單一個模組210a或210b電性連接器件205a或250b；不過，於其它實施例中，複數個模組可能會電性連接該器件。於此等實施例中，所有該等模組210a或210b會被附接至電 路板260a或260b的第一表面261；所有該等模組會被附接至該電路板的第二表面262；或者，一或更多個模組會被附接至該電路板的第一表面，而一或更多個模組會被附接至該第二表面。 Each of the Figures 3A and 3B shows only a single module 210a or 210b electrically connected to the device 205a or 250b; however, in other embodiments, a plurality of modules may be electrically connected to the device. In these embodiments, all of the modules 210a or 210b will be attached to the battery. First surface 261 of the road plate 260a or 260b; all of the modules will be attached to the second surface 262 of the circuit board; or one or more modules will be attached to the first of the circuit board The surface, and one or more modules are attached to the second surface.

圖3A和3B雖然顯示一模組卡220a或220b被配向成實質上垂直於(圖3A)或平行於(圖3B)電路板260a或260b的第一表面261；不過，於其它實施例中，一雷同於模組210a或201b之模組的模組卡亦可能相對於該電路板的第一表面傾斜任何其它角度，例如，舉例來說，15°、30°、45°、60°、或是75°。 3A and 3B show that a module card 220a or 220b is oriented substantially perpendicular (Fig. 3A) or parallel to the first surface 261 of the circuit board 260a or 260b (Fig. 3B); however, in other embodiments, A module card that is identical to the module of module 210a or 201b may also be tilted at any other angle relative to the first surface of the board, such as, for example, 15°, 30°, 45°, 60°, or It is 75°.

圖3A和3B雖然顯示模組卡220a、220b透過一插槽266a、266b被電性連接至一電路板260a或260b；不過，亦可以使用其它連接配置。舉例來說，本發明涵蓋利用一帶狀連接器將一電路板電性連接至模組卡，該帶狀連接器延伸在模組卡的終端和電路板的接點之間。 3A and 3B, the display module cards 220a, 220b are electrically connected to a circuit board 260a or 260b through a slot 266a, 266b; however, other connection configurations may be used. For example, the present invention contemplates electrically connecting a circuit board to a module card using a ribbon connector that extends between the terminals of the module card and the contacts of the circuit board.

圖4A所示的係根據圖1中所示之本發明的另一特殊實施例的器件305。如在圖4A中所見，器件305包含一電路板360，而接點365為一第二微電子組件340的上終端，該等接點365曝露在該第二微電子組件的第一表面347處。第二微電子組件340被附接至該電路板的第一表面361並且電性連接導體組370。第二微電子組件340的下終端345會電性連接曝露在該電路板360的第一表面361處的對應接點375。 Figure 4A shows a device 305 according to another particular embodiment of the invention shown in Figure 1. As seen in FIG. 4A, device 305 includes a circuit board 360, and contact 365 is the upper terminal of a second microelectronic assembly 340 that is exposed at first surface 347 of the second microelectronic assembly. . A second microelectronic assembly 340 is attached to the first surface 361 of the circuit board and electrically coupled to the conductor set 370. The lower terminal 345 of the second microelectronic assembly 340 is electrically coupled to a corresponding contact 375 that is exposed at the first surface 361 of the circuit board 360.

被接合至該電路板360的微電子組件的形式為一第一微電子組件310。在圖4A中所示的範例中，微電子組件310係一其中具有一或更多個微電子元件330的微電子封裝，它們具有一表面面向一封裝基板320的第一表面321。於一特殊的實施例中，該第一微電子組件310可能包含複 數個微電子元件330，它們會以和參考圖2C或圖2D所示及所述相同的方式來連接導體組370的匯流排F0、F1、F2、以及F3，端視該等微電子元件究竟係第一類型或第二類型而定。 The microelectronic assembly bonded to the circuit board 360 is in the form of a first microelectronic assembly 310. In the example shown in FIG. 4A, microelectronic assembly 310 is a microelectronic package having one or more microelectronic components 330 therein having a first surface 321 that faces a package substrate 320. In a particular embodiment, the first microelectronic component 310 may comprise a complex a plurality of microelectronic components 330 that connect the busbars F0, F1, F2, and F3 of the conductor set 370 in the same manner as described and described with respect to FIG. 2C or FIG. 2D, looking at the microelectronic components. Depending on the first type or the second type.

於一特殊的範例中，微電子組件310可能包含複數個堆疊的微電子元件330，它們會藉由導體結構(例如，直通矽穿孔(Through-Silicon Via，TSV))來電性互連。該微電子元件330有多個位址輸入335，它們會被電性連接至曝露在和該第一表面321反向之基板320的第二表面322處的終端325。 In a particular example, microelectronic assembly 310 may include a plurality of stacked microelectronic components 330 that are electrically interconnected by a conductor structure (eg, Through-Silicon Via (TSV)). The microelectronic component 330 has a plurality of address inputs 335 that are electrically coupled to terminals 325 that are exposed at a second surface 322 of the substrate 320 that is opposite the first surface 321 .

第二微電子組件340包含一其中具有主動式裝置的微電子元件341，而且該第二微電子組件的上終端365會電性連接該電路板之的導體組370，延伸穿過該第二微電子組件。 The second microelectronic component 340 includes a microelectronic component 341 having an active device therein, and the upper terminal 365 of the second microelectronic component is electrically connected to the conductor set 370 of the circuit board and extends through the second micro Electronic components.

在圖4A的實施例中，該第一微電子組件(或微電子封裝)310的該等微電子元件330可能具有記憶體儲存陣列功能，而該第二微電子組件(或微電子封裝)340的微電子元件341可能具有微處理器功能。 In the embodiment of FIG. 4A, the microelectronic components 330 of the first microelectronic component (or microelectronic package) 310 may have a memory storage array function, and the second microelectronic component (or microelectronic package) 340 The microelectronic component 341 may have microprocessor functionality.

於一示範性實施例中，該第一微電子組件310的微電子元件330可能會藉由僅延伸在該等第一微電子組件和第二微電子組件裡面而沒有延伸在電路板360裡面的電性連接線直接被電性連接至該第二微電子組件340的微電子元件341。如本文中的用法，當延伸在一第一微電子組件的一第一微電子元件和一第二微電子組件的一第二微電子元件之間的電性連接線僅延伸在該等第一微電子組件和第二微電子組件之間而沒有延伸在該等第一微電子組件和第二微電子組件外部的某個結構(舉例來說，一電路板)裡面時，該等第一微電子元件和第二微電子元件彼此會「直接」連接。 In an exemplary embodiment, the microelectronic component 330 of the first microelectronic component 310 may not extend inside the circuit board 360 by extending only within the first microelectronic component and the second microelectronic component. The electrical connection line is electrically connected directly to the microelectronic element 341 of the second microelectronic assembly 340. As used herein, an electrical connection line extending between a first microelectronic component of a first microelectronic component and a second microelectronic component of a second microelectronic component extends only in the first The first micro between the microelectronic component and the second microelectronic component without extending within a structure (eg, a circuit board) external to the first microelectronic component and the second microelectronic component The electronic component and the second microelectronic component are "directly" connected to each other.

於其中一範例中，第一微電子組件310的微電子元件330和第二微電子組件340的微電子元件341之間的電性連接線可能包含延伸在一垂直於該第二微電子組件之第一表面347(該第二微電子組件的該等上終端(接點365)曝露在該表面處)的方向中的互連元件，該等互連元件會被配置成用於進行封裝上封裝堆疊。 In one example, the electrical connection between the microelectronic component 330 of the first microelectronic component 310 and the microelectronic component 341 of the second microelectronic component 340 may comprise extending perpendicular to the second microelectronic component. Interconnecting elements in the direction of the first surface 347 (the upper terminals of the second microelectronic assembly (contact 365) are exposed at the surface), the interconnecting elements being configured for encapsulation on the package Stacking.

於其中一實施例中，第一微電子組件310的微電子元件330和第二微電子組件340的微電子元件341之間的電性連接線可能包含一焊接穿孔陣列，從該第二微電子組件的終端365處延伸至曝露在該第二微電子組件的一基板的表面343處的接點。 In one embodiment, the electrical connection between the microelectronic component 330 of the first microelectronic component 310 and the microelectronic component 341 of the second microelectronic component 340 may comprise an array of soldered vias from the second microelectronic The terminal 365 of the assembly extends to a junction exposed at a surface 343 of a substrate of the second microelectronic assembly.

圖4B所示的係根據圖1中所示之本發明的另一特殊範例的器件305b，其係圖4A的器件305的變化例。如在圖4B中所見，器件305b包含圖4A中所示之相同的第二微電子組件340；但是，其並沒有包含電路板360。一導體組370會受到該第二微電子組件340的基板342的支撐及/或位於該第二微電子組件340的基板342裡面。該導體組370會電性連接該第二微電子組件340之第一表面347處的接點365。器件305b可能會經由曝露在該第二微電子組件340之下表面344處的終端345電性連接一電路板，例如，電路板360。 4B is a device 305b according to another specific example of the present invention shown in FIG. 1, which is a variation of the device 305 of FIG. 4A. As seen in FIG. 4B, device 305b includes the same second microelectronic assembly 340 shown in FIG. 4A; however, it does not include circuit board 360. A conductor set 370 is supported by the substrate 342 of the second microelectronic assembly 340 and/or within the substrate 342 of the second microelectronic assembly 340. The conductor set 370 is electrically connected to the contact 365 at the first surface 347 of the second microelectronic assembly 340. Device 305b may be electrically coupled to a circuit board, such as circuit board 360, via terminal 345 exposed at a lower surface 344 of the second microelectronic assembly 340.

圖4C所示的係根據圖1中所示之本發明的另一特殊範例的器件305c，其係圖4B的器件305b的變化例。如在圖4C中所見，器件305c包含一第二微電子組件340c，雷同於圖4B中所示的第二微電子組件340；但是，其並沒有包含基板342。一導體組370c會受到該第二微電子組件340c的一模造區348的支撐及/或位於該第二微電子組件340c的模造區348裡 面。該導體組370c會利用曝露在該第二微電子組件340c之下表面344處的終端345來電性連接該微電子元件341的元件接點349。 4C is a device 305c according to another particular example of the present invention shown in FIG. 1, which is a variation of device 305b of FIG. 4B. As seen in FIG. 4C, device 305c includes a second microelectronic component 340c that is identical to second microelectronic component 340 shown in FIG. 4B; however, it does not include substrate 342. A conductor set 370c is supported by a molding region 348 of the second microelectronic assembly 340c and/or is located in the molding region 348 of the second microelectronic assembly 340c. surface. The conductor set 370c electrically connects the component contacts 349 of the microelectronic component 341 with a terminal 345 exposed at a lower surface 344 of the second microelectronic component 340c.

圖5A所示的係根據圖1中所示之本發明的又一特殊範例的器件405。如在圖5A中所見，器件405包含一電路板460，而接點465為一第二微電子組件440的上終端，該等接點465曝露在該第二微電子組件的第一表面447處，或者，曝露在該第二微電子組件的第一表面處的一介電層(圖中並未顯示)處。第二微電子組件440被附接至該電路板的第一表面461並且電性連接導體組470。曝露在第二微電子組件440的第二表面444處的下終端445會電性連接曝露在該電路板460的第一表面461處的對應接點475。 Figure 5A shows a device 405 according to yet another particular example of the invention shown in Figure 1. As seen in FIG. 5A, device 405 includes a circuit board 460, and contact 465 is the upper terminal of a second microelectronic assembly 440 that is exposed at first surface 447 of the second microelectronic assembly. Or, exposed to a dielectric layer (not shown) at the first surface of the second microelectronic component. A second microelectronic assembly 440 is attached to the first surface 461 of the circuit board and electrically coupled to the conductor set 470. The lower terminal 445 exposed at the second surface 444 of the second microelectronic assembly 440 is electrically connected to a corresponding contact 475 exposed at the first surface 461 of the circuit board 460.

被接合至該電路板460的微電子組件的形式為一第一微電子組件410。在圖5A中所示的範例中，微電子組件410係一其中具有一或更多個微電子元件430的微電子封裝，它們具有一表面面向一封裝基板420的第一表面421。該微電子元件430具有多個位址輸入435，它們會被電性連接至曝露在和該第一表面421反向之基板420的第二表面422處的終端425。於一特殊的實施例中，該第一微電子組件410可能包含複數個微電子元件430，它們會以和參考圖2C或圖2D所示及所述相同的方式來連接導體組470的匯流排F0、F1、F2、以及F3，端視該等微電子元件究竟係第一類型或第二類型而定。 The microelectronic assembly bonded to the circuit board 460 is in the form of a first microelectronic assembly 410. In the example shown in FIG. 5A, microelectronic component 410 is a microelectronic package having one or more microelectronic components 430 therein having a first surface 421 with a surface facing a package substrate 420. The microelectronic element 430 has a plurality of address inputs 435 that are electrically coupled to a terminal 425 that is exposed at a second surface 422 of the substrate 420 that is opposite the first surface 421. In a particular embodiment, the first microelectronic component 410 may include a plurality of microelectronic components 430 that connect the busbars of the conductor set 470 in the same manner as described and described with respect to FIG. 2C or FIG. 2D. F0, F1, F2, and F3 depend on whether the microelectronic components are of the first type or the second type.

在圖5A的實施例中，第一微電子組件410可能包含一第一微電子元件430以及多個額外的微電子元件，每一個微電子元件中皆有主動式裝置。於其中一範例中，該第一微電子組件410的該等終端425會藉由延伸貫穿該第一微電子元件430的直通矽穿孔來電性連接該等額外的微電 子元件。 In the embodiment of FIG. 5A, the first microelectronic component 410 may include a first microelectronic component 430 and a plurality of additional microelectronic components, each of which has an active device. In one example, the terminals 425 of the first microelectronic component 410 are electrically connected to the additional microelectronics by a through-via via extending through the first microelectronic component 430. Child component.

該第二微電子組件440可能包含一或更多個微電子元件，每一個微電子元件中皆有主動式裝置，而且該第二微電子組件的上終端465會藉由至少部分延伸在該第二微電子封裝裡面的電性連接線來電性連接該電路板的導體組470。該等接點(或是上終端)465會曝露在一疊置在該第二微電子組件440的第一表面447上方的介電層處。於一示範性實施例中，該第二微電子組件440的該等微電子元件中的一或更多者會有一邏輯功能。 The second microelectronic component 440 may include one or more microelectronic components, each of which has an active device, and the upper terminal 465 of the second microelectronic component is at least partially extended in the first An electrical connection line within the two microelectronic package electrically connects the conductor set 470 of the circuit board. The contacts (or upper terminals) 465 are exposed at a dielectric layer overlying the first surface 447 of the second microelectronic assembly 440. In an exemplary embodiment, one or more of the microelectronic components of the second microelectronic component 440 have a logic function.

於一特殊的範例中，該第二微電子組件440的上終端465和該導體組470之間的此等電性連接線可能包含延伸貫穿該等一或更多個微電子元件的直通矽穿孔446。此等電性連接線可能還包含延伸在該等下終端445和曝露在電路板460之第一表面461處的對應接點475之間的接合單元。 In a particular example, the electrical connection between the upper terminal 465 of the second microelectronic assembly 440 and the conductor set 470 may include through-through perforations extending through the one or more microelectronic components. 446. The electrical connections may also include engagement elements extending between the lower terminals 445 and corresponding contacts 475 exposed at the first surface 461 of the circuit board 460.

於其中一範例中，該第二微電子組件440可能包含一第一微電子元件以及至少一第二微電子元件，每一個微電子元件中皆有主動式裝置，該等第一微電子元件及第二微電子元件係以堆疊配置來排列。於一特殊的實施例中，該第二微電子組件440的該等上終端465會藉由延伸貫穿該第二微電子組件之至少一第二微電子元件的直通矽穿孔446來電性連接該電路板460的導體組470。圖5A中所示的每一個該等上終端465雖然對齊(在水平方向中)並且被連接至該等直通矽穿孔446；不過，該等上終端未必要對齊該等直通矽穿孔，所有該等上終端亦未必要連接此等直通矽穿孔。 In one example, the second microelectronic component 440 may include a first microelectronic component and at least a second microelectronic component. Each of the microelectronic components has an active device, and the first microelectronic component and The second microelectronic components are arranged in a stacked configuration. In a particular embodiment, the upper terminals 465 of the second microelectronic component 440 are electrically connected to the circuit by through-through turns 446 extending through at least one second microelectronic component of the second microelectronic component. Conductor set 470 of plate 460. Each of the upper terminals 465 shown in Figure 5A is aligned (in the horizontal direction) and is connected to the through-holes 446; however, the upper terminals are not necessarily aligned with the through-holes, all of which are It is not necessary for the upper terminal to connect to these through-holes.

圖中所示的該等第一微電子組件410和第二微電子組件440雖然係經封裝的結構；不過，情況未必係如此。於其中一實施例中，第一微電子組件410可能係一具有記憶體儲存陣列功能的微電子元件，而第二 微電子組件440可能係一具有邏輯功能的微電子元件。圖中所示的第一微電子組件410在終端425和接點465之間雖然具有覆晶連接；不過，情況未必係如此。於其中一範例中，第一微電子組件410可能係一具有記憶體儲存陣列功能的微電子元件，被配向成使其載有接點的表面背向第二微電子組件440的上表面447，而且該第一微電子組件410的終端425(其可能為元件接點)會被線焊至該第二微電子組件之上表面處的接點465。 The first microelectronic component 410 and the second microelectronic component 440 shown in the figures are encapsulated structures; however, this need not be the case. In one embodiment, the first microelectronic component 410 may be a microelectronic component having a memory storage array function, and the second Microelectronic component 440 may be a microelectronic component having a logic function. The first microelectronic assembly 410 shown in the figures has a flip chip connection between the terminal 425 and the contacts 465; however, this need not be the case. In one example, the first microelectronic component 410 may be a microelectronic component having a memory storage array function that is oriented such that its surface carrying the contacts faces away from the upper surface 447 of the second microelectronic component 440. Moreover, the terminal 425 (which may be a component contact) of the first microelectronic component 410 is wire bonded to the contacts 465 at the upper surface of the second microelectronic component.

於一特殊的範例中，第二微電子組件440之上表面447處的接點465能夠共支撐於其中具有DDR3或DDR4記憶體元件的微電子組件410。 In a particular example, the contacts 465 at the upper surface 447 of the second microelectronic assembly 440 can be co-supported by the microelectronic assembly 410 having DDR3 or DDR4 memory elements therein.

圖5B所示的係根據圖1中所示之本發明的另一特殊範例的器件405b，其係圖5A的器件405的變化例。如在圖5B中所見，器件405b包含圖5A中所示之相同的第二微電子組件440；但是，其並沒有包含電路板460。 Figure 5B shows a device 405b according to another particular example of the invention shown in Figure 1, which is a variation of device 405 of Figure 5A. As seen in FIG. 5B, device 405b includes the same second microelectronic assembly 440 shown in FIG. 5A; however, it does not include circuit board 460.

一導體組470b會受到該第二微電子組件440的微電子元件的支撐及/或位於該第二微電子組件440的微電子元件裡面。舉例來說，該導體組470b可能包含TSV及/或被連接至TSV的再分配線路。該導體組470b會電性連接該第二微電子組件440之第一表面447處的接點465。器件405b可能會經由曝露在該第二微電子組件440之下表面444處的終端445電性連接一電路板，例如，電路板460。在圖5B的實施例中，微電子組件440中的該等微電子元件中的一或更多者可能係一用於導體組470b的支撐結構，或者，一疊置在該微電子組件中該等微電子元件的其中一者上方的介電層可能係一用於該導體組的支撐結構。 A conductor set 470b can be supported by the microelectronic components of the second microelectronic component 440 and/or within the microelectronic components of the second microelectronic component 440. For example, the conductor set 470b may include TSVs and/or redistribution lines that are connected to the TSVs. The conductor set 470b is electrically connected to the contacts 465 at the first surface 447 of the second microelectronic assembly 440. Device 405b may be electrically coupled to a circuit board, such as circuit board 460, via terminal 445 exposed at a lower surface 444 of the second microelectronic assembly 440. In the embodiment of FIG. 5B, one or more of the microelectronic components in the microelectronic assembly 440 may be a support structure for the conductor set 470b, or a stack of the microelectronic components. The dielectric layer over one of the microelectronic components may be a support structure for the conductor set.

上面已圖解和討論的每一個範例皆能夠利用在其多面上有多個接點的微電子元件來施行，該等多面面向該微電子組件之第一表面之面向的相同方向，或者，可能背向該微電子組件之第一表面之面向的方向。因此，於一特殊的範例中，該等微電子組件可能係如共同擁有的美國專利申請案第13/439,317號的圖13至20之任何圖式的範例中所示和所述，本文以引用的方式將其揭示內容併入。 Each of the examples illustrated and discussed above can be implemented using microelectronic elements having a plurality of contacts on their faces that face the same direction of the face of the first surface of the microelectronic assembly, or The direction facing the first surface of the microelectronic assembly. Thus, in a particular example, such microelectronic components may be as shown and described in the examples of any of Figures 13 to 20 of commonly-owned U.S. Patent Application Serial No. 13/439,317, the disclosure of which is incorporated herein by reference. The way to incorporate its disclosure.

上面所述的範例雖然引用疊置在一基板上方的微電子元件；不過，該基板可能會在適當的情況被省略，因為當該等微電子元件一起被排列在一模造單元(舉例來說，晶圓級單元)裡面時，其中的一介電層可以被形成在該等微電子元件的接點承載面之上或上方，用以支撐其上的線路和電性互連線。 The examples described above refer to microelectronic components stacked above a substrate; however, the substrate may be omitted where appropriate, as the microelectronic components are arranged together in a molding unit (for example, In the wafer level unit, a dielectric layer may be formed on or over the contact carrying surface of the microelectronic components to support the lines and electrical interconnections thereon.

於其它範例中，其中具有多個堆疊微電子元件的微電子組件可能係如參考共同擁有的美國專利申請案第13/439,317號的圖21至25所示及/或所述的單一或多重堆疊施行方式，本文以引用的方式將其揭示內容併入。 In other examples, a microelectronic component having a plurality of stacked microelectronic components therein may be a single or multiple stack as shown and/or described in Figures 21 through 25 of commonly owned U.S. Patent Application Serial No. 13/439,317. In the manner of implementation, the disclosure is incorporated herein by reference.

又，於其它範例中，其中具有四個微電子元件的微電子組件可能係如共同擁有的美國專利申請案第13/337,565號和第13/337,575號的圖9A至B、9C、9D、9F、9G、9H、12B、12C、或是12D所示及所述，或者，可能係如共同擁有的美國專利申請案第13/354,747號的圖7A至B、8、11A、11B、11C、11D、12、13B、14B、或是14C所示及所述，本文以引用的方式將其揭示內容併入。 Moreover, in other examples, the microelectronic assembly having four microelectronic components therein may be as shown in Figures 9A to B, 9C, 9D, 9F of commonly owned U.S. Patent Application Serial Nos. 13/337,565 and 13/337,575. And, as shown or described in the context of U.S. Patent Application Serial No. 13/354,747, commonly owned U.S. Patent Application Serial No. 13/354,747, which is incorporated herein by reference. , 12, 13B, 14B, or 14C, as shown and described herein, the disclosure of which is incorporated herein by reference.

上面參考圖1至5所述的微電子封裝和微電子組件能夠用於 建構各式各樣電子系統，例如，圖6中所示的系統500。舉例來說，根據本發明進一步實施例的系統500包含複數個模組或器件506，例如，上面配合其它電子器件508、510、以及511所述的微電子封裝及/或微電子組件。 The microelectronic package and microelectronic assembly described above with reference to Figures 1 through 5 can be used A wide variety of electronic systems are constructed, such as system 500 shown in FIG. For example, system 500 in accordance with a further embodiment of the present invention includes a plurality of modules or devices 506, such as microelectronic packages and/or microelectronic assemblies as described above in conjunction with other electronic devices 508, 510, and 511.

於圖中所示的示範性系統500中，該系統可能包含一電路板、主機線路板、或是直豎板502，例如，撓性印刷電路線路板，而且該電路板可能包含眾多導體504(圖6中僅描繪其中一個)，用以彼此互連該等模組或器件506、508、510。此電路板502會傳輸訊號給系統500中所包含的每一個該等微電子封裝及/或微電子組件以及從系統500中所包含的每一個該等微電子封裝及/或微電子組件處傳輸訊號。然而，這僅為示範性；用於達成該等模組或器件506之間的電性連接的任何合宜結構皆可被使用。 In the exemplary system 500 shown in the figures, the system may include a circuit board, a host circuit board, or a straight riser board 502, such as a flexible printed circuit board, and the board may include a plurality of conductors 504 ( Only one of them is depicted in FIG. 6 to interconnect the modules or devices 506, 508, 510 with each other. The circuit board 502 transmits signals to and from each of the microelectronic packages and/or microelectronic components included in the system 500. Signal. However, this is merely exemplary; any suitable structure for achieving electrical connections between the modules or devices 506 can be used.

於一特殊的實施例中，系統500可能還包含一處理器，例如，半導體晶片508，俾使得每一個模組或器件506能夠被配置成用以在一時脈週期中平行傳輸數個(N個)資料位元，而且該處理器會被配置成用以在一時脈週期中平行傳輸數個(M個)資料位元，M大於或等於N。 In a particular embodiment, system 500 may also include a processor, such as semiconductor wafer 508, such that each module or device 506 can be configured to transmit a plurality of (N in parallel) in a clock cycle. Data bits, and the processor is configured to transmit a plurality of (M) data bits in parallel in a clock cycle, M being greater than or equal to N.

在圖6中所示的範例中，器件508係一半導體晶片，而器件510係一顯示螢幕；但是，任何其它器件皆能夠使用在系統500之中。當然，為清楚起見，圖6中雖然僅描繪兩個額外器件508和511；不過，系統500亦可能包含任何數量的此等器件。 In the example shown in FIG. 6, device 508 is a semiconductor wafer and device 510 is a display screen; however, any other device can be used in system 500. Of course, for the sake of clarity, only two additional devices 508 and 511 are depicted in FIG. 6; however, system 500 may also include any number of such devices.

模組或器件506以及器件508和511能夠被鑲嵌在一共同殼體501之中，圖中以虛線來概略描繪，並且能夠在必要時彼此電性互連，用以形成所希的電路。殼體501被描繪成可以使用在蜂巢式電話或個人數位助理中之類型的可攜式殼體，而螢幕510則會曝露在該殼體的表面處。 於一結構506包含一光敏元件(例如，成像晶片)的實施例中，一透鏡511或是其它光學裝置會被提供用以將光送往該結構。再次地，圖6中所示之簡化系統僅為示範性；利用上面討論的結構亦能夠達成其它系統，包含一般視為固定結構的系統在內，例如，桌上型電腦、路由器、以及類似物。 The module or device 506 and the devices 508 and 511 can be embedded in a common housing 501, depicted schematically in dashed lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing 501 is depicted as a portable housing of the type that can be used in a cellular telephone or a personal digital assistant, while the screen 510 is exposed at the surface of the housing. In embodiments where a structure 506 includes a photosensitive element (e.g., an imaging wafer), a lens 511 or other optical device would be provided to deliver light to the structure. Again, the simplified system shown in Figure 6 is merely exemplary; other systems can be implemented using the structure discussed above, including systems that are generally considered to be fixed structures, such as desktop computers, routers, and the like. .

上面參考圖1至5所述的微電子封裝和微電子組件亦能夠用於建構諸如圖7中所示之系統600的電子系統。舉例來說，根據本發明進一步實施例的系統600和圖6中所示的系統500相同；不過，器件506已由複數個器件606取代。 The microelectronic package and microelectronic assembly described above with respect to Figures 1 through 5 can also be used to construct an electronic system such as system 600 shown in Figure 7. For example, system 600 in accordance with a further embodiment of the present invention is identical to system 500 shown in FIG. 6; however, device 506 has been replaced by a plurality of devices 606.

該等器件606中的每一者可能係或者可能包含上面參考圖1至5所述的微電子封裝或微電子組件中的一或更多者。於一特殊的範例中，該等器件606中的一或更多者可能係圖1中所示之器件5的變化例，其中，支撐結構60包含曝露的邊緣接點，而且每一個器件5的支撐結構皆會適合插入一插槽605之中。 Each of the devices 606 may or may include one or more of the microelectronic packages or microelectronic assemblies described above with respect to Figures 1 through 5. In a particular example, one or more of the devices 606 may be a variation of the device 5 shown in FIG. 1, wherein the support structure 60 includes exposed edge contacts and each device 5 The support structure will fit into a slot 605.

每一個插槽605可能在該插槽的一或兩側處包含複數個接點607，俾使得每一個插槽605皆會適合用於配接一對應器件606(例如，上面所述之器件5的變化例)之對應的曝露邊緣接點。於圖中所示的示範性系統600中，該系統可能包含一第二電路板602或是電路線路板，例如，撓性印刷電路線路板，而且該第二電路板可能包含眾多導體604(圖7中僅描繪其中一個)，用以彼此互連該等器件606。 Each of the slots 605 may include a plurality of contacts 607 at one or both sides of the slot such that each slot 605 is adapted to be mated with a corresponding device 606 (eg, device 5 described above) The corresponding exposed edge contact of the variation). In the exemplary system 600 shown in the figures, the system may include a second circuit board 602 or a circuit board, such as a flexible printed circuit board, and the second board may include a plurality of conductors 604 (Fig. Only one of them is depicted in Figure 7 to interconnect the devices 606 with one another.

於一特殊的範例中，一諸如系統600的模組可能包含複數個器件606，每一個器件606都係上面所述的器件5的變化例。每一個器件606會被鑲嵌至並且電性連接該第二電路板602，用以傳輸訊號至每一個器件 606以及從每一個器件606處傳輸訊號。系統600的該特定範例僅為示範性；用於達成該等器件606之間的電性連接的任何合宜結構皆可被使用。 In a particular example, a module such as system 600 may include a plurality of devices 606, each of which is a variation of device 5 described above. Each device 606 is embedded and electrically connected to the second circuit board 602 for transmitting signals to each device. 606 and transmitting signals from each of the devices 606. This particular example of system 600 is merely exemplary; any suitable structure for achieving an electrical connection between the devices 606 can be used.

本發明之上述實施例的各項特點能夠以上面明確說明以外的方式來組合，其並沒有脫離本發明的範疇或精神。本揭示內容希望涵蓋上面所述之本發明的實施例的所有此等組合和變化。 The features of the above-described embodiments of the present invention can be combined in other ways than those explicitly described above without departing from the scope or spirit of the invention. The disclosure is intended to cover all such combinations and modifications of the embodiments of the invention described above.

下面段落額外說明本發明的特點和實施例：一種微電子封裝家族，其包含：複數個微電子封裝，每一者皆具有用於連接一外部器件之對應接點的終端而且每一者皆包含一微電子元件，該微電子元件具有一具有給定數量儲存位置的記憶體儲存陣列，每一個微電子封裝的該等終端被配置成用以接收明確指定該等儲存位置中其中一者的對應命令和位址資訊，每一個微電子元件皆具有連接該個別微電子封裝之該等終端的多個輸入，其中，該家族中的一第一微電子封裝的微電子元件會被配置成以第一取樣率來取樣經由該第一封裝之該等終端與其耦合的第一命令和位址資訊，以及該家族中的一第二微電子封裝的微電子元件會被配置成以大於該第一取樣率的第二取樣率來取樣經由該第二封裝之該等終端與其耦合的第二命令和位址資訊，該第一封裝的該等終端被配置成用以連接至根據一第一預設排列方式排列的該外部器件的一組接點，用以接收該第一命令和位址資訊，而該第二封裝的該等終端被配置成用以連接至根據一第二預設排列方式排列的該外部器件的一組接點，用以接收該第二命令和位址資訊， 其中，根據該第二預設排列方式排列的接點組包含佔據和根據該第一預設排列方式排列的接點組相同位置的至少某些接點，根據該第二預設排列方式排列的接點組的數量少於根據該第一預設排列方式排列的接點組。 The following paragraphs additionally illustrate features and embodiments of the present invention: a family of microelectronic packages comprising: a plurality of microelectronic packages, each having a terminal for connecting a corresponding contact of an external device and each containing a microelectronic component having a memory storage array having a given number of storage locations, each of the terminals of the microelectronic package being configured to receive a correspondence specifying one of the storage locations Command and address information, each microelectronic component having a plurality of inputs to the terminals of the individual microelectronic package, wherein a microelectronic component of a first microelectronic package of the family is configured to a sampling rate to sample first command and address information coupled thereto via the terminals of the first package, and a microelectronic component of a second microelectronic package in the family is configured to be greater than the first sampling a second sampling rate of the rate to sample second command and address information coupled thereto via the terminals of the second package, the terminals of the first package being matched Forming a set of contacts for connecting to the external device arranged according to a first predetermined arrangement for receiving the first command and address information, and the terminals of the second package are configured to be used Connecting to a set of contacts of the external device arranged according to a second preset arrangement for receiving the second command and address information, The contact group arranged according to the second preset arrangement includes at least some contacts occupying the same position as the contact group arranged according to the first preset arrangement, and arranged according to the second preset arrangement. The number of contact groups is less than the set of contacts arranged according to the first predetermined arrangement.

因此，舉例來說，圖1中所示的微電子封裝10在任何前述實施例中可能係前面實施例中所述之任何類型封裝。舉例來說，第一類型微電子封裝110c(圖2C)可能包含一微電子元件131，其被配置成以第一取樣率來取樣經由此封裝之終端125與其耦合的第一命令和位址資訊。舉例來說，第二類型微電子封裝110d可能包含微電子元件132，其被配置成以大於該第一取樣率的第二取樣率來取樣經由該第二封裝之終端125與其耦合的第二命令和位址資訊。 Thus, for example, the microelectronic package 10 shown in FIG. 1 may be any type of package described in the previous embodiments in any of the foregoing embodiments. For example, the first type of microelectronic package 110c (FIG. 2C) may include a microelectronic component 131 configured to sample the first command and address information coupled thereto via the packaged terminal 125 at a first sampling rate. . For example, the second type of microelectronic package 110d may include a microelectronic element 132 configured to sample a second command coupled thereto via the second packaged terminal 125 at a second sampling rate greater than the first sampling rate. And address information.

如能夠在圖2C中所見，該第一封裝110c的該等終端125會被配置成用以連接至根據一第一預設排列方式排列的外部器件105c的一組接點165，用以接收該第一命令和位址資訊。如能夠在圖2D中所見，該第二封裝110d的該等終端125會被配置成用以連接至根據一第二預設排列方式排列的外部器件105d的一組接點165，用以接收該第二命令和位址資訊。 As can be seen in FIG. 2C, the terminals 125 of the first package 110c are configured to be connected to a set of contacts 165 of the external device 105c arranged according to a first predetermined arrangement for receiving the First command and address information. As can be seen in FIG. 2D, the terminals 125 of the second package 110d are configured to be connected to a set of contacts 165 of the external device 105d arranged according to a second predetermined arrangement for receiving the Second command and address information.

參考圖2C與2D，根據第二預設排列方式排列的接點165組168可能包含佔據和根據該第一預設排列方式排列的接點組相同位置的至少某些接點，根據該第二預設排列方式排列的接點165組168的數量可能少於根據該第一預設排列方式排列的接點組。 Referring to FIGS. 2C and 2D, the set of contacts 165 arranged according to the second predetermined arrangement may include at least some of the contacts occupying the same position as the set of contacts arranged according to the first predetermined arrangement, according to the second The number of sets 168 of contacts 165 arranged in a predetermined arrangement may be less than the set of contacts arranged according to the first predetermined arrangement.

下面有編號的段落提供本發明的實施例和本文中的特點的進一步示範性說明。 The following numbered paragraphs provide further exemplary illustrations of embodiments of the invention and features herein.

1.一種模組，用以連接至少一微電子組件，每一個微電子組件皆包含一 組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊，該模組包括：一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊；至少一組共支撐接點，它們會被耦合至該組導體，每一組共支撐接點皆會曝露在該第一表面或是該第二表面處，每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電子組件的該終端組；以及複數個模組接點，它們會被耦合至該組導體，該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊，該等模組接點會被配置成用以連接位於該模組外部的一器件，其中，該至少一組共支撐接點中的每一者皆包含多個第一接點，它們具有(a)根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成以第一取樣率來取樣經由該等第一接點(該等第一接點具有第一數量的接點)與其耦合的命令與位址資訊，以及(b)根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成以大於第一取樣率的第二取樣率來取樣經由該等第一接點中的一子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該子集包含佔據和被指派至該第一預設排 列方式之第一接點相同位置的某些第一接點，該第二數量少於該第一數量。 A module for connecting at least one microelectronic component, each microelectronic component comprising a group terminal and a microelectronic component having a memory storage array having a given number of storage locations, the microelectronic component of each microelectronic component having a plurality of inputs that are connected to the terminals for receiving the explicit designation And command and address information of one of the storage locations, the module comprising: a circuit board having first and second opposite surfaces and carrying a set of conductors configured to carry The command and address information; at least one set of co-supporting contacts that are coupled to the set of conductors, each set of common support contacts being exposed to the first surface or the second surface, each set The common support contacts are configured to be coupled to the terminal set of a single microelectronic component of the at least one microelectronic component; and a plurality of modular contacts that are coupled to the set of conductors, the modules The contacts are configured to carry information transmitted to and from the at least one set of co-supporting contacts, the module contacts being configured to connect a device external to the module, wherein The at least one group Each of the splicing points includes a plurality of first contacts having (a) address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein The microelectronic component is configured to sample command and address information coupled thereto via the first contacts (the first contacts have a first number of contacts) at a first sampling rate, and (b) Addressing and command information assignment according to a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic component is configured to be at a second sampling rate greater than the first sampling rate Sampling command and address information coupled thereto via a subset of the first contacts (which includes a second number of first contacts), the subset including occupancy and assignment to the first predetermined row Some first contacts of the same position of the first contact of the column mode, the second number is less than the first number.

2.根據第1段的模組，其中，根據該第二預設排列方式排列的第一接點的子集中的所有接點會佔據和被指派至該第一預設排列方式的第一接點相同的位置。 2. The module of paragraph 1, wherein all contacts in the subset of first contacts arranged according to the second predetermined arrangement occupy and are assigned to the first connection of the first preset arrangement Click the same location.

3.根據第1段的模組，其中，該第二取樣率係該第一取樣率的整數倍。 3. The module of paragraph 1, wherein the second sampling rate is an integer multiple of the first sampling rate.

4.根據第1段的模組，其中，每一組共支撐接點中的該等第一接點包含被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊的接點。 4. The module of paragraph 1, wherein the first of the plurality of co-supporting contacts comprises a bit assigned to carry a position that can be used to explicitly specify a location within the memory storage array The contact point of the address information.

5.根據第1段的模組，進一步包括一被耦合至該組導體的裝置，該裝置可操作用以將該命令與位址資訊驅動至該等第一接點。 5. The module of paragraph 1, further comprising a device coupled to the set of conductors, the device being operative to drive the command and address information to the first contacts.

6.根據第5段的模組，其中，該裝置會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過該第一排列方式來連接該模組和第一類型微電子組件以及透過該第二排列方式來連接該模組和第二類型微電子組件。 6. The module of paragraph 5, wherein the apparatus is configured to operate in each of the first mode and the second mode to connect the module and the first arrangement respectively The first type of microelectronic assembly and the second arrangement are used to connect the module and the second type of microelectronic assembly.

7.根據第6段的模組，進一步包括該第一類型微電子組件，其中，該至少一組共支撐接點中的一組會電性連接該第一類型微電子組件的該等終端。 7. The module of clause 6, further comprising the first type of microelectronic assembly, wherein one of the at least one set of co-support contacts is electrically coupled to the terminals of the first type of microelectronic assembly.

8.根據第6段的模組，進一步包括該第二類型微電子組件，該至少一組共支撐接點中的一組會電性連接該第二類型微電子組件的該等終端。 8. The module of clause 6, further comprising the second type of microelectronic assembly, one of the at least one set of co-supporting contacts electrically connecting the terminals of the second type of microelectronic assembly.

9.根據第1段的模組，其中，該微電子組件係一微電子封裝，且其中，該等終端係表面鑲嵌終端並且會曝露在該微電子封裝的一表面處。 9. The module of clause 1, wherein the microelectronic component is a microelectronic package, and wherein the terminals are surface mounted with a terminal and are exposed at a surface of the microelectronic package.

10.根據第1段的模組，其中，該電路板係一模組卡，且其中，該等模 組接點係該等第一表面和第二表面中至少其中一者處的複數個平行曝露接點，用以在該模組被插入一第二電路板的插槽中時配接該插槽的接點。 10. The module of paragraph 1, wherein the circuit board is a module card, and wherein the modules The set of contacts is a plurality of parallel exposed contacts at at least one of the first surface and the second surface for mating the socket when the module is inserted into a slot of a second circuit board The junction.

11.根據第1段的模組，其中，該電路板係一模組卡，且其中，該等模組接點係該等第一表面和第二表面中其中一者處的複數個接點，用以在該模組被附接至一第二電路板的連接器時配接該連接器的接點。 11. The module of paragraph 1, wherein the circuit board is a module card, and wherein the module contacts are a plurality of contacts at one of the first surface and the second surface For mating the connector of the connector when the module is attached to a connector of a second circuit board.

12.根據第1段的模組，其中，該等模組接點係曝露在該等第一表面和第二表面中其中一者處的表面鑲嵌接點，用以在該模組接合一第二電路板時面向並且電性連接該第二電路板的接點。 12. The module of paragraph 1, wherein the module contacts are surface inlaid contacts exposed at one of the first surface and the second surface for engaging in the module The two circuit boards face and electrically connect the contacts of the second circuit board.

13.根據第1段的模組，其中，該至少一組共支撐接點中的每一者皆包含被配置成用以攜載該命令與位址資訊以外之資訊的第二接點。 13. The module of clause 1, wherein each of the at least one set of co-supporting contacts comprises a second contact configured to carry information other than the command and address information.

14.根據第13段的模組，其中，該至少一組共支撐接點中的每一者會曝露在該電路板之第一表面的一對應區域中，其中，該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的一周圍的至少第一與第二反向邊緣相鄰的第一區域與第二區域中，且其中，該個別共支撐接點組的所有第一接點會被設置在該個別共支撐接點組的該等第一區域與第二區域之間。 14. The module of clause 13, wherein each of the at least one set of co-supporting contacts is exposed in a corresponding region of the first surface of the circuit board, wherein the at least one set of co-supporting At least some of the second contacts of each of the points are disposed in a first region adjacent to at least a first and second reverse edges of a region of the region of the individual co-supporting contact group In the second region, and wherein all of the first contacts of the individual co-supporting contact groups are disposed between the first regions and the second regions of the individual co-supporting contact groups.

15.根據第14段的模組，其中，該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的該周圍的至少第三與第四反向邊緣相鄰的第三區域與第四區域中，該等第三邊緣與第四邊緣中的每一者延伸在一位於該等第一邊緣與第二邊緣之間的方向中，且其中，該個別共支撐接點組的所有第一接點會被設置在該個別共支撐接點組的該等第三區域與第四區域之間。 15. The module of clause 14, wherein at least some of the second contacts of each of the at least one set of co-supporting contacts are disposed in the region of the individual co-supporting contact set In each of the third and fourth regions adjacent to at least the third and fourth reverse edges, each of the third and fourth edges extends between the first edge and the second edge In the direction between the edges, and wherein all of the first contacts of the individual co-supporting contact sets are disposed between the third and fourth regions of the individual co-supporting contact set.

16.根據第1段的模組，其中，該第一類型微電子組件中的微電子元件係DDRx型，而且該第二類型微電子組件中的微電子元件係LPDDRx型。 16. The module of paragraph 1, wherein the microelectronic component of the first type of microelectronic component is of the DDRx type and the microelectronic component of the second type of microelectronic component is of the LPDDRx type.

17.根據第1段的模組，其中，該第一類型微電子組件中的微電子元件係GDDRx型。 17. The module of paragraph 1, wherein the microelectronic component of the first type of microelectronic component is of the GDDRx type.

18.根據第1段的模組，其中，該至少一組共支撐接點在該第一表面處包含一第一組並且在該第一表面處包含一第二組，該第二組在一平行於該第一表面的方向中與該第一組隔開。 18. The module of paragraph 1, wherein the at least one set of co-supporting contacts comprises a first set at the first surface and a second set at the first surface, the second set Separate from the first group in a direction parallel to the first surface.

19.根據第1段的模組，其中，該至少一組共支撐接點在該第一表面處包含一第一組並且在該第二表面處包含一第二組。 19. The module of paragraph 1, wherein the at least one set of co-supporting joints comprises a first set at the first surface and a second set at the second surface.

20.根據第1段的模組，其中，每一組共支撐接點中的第一接點包含第一群第一接點和第二群第一接點，每一群第一接點會被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊。 20. The module of paragraph 1, wherein the first of the plurality of common support contacts comprises a first group of first contacts and a second group of first contacts, each of the first contacts being Assigned to carry address information that can be used to explicitly specify a location within the memory storage array.

21.根據第20段的模組，其中，在每一組共支撐接點裡面，該第一群的該等第一接點中的每一者的訊號指派會以一理論軸為基礎對稱於該第二群的一對應第一接點的訊號指派。 21. The module of paragraph 20, wherein in each set of co-supporting contacts, the signal assignment of each of the first contacts of the first group is symmetric based on a theoretical axis A signal assignment of the second group corresponding to the first contact.

22.根據第20段的模組，其中，當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該微電子元件會被配置成用以連接該等第一群和第二群中每一群中的第一接點。 22. The module of paragraph 20, wherein the microelectronic component of the first type of microelectronic component is configured when each set of co-supporting contacts has an assignment arranged according to the first predetermined arrangement The first contact in each of the first group and the second group is connected.

23.根據第20段的模組，其中，該第一類型微電子組件包含複數個微電子元件，且其中，當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該等複數個微電子元件中的每一者會被配置成用以連接該等第一群和第二群中每一群中的第一接點。 23. The module of paragraph 20, wherein the first type of microelectronic component comprises a plurality of microelectronic components, and wherein each set of co-supporting contacts has an arrangement arranged according to the first predetermined arrangement Each of the plurality of microelectronic components of the first type of microelectronic assembly is configured to connect a first contact in each of the first and second groups.

24.根據第20段的模組，其中，當每一組共支撐接點具有根據該第二預設排列方式所排列的指派時，該第二類型微電子組件的該微電子元件會被配置成用以連接該第一群的第一接點而不連接該第二群的第一接點。 24. The module of paragraph 20, wherein the microelectronic component of the second type of microelectronic component is configured when each set of co-supporting contacts has an assignment arranged according to the second predetermined arrangement The first contact for connecting the first group is not connected to the first contact of the second group.

25.根據第20段的模組，其中，該第二類型微電子組件包含複數個微電子元件，其包括前半部微電子元件和後半部微電子元件，且其中，當每一組共支撐接點具有根據該第二預設排列方式所排列的指派時，該第二類型微電子組件的前半部微電子元件中的每一者會被配置成用以連接該第一群第一接點而不連接該第二群第一接點，而該第二類型微電子組件的後半部微電子元件中的每一者會被配置成用以連接該第二群第一接點而不連接該第一群第一接點。 25. The module of paragraph 20, wherein the second type of microelectronic component comprises a plurality of microelectronic components comprising a front half microelectronic component and a second half microelectronic component, and wherein each group is co-supported Each of the first half of the microelectronic components of the second type of microelectronic component is configured to connect to the first group of first contacts while the dots have an assignment arranged according to the second predetermined arrangement The second group of first contacts are not connected, and each of the second half of the second type of microelectronic components is configured to connect to the second group of first contacts without connecting the first A group of first contacts.

26.一種模組，用以連接至少一微電子組件，每一個微電子組件皆包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊，該模組包括：一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊；至少一組共支撐接點，它們會被耦合至該組導體，每一組共支撐接點皆會曝露在該第一表面或是該第二表面處，每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電子組件的該終端組；以及複數個模組接點，它們會被耦合至該組導體，該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊，該等模組接點 會被配置成用以連接位於該模組外部的一器件，其中，該至少一組共支撐接點中的每一者皆包含多個第一接點，它們具有(a)根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第一子集(其包含第一數量的第一接點)與其耦合的命令與位址資訊，以及(b)根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派的多個第一接點，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第二子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該等第一子集與第二子集包含佔據相同位置的某些第一接點，該第二數量少於該第一數量。 26. A module for connecting at least one microelectronic component, each microelectronic component comprising a set of terminals and a microelectronic component having a memory storage array having a given number of storage locations, each microelectronic component The microelectronic component has a plurality of inputs that connect to the terminals to receive command and address information that explicitly specifies one of the storage locations, the module comprising: a circuit board having a first And a second inverted surface carrying a set of conductors configured to carry the command and address information; at least one set of co-supporting contacts that are coupled to the set of conductors, each set The common support contacts are exposed at the first surface or the second surface, and each set of common support contacts is configured to be connected to the terminal of the single microelectronic assembly of the at least one microelectronic component And a plurality of module contacts that are coupled to the set of conductors, the module contacts being configured to carry information transmitted to and from the at least one set of co-supporting contacts, Module connection Will be configured to connect a device external to the module, wherein each of the at least one set of co-supporting contacts comprises a plurality of first contacts having (a) according to An address and command information assignment of a first predetermined arrangement of a type of microelectronic component, wherein the microelectronic component is configured to sample via a first subset of the first contacts (its a command and address information including a first number of first contacts) coupled thereto, and (b) an address and command information assigned according to a second predetermined arrangement for connecting the second type of microelectronic components a plurality of first contacts, wherein the microelectronic component is configured to sample a command coupled thereto via a second subset of the first contacts (which includes a second number of first contacts) Address information, the first subset and the second subset include certain first contacts occupying the same location, the second number being less than the first number.

27.根據第26段的模組，其中，該第一類型微電子組件的命令與位址資訊包含同位元資訊，該第一類型微電子組件中的微電子元件會被配置成用以取樣該同位元資訊，而用於連接第二類型微電子組件的該等第一接點中的第二子集不會被配置成用以取樣該同位元資訊。 27. The module of paragraph 26, wherein the command and address information of the first type of microelectronic component comprises parity information, and the microelectronic component of the first type of microelectronic component is configured to sample the The parity information, and the second subset of the first contacts for connecting the second type of microelectronic components are not configured to sample the parity information.

28.根據第26段的模組，其中，該第二類型微電子組件中的微電子元件係DDR3型，而該第一類型微電子組件中的微電子元件係DDR4型。 28. The module of paragraph 26, wherein the microelectronic component of the second type of microelectronic component is of the DDR3 type and the microelectronic component of the first type of microelectronic component is of the DDR4 type.

29.根據第28段的模組，其中，具有DDR4型微電子元件之該第一類型微電子組件中的命令與位址資訊包含同位元資訊，而且該第一類型微電子組件中的該DDR4型微電子元件會被配置成用以取樣該同位元資訊。 29. The module of clause 28, wherein the command and address information in the first type of microelectronic component having a DDR4 type microelectronic component comprises parity information, and the DDR4 in the first type of microelectronic component The microelectronic component will be configured to sample the homostat information.

30.根據第26段的模組，其中，該第二類型微電子組件中的微電子元件 係DDRx型，而該第一類型微電子組件中的微電子元件係DDR(x+1)型。 30. The module of paragraph 26, wherein the microelectronic component of the second type of microelectronic assembly It is of the DDRx type, and the microelectronic component in the first type of microelectronic component is of the DDR(x+1) type.

5‧‧‧器件 5‧‧‧Device

10‧‧‧微電子組件 10‧‧‧Microelectronic components

25a‧‧‧終端 25a‧‧‧ Terminal

25b‧‧‧終端 25b‧‧‧ Terminal

30‧‧‧微電子元件 30‧‧‧Microelectronic components

35a‧‧‧元件接點 35a‧‧‧Component contacts

35b‧‧‧元件接點 35b‧‧‧Component contacts

60‧‧‧支撐結構 60‧‧‧Support structure

65‧‧‧第一接點 65‧‧‧First contact

67‧‧‧第二接點 67‧‧‧second junction

70‧‧‧第一導體組 70‧‧‧First Conductor Group

71‧‧‧第二導體組 71‧‧‧Second conductor set

80‧‧‧裝置 80‧‧‧ device

Claims (30)

一種模組，用以連接至少一微電子組件，每一個微電子組件皆包含一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊，該模組包括：一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊；至少一組共支撐接點，它們會被耦合至該組導體，每一組共支撐接點皆會曝露在該第一表面或是該第二表面處，每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電子組件的該終端組；以及複數個模組接點，它們會被耦合至該組導體，該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊，該等模組接點會被配置成用以連接位於該模組外部的一器件，其中，該至少一組共支撐接點中的每一者皆包含多個第一接點，它們具有(a)根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成以第一取樣率來取樣經由該等第一接點(該等第一接點具有第一數量的接點)與其耦合的命令與位址資訊，以及(b)根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成以大於第一取樣率的 第二取樣率來取樣經由該等第一接點中的一子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該子集包含佔據和被指派至該第一預設排列方式之第一接點相同位置的某些第一接點，該第二數量少於該第一數量。 a module for connecting at least one microelectronic component, each microelectronic component comprising a set of terminals and a microelectronic component having a memory storage array having a given number of storage locations, each of the microelectronic components The microelectronic component has a plurality of inputs that connect to the terminals to receive command and address information that explicitly specifies one of the storage locations, the module comprising: a circuit board having first and first a reversed surface and carrying a set of conductors configured to carry the command and address information; at least one set of co-supporting contacts that are coupled to the set of conductors, each set of co-support The contacts are exposed at the first surface or the second surface, and each set of common support contacts is configured to be connected to the terminal group of the single microelectronic assembly of the at least one microelectronic component; And a plurality of module contacts that are coupled to the set of conductors, the module contacts being configured to carry information transmitted to and from the at least one set of co-supporting contacts, the modules Group contact Configuring to connect a device external to the module, wherein each of the at least one set of co-support contacts includes a plurality of first contacts having (a) for connecting the first An address and command information assignment of the first predetermined arrangement of the type microelectronic components, wherein the microelectronic component is configured to sample at the first sampling rate via the first contacts (the first The contacts have a first number of contacts) command and address information coupled thereto, and (b) address and command information assignments arranged according to a second predetermined arrangement for connecting the second type of microelectronic components, Wherein the microelectronic component is configured to be greater than the first sampling rate a second sampling rate to sample command and address information coupled thereto via a subset of the first contacts (which includes a second number of first contacts), the subset including occupancy and assignment to the first Certain first contacts of the same location of the first contact of a predetermined arrangement, the second number being less than the first number. 根據申請專利範圍第1項的模組，其中，根據該第二預設排列方式排列的第一接點的子集中的所有接點會佔據和被指派至該第一預設排列方式的第一接點相同的位置。 The module of claim 1, wherein all contacts in the subset of the first contacts arranged according to the second predetermined arrangement occupy and are assigned to the first of the first preset arrangements The same location of the contacts. 根據申請專利範圍第1項的模組，其中，該第二取樣率係該第一取樣率的整數倍。 The module of claim 1, wherein the second sampling rate is an integer multiple of the first sampling rate. 根據申請專利範圍第1項的模組，其中，每一組共支撐接點中的該等第一接點包含被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊的接點。 The module of claim 1, wherein the first of the plurality of common support contacts is configured to carry a position that can be used to explicitly designate a location within the memory storage array. The contact point of the address information. 根據申請專利範圍第1項的模組，進一步包括一被耦合至該組導體的裝置，該裝置可操作用以將該命令與位址資訊驅動至該等第一接點。 The module of claim 1 further comprising a device coupled to the set of conductors, the device being operative to drive the command and address information to the first contacts. 根據申請專利範圍第5項的模組，其中，該裝置會被配置成用以操作在第一模式與第二模式的每一者之中，以便分別透過該第一排列方式來連接該模組和第一類型微電子組件以及透過該第二排列方式來連接該模組和第二類型微電子組件。 The module of claim 5, wherein the device is configured to operate in each of the first mode and the second mode to connect the module through the first arrangement And the first type of microelectronic assembly and the second arrangement to connect the module and the second type of microelectronic assembly. 根據申請專利範圍第6項的模組，進一步包括該第一類型微電子組件，其中，該至少一組共支撐接點中的一組會電性連接該第一類型微電子組件的該等終端。 The module of claim 6, further comprising the first type of microelectronic assembly, wherein one of the at least one set of co-support contacts is electrically connected to the terminals of the first type of microelectronic assembly . 根據申請專利範圍第6項的模組，進一步包括該第二類型微電子組件，該至少一組共支撐接點中的一組會電性連接該第二類型微電子組件的 該等終端。 The module of claim 6, further comprising the second type of microelectronic assembly, wherein one of the at least one set of co-supporting contacts is electrically connected to the second type of microelectronic assembly These terminals. 根據申請專利範圍第1項的模組，其中，該微電子組件係一微電子封裝，且其中，該等終端係表面鑲嵌終端並且會曝露在該微電子封裝的一表面處。 The module of claim 1, wherein the microelectronic component is a microelectronic package, and wherein the terminals are surface-embedded and exposed to a surface of the microelectronic package. 根據申請專利範圍第1項的模組，其中，該電路板係一模組卡，且其中，該等模組接點係該等第一表面和第二表面中至少其中一者處的複數個平行曝露接點，用以在該模組被插入一第二電路板的插槽中時配接該插槽的接點。 The module of claim 1, wherein the circuit board is a module card, and wherein the module contacts are at least one of the first surface and the second surface Parallel exposure contacts for mating the contacts of the slot when the module is inserted into a slot of a second circuit board. 根據申請專利範圍第1項的模組，其中，該電路板係一模組卡，且其中，該等模組接點係該等第一表面和第二表面中其中一者處的複數個接點，用以在該模組被附接至一第二電路板的連接器時配接該連接器的接點。 The module of claim 1, wherein the circuit board is a module card, and wherein the module contacts are a plurality of connections of one of the first surface and the second surface a point for mating the connector of the connector when the module is attached to a connector of a second circuit board. 根據申請專利範圍第1項的模組，其中，該等模組接點係曝露在該等第一表面和第二表面中其中一者處的表面鑲嵌接點，用以在該模組接合一第二電路板時面向並且電性連接該第二電路板的接點。 The module of claim 1, wherein the module contacts are exposed at a surface of one of the first surface and the second surface for engaging the module The second circuit board faces and electrically connects the contacts of the second circuit board. 根據申請專利範圍第1項的模組，其中，該至少一組共支撐接點中的每一者皆包含被配置成用以攜載該命令與位址資訊以外之資訊的第二接點。 The module of claim 1, wherein each of the at least one set of co-supporting contacts comprises a second contact configured to carry information other than the command and address information. 根據申請專利範圍第13項的模組，其中，該至少一組共支撐接點中的每一者會曝露在該電路板之第一表面的一對應區域中，其中，該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的一周圍的至少第一與第二反向邊緣相鄰的第一區域與第二區域中，且其中，該個別共支撐接點組的所有第一接點會被設置在 該個別共支撐接點組的該等第一區域與第二區域之間。 The module of claim 13, wherein each of the at least one set of co-supporting contacts is exposed in a corresponding area of the first surface of the circuit board, wherein the at least one group of the common supports At least some of the second contacts of each of the contacts are disposed in a first region adjacent at least a first and second reverse edges of a region of the region of the individual co-supporting contact groups And in the second area, and wherein all of the first contacts of the individual co-supporting contact group are set Between the first and second regions of the individual co-supporting contact set. 根據申請專利範圍第14項的模組，其中，該至少一組共支撐接點中的每一者的至少某些該等第二接點會被設置在和該個別共支撐接點組之該區域的該周圍的至少第三與第四反向邊緣相鄰的第三區域與第四區域中，該等第三邊緣與第四邊緣中的每一者延伸在一位於該等第一邊緣與第二邊緣之間的方向中，且其中，該個別共支撐接點組的所有第一接點會被設置在該個別共支撐接點組的該等第三區域與第四區域之間。 The module of claim 14, wherein at least some of the at least some of the at least one set of co-supporting contacts are disposed in the region of the individual co-supporting contact group In the third and fourth regions of the surrounding at least third and fourth reverse edges, each of the third and fourth edges extends at a first edge and In the direction between the two edges, and wherein all of the first contacts of the individual co-supporting contact group are disposed between the third and fourth regions of the individual co-supporting contact group. 根據申請專利範圍第1項的模組，其中，該第一類型微電子組件中的微電子元件係DDRx型，而且該第二類型微電子組件中的微電子元件係LPDDRx型。 The module of claim 1, wherein the microelectronic component of the first type of microelectronic component is of the DDRx type, and the microelectronic component of the second type of microelectronic component is of the LPDDRx type. 根據申請專利範圍第1項的模組，其中，該第一類型微電子組件中的微電子元件係GDDRx型。 The module of claim 1, wherein the microelectronic component of the first type of microelectronic component is of the GDDRx type. 根據申請專利範圍第1項的模組，其中，該至少一組共支撐接點在該第一表面處包含一第一組並且在該第一表面處包含一第二組，該第二組在一平行於該第一表面的方向中與該第一組隔開。 The module of claim 1, wherein the at least one set of co-supporting joints comprises a first group at the first surface and a second group at the first surface, the second group A direction parallel to the first surface is spaced apart from the first set. 根據申請專利範圍第1項的模組，其中，該至少一組共支撐接點在該第一表面處包含一第一組並且在該第二表面處包含一第二組。 The module of claim 1, wherein the at least one set of co-supporting contacts comprises a first set at the first surface and a second set at the second surface. 根據申請專利範圍第1項的模組，其中，每一組共支撐接點中的第一接點包含第一群第一接點和第二群第一接點，每一群第一接點會被指派用以攜載能夠用以明確指定該記憶體儲存陣列裡面的一位置的位址資訊。 According to the module of claim 1, wherein the first contact of each group of the common support contacts comprises a first group of first contacts and a second group of first contacts, each group of first contacts It is assigned to carry address information that can be used to explicitly specify a location within the memory storage array. 根據申請專利範圍第20項的模組，其中，在每一組共支撐接點裡面，該第一群的該等第一接點中的每一者的訊號指派會以一理論軸為基礎對稱 於該第二群的一對應第一接點的訊號指派。 According to the module of claim 20, in each group of common support contacts, the signal assignment of each of the first contacts of the first group is symmetric based on a theoretical axis Signal assignment to a corresponding first contact of the second group. 根據申請專利範圍第20項的模組，其中，當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該微電子元件會被配置成用以連接該等第一群和第二群中每一群中的第一接點。 The module of claim 20, wherein the microelectronic component of the first type of microelectronic component is to be used when each set of common support contacts has an arrangement arranged according to the first predetermined arrangement And configured to connect the first contacts in each of the first group and the second group. 根據申請專利範圍第20項的模組，其中，該第一類型微電子組件包含複數個微電子元件，且其中，當每一組共支撐接點具有根據該第一預設排列方式所排列的指派時，該第一類型微電子組件的該等複數個微電子元件中的每一者會被配置成用以連接該等第一群和第二群中每一群中的第一接點。 The module of claim 20, wherein the first type of microelectronic component comprises a plurality of microelectronic components, and wherein each set of co-supporting contacts has an arrangement according to the first predetermined arrangement When assigned, each of the plurality of microelectronic components of the first type of microelectronic assembly is configured to connect a first contact in each of the first and second groups. 根據申請專利範圍第20項的模組，其中，當每一組共支撐接點具有根據該第二預設排列方式所排列的指派時，該第二類型微電子組件的該微電子元件會被配置成用以連接該第一群的第一接點而不連接該第二群的第一接點。 The module of claim 20, wherein the microelectronic component of the second type of microelectronic component is to be used when each set of common support contacts has an arrangement arranged according to the second predetermined arrangement The first contact is configured to connect to the first group and not to the first node of the second group. 根據申請專利範圍第20項的模組，其中，該第二類型微電子組件包含複數個微電子元件，其包括前半部微電子元件和後半部微電子元件，且其中，當每一組共支撐接點具有根據該第二預設排列方式所排列的指派時，該第二類型微電子組件的前半部微電子元件中的每一者會被配置成用以連接該第一群第一接點而不連接該第二群第一接點，而該第二類型微電子組件的後半部微電子元件中的每一者會被配置成用以連接該第二群第一接點而不連接該第一群第一接點。 The module of claim 20, wherein the second type of microelectronic component comprises a plurality of microelectronic components including a front half microelectronic component and a second half microelectronic component, and wherein each group is supported When the contacts have an arrangement arranged according to the second predetermined arrangement, each of the first half of the microelectronic components of the second type of microelectronic component is configured to connect to the first group of first contacts Not connecting the second group of first contacts, and each of the second half of the second type of microelectronic components is configured to connect to the second group of first contacts without connecting the The first group of first contacts. 一種模組，用以連接至少一微電子組件，每一個微電子組件皆包含 一組終端以及一具有一具有給定數量儲存位置之記憶體儲存陣列的微電子元件，每一個微電子組件的該微電子元件皆有多個輸入，它們會連接該等終端，以便接收明確指定該等儲存位置中其中一者的命令與位址資訊，該模組包括：一電路板，其具有第一與第二反向的表面並且承載一組導體，該組導體被配置成用以攜載該命令與位址資訊；至少一組共支撐接點，它們會被耦合至該組導體，每一組共支撐接點皆會曝露在該第一表面或是該第二表面處，每一組共支撐接點皆會被配置成用以連接至該至少一微電子組件的單一微電子組件的該終端組；以及複數個模組接點，它們會被耦合至該組導體，該等模組接點會被配置成用以攜載傳輸至和傳輸自該至少一組共支撐接點的資訊，該等模組接點會被配置成用以連接位於該模組外部的一器件，其中，該至少一組共支撐接點中的每一者皆包含多個第一接點，它們具有(a)根據用於連接第一類型微電子組件的第一預設排列方式所排列的位址與命令資訊指派，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第一子集(其包含第一數量的第一接點)與其耦合的命令與位址資訊，以及(b)根據用於連接第二類型微電子組件的第二預設排列方式所排列的位址與命令資訊指派的多個第一接點，其中，該微電子元件會被配置成用以取樣經由該等第一接點中的第二子集(其包含第二數量的第一接點)與其耦合的命令與位址資訊，該等第一子集與第二子集包含佔據相同位置的某些 第一接點，該第二數量少於該第一數量。 a module for connecting at least one microelectronic component, each microelectronic component comprising a set of terminals and a microelectronic component having a memory storage array having a given number of storage locations, the microelectronic component of each microelectronic component having a plurality of inputs that are connected to the terminals for receiving an explicit designation Command and address information for one of the storage locations, the module comprising: a circuit board having first and second opposing surfaces and carrying a set of conductors configured to carry Carrying the command and address information; at least one set of co-supporting contacts that are coupled to the set of conductors, each set of common support contacts being exposed to the first surface or the second surface, each The set of common support contacts are configured to be coupled to the terminal set of a single microelectronic component of the at least one microelectronic component; and a plurality of modular contacts that are coupled to the set of conductors, the modes The set of contacts is configured to carry information transmitted to and from the at least one set of co-supported contacts, the modular contacts being configured to connect a device external to the module, wherein At least one group Each of the support contacts includes a plurality of first contacts having (a) address and command information assignments arranged according to a first predetermined arrangement for connecting the first type of microelectronic components, wherein The microelectronic component is configured to sample command and address information coupled thereto via a first subset of the first contacts (which includes a first number of first contacts), and (b) a plurality of first contacts assigned with address information and command information arranged in a second predetermined arrangement for connecting the second type of microelectronic components, wherein the microelectronic component is configured to be sampled via the a second subset of the first contacts (which includes a second number of first contacts) with command and address information coupled thereto, the first subset and the second subset containing certain portions occupying the same location The first contact, the second number is less than the first quantity. 根據申請專利範圍第26項的模組，其中，該第一類型微電子組件的命令與位址資訊包含同位元資訊，該第一類型微電子組件中的微電子元件會被配置成用以取樣該同位元資訊，而用於連接第二類型微電子組件的該等第一接點中的第二子集不會被配置成用以取樣該同位元資訊。 The module of claim 26, wherein the command and address information of the first type of microelectronic component comprises parity information, and the microelectronic component of the first type of microelectronic component is configured to be sampled The parity information, and the second subset of the first contacts for connecting the second type of microelectronic components are not configured to sample the peer information. 根據申請專利範圍第26項的模組，其中，該第二類型微電子組件中的微電子元件係DDR3型，而該第一類型微電子組件中的微電子元件係DDR4型。 The module of claim 26, wherein the microelectronic component of the second type of microelectronic component is of the DDR3 type, and the microelectronic component of the first type of microelectronic component is of the DDR4 type. 根據申請專利範圍第28項的模組，其中，具有DDR4型微電子元件之該第一類型微電子組件中的命令與位址資訊包含同位元資訊，而且該第一類型微電子組件中的該DDR4型微電子元件會被配置成用以取樣該同位元資訊。 The module according to claim 28, wherein the command and address information in the first type of microelectronic component having the DDR4 type microelectronic component includes the same bit information, and the first type of microelectronic component The DDR4 type microelectronic component will be configured to sample the same bit information. 根據申請專利範圍第26項的模組，其中，該第二類型微電子組件中的微電子元件係DDRx型，而該第一類型微電子組件中的微電子元件係DDR(x+1)型。 The module of claim 26, wherein the microelectronic component of the second type of microelectronic component is of the DDRx type, and the microelectronic component of the first type of microelectronic component is of the DDR(x+1) type .
TW104114389A 2012-08-27 2013-08-27 Co-support system and microelectronic assembly TWI541651B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201213595486A 2012-08-27 2012-08-27
US13/839,402 US8787034B2 (en) 2012-08-27 2013-03-15 Co-support system and microelectronic assembly
US13/840,353 US8848391B2 (en) 2012-08-27 2013-03-15 Co-support component and microelectronic assembly
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109983782B (en) * 2016-09-30 2021-06-01 雅马哈株式会社 Conversation assistance device and conversation assistance method
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163024A (en) * 1983-12-30 1992-11-10 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US5210639A (en) * 1983-12-30 1993-05-11 Texas Instruments, Inc. Dual-port memory with inhibited random access during transfer cycles with serial access
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
JPH09298217A (en) * 1996-05-07 1997-11-18 Hitachi Ltd Semiconductor device, its manufacture and electronic device
JP2000223657A (en) * 1999-02-03 2000-08-11 Rohm Co Ltd Semiconductor device and semiconductor chip used for the same
JP3935321B2 (en) * 2001-02-16 2007-06-20 松下電器産業株式会社 Multi-chip module
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP4610235B2 (en) * 2004-06-07 2011-01-12 ルネサスエレクトロニクス株式会社 Hierarchical module
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US8586870B2 (en) * 2009-03-27 2013-11-19 Molex Incorporated Microelectronic component support with reinforced structure
WO2012019909A1 (en) * 2010-08-13 2012-02-16 Tesa Se Method for encapsulating an electronic arrangement
TWI533412B (en) * 2010-08-13 2016-05-11 金龍國際公司 Semiconductor device package structure and forming method of the same

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