TW201528342A - Method to reduce K value of dielectric layer for advanced finfet formation - Google Patents

Abstract

Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.

Description

Method for reducing the K value of a dielectric layer for advanced fin field effect transistor formation

The embodiments described herein relate generally to a method of forming a gate in a semiconductor component. More particularly, the embodiments described herein relate to methods for reducing the K value of an intermediate electrical layer in an advanced fin field effect transistor (FinFET) formation process.

There is an increasing demand for smaller electronic components with denser circuits, and in response to this increased demand, components having three-dimensional (3D) structures have been developed. An example of such a component can include a FinFET having a conductive fin-like structure that rises vertically above the horizontally extending substrate. Conventional FinFETs can be formed on a substrate, such as a semiconductor substrate or an insulator overlying germanium. The substrate may include a semiconductor substrate and an oxide layer disposed on the semiconductor substrate.

According to the continuing demand for components that continue to be smaller, the reduced gate pitch increases the parasitic capacitance of the contacts to the gate and the epitaxial to gate, thereby increasing the overall gate capacitance. a conventional capacitive element (such as Minimizing the overlap capacitance, channel capacitance, junction capacitance, and internal and external edge capacitance becomes increasingly challenging. Furthermore, the critical dimensions of the gate and contacts have been scaled at a slower rate than the gate pitch. Thus, parasitic edge capacitance (contact to gate capacitance and epitaxial to gate capacitance) becomes an increasingly significant problem.

Therefore, there is a need in the art for a method for reducing parasitic capacitance in a FinFET structure.

In one embodiment, a method of forming a gate is provided. The method includes the steps of: transferring a substrate to a plasma processing apparatus, the substrate having a 3D structure, the 3D structure comprising a gate dielectric structure configured to be adjacent to a dummy gate (dummy Gate) structure. In the device, the vertically oriented portion of the gate dielectric structure can be exposed to ions. One or more ion bombardment angles may be selected in response to the aspect ratio of the 3D structure.

In another embodiment, a method of forming a gate is provided. The method includes the steps of transferring a substrate to a plasma processing apparatus having a 3D structure, the 3D structure including a gate dielectric structure configured to be adjacent to the dummy gate structure. A barrier layer can be formed on the gate dielectric structure. The barrier layer can be exposed to ions along the one or more ion bombardment angles in the device, the ion bombardment angle being selected in response to the aspect ratio of the 3D structure.

In yet another embodiment, a method of forming a gate is provided. The method includes the steps of transferring a substrate to a plasma processing apparatus having a 3D structure, the 3D structure including a gate dielectric disposed on one or more fin structures. The gate dielectric can be exposed in the device To the ions, one or more ion bombardment angles can be selected depending on the aspect ratio of the fin structure.

100‧‧‧ Equipment

101‧‧‧ ions

102‧‧‧Processing chamber

106‧‧‧ source

108‧‧‧Modification components

112, 114‧‧‧ insulator

113‧‧‧ Directional components

134‧‧‧ platform

138‧‧‧Substrate

140‧‧‧ Plasma

141‧‧‧ border

142‧‧‧Electrochemical sheath

144‧‧‧ trench

147‧‧‧ side wall

150, 151‧‧ plane

169‧‧‧ Path

171‧‧‧ Path

188‧‧‧ gas source

190‧‧‧ bias source, controller

192‧‧‧CPU

194‧‧‧ memory

196‧‧‧Support circuit

200‧‧‧ characteristics

201‧‧‧Insulator materials

202‧‧‧Substrate

203‧‧‧Fin structure

204‧‧‧ gate

206‧‧‧gate dielectric

208‧‧‧Second area

209‧‧‧ Path

210‧‧‧First area

211‧‧‧ Path

212‧‧‧ side wall

213‧‧‧ upper surface

214‧‧‧Materials

216‧‧‧ bottom area

218‧‧‧ top area

220‧‧‧pitch length

222‧‧‧ Height

302‧‧‧Substrate

310‧‧‧Fin structure

320‧‧‧Insulation

332‧‧‧ side wall

334‧‧‧Top area

336‧‧‧ horizontally oriented area

350‧‧‧ dielectric material layer

354‧‧‧Area

360‧‧‧Barrier layer

362‧‧‧ ions

364‧‧‧ incident ions

A more specific description of the disclosure of the present invention, which is briefly summarized above, may be obtained by reference to the accompanying drawings. It is to be understood, however, that the appended claims

1 is a schematic diagram of a plasma processing apparatus for performing the embodiments disclosed herein.

2A through 2C are partial cross-sectional views of the substrate illustrating a bidirectional angular ion bombardment process for performing the embodiments disclosed herein.

3A through 3C are partial cross-sectional views of the substrate illustrating a procedure for forming a 3D structure in accordance with one embodiment disclosed herein.

To assist in understanding, the same component symbols have been used, if possible, to designate the same components common to the various figures. It is contemplated that elements disclosed in one embodiment may be beneficially incorporated in other embodiments without further recitation.

The embodiments described herein relate generally to methods for forming a gate structure, and more particularly to forming a gate dielectric layer having a reduced K value. The gate dielectric material can be formed by exposing the as-deposited dielectric layer to energetic ions to form a low dielectric constant material. The membrane properties of the gate dielectric can be adjusted by ion bombardment to reduce the K value. The gate dielectric of the gate dielectric can modify the composition and/or structure of the gate dielectric without exceeding The thermal budget of the processed material. A gate dielectric with a low K value provides reduced parasitic capacitance.

The improved gate and gate dielectrics are particularly advantageous for 3D FinFET structures, as will be described in more detail below. Processes that can be performed to reduce the K value of the gate dielectric material can include light ion implantation of species such as He, H, or Ne, direct ion implantation of carbon and/or boron based ions, carbon and/or Or deposition and knock on of the boron film, and deposition, flashback, and ion implantation of carbon and/or boron ions performed in parallel. The above process benefits from the angular bombardment of ions at various stages of FinFET formation. For example, the processes may be performed after the gate dielectric has been deposited, after the gate dielectric has been etched, and after the dummy gate removal process. Various FinFET formation processes can be used during various stages of FinFET formation to provide a gate dielectric with a reduced K value while maintaining gate dielectric integrity at a reduced critical dimension.

1 is a diagrammatic view of a plasma processing apparatus 100 for performing the processes disclosed herein. In addition to the apparatus 100 described below, more conventional ion implantation equipment, such as beamline ion implantation equipment, can be used to perform the methods described herein. An example of a beamline ion implantation device is Varian VIISta® Trident, which is available from Applied Materials, Inc., Santa Clara, California. The plasma processing apparatus 100 includes a processing chamber 102, a platform 134, a source 106, and a conditioning element 108. The platform 134 can be transferred into the processing chamber 102 and positioned in the processing chamber 102 to support the substrate 138. The platform 134 can be coupled to an actuator (not shown) that can cause the platform 134 to move in a scanning motion. The scanning motion can be a reciprocating movement in a single plane, A single plane can modify element 108 substantially in parallel. Source 106 is mounted to generate plasma 140 in processing chamber 102. The modifying element 108 includes a pair of insulators 112, 114 that define a gap between the insulators 112, 114 that has a horizontal spacing (G). The insulators 112, 114 may comprise an insulating material, a semiconductor material, or a conductive material. The modifying element also includes a directional element 113 that is disposed at a location relative to the insulators 112, 114 such that ions 101 are provided toward the substrate 138.

In operation, gas source 188 can supply ionizable gas to processing chamber 102. Examples of particularly ionizable gases may include BF ₃ , BI ₃ , N ₂ , Ar, PH ₃ , AsH ₃ , B ₂ H ₆ , H ₂ , Xe, Kr, Ne, He, CH ₄ , CF ₄ , AsF ₅ , PF ₃ and PF ₅ . More specifically, the ionic species may include He ⁺ , H ₃ ⁺ , H ₂ ⁺ , H ⁺ , Ne ⁺ , F ⁺ , C ⁺ , CF _x ⁺ , CH _x ⁺ , C _x H _y , N ⁺ , B ⁺ , BF ₂ ⁺ , B ₂ H _x ⁺ , Xe ⁺ and molecular carbon, boron, or boron carbide ions. Source 106 can generate plasma 140 by exciting and ionizing the gas provided to processing chamber 102. Ion 101 is attracted from plasma 140 across plasma sheath 142. For example, bias source 190 is provided to bias substrate 138 to attract ions 101 from plasma 140 across plasma sheath 142. The bias source 190 can be a DC power supply to provide a DC voltage bias signal or an RF power supply to provide an RF bias signal.

The modifying element 108 modifies the electric field within the plasma sheath 142 to control the shape of the boundary 141 between the plasma 140 and the plasma sheath 142. The modifying element 108 includes insulators 112, 114 and a directional element 113. The insulators 112, 114 and the directional element 113 may be fabricated from materials such as quartz, alumina, boron nitride, glass, tantalum nitride, and other suitable materials. The boundary 141 between the plasma 140 and the plasma sheath 142 is dependent on the directional element 113 relative to the insulator 112, 114. The placement relationship is because the directional element 113 may change the electric field within the plasma sheath 142.

The ions following the track path 171 can strike the substrate 138 at an angle of about + theta to the normal to plane 151. The ions following the orbital path 169 can strike the substrate 138 at an angle of about -[theta] at a vertical plane 151. Thus, the angle of incidence of the vertical plane 151 can range from about +1° to about +65° and between about -1° to about -65°, excluding 0°. For example, the first range of incident angles of the vertical plane 150 may be between about +5° and about +65°, and the second range of incident angles of the vertical plane 150 may be between about -5° and about -65°. between. In one embodiment, the first range of incident angles relative to plane 151 may be between about -10° and about -20°, and the second range of incident angles relative to plane 151 may be between about +10° to about Between +20°. Additionally, some ion tracks, such as paths 169 and 171, may cross each other.

In one embodiment, the angle of incidence (θ) may range from about +89° to about -89° (excluding 0°), depending on a number of factors including, but not limited to, directional elements Positioning of 113, horizontal spacing (G) between insulators 112, 114, vertical spacing (Z) of insulators 112, 114 above plane 151, dielectric constant of directional element 113 and insulators 112, 114, and other plasma Processing parameters.

The range of incident angles can be selected based on the aspect ratio of the 3D features on the substrate 138. For example, the sidewalls 147 of the trenches 144 (detailed dimensions for clarity) can be more uniformly processed by the ions 101 (compared to conventional plasma processing apparatus and programs). The aspect ratio can be defined as the relationship between "pitch between sidewalls 147" and "height of sidewalls 147 extending from substrate 138" that can determine the angle at which ions 101 are provided to provide sidewalls. More uniform processing on 147. The aspect ratio of the 3D structure can be provided by controller 190 prior to performing the ion bombardment process. Alternatively, the sensor in device 100 can determine the aspect ratio of the 3D structure prior to performing the ion bombardment process. In either example, the ion bombardment angle can be selected to respond to the aspect ratio of the 3D structure.

For example, the first range of the vertical plane 151 and the angle of incidence suitable for striking the sidewall 147 may be between about +60° to about +90°, and the second range of incident angles may be between about -60° to about - Between 90°. In one embodiment, the first range of the vertical plane 151 and the angle of incidence suitable for striking the sidewall 147 may be between about -70° and about -80°, while the vertical plane 151 is adapted to strike the angle of incidence of the sidewall 147. The second range can be between about +70° to about +80°. In one embodiment, the angle at which ions 101 are provided may be selected to avoid contact with material beneath sidewall 147, which in one embodiment is substrate 138 in one embodiment or an insulator in another embodiment.

The device 100 described above can be controlled by a processor-based system controller, such as the controller 190. For example, controller 190 can be configured to control the flow of various precursor gases and purge gases from a gas source, such as gas source 188, at different stages of the substrate processing program. The controller 190 includes a programmable central processing unit (CPU) 192 (which can be operated in conjunction with the memory 194 and a plurality of storage devices), an input control unit, and a display unit (not shown), such as a power supply, a clock, Cache storage, input/output (I/O) circuitry, and the like, the components described above couple various components of device 100 to assist in controlling substrate processing. The controller 190 also includes hardware for monitoring substrate processing through sensors in the device 100, the sensors including sensors that monitor precursors and purge gas streams. Measuring system parameters (such as substrate temperature and position, Other sensors of chamber atmosphere pressure and similar parameters may also provide information to controller 190.

To assist in controlling the apparatus 100 described above, the CPU 192 can be any form of a general purpose computer processor that can be used in an industrial facility, such as a programmable logic controller (PLC), for controlling various chambers and Subprocessor. The memory 194 is coupled to the CPU 192 and the memory 194 is non-transitory and can be one or more of the easily accessible memories, such as random access memory (RAM), read only. Memory (ROM), floppy disk, hard drive, or any other form of local or remote digital storage device. The support circuit 196 is coupled to the CPU 192 to support the processor in a conventional manner. Depositing, etching, implanting, and other processes are generally stored in memory 194, typically as a software routine. The software routine can also be stored in the second CPU (not shown) and/or executed by the second CPU, which is located at the far end of the hardware controlled by the CPU 192.

Memory 194 is in the form of a computer readable storage medium containing instructions that, when executed by CPU 192, facilitate operation of device 100. The instructions in memory 194 are in the form of a program product such as a program for implementing the methods disclosed herein. The code can conform to any of a number of different programming languages. In one example, the disclosure of the present disclosure can be implemented as a program product stored on a computer readable storage medium for use with a computer system. The program of the program product defines the functionality of an embodiment, including the methods described herein. Illustrative computer readable storage media include, but are not limited to: (i) non-writable storage media, such as a read-only memory device in a computer, such as a CD-ROM disc that can be read by a CD-ROM drive, flashing Memory, ROM a wafer, or any type of solid non-volatile semiconductor memory, information permanently stored on the non-writable storage medium; and (ii) a writable storage medium, such as a floppy disk in a floppy disk drive, or a hard disk drive , or any form of solid state random access semiconductor memory, the changeable information is stored on the writable storage medium. Such computer readable storage media, when piggybacked with computer readable instructions (these instructions indicate the functionality of the methods described herein), are embodiments of the present disclosure.

2A through 2C are cross-sectional views of a portion of the substrate illustrating the bidirectional angular ion bombardment utilized by the embodiments disclosed herein. 2A depicts a 3D feature 200 that includes a substrate 202 having a gate 204 formed on the substrate 202 and a gate dielectric 206 layer formed on the gate 204. In some embodiments, gate 204 can be a dummy gate. In other embodiments, the gate 204 can represent a fin structure having a gate dielectric 206 disposed thereon.

Bi-directional angular ion bombardment is performed by directing ions from the first region 210 toward the gate dielectric 206. The plasma can travel along one or more paths 211 that are selected to attack the vertical portion 212 of the gate dielectric 206 and to avoid ion bombardment of the material 214 under the gate dielectric 206. Similarly, ions can be accelerated from the second region 208 toward the gate dielectric 206. The plasma can travel along one or more paths 209, attacking the vertical portion 212 of the gate dielectric 206 and avoiding bombarding the material 214 under the gate dielectric 206.

In a bi-directional angular ion bombardment process, the angle or orbit at which ions are directed toward the substrate 202 is selected based on the aspect ratio of the 3D features 200. The aspect ratio can be defined as "pitch length 220" versus "gate extending above substrate 202" The ratio of the height of the dielectric 206 to 222". In this regard, ions traveling along paths 211, 209 can strike any point along the vertical portion 212 between the bottom region 216 and the top region 218 of the gate dielectric 206.

Figure 2B schematically illustrates the structure of Figure 2A after the gate material 204 (such as a dummy gate) has been removed. The surface of the gate dielectric 206 of the adjacent adjacent gate material 204 is exposed. The bi-directional angular bombardment process can be performed on the exposed surface in the manner described above for Figure 2A.

FIG. 2C schematically illustrates another embodiment of a bidirectional angular ion bombardment process. In this embodiment, the fin structure 203 extends from the substrate 202 and the insulator material 201, which is disposed adjacent the lower portion of the fin structure 203. The gate dielectric is deposited over the fin structure 203 on the sidewall 212 and the upper surface 213. Side wall 212 and upper surface 213 are subjected to ion bombardment. As illustrated, bi-directional ion bombardment can strike the gate dielectric 206 along the entire sidewall 212 and the upper surface 213.

3A through 3C depict a procedure for forming a 3D structure in accordance with one embodiment described herein. A substrate 302 having a fin structure 310 extending from the substrate 302 can be provided as depicted in FIG. 3A. An insulator 320, such as SiO ₂ or SiN, may be formed on the substrate 302 such that a portion of the fin structure 310 remains extended beyond the insulator 320.

Next, a gate dielectric layer 350 is formed over the insulator 320 and the fin structure 310, as depicted in FIG. 3B. The gate dielectric layer 350 can serve as a spacer between the fin structure 310 and the subsequently deposited gate. The gate dielectric layer 350 can be, for example, Al ₂ O ₃ , SiN, BN, SiCN, or SiO ₂ , or other dielectric material that can be processed using the processes disclosed herein to reduce the K value while maintaining the gate dielectric layer. The thickness of the 350 is integral. The gate dielectric layer 350 can be deposited over the insulating layer 320 and the fin structure 310 in a conformal manner by a suitable process such as CVD, ALD, PVD, or the like. In one example, the tantalum nitride layer can be deposited by CVD to form the gate dielectric layer 350. Silica precursor (such as SiH ₄₎ and nitrogen precursor (such as N ₂ or NH ₃₎ becomes available energy plasma and is deposited by a CVD process to form a gate dielectric 350.

After the gate dielectric layer 350 has been formed, one or more ion implantation processes may be performed to modify the K value of the gate dielectric layer 350. In one embodiment, a light ion implantation process can be performed on the gate dielectric layer 350. In this embodiment, a light ion species (such as hydrogen) or a halide ion (such as He or Ne) can be implanted into the gate dielectric layer 350 to create holes within the dielectric material. The implanted light ions can form bubbles or voids in the dielectric material, and the K value of the dielectric material is reduced by changing the physical structure of the gate dielectric layer 350. After light ion implantation, a low temperature anneal is optionally performed to diffuse light ions from the gate dielectric layer 350, as appropriate. For example, the untreated SiN gate dielectric layer 350 can exhibit a K value of about 7.5. The gate dielectric material 350 after performing the light ion implantation process can exhibit a K value of about 5.1. Thereby, the K value of the dielectric material can be lowered.

Various aspects of the light ion implantation process can be controlled to adjust the K value. The size of the holes formed within the gate dielectric layer 350 can be controlled by ion energy and ion flux/dose. In one example, a cesium ion implant can be provided at a dose of between about 1 x 10 ¹⁵ (ions/cm ² ) to about 1 x 10 ¹⁹ (ions/cm ² ), such as about 2 x 10 ¹⁷ (ions/cm ² ). In this regard, the sputum dose regime maintains the front implant thickness of the gate dielectric layer 350. The light ion species used can also reduce sputtering of the gate dielectric material 350 from the surface of the fin structure 310. The temperature at which the light ion implantation process is performed may also affect the resulting structure by diffusing ions implanted in the gate dielectric layer 350 out of the gate dielectric layer 350 to form the resulting voids, in some embodiments. The gap may be empty filled with helium. Processing parameters (especially such as chamber pressure, gas flow rate, and plasma source power) can be selected to enhance the light ion implantation process.

Moreover, the impact angle of the light ion species striking the gate dielectric layer can be selected based on the aspect ratio of the features formed by the fin structure 310. For bombardment on the sidewall 332 of the gate dielectric material 350, the adjustment of the bombardment angle can be selective. In this regard, implantation on the region 354 below the gate dielectric material 350 can be avoided. However, the gate dielectric layer 350 disposed on the top region 334 of the fin structure can be bombarded by ions because the bombardment of the top region 334 is not determined by angular bombardment depending on the aspect ratio. The angle of implantation can be determined by the aspect ratio of features (which can be fin structure 310).

A bombardment angle having a substantially vertical orientation (90°) with respect to the surface of the gate dielectric layer 350 can implant ions of greater depth than a implant angle having a substantially parallel orientation (0°). The continuum of the implant angle between the vertical and parallel limits (mainly determined by the aspect ratio of the features to avoid shadowing effects) can be utilized to select the depth of ion implantation. Similarly, the molecular weight of the ions selected for bombardment helps determine the depth of the implant. Ions with smaller molecular weights can be implanted deeper than ions with larger molecular weights. For example, assuming that the other implant variables are the same, the hydrogen ions will penetrate the gate dielectric layer 350 deeper than the helium ions. In various embodiments, the resulting light ion implant depth can be between about 1 nm and about 8 nm. The implant energy used to implant ions also affects the depth of the implant. For example, high implant energy will be provided for deeper implants.

After the light ion species has been implanted, a thermal annealing process can be performed at a temperature below about 400 ° C (such as about 350 ° C) to activate the formation of voids within the gate dielectric material.

In another embodiment, a direct ion implantation process containing boron and/or carbon ions can be performed after depositing the gate dielectric material 350. In this embodiment, various boron-containing and carbon-containing precursors can be ionized, and boron and/or carbon ions can be implanted into the dielectric material layer 350. In one example, only boron ions can be implanted, and in another example, only carbon ions can be implanted. In certain embodiments, boron and carbon containing ions can be implanted.

Similar to the light ion implantation process, the bidirectional angular ion bombardment process can be specified by the aspect ratio of the feature. The processing parameters used to perform the direct ion implantation process can be selected to enhance direct ion implantation. In one example, the ion precursor is provided at a rate of about 25 sccm and the ion precursor energy is provided at an RF power of about 1500 W, the precursor being provided at a dose of about 5 x ^{10 16} ions/cm ² and the process is at about 350 ° C. The temperature is executed. The direct ion implantation process can optionally be performed at elevated temperatures that will alter the composition of the gate dielectric layer 350 by changing the chemical composition of the material. For example, boron and/or carbon ions can act as doped gate dielectric layer 350 and establish a dielectric material with a reduced K value. After the boron and/or carbon ions have been implanted in the gate dielectric layer 350, a thermal annealing process can also be performed, which is similar to the annealing process described for the light ion implantation process.

In another embodiment, the deposition and flyback process can be performed after deposition of the gate dielectric material 350, as depicted in Figure 3B'. The term "return" can be defined as a recoil ion implantation in which ions are implanted through a gate A surface layer formed on the electrolyte drives the dopant into the gate dielectric. The deposition and flyback process can begin by depositing a thin barrier layer 360 over the gate dielectric layer 350. The barrier layer 360 can include boron and/or carbon atoms deposited on the surface of the gate dielectric layer 350. The barrier layer 360 function can provide additional protection to the fin structure 310 during subsequent ion implantation and serve as a source of implant ions. After or during formation of the barrier layer 360, the strikeback ions 362 can bombard the barrier layer 360 and push boron and/or carbon ions present in the barrier layer 360 into the gate dielectric layer 350.

The strikeback ions 362 can be the same ions as the ions used to form the barrier layer 360. In this regard, boron and/or carbon ions can be used as the barrier layer 360 and as the flyback ion 362. The use of deposition and flyback processes can also advantageously benefit from the multiplication effect. When a single hitback ion 362 strikes the barrier layer 360 but causes multiple atoms to implant into the gate dielectric layer 350, a multiplication effect is created. For example, barrier layer 360 is deposited and a strikeback ion 362 is provided to bombard the barrier layer. The bombardment ions then drive ions present in the barrier layer 360 into the gate dielectric layer 350. Due to the bombardment process, multiple ions can be implanted when a single strikeback ion 362 contacts the barrier layer. The multiplying effect can be effective to reduce the K value of the gate dielectric layer 350 and reduce the amount of ions that need to bombard the barrier layer 360.

Similar to the direct ion implantation process described above, boron ions, carbon ions, and combinations of boron and carbon ions can be implanted into the gate dielectric layer 350 by a deposition and flyback process. The implant process can be adjusted to provide the desired result by utilizing a bidirectional angular ion implantation process. For example, a 2 nm barrier layer 360 is deposited using a mixture of CH ₄ /H ₂ or B ₂ H ₆ /CH ₄ /H ₂ at a bias of about 3 kV and a dose of about 2×10 ¹⁶ cm ² . -20° angular bidirectional ion implantation. The bidirectional angular ion implantation process can depend on the aspect ratio of the characteristics of the implanted ions therein. After the boron and/or carbon ions have been implanted in the gate dielectric layer 350, a thermal annealing process can also be performed, which is similar to the annealing process described for the direct ion implantation process.

In yet another embodiment, an ion assisted deposition and doping (IADD) process can be performed after depositing the gate dielectric layer 350, as depicted in Figure 3B. The term "IADD" can refer to a deposited film/barrier. A process in which a layer is applied to the surface of a material. The process may involve directing ions to the material at a range of angles while changing the physical or chemical structure of the underlying material. In the IADD process, deposition of the barrier layer 360, breakdown of the barrier layer, and direct ion implantation can be performed simultaneously in parallel.

Here, the deposition process may utilize a suitable boron and/or carbon precursor to form a barrier layer 360 containing boron and/or carbon atoms. The strikeback ions 362 can be boron and/or carbon ions; however, the strikeback ions 362 can also be ions other than boron and/or carbon. For example, the strikeback ions 362 can be arsenic. Other incident ions 364 (such as hydrogen, boron, and carbon ions) may also be provided in conjunction with the knockback ions 362. In this example, arsenic ions can be sputtered over the barrier layer 360 and implanted within the barrier layer 360. The strikeback ions 362 can strike atoms (boron and/or carbon) of the barrier layer 360 into the gate dielectric layer 350. The deposition and knockback process can benefit from the multiplication effects described above. Although the deposition and flyback process is performed, the incident ions 364 can also be implanted directly into the gate dielectric layer 350.

The ion dose enhancement in the material being processed (gate dielectric layer 350) is maintained by the IADD process. For example, using AsH ₃ as the flyback ion source and the IADD process using H ₂ as the incident ion source provides just between 5.0 x 10 ¹⁴ (atoms/cm ² ) to about ^1.5 x 10 ¹⁵ (atoms/cm ² ). The dose is maintained for a deposition depth ranging from about 1.0 nm to about 8.0 nm. In this example, when the barrier layer 360 is sputtered away, the retention dose saturates the barrier layer 360. The thickness of the knockback ion deposit (amount) can also be a variable that controls the saturation of the dose.

The IADD process can also be adjusted to provide the desired result by utilizing a bidirectional angular ion implantation process. The bidirectional angular ion implantation process can depend on the aspect ratio of the characteristics of the implanted ions therein. The strike ions 362 and the incident ions 364 for direct implantation may be provided at a range of angles relative to the surface of the substrate 302. After the flashback ions 362 and the incident ions 364 have been implanted in the gate dielectric layer 350, a thermal annealing process similar to the annealing process described above can also be performed.

Referring now to Figure 3C, a portion of the gate dielectric layer 350 can be removed. For example, the horizontally oriented region 336 of the gate dielectric layer 350 can remain unmasked and exposed to a dry or wet etch process. The etch process will remove the gate dielectric layer 350 from the horizontally oriented region 336. FIG. 3C illustrates the resulting substrate 302 having a gate dielectric layer 350 formed overlying the fin structure 310.

In some embodiments, the light ion implantation process, direct ionation, can be performed after the gate dielectric layer 350 has been etched (rather than directly after deposition of the gate dielectric layer 350 as depicted in FIG. 2C). The implant process, the deposition and flyback process, and the IADD process (described above for Figures 3B' and 3B). The gate material (not shown) can then be deposited over the substrate to form the finish. The FinFET structure.

The methods described herein can be automated by, for example, a program that actually implements instructions on a computer readable storage medium that can be read by a machine that can execute the instructions. Universal computer is one of these machines example. A non-limiting list of suitable storage media known in the art includes devices such as readable or writable CDs, flash memory chips, various magnetic storage media, and the like.

In summary, various ion implantation processes, such as light ion implantation, direct ion implantation, deposition and flyback, and IADD, can be performed at various stages of 3D structure formation, in accordance with various embodiments. The ion implantation process can benefit from the use of bidirectional angle implants to more precisely adjust certain aspects of the ion implantation process. All of the processes described herein can be performed at room temperature or elevated temperatures. Some processes can be performed at room temperature or at elevated temperatures, depending on the desired implant characteristics. The ion implantation process can advantageously reduce the K value of the gate dielectric material while maintaining the integrity of the gate dielectric without increasing the thickness of the gate dielectric material. The resulting gate dielectric material can reduce the overall gate height while minimizing parasitic capacitance, while providing improved microelectronic components.

While the foregoing is directed to the embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the scope of the disclosures of the present disclosure, and the scope of the disclosure is determined by the scope of the appended claims.

200‧‧‧ characteristics

202‧‧‧Substrate

204‧‧‧ gate

206‧‧‧gate dielectric

208‧‧‧Second area

209‧‧‧ Path

210‧‧‧First area

211‧‧‧ Path

212‧‧‧ side wall

214‧‧‧Materials

216‧‧‧ bottom area

218‧‧‧ top area

220‧‧‧pitch length

222‧‧‧ Height

Claims (20)

A method of forming a gate, comprising the steps of: transferring a substrate to a plasma processing apparatus, the substrate having a 3D structure, the 3D structure comprising a gate dielectric structure, the gate dielectric The structure is configured to be adjacent to a dummy gate structure; and the device exposes a vertically oriented portion of the gate dielectric structure to the ions, wherein the one or more ion bombardment angles are one of the 3D structures Choose from a wide aspect ratio. The method of claim 1, wherein the gate dielectric structure comprises a material selected from the group consisting of boron nitride, tantalum nitride, tantalum nitride carbon, and germanium dioxide, and The dummy gate structure includes a crucible material. The method of claim 1, wherein the ions exposed to the vertically oriented portion of the gate dielectric structure are selected from the group consisting of He ⁺ , H ₃ ⁺ , H ₂ ⁺ , H ⁺ , Ne ⁺ , F ⁺ , CF A group consisting of _x ⁺ , CH _x ⁺ , CH _x ⁺ , B ⁺ , BF ₂ ⁺ , B _x H _y ⁺ , Xe ⁺ , C _x H _y ⁺ , molecular carbon, boron, and boron carbide. The method of claim 1 wherein the plasma produces at least one void within the gate dielectric structure. The method of claim 1, wherein a first bombardment angle is between about +10° and about +20°, and wherein a second bombardment angle is between about -10° and about -20°. The method of claim 1 further comprising the step of exposing the gate dielectric structure to ions at a temperature of less than about 400 ° C in the apparatus. The method of claim 1, further comprising the step of etching the gate dielectric structure prior to exposing the gate dielectric structure to ions. The method of claim 1 further comprising the step of removing the dummy gate structure prior to exposing the gate dielectric structure to ions. A method of forming a gate includes the steps of: transferring a substrate to a plasma processing apparatus, the substrate having a 3D structure, the 3D structure including a gate dielectric structure, the gate dielectric structure Arranged adjacent to a dummy gate structure; forming a barrier layer on the gate dielectric structure; and exposing the barrier layer to ions in the device, wherein one or more ion bombardment angles are 3D The aspect ratio of the structure is chosen. The method of claim 9, wherein the barrier layer comprises at least one of carbon and boron. The method of claim 9, wherein the plasma comprises at least one of boron, carbon, and arsenic. The method of claim 9, wherein the step of forming a barrier layer and the step of exposing the barrier layer to ions are performed simultaneously. The method of claim 9, further comprising the step of removing the dummy gate structure before forming a barrier layer on the gate dielectric structure and exposing the barrier layer to ions. A method of forming a gate includes the steps of: transferring a substrate to a plasma processing apparatus, the substrate having a 3D structure, the 3D structure including a gate dielectric structure, the gate dielectric structure Disposed on at least two fin structures; the device exposes the gate dielectric structure to ions, wherein one or more ion bombardment angles are selected in response to an aspect ratio of the fin structure. The method of claim 14, wherein the gate dielectric structure comprises a material selected from the group consisting of boron nitride, tantalum nitride, tantalum nitride carbon, and germanium dioxide, and The at least two fin structures comprise a stack of materials. The method of claim 14, wherein the ions exposed to the gate dielectric structure are selected from the group consisting of He ⁺ , H ₃ ⁺ , H ₂ ⁺ , H ⁺ , Ne ⁺ , F ⁺ , CF _x ⁺ , CH _x a group consisting of ⁺ , CH _x ⁺ , B ⁺ , BF ₂ ⁺ , B _x H _y ⁺ , Xe ⁺ , C _x H _y ⁺ , molecular carbon, boron, and boron carbide. The method of claim 14, wherein a first impact angle is between about +10° and about +20°, and wherein a second impact angle is between about -10° and about -20°. The method of claim 14, wherein the step of exposing the gate dielectric structure is performed at a temperature below about 400 °C. The method of claim 14, further comprising the step of etching the gate dielectric structure prior to exposing the gate dielectric structure to ions. The method of claim 14, further comprising the step of forming a barrier layer overlying the gate dielectric structure, wherein the barrier layer comprises at least one of boron and carbon.