TW201528273A - Semiconductor memory device and programmable method for flash memeory - Google Patents

Abstract

A new programming method of avoiding deteriorating an insulating film in a memory cell is provided. The programming method for flash memory of the present invention makes a string including programming units which were already programmed to be electrically isolated with a bit line BL, makes a strong including non-programming units which were not programmed to be electrically connected with the bit line BL, applies a programming voltage to selected bit lines and applies a pass voltage to un-selected bit lines. Moreover, during a period for applying the programming voltage, the P-well is generated carriers and hot carriers are injected into the memory cell depending on an accelerating electric field made by a depletion region.

Description

Semiconductor memory device and stylized method of flash memory

The present invention relates to a semiconductor memory device, and more particularly to a stylized method for a NAND type flash memory.

A typical NAND type flash memory includes a memory array formed with a plurality of NAND strings, and the NAND string includes a plurality of memory cells connected in series and a bit line selection transistor connected to both ends thereof The source line selects the transistor. 1 is a circuit diagram showing the composition of a NAND string formed in a memory array. In the memory block, a plurality of NAND strings (hereinafter referred to as cell units NU) in which a plurality of memory cells are connected in series are formed in the row and column direction. In the example shown, the composition of one cell group NU includes 32 memory cells MCi (i = 0, 1, ..., 31) connected in series and bit line selection power connected to both ends thereof. The crystal TD and the source line select the transistor TS. The drain of the bit line selection transistor TD is connected to its corresponding one bit line BL, the source of the source line selection transistor TS is connected to the common source line SL. The control gate of the memory cell MCi is connected to the word line WLi. The gates of the bit line selection transistor TD and the source line selection transistor TS are respectively connected to the selection gate lines SGD and SGS extending in parallel with the word line WLi.

In general, the memory cell includes a tunneling oxide layer having a source/drain formed in an N-type diffusion region in the P well, a channel formed between the source/drain, and a tunnel oxide. A floating gate (charge accumulating layer) on the layer film and a control gate formed on the floating gate through the dielectric film. In general, when the floating gate does not accumulate charge, that is, when the data "1" is written, the threshold is negative and the memory cell is normally on. When the electrons are accumulated in the floating gate, that is, when the data "0" is written, the threshold value is shifted in the positive direction, and the memory unit is normally off.

FIG. 2 is a table showing an example of a bias voltage applied during each operation of the flash memory. In the read operation, a positive voltage is applied to the bit line, and a voltage is applied to the selected word line, and a read unselected voltage (eg, 4.5 V) is applied to the unselected word line to select the gate line. SGD and SGS apply a positive voltage (for example, 4.5 V) to turn on the bit line selection transistor TD and the source line selection transistor TS, and apply 0 V to the common source line SL. Thus, the page data of the selected word line is read out via the bit line, and it is detected whether the threshold of the read cell is higher than the voltage applied to the selected word line.

In a stylized (write) operation, a high voltage is applied to the selected word line The stylized voltage Vprg (15V~20V) applies an intermediate potential (for example, 10V) to the unselected word line, turns on the bit line selection transistor TD, and turns off the source line selection transistor TS. A potential corresponding to the material of "0" or "1" is supplied to the bit line BL. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well, and the electrons of the floating gate are extracted to the substrate, thereby being erased in units of blocks. data. For a more detailed description of the NAND type flash memory, refer to Japanese Laid-Open Patent Publication No. 2011-253591.

Flash memory needs to have certain endurance (data rewriting times) or data retention characteristics. When FMN tunneling (Fowler-Nordheim tunneling) current flows through the gate oxide layer, if a part of electrons are trapped by the oxide layer and the electron is stored in the oxide layer, even if a voltage is applied to the control gate, the FN tunneling current is difficult. Flowing through, this will limit the number of data rewrites. In addition, if the charge stored in the floating gate leaks over time, the stored data is lost. Therefore, it is desirable to make the characteristics of the insulating layer surrounding the floating gate not deteriorate. In the conventional stylized mode, a high voltage is applied to the control gate so that the substrate (P well) is 0V, and a high electric field is applied to the tunnel oxide layer to inject electrons by the FN tunneling effect, however, the oxidation is performed. Applying a high electric field to the layer and repeating the stylization and erasing operations will result in a decrease in the reliability of the oxide layer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above conventional problems and to provide a stylized method and semiconductor memory device for improving the reliability of a memory cell insulating layer.

The present invention provides a stylized method for a flash memory device, wherein the flash memory includes: a memory array, and the memory array is formed in a first semiconductor region of a first conductivity type a plurality of NAND type cell groups; wherein the stylization method comprises: electrically separating a cell group including the stylized unit from a corresponding bit line, and electrically coupling the cell group not including the stylized unit to a corresponding bit a line; applying a stylized voltage to the selected word line, and applying a non-selected voltage to the unselected word line; generating a carrier in the first semiconductor region during the application of the stylized voltage; And injecting a hot carrier into the stylized unit.

Another embodiment of the present invention provides a semiconductor memory device including: a memory array formed in a first semiconductor region having a first conductivity type; and a plurality of cell groups formed in the memory array, wherein the plurality of cells A unit group has a plurality of memory units connected in series, and one of the plurality of unit groups includes a stylized stylized unit; wherein, during a stylization, the unit group including the stylized unit is caused Electrically separating from the bit line, coupling the group of cells not including the stylized unit to a bit line, applying a stylized voltage to the selected word line, and applying a non-selected word line to the non-selected word line Selecting a voltage and generating a carrier in the first semiconductor region; and during the stylizing, the cell group including the stylizing unit is formed with a depletion region, and the carrier is formed in the depletion region A hot carrier is injected into the stylizing unit.

According to the present invention, it can be programmed by injecting a hot carrier, whereby the electric field applied to the insulating layer of the memory cell can be reduced as compared with the case of injecting electrons by FN tunneling, thereby suppressing deterioration of the insulating layer. Improve reliability.

S100~S108‧‧‧Steps

10‧‧‧Flash memory

100‧‧‧ memory array

110‧‧‧Input and output buffers

120‧‧‧ address register

130‧‧‧data register

140‧‧‧ Controller

150‧‧‧word line selection circuit

160‧‧‧Page buffer/sense circuit

170‧‧‧ column selection circuit

180‧‧‧Internal voltage generation circuit

200, 330‧‧‧P well area

210, 350‧‧ ‧ Vacant Zone

220, 322, 332‧‧‧ contact areas

230, 360‧‧‧ reverse layer

300‧‧‧矽 substrate

310A‧‧‧ surrounding area

310B‧‧‧Array area

320‧‧‧N well area

340, BLK (0), BLK (1), ..., BLK (m) ‧ ‧ blocks

Ax‧‧‧ address information

Ay‧‧‧Listing address information

BL, BL0, BL1, ..., BLn-1, BLn‧‧‧ bit lines

C1, C2, C3‧‧‧ control signals

SL‧‧‧Common source line

TD, TD-1, TD-2, TD-3‧‧‧ bit line selection transistor

TS‧‧‧Source line selection transistor

SGD, SGS‧‧‧ select gate line

WL, WL0~WL31‧‧‧ character line

MC0~MC31‧‧‧ memory unit

V1, V2, Vx‧‧‧ potential

Vers‧‧‧ erase voltage

VN-well‧‧‧N well voltage

Vprg‧‧‧ stylized voltage

Vread‧‧‧ read unselected voltage

Vpass‧‧‧Unselected voltage

VP-well‧‧‧P well voltage

VBL‧‧‧ bit line voltage

VSGD‧‧‧Select the voltage of the gate line SGD

VSGS‧‧‧Select the voltage of the gate line SGS

VSL‧‧‧ Common source line SL voltage

Vth‧‧‧ threshold

Ta, Tb, Tp‧‧‧ stylized period

T1, T2, T3, T4, T5‧‧‧ moments

NU‧‧ unit group

FIG. 1 is a circuit diagram exemplarily showing the configuration of a NAND string of flash memory.

FIG. 2 is a table showing an example of a bias voltage applied during each operation of the flash memory.

FIG. 3 is a block diagram of a flash memory according to an embodiment of the invention.

Fig. 4 is a view showing the voltage applied to each portion when the flash memory is programized in accordance with the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the unit group including the stylized unit of FIG. 4.

6 is a schematic cross-sectional view showing a unit group not including a stylized unit in FIG. 4.

Figure 7 is a timing diagram based on the stylized operation of Figure 4.

Figure 8 is a flow chart showing the stylization operation of the flash memory in accordance with the second embodiment of the present invention.

9(A) and 9(B) are schematic views for explaining the stylized periods Ta and Tb according to the second embodiment of the present invention.

Fig. 10 (A) is a schematic plan view showing a wafer of a flash memory according to a third embodiment of the present invention.

Fig. 10 (B) is a partially enlarged view of a cross-sectional view taken along line A-A of Fig. 10 (A).

Fig. 11 is a view showing the voltage applied to each portion when the stylization operation is performed according to the third embodiment of the present invention.

Figure 12 is a diagram for explaining the stylized operation of the bit line BL-1 of Figure 11; Slightly sectional view.

Fig. 13 is a schematic cross-sectional view for explaining the state of the bit line BL-2 of Fig. 11 .

Figure 14 is a timing diagram based on the stylized operation of Figure 11.

Embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that in the drawings, the parts are emphasized for easy understanding, and the size and proportion of the device in the figure are not the same as the actual device specifications.

FIG. 3 is a block diagram of a flash memory according to an embodiment of the invention. It should be noted that the configuration of the flash memory shown here is merely an example, and the present invention is not necessarily limited to this configuration.

Referring to FIG. 3, the flash memory 10 includes a memory array 100 formed with a plurality of memory cells arranged in a matrix, and an input/output buffer 110 connected to the external input/output terminal I/O and held. Input and output data; address register 120, receiving address data from input/output buffer 110; data register 130, holding input and output data; controller 140, based on instruction data from input/output buffer 110 and An external control signal (not shown, for example, chip enable or address latch enable, etc.) provides a control signal C1, a control signal C2, a control signal C3, and the like for controlling each part; The word line selection circuit 150 decodes the row address information Ax from the address register 120, and selects a block and selects a word line based on the decoding result; The sensor/sense circuit 160 holds the data read from the page selected by the word line selection circuit 150 or the write data for the selected page; the column selection circuit 170, for the address from the address register 120 The column address information Ay is decoded, and the column data in the page buffer 160 is selected based on the decoding result; the internal voltage generating circuit 180 generates a voltage (program) for reading, programming, and erasing data. Voltage Vprg, unselected voltage Vpass, read unselected voltage Vread, erase voltage Vers, etc.).

The memory array 100 has a plurality of memory blocks BLK(0), BLK(1), ..., BLK(m) arranged in the column direction. In this embodiment, the page buffer/sense circuit 160 is disposed at one end of the block, but the present invention is not limited thereto. In a possible embodiment, the page buffer/sense circuit 160 may also be configured in the block. The other end or both ends.

Referring to FIG. 1 and FIG. 3 simultaneously, n+1 cell groups NU are arranged in the row direction in one memory block. The cell group NU includes: a plurality of memory cells MCi (i=0, 1, . . . , 31) connected in series; a bit line selection transistor TD disposed at one end of the cell group NU and connected to the memory cell MC31 The drain side; the source line selection transistor TS is disposed at the other end of the cell group NU and is connected to the source side of the memory cell MC0. The drain of the bit line selection transistor TD is connected to the corresponding bit line BL, and the source of the source line selection transistor TS is connected to the common source line SL.

The control gate of the memory cell MCi is connected to the corresponding word line WLi; the gates of the bit line selection transistor TD and the source line selection transistor TS are respectively connected to the selection gate line SGD parallel to the word line WL. , SGS. The word line selection circuit 150 selects a memory block based on the row address Ax, and selects the memory block via the memory block The gate line SGS, SGD selectively drives the bit line selection transistor TD and the source line selection transistor TS.

The memory unit is constructed in the same manner as a general flash memory. That is, the memory cell includes a tunneling oxide layer having a source/drain formed in the N-type diffusion region in the P well, a channel formed between the source/drain, and a tunnel oxide layer. The upper floating gate (charge accumulation layer) and the control gate formed on the floating gate through the dielectric film. When the floating gate does not accumulate charge or erases the charge, that is, when the data "1" is written, the threshold is negative and the memory cell is normally on. When the electrons are accumulated in the floating gate, that is, when the data "0" is written, the threshold value is shifted in the positive direction, and the memory unit is normally off.

The present invention provides a stylized method for flash memory. In the previous stylization method, electrons from the substrate were injected into the floating gate by FN tunneling for stylization. The stylized method provided by the present invention is programmed by injecting hot electrons from the substrate into the floating gate.

Hereinafter, a first embodiment in which a program operation of a flash memory is performed in accordance with the present invention will be described. 4 is a schematic diagram showing voltages applied to respective portions when a flash memory is programmed in accordance with a first embodiment of the present invention, and FIG. 5 is a diagram showing a memory unit to be programmed in FIG. 4 (hereinafter, FIG. 6 is a schematic cross-sectional view of a unit group NU not including a stylized unit in FIG. 4, and FIG. 7 is a stylized operation according to FIG. The timing diagram shown.

Referring to FIGS. 4-6, the flash memory of the present embodiment forms a semiconductor region 200 of the P-well on the semiconductor region of the N-type germanium substrate or the N-well. When stylized, 0V is applied to the P well. A cell group NU in which NMOS transistors are connected in series is formed in the P well 200, that is, a bit line selection transistor TD, memory cells MC0 to MC31, and a source line selection transistor TS are formed. The control gate of the bit line selection transistor TD is electrically coupled to the floating gate, the selection gate line SGD is coupled to the control gate of the bit line selection transistor TD, and the bit line BL is coupled to the bit line The drain region of the transistor TD is selected, and the bit line selection transistor TD source region is commonly used as the drain region of the memory cell MC31. The word lines WL0 WL WL31 are respectively coupled to the control gates of the memory cells MC0 MC MC31. The control gate of the source line selection transistor TS is electrically coupled to the floating gate, the selection gate line SGS is coupled to the control gate of the source line selection transistor TS, and the source line selects the drain region of the transistor TS The common source line SL is coupled to the source region of the source line selection transistor TS.

Fig. 4 shows an example of selecting a word line WL29 in the selected block and programming the page. Referring to FIG. 4, a positive potential (ie, VSGD>0V) is applied to the selection gate line SGD of the bit line selection transistor TD, and 0V is applied to the selection gate line SGS of the source line selection transistor TS (VSGS=0V). ). A positive potential (VBL>0 V) is applied to the bit line BL corresponding to the cell group NU including the stylized unit, and 0 V (VBL=0 V) is applied to the bit line BL corresponding to the cell group NU not including the stylized unit. A 0V or positive potential is applied to the common source line SL, for example, 1.2V is applied.

Here, the relationship between the voltage VSGD applied to the selection gate line SGD and the voltage VBL applied to the bit line is set as follows. That is, the bit line selection transistor TD corresponding to the cell group NU including the stylized unit is turned off, and the bit line selection transistor TD corresponding to the cell group NU not including the stylized unit is turned on. Specifically, the voltage VSGD applied to the selection gate line SGD is set to VBL+Vth>VSGD>0V. Here, Vth is the threshold value of the bit line selection transistor TD. Therefore, the bit line selection transistor TD connected to the bit line to which VBL>0V is applied is turned off, and the bit line selection transistor TD connected to the bit line to which VBL=0V is applied is turned on. . Therefore, the source line selection transistor TS is turned off, whereby the cell group NU including the stylized unit is electrically disconnected from the bit line BL and the common source line SL, and the unit group NU not including the stylized unit is electrically disconnected. Sexually coupled to bit line BL.

A relatively high normalized voltage Vprg is applied to the selected word line WL29. The stylized voltage Vprg can be a stylized voltage (eg, a voltage below 20V) applied in conventional flash memory. A non-selected voltage Vpass is applied to the unselected word line WL. The unselected voltage Vpass is a voltage that is lower than the stylized voltage Vprg and greater than 0 V and is sufficient to cause the memory cell holding the data "0" to be turned on. At this time, the potential of the word line WL29 rises by the stylized voltage Vprg, whereby the potential of the pupil surface of the stylizing unit is boosted by the boot. Further, by applying a non-selected voltage, the potential of the surface of the memory cell connected to the unselected word line also rises a little. Thus, as shown in FIG. 5, the cell group NU including the stylized unit is floating, so that there is a gap in the vicinity of the channel and the source/drain region of the bit line selection transistor TD and the memory cells MC0 to MC31. Area 210.

On the other hand, in the cell group NU not including the stylizing unit, 0 V (VBL = 0 V) is applied to the bit line BL, and the bit line selecting transistor TD is turned on. Therefore, the inversion layer 230 is formed by the stylized voltage Vprg applied to the selected word line and the unselected voltage Vpass applied to the unselected word line, and the potential of the channel of the memory cell in the cell group NU, The potential is 0 V as the bit line potential, and no depletion region is formed in the channel of the cell group NU not including the stylized unit.

Next, as shown in FIG. 7, a negative voltage (VSL<0 V) is applied to the common source line SL, and a negative voltage (VSGS<0 V) is applied to the selection gate line SGS. In the preferred embodiment, the stylized period Tp for applying a negative voltage to the common source line SL and the selection gate line SGS is the same. Alternatively, a negative voltage can be applied to the select gate line SGS at the beginning of the program. Referring to FIG. 5 and FIG. 7 simultaneously, a negative voltage is applied to the contact region 220 coupled to the common source line SL, thereby forming a forward bias between the contact region 220 and the P well (Vp-well = 0 V). Flow from the contact area 220 into the P well. At this time, a negative voltage is applied to the selection gate line SGS, and thus the source selection transistor TS is turned off. Electrons flowing from the contact region 220 diffuse within the P well 200 and reach the stylized unit. At this time, the potential of the surface of the germanium of the stylized unit rises, and the depletion region 210 is formed therein, so that electrons are accelerated by energy and become hot electrons through the electric field thereof, and are injected into the floating gate (charge) across the gate oxide layer. In the storage layer). If the acceleration energy of the electron is higher than the barrier of the oxide layer, electrons can be injected into the charge storage layer even if the electric field of the oxide layer is not too high, so that the electric field transmitted through the oxide layer is lowered to suppress the oxide layer. Deterioration. Next, please refer to FIG. 6 and FIG. 7 at the same time, since no depletion zone is formed in the cell group not including the stylized unit, Heat electronic. Further, if the stylized voltage Vprg applied to the selected word line WL29 is not too high, electron injection due to FN tunneling does not occur in the charge storage layer of the corresponding memory cell.

In the erase operation of the flash memory, a high voltage erase voltage is applied to the P well of the selected block, and 0 V is applied to all the word lines in the block, which is maintained in the charge storage layer at this time. Electrons are released to the surface of the crucible by an oxide layer between the surface of the crucible and the charge storage layer. However, when the erase operation is performed, if the electric field of the oxide layer is high, the reliability of the oxide layer of the memory cell is deteriorated. At this time, if the erasing time is lengthened and the electric field to the oxide layer is lowered, the deterioration of the reliability of the oxide layer can be reduced. For example, when the erasing time is, for example, about 0.1 sec, the electric field of the oxide layer can be reduced to about 2/3, thereby suppressing the deterioration of the reliability of the oxide layer.

Further, in the above embodiment, the negative voltage is applied to the diffusion region 220 to which the common source line SL is connected, but the negative voltage does not have to be applied via the common source line SL. For example, another N-type diffusion region may be formed in the P-well 200, and a negative voltage for biasing the forward bias may be applied to the diffusion region. In this case, it is not necessary to apply a negative bias to the common source line SL. Pressure.

Next, the stylized operation of the flash memory according to the second embodiment of the present invention will be described. Figure 8 is a flow chart showing the stylization operation of the flash memory in accordance with the second embodiment of the present invention. This stylized operation can be performed, for example, by controller 140 (Fig. 3). Referring to FIG. 8, the controller 140 receives the stylized command and decodes the command (S100) to start stylization. Obtaining the programized row address Ax (S102) from the address information received after the stylized command, It is also determined whether the row address Ax is greater than a threshold (S104). The threshold value is set in accordance with the number of memory cells constituting the cell group NU. For example, when the cell group NU has 32 memory cells, the threshold value can be set to, for example, half of the number of the memory cells (i.e., 16). In other words, it is determined whether the distance between the stylized unit and the source line is greater than half of the number of memory cells.

Referring to FIG. 9(A), the controller 140 sets a stylized period in which a negative bias voltage is applied to the common source line SL when the row address Ax does not reach the threshold value, that is, when it is relatively close to the common source line SL. Tp = Ta (Fig. 8, S106). On the other hand, referring to FIG. 9(B), when the row address Ax is larger than the threshold value, that is, when it is relatively far from the common source line SL, it is set as a stylized period in which a negative bias voltage is applied to the common source line SL. Tp = Tb (Tb > Ta) (Fig. 8, S108). When the position of the stylizing unit is away from the common source line SL, the distance or time of electron diffusion becomes long. Therefore, by setting the stylized periods Ta and Tb corresponding to the diffusion distance, the unevenness of the amount of electrons injected into the stylizing unit is suppressed, whereby the threshold distribution width of the memory unit can be narrowed.

In the above embodiment, the stylized periods Ta and Tb are set depending on whether or not the row address Ax is greater than the threshold value. However, the stylized period may be set to be further subdivided. For example, if the number of memory cells included in the cell group NU is as large as 64 or 128, the difference in diffusion distance from the source line to the stylized cell becomes larger. Therefore, a plurality of thresholds may be prepared. For example, the row address Ax is determined to correspond to the four group of word lines WL0 to WL15, the word lines WL16 to WL31, the word lines WL32 to WL47, and the word lines WL48 to WL63. A group, and select the matching stylization period from the four stylization periods Ta<Tb<Tc<Td.

Next, a third embodiment of the present invention will be described. Fig. 10 (A) is a schematic plan view showing a wafer of a flash memory according to a third embodiment of the present invention, and Fig. 10 (B) is a partially enlarged view taken along line A-A of Fig. 10 (A). Referring to FIG. 3 and FIG. 10(A) simultaneously, an address register 120, a data register 130, a controller 140, a word line selection circuit 150, and a page buffer are formed in the peripheral area 310A of the substrate 300. The sensing circuit 160, the column selection circuit 170, the internal voltage generating circuit 180, and the like. The substrate 300 is, for example, a P-type germanium substrate. A memory array 100 is formed in the array region 310B. In the array region 310B, an N well region 320 is formed on the substrate 300, and a P well region 330 is formed in the N well region 320. A method of forming the N well region 320 and the P well region 330 is, for example, an ion implantation method. The P-well region 330 defines a memory block 340 in which a plurality of cell groups NU as shown in FIG. 1 are disposed.

11 is a schematic view showing voltages applied to respective portions when a program operation is performed according to a third embodiment of the present invention, and FIG. 12 is a schematic cross-sectional view for explaining a stylized operation of the bit line BL-1 of FIG. Fig. 13 is a schematic cross-sectional view for explaining the state of the bit line BL-2 of Fig. 11, and Fig. 14 is a timing chart according to the stylized operation of Fig. 11.

Referring to FIG. 14, at time t1, V2 is applied to the bit line corresponding to the cell group including the stylized unit, and V1 is applied to the bit line corresponding to the other cell group not including the stylized unit. In a preferred aspect, V1 is a potential (V1 ≧ Vx) equal to or higher than the potential Vx of the forward bias applied to the P well region 330 during stylization, and V2 is a potential higher than V1 ( V2>V1). At time t1, to the P well area Field 330 applies 0V, applying a potential of VN-well to N-well region 320. The potential of the VN-well is preferably Vx > VN-well ≧ 0V.

Referring to FIG. 14, at a timing substantially the same as the potential of V1 or V2 applied to the bit line BL, a positive potential (VSGD) is applied to the selected gate line SGD of the bit line selection transistor TD of the selected block. 0V), and 0V (VSGS = 0V) is applied to the selection gate line SGS of the source line selection transistor TS. The relationship between the potential VSGD applied to the selection gate line SGD and the potentials V1, V2 applied to the bit line is set such that the bit line selection transistor TD corresponding to the bit line to which V2 is applied is turned off, and The bit line selection transistor TD corresponding to the bit line to which V1 is applied is turned on. Specifically, the potential VSGD of the selection gate line SGD of the bit line selection transistor TD is set to Vth + V1 ≦ VSGD < Vth + V2. Here, Vth is the threshold value of the bit line selection transistor TD. Therefore, the bit line selection transistor TD connected to the bit line to which V2 is applied is turned off, and the bit line selection transistor TD connected to the bit line to which V1 is applied is turned on. Further, since the source line selection transistor TS is off, the cell group NU corresponding to the bit line to which V2 is applied is electrically disconnected from the bit line BL and the common source line SL, and is applied with V1. The cell group NU corresponding to the bit line is electrically coupled to the bit line BL.

Fig. 11 is a view showing the voltage applied to each portion when the stylization operation is performed according to the third embodiment of the present invention. Referring to FIG. 11, V2 is applied to the bit line BL-1 to disconnect the bit line selection transistor TD-1 connected to the bit line BL-1, and the corresponding cell group NU is floating. On the other hand, V1 is applied to the bit lines BL-2 and BL-3, and the bit line selection transistors TD-2 and TD-3 connected to the bit lines BL-2 and BL-3 are selected. When it is turned on, the corresponding cell group NU is electrically connected to the bit lines BL-2 and BL-3.

Next, at time t2, a higher normalized voltage Vprg is applied to the selected word line, and a non-selected voltage Vpass is applied to the unselected word line. The stylized voltage Vprg and the unselected voltage Vpass are applied until time t5. The stylized voltage Vprg can be set to a stylized voltage (for example, a voltage lower than 20V) applied in a conventional flash memory. Further, the unselected voltage Vpass is a potential of a magnitude lower than the stylized voltage Vprg and sufficient to turn on the memory cell holding the data "0". As shown in FIG. 11, the program voltage Vprg is applied to the selected word line WL29, and the unselected voltage Vpass is applied to the other non-selected word lines.

At time t3 to time t4 in the period in which the stylized voltage Vprg and the unselected voltage Vpass are applied, a potential Vx higher than the N well region 320 is applied to the P well region 330 to form a forward bias. Thus, the material "0" is written to the selected stylized unit.

Fig. 12 is a schematic cross-sectional view for explaining a stylized operation of the bit line BL-1 of Fig. 11 . Referring to FIG. 12, a potential VN-well is applied to the contact region 322 of the N-well region 320, and a potential Vx higher than VN-well is applied to the contact region 332 of the P-well region 330, and the P-well region 330 and the N-well region 320 are applied. The junction between them becomes a forward bias, and electrons are injected from the N well region 320 into the P well region 330. At this time, since the cell group NU corresponding to the bit line to which the potential V2 is applied is in the floating state, the potential of the pupil surface of the stylized unit to which the stylized voltage Vprg is applied rises. Further, the potential of the surface of the memory of the memory cell to which the unselected voltage Vpass is applied also rises a little. As described above, as shown in FIG. 12, the depletion region 350 is formed in the channel of the memory cells MC0 to MC31 corresponding to the bit line to which V2 is applied. At this time, from N The well region 320 is injected into certain electrons of the P well region 330, and the depletion region 350 deep in the channel of the stylized unit is accelerated by the electric field and injected into the floating gate (charge storage layer) of the stylized unit. Thus, the threshold value of the stylized unit is shifted in the positive direction, and the data "0" is written.

Fig. 13 is a schematic cross-sectional view for explaining the state of the bit line BL-2 of Fig. 11; In the period in which the Vx potential is applied to the P well region 330, electrons are injected from the N well region 320 to the P well region 330 as in the case of FIG. When the V1 potential is applied to the bit line BL-2, the bit line selection transistor TD-2 is turned on, and thus the inversion layer 360 is formed in the channel of the memory cell of the cell group NU, the channel The potential becomes the same potential as V1. When some electrons from the N-well region 320 reach the vicinity of the channel of the memory cell to which the stylized voltage Vprg (corresponding to the word line WL29) is applied, the electrons are not accelerated by the electric field because no depletion region is formed in the channel. Therefore, electrons are not injected into the floating gate of the memory cell corresponding to the selected word line WL29. Therefore, the threshold is unchanged and the data is "1".

In the present embodiment, the P well region 330 in the array region 310B is divided so that when the selected block is programmed, the potential of the P well region including the selected block is compared with the N well region 320. The positive potential and the other P well regions are fixed to 0V during stylization, reducing the forward current flowing from the N well region 320 to the P well region 330.

Although the first embodiment to the third embodiment have been described in detail, the present invention includes the first embodiment to the third embodiment, and further includes the first embodiment. The combined aspect of the example to the third embodiment. For example, in the third embodiment, as in the case of the second embodiment, the application period of the forward bias voltage applied to the P well region 330 may be changed in accordance with the position of the programmed row address.

The present invention is not limited to the specific embodiment, and various modifications and changes can be made without departing from the spirit and scope of the invention.

10‧‧‧Flash memory

100‧‧‧ memory array

110‧‧‧Input and output buffers

120‧‧‧ address register

130‧‧‧data register

140‧‧‧ Controller

150‧‧‧word line selection circuit

160‧‧‧Page buffer/sense circuit

170‧‧‧ column selection circuit

180‧‧‧Internal voltage generation circuit

Ax‧‧‧ address information

Ay‧‧‧Listing address information

BLK (0), BLK (1), ..., BLK (m) ‧ ‧ blocks

C1, C2, C3‧‧‧ control signals

Vers‧‧‧ erase voltage

Vprg‧‧‧ stylized voltage

Vread‧‧‧ read unselected voltage

Vpass‧‧‧Unselected voltage

Claims (18)

A method of programming a flash memory, the flash memory comprising a memory array, wherein the memory array is formed with a plurality of NAND type cell groups in a first semiconductor region of a first conductivity type, and the fast The flash memory staging method is characterized in that: the unit group including the stylized unit is electrically separated from the corresponding bit line, and the unit group not including the stylized unit is electrically coupled to the corresponding bit line; Applying a stylized voltage to the selected word line and applying a non-selected voltage to the unselected word line; generating a carrier in the first semiconductor region during application of the stylized voltage; The stylized unit injects a hot carrier. The method of staging a flash memory according to claim 1, wherein the step of generating the carrier comprises forming a forward bias of the first semiconductor region. The method for staging a flash memory according to claim 2, wherein the step of forming a forward bias comprises: applying a first voltage to the first semiconductor region; and forming a pair on the first A second voltage is applied to the second semiconductor region in the semiconductor region; wherein the second voltage is greater than the first voltage. A method of staging a flash memory as described in claim 1 of the patent application, Furthermore, the method includes: forming the first semiconductor region on the P-type germanium substrate; and forming a plurality of second semiconductor regions having the second conductivity type in the first semiconductor region; wherein the first conductivity type is N-type And the second conductivity type is a P type. The method of programming a flash memory according to claim 4, wherein the second semiconductor region including the stylizing unit of the plurality of second semiconductor regions is applied to the first semiconductor High potential in the area. The method for programming a flash memory according to claim 1, wherein one end of the unit group is connected to a corresponding bit line via a bit line selection transistor, and the other end is via a source line. Selecting a transistor to be connected to the source line, the unit group including the stylizing unit being connected to the bit line by causing the bit line selection transistor and the source line selection transistor to be disconnected The line and the source line are electrically separated, and the unit group not including the stylizing unit is electrically coupled to the bit line by turning on the bit line selection transistor. The method for staging a flash memory according to claim 6, wherein a first potential is applied to a bit line corresponding to the cell group including the stylized unit, and the stylized unit is not included Applying a second potential to the bit line corresponding to the cell group, applying a third potential to a gate of the bit line selection transistor, and the first potential is greater than the second potential, the third potential Between the first potential and the second potential. A method of staging a flash memory as described in claim 6 of the patent application, A voltage that produces a forward bias is applied to the diffusion region of the source line selection transistor. The method of staging a flash memory according to claim 1, wherein the period during which the carrier is generated may be changed according to a position of the selected word line. The method for staging a flash memory according to claim 9, wherein the period in which the carrier is generated is the first period when the position of the selected word line is equal to or less than the first threshold. And when the position of the selected word line is larger than the first threshold, the second period is larger than the first period. The method of staging a flash memory according to claim 1, wherein a depletion region is formed in a channel of the stylizing unit. A semiconductor memory device comprising: a memory array formed in a first semiconductor region having a first conductivity type; and a plurality of cell groups formed in the memory array, wherein the plurality of cell groups have a plurality of series a memory unit, and one of the plurality of unit groups includes a stylized stylized unit; wherein, during a stylization, the unit group including the stylized unit and a corresponding bit line are Electrically separating, coupling the group of cells not including the stylizing unit to a corresponding bit line, applying a stylized voltage to the selected word line, and applying a non-selected voltage to the unselected word line And generating a carrier in the first semiconductor region; During the stylization, the group of cells including the stylized unit is formed with a depletion region, and the carrier is injected into the stylized unit by forming a hot carrier in the depletion region. The semiconductor memory device according to claim 12, further comprising: a second semiconductor region having a second conductivity type formed on the germanium substrate having the first conductivity type, wherein the first semiconductor region It is formed in the second semiconductor region. The semiconductor memory device of claim 13, wherein the carrier is generated by applying a forward bias to the first semiconductor region. The semiconductor memory device according to claim 14, wherein the application of the forward bias is performed by applying a voltage higher than the second semiconductor region to the first semiconductor region. The semiconductor memory device according to claim 15, wherein the period in which the carrier is generated is set according to a position of the selected word line. The semiconductor memory device of claim 12, wherein one end of the cell group is connected to a corresponding bit line via a bit line selection transistor, and the other end is connected via a source line selection transistor. In the source line, the cell group including the stylizing unit, the cell group and the bit are made non-switched by the bit line selection transistor and the source line selection transistor The source line and the source line are electrically separated, and the group of cells not including the stylizing unit is electrically coupled to the bit line by turning on the bit line selection transistor. The semiconductor memory device of claim 17, wherein Applying a first potential to a bit line corresponding to the cell group including the stylized unit, and applying a second potential to a bit line corresponding to the cell group not including the stylized unit, for the bit line The third potential is applied to the gate of the selected transistor, and the first potential is greater than the second potential, and the third potential is between the first potential and the second potential.