TW201526165A - Three-dimensional memory and method of forming the same - Google Patents

Abstract

A method of forming a three-dimensional memory is provided. A stacked structure is patterned to form a comb structure including a bit line pad extending along a first direction and comb-teeth portions extending along a second direction. A charge storage layer is formed on top and sidewall of the comb structure. Bit lines and auxiliary gates are formed on the charge storage layer and extend along the first direction. Each bit line covers top and sidewall of partial comb-teeth portions in a first area. Auxiliary gates cover top and sidewall of edge regions of the bit line pad. The charge storage layer on top of the bit line pad is removed. The stacked structure of the bit line pad is patterned to form a stepped structure. An ion implantation is performed to the stepped structure, to form a doped region in the semiconductor layer below each step surface of the stepped structure.

Description

Three-dimensional memory and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a three-dimensional memory and a method of fabricating the same.

As the demand for storage subsystems in consumer products is getting higher and higher, and the standards for reading and writing speed or capacity of products are becoming higher and higher, high-capacity related products have become the mainstream in the industry. In view of this, the development of memory (especially NAND flash memory) must also meet this need.

However, current planar NAND flash memory is limited by the critical size of components in integrated circuits, facing the bottleneck of memory cells. Therefore, designers are looking for a technology with multi-plane 3D NAND flash memory to achieve greater storage capacity and lower unit cost.

The invention provides a three-dimensional memory and a manufacturing method thereof, which can improve the uniformity and reliability of components.

The present invention provides a three-dimensional memory and a method of fabricating the same that can establish a low resistance current path to increase the on current.

The invention provides a three-dimensional memory and a manufacturing method thereof, which reduce the on-resistance value and increase the on-current.

The present invention provides a method of fabricating a three-dimensional memory comprising forming a stacked structure on a substrate. The stacked structure includes a plurality of semiconductor layers and a plurality of insulating layers alternating with each other. The stacked structure is patterned and a plurality of trenches are formed in the substrate to form a first comb structure. The first comb structure includes a bit line pad and a plurality of combs. The bit line pads extend in a first direction. A first end of each comb portion is coupled to the bit line pad, the comb portion extends in a second direction, and the first direction is different from the second direction. A charge storage layer is formed on an upper surface and a sidewall of the first comb structure. A plurality of word lines and two first auxiliary gates are formed on the charge storage layer. Each of the word lines extends in the first direction to cover an upper surface and a sidewall of the comb portion of the first region, and each of the first auxiliary gates extends in the first direction to cover the bit The upper surface and the side wall of the edge region of the wire pad. The charge storage layer on the upper surface of the bit line pad is removed, and the stacked structure of the bit line pad is patterned to form a ladder structure. The ladder structure is subjected to an ion implantation process to form a doped region in the semiconductor layer under each of the step surfaces of the ladder structure. A plurality of contact windows are formed, the contact windows being in contact with the doped regions, respectively.

The present invention further provides a method of fabricating a three-dimensional memory comprising forming a stacked structure on a substrate. The stacked structure includes a plurality of semiconductor layers and a plurality of insulating layers alternating with each other. The stacked structure is patterned to form a first comb structure and a plurality of trenches are formed in the substrate. The first comb structure includes a bit line pad and a plurality of combs. The bit line pads extend in a first direction, a first end of each comb portion is connected to the bit line pad, and the comb portion extends in a second direction, and the first direction is The second direction is different. A charge storage layer is formed on an upper surface and a sidewall of the first comb structure. A plurality of word lines and a plurality of island gates are formed on the charge storage layer. Each of the word lines extends in the first direction and covers an upper surface and a sidewall of the comb portion of the first region, and the island gates are separated from each other, aligned along the first direction, and The charge storage layer covering the upper surface and the sidewall of the comb portion of the second region.

The invention also provides a three-dimensional memory comprising a substrate having a plurality of trenches, a plurality of stacked structures, a plurality of doped regions, a charge storage layer, a plurality of word lines, two first auxiliary gates, and a plurality of contact plugs Plug. A plurality of stacked structures are located on the substrate between the trenches. Each stacked structure includes a plurality of semiconductor layers and a plurality of insulating layers alternating with each other. The stack structure and the substrate frame constitute a first comb structure. The first comb structure includes a bit line pad and a plurality of combs. The bit line pads extend in a first direction, and the stacked structure of the bit line pads has a ladder structure. A first end of each comb is coupled to the bit line pad. The comb extends in a second direction, and the first direction is different from the second direction. A plurality of doped regions are located in the semiconductor layer below a plurality of ladder faces of the ladder structure. A charge storage layer covers the upper surface and the sidewall of the first comb structure. Each word line extends in the first direction to cover the upper surface of the comb portion of the first region and the charge storage layer on the sidewall. Each of the first auxiliary gates extends in the first direction to cover the upper surface of the edge region of the bit line pad and the charge storage layer on the sidewall. A plurality of contact windows are in contact with the doped regions, respectively.

The invention also provides a three-dimensional memory comprising: a substrate having a plurality of trenches, a plurality of stacked structures, a plurality of doped regions, a charge storage layer, a plurality of word lines, a plurality of island gates, and a plurality of auxiliary gates Extreme and most contact plugs. A plurality of stacked structures are located on the substrate between the trenches, and each stacked structure includes a plurality of semiconductor layers and a plurality of insulating layers alternating with each other, and the stacked structure and the substrate frame constitute a first comb structure. The first comb structure includes a bit line pad and a plurality of combs. The bit line pads extend in a first direction, and the stacked structure of the bit line pads has a ladder structure. A first end of each comb is coupled to the bit line pad. The comb extends in a second direction, and the first direction is different from the second direction. A plurality of doped regions are located in the semiconductor layer below a plurality of ladder faces of the ladder structure, and the junction depths of the doped regions are substantially the same. A charge storage layer covers the upper surface and the sidewall of the first comb structure. Each word line extends in the first direction to cover the upper surface of the comb portion of the first region and the charge storage layer on the sidewall. The island gates are separated from each other, the island gates are arranged along the first direction, and cover the comb portion of the second region between the bit line pad and the word line The charge storage layer of the upper surface and the sidewalls. The auxiliary gate is located on the charge storage layer between the comb portion of the third region between the island gate and the word line, and the surface of the auxiliary gate is lower than the The upper surface of the comb portion of the third zone, and the two auxiliary gates are connected to an island gate. Each of the contact plugs is located at a second end of each comb portion of the first comb structure, and electrically connects the semiconductor layer of the stack structure corresponding to the comb portion to the substrate.

The bit line pads of the three-dimensional memory of the present invention are stepped, and doped regions are formed on the surface of the semiconductor layer under each of the facets. Since the doped region is formed after the formation of the stepped structure, before the formation of the dielectric layer, by the ion implantation process, and the thickness of the insulating layer above the semiconductor layer is the same, the junction depth of the plurality of doped regions is The doping concentration is substantially the same, so the uniformity and reliability of the component can be improved.

Furthermore, the present invention also forms a first auxiliary gate on the upper surface and the sidewall of the edge of the bit line pad of the three-dimensional memory. After the voltage is applied, a channel can be formed in the semiconductor layer to establish a low resistance value. Current path to increase the on current.

In addition, an island gate and a second auxiliary gate are further disposed on the charge storage layer between the ground selection lines GSL1, GSL2 and the bit line pads. The second auxiliary gate is located on both sides of the comb and is electrically connected to the island gate. When a voltage is applied to the island gate, the semiconductor layer in the stacked structure of the comb portion covered by the island gate and the second auxiliary gate may generate a depletion region to reduce the on-resistance value and increase the on-current.

The above described features and advantages of the present invention will be more apparent from the following description.

1 to 8 are top views of a flow of a method of manufacturing a three-dimensional memory according to an embodiment of the present invention. 1A to 8A are cross-sectional views taken along line A-A of Figs. 1 to 8. 1B to 8B are cross-sectional views taken along line B-B of Figs. 1 to 8. 1C to 8C are cross-sectional views taken along line C-C of Figs. 1 to 8. 1D to 8D are cross-sectional views taken along line D-D of Figs. 1 to 8.

Referring to FIGS. 1 through 1D, a stacked structure 12 is formed on the substrate 10. The stacked structure 12 includes a plurality of insulating layers 14 and a plurality of semiconductor layers 16 that alternate with each other. The material of the insulating layer 14 may be a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof. The thickness of the insulating layers 14 may be the same or different from each other, and the thickness thereof is, for example, but not limited to, 200 angstroms to 500 angstroms. The material of the semiconductor layer 16 is, for example, undoped polysilicon or doped polysilicon. The thickness of the semiconductor layers 16 may be the same or different from each other, and the thickness thereof is, for example, but not limited to, 200 angstroms to 500 angstroms. The thickness and number of layers of the insulating layer 14 and the semiconductor layer 16 are not limited to the above and the drawings, and can be adjusted according to actual needs.

Next, a plurality of first contact plugs 122, a plurality of second contact plugs 222, a plurality of first isolation plugs 124, and a plurality of second isolation plugs 224 are formed in the stacked structure 12. The order in which the first contact plug 122, the second contact plug 222, the first isolation plug 124, and the second isolation plug 224 are formed is not particularly limited.

In an embodiment, the first isolation plug 124 and the second isolation plug 224 may be formed first, and then the first contact plug 122 and the second contact plug 222 are formed. The first isolation plug 124 and the second isolation plug 224 are formed by forming an opening 24 in the stacked structure 12, and then forming an insulating material layer in the opening 24, and then removing it by chemical mechanical polishing or etchback. A layer of insulating material on the surface of the stacked structure 12. The material of the insulating material layer is, for example, cerium oxide, cerium nitride, cerium oxynitride or a combination thereof. Thereafter, a cap layer 18 is formed on the surface of the stacked structure 12 and on the surfaces of the first isolation plug 124 and the second isolation plug 224. The material of the cap layer 18 may be a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof, but the material of the cap layer 18 may be different from the material of the insulating layer 14. The thickness of the cap layer 18 may be greater than the thickness of the insulating layer 14. The first contact plug 122 and the second contact plug 222 may be formed by forming a plurality of contact windows 22 in the cap layer 18 and the stack structure 12, and then forming conductors on the stack structure 12 and in the contact holes 22. The layer of material is then removed by chemical mechanical polishing or etch back to remove the layer of conductor material on the surface of the cap layer 18. The material of the conductor material layer is, for example, doped polysilicon or doped polysilicon. Thereafter, a cap layer 20 is formed on the surface of the cap layer 18 and on the surfaces of the first contact plug 122 and the second contact plug 222. The material of the cap layer 20 may be a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof. The material of the cap layer 20 may be the same as or different from the material of the insulating layer 14.

In another embodiment, the first contact plug 122 and the second contact plug 222 may be formed first, and then the first isolation plug 124 and the second isolation plug 224 are formed. For the sake of clarity, the top views 18, 20 are not depicted in the top views of Figures 1-8.

Referring to FIGS. 2 to 2D, the stacked structure 12, the cap layer 18, and the cap layer 20 are patterned into a plurality of patterned stacked structures 12a to form a first comb structure 130 and a second comb structure 230, and A plurality of trenches 26 are formed in the substrate 10. The first comb structure 130 includes a bit line pad 132 and a plurality of comb portions 134. The bit line pads 132 extend in a first direction. Each comb portion 134 extends in a second direction, the first direction being different from the second direction. In an embodiment, the first direction is, for example, the X direction; the second direction is, for example, the Y direction. The first end 134a of each comb portion 134 is connected to the bit line pad 132; the second end 134b is in contact with the first contact plug 122 to electrically connect the comb portion 134 of the corresponding first comb structure 130. The multilayer semiconductor layer 16 of the stacked structure 12a is bonded to the substrate 10. In particular, the first contact plug 122 vertically connects the multilayer semiconductor layer 16 of the stacked structure 12a with the substrate 10, also referred to as a first source contact plug.

Similarly, the second comb structure 230 includes a bit line pad 232 and a plurality of comb portions 234. The bit line pads 232 of the second comb structure 230 extend in the first direction and are disposed corresponding to the bit line pads 232 of the first comb structure 130. Each comb portion 234 of the second comb structure 230 extends in a second direction and is alternately disposed with the comb portion 134 of the first comb structure 130. The first end 234a of each comb portion 234 is connected to the bit line pad 232; the second end 234b is in contact with the second contact plug 222 to electrically connect the comb portion 234 of the corresponding second comb structure 230. The semiconductor layer 16 of the stacked structure 12a is bonded to the substrate 10. The second contact plug 222 vertically connects the semiconductor layer 16 to the substrate 10, also referred to as a second source contact plug.

Moreover, between each of the first contact plugs 122 and the bit line pads 232 of the second comb structure 230, the first isolation plugs 124 are electrically isolated. Between each of the second contact plugs 222 and the bit line pads 132 of the first comb structure 130, the second isolation plugs 224 are electrically isolated.

Referring to FIGS. 3 through 3D, a charge storage layer 28 is formed on the upper surface and sidewalls of the first comb structure 130 and the second comb structure 230. The charge storage layer 28 can be a single layer of material or a plurality of layers of material. The material of the charge storage layer 28 includes tantalum nitride. In an embodiment, the charge storage layer 28 includes a stack structure of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxide layer. A conductor layer 30 is formed on the charge storage layer 28. The material of the conductor layer 30 is, for example, undoped polysilicon or doped polysilicon. The charge storage layer 28 and the conductor layer 30 can be formed by a chemical vapor phase method, respectively.

Thereafter, a patterned photoresist layer 32 is formed on the conductor layer 30. The patterned photoresist layer 32 covers the memory cell array region 100, regions 102, 202, 105, 205, 108, 208. Regions 102 and 202 are located on either side of memory cell array region 100, respectively. Regions 108 and 208 are regions that cover bit line pads 138 and their surrounding regions and bit line pads 238, respectively, and their surroundings. Region 105 is located between region 108 and region 102. Region 105 includes region 104 and region 106. Where region 104 is near region 102; region 106 is near region 108. Region 205 is located between region 208 and region 202. Region 205 includes region 204 and region 206. Where region 204 is near region 202; region 206 is near region 208.

Referring to FIG. 4 to FIG. 4D, the patterned photoresist layer 32 is used as a mask, and the conductor layer 30 is etched to pattern the conductor layer 30 to form a plurality of word lines WL1 and WL2 extending in the first direction. WL3, WL4, ground select lines GSL1, GSL2, first patterned conductor layers 136, 236, and second patterned conductor layers 138, 238. The word lines WL1, WL2, WL3, WL4 are located in the memory cell array region 100. In the drawing, only the word lines WL1, WL2, WL3, WL4 are represented, however, the number of word lines is not limited thereto. Referring to FIGS. 4 and 4A, the ground selection lines GSL1, GSL2 are located in the regions 102 and 202, respectively. Referring to Figures 4, 4B and 4C, the first patterned conductor layers 136, 236 are located within regions 105 and 205, respectively. Referring to Figures 4 and 4D, second patterned conductor layers 138, 238 are located within regions 108 and 208, respectively. Thereafter, the patterned photoresist layer 32 is removed.

Referring to FIGS. 5 through 5D, a patterned photoresist layer 34 is formed on the substrate 10. The patterned photoresist layer 34 has openings 36, 37, 38, 46, 47, 48. The opening 36 exposes the first patterned conductor layer 136 of the region 104. The first patterned conductor layer 136 of the opening 37 in the exposed region 105 above the second isolation plug 224. The opening 38 exposes the second patterned conductor layer 138 in the central region of the region 108. The opening 46 exposes the first patterned conductor layer 236 of the region 204. The opening 47 exposes the first patterned conductor layer 236 in the region 205 above the first isolation plug 124. The opening 48 exposes the second patterned conductor layer 238 in the central region of the region 208.

Referring to FIGS. 5 to 5D and FIGS. 6 to 6D, the patterned photoresist layer 34 is used as a mask to remove the second patterned conductor layers 138 and 238 exposed by the openings 38, 48, leaving the bit layer The second patterned conductor layers 138, 238 on the edge regions of the wire pads 132, 232 can serve as first auxiliary gates 138a, 138b, 238a, 238b. In the same removal step, the second patterned conductor layers 138c, 138d remaining between adjacent two bit line pads 132 may be connected to the first auxiliary gates 138a, 138b; The second patterned conductor layers 238c, 238d between the bit line pads 232 can be connected to the first auxiliary gates 238a, 238b.

At the same time, with the patterned photoresist layer 34 as a mask, the first patterned conductor layer 136 exposed by the openings 36, 37 and the first patterned conductor layer 236 exposed by the openings 46, 47 are removed. More specifically, referring to FIG. 6 and FIG. 6C, the first patterned conductor layer 136 exposed by the opening 37 above the second isolation plug 224 in the region 106 is completely removed, leaving the first patterned The conductor layers 136 are separated from each other and can be used as the island gates 136a. The island gate 136a covers the charge storage layer 28 on the comb portion 134 of the region 106 and extends over the charge storage layer 28 on either side of the comb portion 134. Within region 104, the first patterned conductor layer 136 exposed by opening 36 is removed to a lower surface than second contact plug 222, and the remaining first patterned conductor layer 136 can be used as a second Auxiliary gate 136b. In region 105, an island gate 136a is in contact with two adjacent second auxiliary gates 136b. When a voltage is applied to the island gate 136a, the semiconductor layer 16 in the stacked structure 12a of the comb portion 134 can generate a depletion region to lower the on-resistance value.

Similarly, referring to FIG. 6 and FIG. 6C, in the region 206, above the first isolation plug 124, the first patterned conductor layer 236 exposed by the opening 47 is completely removed, leaving a first patterning. The conductor layers 236 are separated from each other and can be used as the island gates 236a. The island gate 236a covers the charge storage layer 28 on the comb portion 234 of the region 206 and extends over the charge storage layer 28 on either side of the comb portion 234. Within region 204, the first patterned conductor layer 236 exposed by opening 46 will be removed to a lower surface than second contact plug 122, leaving a first patterned conductor layer 236 as a second Auxiliary gate 236b. In region 205, an island gate 236a is in contact with two adjacent second auxiliary gates 236b. When a voltage is applied to the island gate 236a, the semiconductor body layer 16 in the stacked structure 12a of the comb portion 234 can create a depletion region to reduce the on-resistance value. Thereafter, the patterned photoresist layer 34 is removed.

Thereafter, referring to FIGS. 6-6D and FIGS. 7-7D, the charge storage layer 28 overlying the upper surface of the bit line pads 132, 232 is removed. Thereafter, the top cover layers 18, 20 and the stacked structures 12a of the bit line pads 132, 232 can be patterned by multi-stage lithography and etching to form the ladder structures 140, 240. The step faces of the ladder structures 140, 240 are the insulating layers 14. Then, the ladder structures 140 and 240 are subjected to an ion implantation process to form doped regions 142a to 142h and 242a, respectively, in the topmost semiconductor layer 16 under the ladder surface (insulating layer 14) of the ladder structures 140 and 240. 242h. Since the doped regions 142a-142h and 242a-242h are formed before the formation of the ladder structures 140, 240, before forming the dielectric layer 40 (FIGS. 8 to 8D), the topmost semiconductor layers of the ladder structures 140, 240 are formed. The thickness of the insulating layer 14 covered above is substantially the same. Therefore, the doping regions 142a to 142h and 242a to 242h have substantially the same junction depth and concentration, which can improve the uniformity and reliability of the device.

Thereafter, referring to FIGS. 8-8D, a dielectric layer 40 is formed on the substrate 10, and a plurality of contact windows 144, 244, 146, 246, 148, 248 are formed in the dielectric layer 40. The contact window 144 includes contact windows 144a-144h electrically connected to the doped regions 142a-142h of the bit line pads 132, respectively. The contact window 244 includes contact windows 244a-244h electrically connected to the doped regions 242a-242h of the bit line pads 232, respectively. Contact windows 146 and 246 are electrically coupled to island gates 136a and 236a, respectively. Contact windows 148 and 248 are electrically coupled to first contact plug 122 and second contact plug 222, respectively.

9 is a top view of each level of the stepped structure 140 of the bit line pads 132.

Referring to FIG. 9, each of the semiconductor layers 16 has doped regions 142a to 142h at the bottom surfaces of the corresponding contact windows 144a to 144h. The doped regions 142a-142h have substantially the same junction depth and concentration, which can reduce the junction resistance and improve the uniformity and reliability of the components. First auxiliary gates 138a and 138b are disposed on the upper surface and sidewalls of the edge regions of the bit line pads, and the first auxiliary gates 138a and 138b cover the charge storage layer 28. The first auxiliary gates 138a and 138b may form a channel in the semiconductor layer 16 when a voltage is applied, establishing a path of low resistance.

The three-dimensional memory of the present invention will be described below with reference to Figs. 8 to 8D. This memory can be a vertical NAND Flash.

The three-dimensional memory of the present invention comprises a substrate 10 having a plurality of trenches 26, a plurality of stacked structures 12a, a plurality of doped regions 142a-142h, a charge storage layer 28, a plurality of word lines WL1 WL WL4, and two first auxiliary Gates 138a, 138b, a plurality of contact plugs 124, a plurality of island gates 136a, a plurality of second auxiliary gates 136b, and a plurality of contact windows 144a-144h. A plurality of stacked structures 12a are located on the substrate 10 between the trenches 26. Each of the stacked structures 12a includes a plurality of semiconductor layers 16 and a plurality of insulating layers 14 that alternate with each other. The stacked structure 12a and the substrate 10 constitute a first comb structure 130 and a second comb structure 230. The first comb structure 130 includes a bit line pad 132 and a plurality of comb portions 134. The bit line pads 132 extend in a first direction. The semiconductor layer 16 of the comb portion 134 serves as a bit line. The stack structure 12a of the bit line pads 132 is a ladder structure 140. The first end 134a of each comb portion 134 is coupled to the bit line pad 132, each comb portion 134 extending in a second direction, and the first direction is different from the second direction. The doped regions 142a-142h are located in the semiconductor layer 16 below the plurality of steps of the ladder structure 140. The charge storage layer 28 covers the upper surface of the first comb structure 130 and the sidewalls. The word lines WL1 WL WL4 extend in the first direction to cover the upper surface of the portion of the comb portion 134 of the first region and the charge storage layer 28 on the sidewall. The first auxiliary gates 138a, 138b extend in a first direction to cover the upper surface of the edge regions of the bit line pads 132 and the charge storage layer 28 on the sidewalls, respectively. A plurality of contact windows 144a-144h are in contact with the doped regions 142a-142h, respectively. The island gates 136a are separated from each other and arranged along the first direction to cover the upper surface of the comb portion 134 between the bit line pads 132 and the ground selection line GSL1 and the charge storage layer 28 of the sidewalls. A plurality of second auxiliary gates 136b are located on the charge storage layer 28 between the comb portions 134 of the third region between the island gate 136a and the ground selection line GSL1. The surface of the second auxiliary gate 136b is lower than the upper surface of the comb portion 134, and the two second auxiliary gates 136b are connected to an island gate 136a. The second comb structure 230 and its associated components are similar to the first comb structure 130 and its corresponding components, and will not be described herein.

In summary, the bit line pads of the three-dimensional memory of the present invention are stepped, and doped regions are formed on the surface of the semiconductor layer under each of the facets. Since the doped region is formed after the formation of the stepped structure, before the formation of the dielectric layer, by the ion implantation process, and the thickness of the insulating layer covered over the topmost semiconductor layer of the ladder structure is substantially the same, The junction depth of most of the doped regions is substantially the same as the doping concentration, so that the uniformity and reliability of the components can be improved.

Furthermore, the present invention also forms a first auxiliary gate on the upper surface and the sidewall of the edge of the bit line pad. When a voltage is applied, a channel can be formed in the semiconductor layer to establish a low resistance current path to increase Turn on the current.

In addition, an island gate and a second auxiliary gate are further disposed on the charge storage layer between the ground selection lines GSL1, GSL2 and the bit line pads. Two second auxiliary gates are located on both sides of each comb portion and are electrically connected to an island gate. When a voltage is applied to the island gate, the semiconductor layer in the stacked structure of the comb portion covered by the island gate and the second auxiliary gate may generate a depletion region to reduce the on-resistance value and increase the on-current.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

12‧‧‧Stack structure
12a‧‧‧ patterned stacking structure
14‧‧‧Insulation
16‧‧‧Semiconductor layer
18, 20‧‧‧ top cover
22‧‧‧Contact window
26‧‧‧ditch
28‧‧‧Charge storage layer
30‧‧‧Conductor layer
32, 34‧‧‧ patterned photoresist layer
36, 37, 38, 46, 47, 48‧‧
100‧‧‧Memory Cell Array Area
102, 104, 105, 106, 108, 202, 204, 205, 206, 208‧‧‧ areas
122, 222‧‧‧ first contact plug
124, 224‧‧‧ first isolation plug
132, 232‧‧‧ bit line pads
134, 234‧‧ ‧ comb
136, 236‧‧‧ first patterned conductor layer
136a, 236a‧‧‧ island gate
136b, 236b‧‧‧second auxiliary gate
138, 138c, 138d, 238, 238c, 238d‧‧‧ second patterned conductor layer
138a, 138b, 238a, 238b‧‧‧ first auxiliary gate
140, 240‧‧‧ ladder structure
142a~142h, 242a~242h‧‧‧Doped area
144, 144a~144h, 244, 244a~244h, 146, 246, 148, 248‧‧ Contact
WL1, WL2, WL3, WL4‧‧‧ character lines
GSL1, GSL2‧‧‧ Grounding selection line

1 to 8 are top views of a flow of a method of manufacturing a three-dimensional memory according to an embodiment of the present invention. 1A to 8A are cross-sectional views taken along line A-A of Figs. 1 to 8. 1B to 8B are cross-sectional views taken along line B-B of Figs. 1 to 8. 1C to 8C are cross-sectional views taken along line C-C of Figs. 1 to 8. 1D to 8D are cross-sectional views taken along line D-D of Figs. 1 to 8. 9 is a top plan view of each level of a stepped structure of a bit line pad of a three-dimensional memory in accordance with an embodiment of the present invention.

10‧‧‧Base

14‧‧‧Insulation

16‧‧‧Semiconductor layer

138c‧‧‧Second patterned conductor layer

140‧‧‧ ladder structure

142a~142h‧‧‧Doped area

Claims (10)

A method of fabricating a three-dimensional memory, comprising: forming a stacked structure on a substrate, the stacked structure comprising a plurality of semiconductor layers and a plurality of insulating layers alternating with each other; patterning the stacked structure to form a first comb structure and Forming a plurality of trenches in the substrate, the first comb structure comprising a one-dimensional wire pad and a plurality of comb portions, the bit wire pads extending in a first direction, a first end of each comb portion The bit line pads are connected, the comb portions extend in a second direction, and the first direction is different from the second direction; forming a charge storage layer on the upper surface and the sidewall of the first comb structure; Forming a plurality of word lines and two first auxiliary gates on the charge storage layer, wherein each of the word lines extends in the first direction and covers a portion of the first portion and upper surfaces and sidewalls of the comb portions And the first auxiliary gates extend in the first direction and respectively cover upper surfaces and sidewalls of the edge regions of the bit line pads; removing the charge storage layer on the upper surface of the bit line pads And patterning the bit line pads Stacking the structure to form a ladder structure; performing an ion implantation process on the ladder structure to form a doped region in the semiconductor layer under each step of the ladder structure; and forming a plurality of contact windows, The contact windows are respectively in contact with the doped regions. The method for manufacturing a three-dimensional memory according to claim 1, wherein the forming the word lines and the first auxiliary gates comprises: forming a conductor layer on the charge storage layer; patterning the a conductor layer to form a first patterned conductor layer, a second patterned conductor layer, and the word lines, wherein the second patterned conductor layer extends in the first direction to cover the bit line An upper surface and a sidewall of the pad, and the first patterned conductor layer extends in the first direction adjacent to the second patterned conductor layer to cover the combs of the second region and the third region The upper surface and the sidewall of the portion; removing the second patterned conductor layer covering a central region of the bit line pad, leaving the second patterned conductor layer on the edge region of the bit line pad As the first auxiliary gates; removing a portion of the first patterned conductor layer between the bit line pads and the word lines to form a plurality of island gates a pole, the island gates are separated from each other, arranged along the first direction, and covering the first The charge storage layer of the upper surface and the sidewall of the comb portion; and the portion of the first patterned conductor layer removed from a portion of the third region between the island gates and the word lines, Forming a plurality of second auxiliary gates, the second auxiliary gates covering the charge storage layer between the comb portions of the third region, the surfaces of the second auxiliary gates being lower than the third region The upper surfaces of the comb portions, and the two second auxiliary gates are connected to an island gate. The method for manufacturing a three-dimensional memory according to claim 1, further comprising: forming a second comb structure, wherein the second comb structure is in a step of patterning the stacked structure The wire bonding pad corresponds to the bit wire pad of the first comb structure, and the plurality of comb portions of the second comb structure are alternately arranged with the comb portions of the first comb structure; a second contact end of each comb portion of a comb structure is formed with a first contact plug electrically connecting the semiconductor layers of the stack structure corresponding to the comb portion of the first comb structure and the Forming a second contact plug at one end of each comb portion of the second comb structure to electrically connect the semiconductor layers of the stack structure of the comb portion corresponding to the second comb structure Forming a first isolation plug between each of the first contact plugs and the bit line pads of the second comb structure; and at each of the second contact plugs and the first comb A second isolation plug is formed between the bit line pads of the structure. A method of fabricating a three-dimensional memory, comprising: forming a stacked structure on a substrate, the stacked structure comprising a plurality of semiconductor layers and a plurality of insulating layers alternating with each other; patterning the stacked structure to form a first comb structure and Forming a plurality of trenches in the substrate, the first comb structure comprising a one-dimensional wire pad and a plurality of comb portions, the bit wire pads extending in a first direction, a first end of each comb portion Connected to the bit line pad, and the comb portions extend in a second direction, and the first direction is different from the second direction; forming a charge storage on the upper surface and the sidewall of the first comb structure And forming a plurality of word lines and a plurality of island gates on the charge storage layer, wherein each word line extends in the first direction and covers a portion of the first portion of the comb portion The upper surface and the side wall, and the island gates are separated from each other, arranged along the first direction, and covering the upper surface of the comb portions of the second region and the charge storage layer of the sidewall. The method of manufacturing the three-dimensional memory of claim 4, wherein the forming the word lines and the island gates comprises: forming a conductor layer on the charge storage layer; patterning the conductor a layer to form a patterned conductor layer and the word lines, wherein the patterned conductor layer extends in the first direction to cover upper surfaces of the comb portions of the second region and the third region a sidewall; removing a portion of the patterned conductor layer of the second region to form the island gates; and removing a portion of the third region between the island gates and the word lines The patterned conductor layer is formed to form a plurality of auxiliary gates, the auxiliary gates covering the charge storage layer between the comb portions of the third region, the surfaces of the auxiliary gates being lower than the third region The upper surfaces of the comb portions, and the two auxiliary electrodes are connected to an island gate. The method for manufacturing a three-dimensional memory according to claim 4, further comprising forming a contact plug at a second end of each comb portion of the first comb structure to electrically connect the corresponding one. The semiconductor layers of the stacked structure of the comb portion of the first comb structure and the substrate. A three-dimensional memory comprising: a substrate having a plurality of trenches; a plurality of stacked structures on the substrate between the trenches, each stacked structure comprising a plurality of semiconductor layers and a plurality of insulating layers alternating with each other, The stack structure and the substrate frame form a first comb structure, wherein the first comb structure comprises: a bit line pad, the bit line pad extends in a first direction, and the bit line pad The stacking structure has a ladder structure; and a plurality of comb portions, a first end of each comb portion is connected to the bit line pad, the comb portions extend in a second direction, and the first direction is The second direction is different; a plurality of doped regions are respectively located in the semiconductor layers under the plurality of ladder faces of the ladder structure; a charge storage layer covering the upper surface and the sidewall of the first comb structure a plurality of word lines extending in the first direction to cover a portion of the first portion of the comb portion and the charge storage layer on the sidewall; two first auxiliary gates, Each first auxiliary gate is in the Extending in one direction, respectively, to cover the charge storage layer on the upper surface of the side walls of the two edge regions of the bit line contact pads; and a plurality of the contact window, they are in contact with the plurality of doped regions. The three-dimensional memory of claim 7, further comprising: a plurality of island gates, the island gates being separated from each other, arranged along the first direction, and covering the bit line pads and The charge storage layer of the upper surface and the sidewall of the comb portion of the second region between the word lines; and a plurality of second auxiliary gates located at the island gates and the word lines On the charge storage layer between the comb portions of a third region, the surfaces of the second auxiliary gates are lower than the upper surfaces of the comb portions of the third region, and the second The auxiliary gate is connected to an island gate, wherein the junction depths of the doped regions are substantially the same. The three-dimensional memory of claim 7, further comprising: a second comb structure, wherein a bit line pad of the second comb structure is connected to the bit line of the first comb structure Corresponding to the pad, a plurality of comb portions of the second comb structure are alternately arranged with the comb portions of the first comb structure; a plurality of first contact plugs, each of the first contact plugs being located in each comb portion a second end electrically connecting the semiconductor layers of the stacked structure of the comb portion corresponding to the first comb structure to the substrate; a plurality of second contact plugs, each of the second contact plugs One end of each comb portion of the second comb structure is electrically connected to the semiconductor layers of the stack structure corresponding to the comb portion of the second comb structure and the substrate; a plurality of first isolation plugs a plug between the first contact plug and the bit line pad of the second comb structure; and a plurality of second isolation plugs located at the second contact plug and the first comb The bit line of the structure is between the pads. A three-dimensional memory comprising: a substrate having a plurality of trenches; a plurality of stacked structures on the substrate between the trenches, each stacked structure comprising a plurality of semiconductor layers and a plurality of insulating layers alternating with each other, The stack structure and the substrate frame form a first comb structure, wherein the first comb structure comprises: a bit line pad, the bit line pad extends in a first direction, and the bit line pad The stacking structure has a ladder structure; and a plurality of comb portions, a first end of each comb portion is connected to the bit line pad, the comb portions extend in a second direction, and the first direction is The second direction is different; a plurality of doped regions are respectively located in the semiconductor layers under the plurality of ladder faces of the ladder structure, and the junction depths of the doped regions are substantially the same; a charge storage layer covering On the upper surface and the side wall of the first comb structure; a plurality of word lines, each of the word lines extending in the first direction, covering a portion of the first portion and the upper surface and the side wall of the comb portions The charge storage layer; and more Island-shaped gates, the island-shaped gates being separated from each other, arranged along the first direction, and covering the comb portions of a second region between the bit line pads and the word lines The charge storage layer on the upper surface and the sidewall; a plurality of auxiliary gates on the charge storage layer between the plurality of comb portions of the third region between the island gates and the word lines, The surfaces of the auxiliary gates are lower than the upper surfaces of the comb portions of the third region, and the two auxiliary gates are connected to an island gate; and a plurality of contact plugs, each of the contact plugs is located at the A second end of each comb portion of the first comb structure is electrically connected to the semiconductor layers of the stack structure corresponding to the comb portion and the substrate.