TW201526013A - Storage device and access method therefor - Google Patents

Abstract

A storage device and an access method therefor are disclosed. The device includes a memory and a controller. The memory is used to store a plurality of unit data; the controller receives a plurality of data and encodes the data to generate a plurality of error correction data. The error correction data includes the unit data, and the controller writes the unit data either using an alternating approach or based on a mapping address into the memory. Accordingly, the errors in the error correction data can be equally distributed in the memory, thereby improving the error correction capability of the error correction codes.

Description

Storage device and access method thereof

The present invention relates to an electronic device and a control method thereof, and more particularly to a storage device and an access method thereof.

In recent years, due to the continuous development of flash memory technology, various portable memory devices or solid state drives (SSDs) with flash memory have been widely implemented in many applications. Therefore, access control of flash memory in these portable memory devices has become a hot topic. In the conventional NAND type flash memory, it can be mainly divided into two types of flash memory: single level cell (SLC) and multiple level cell (MLC).

In addition, error correction is very important for maintaining data reliability in a memory device. In particular, error correction becomes more important as the density of memory cells or the number of memory bits per memory cell increases. Furthermore, memory devices (such as flash memory) can also generate erroneous bits at the time of manufacture or after a considerable number of reads and writes.

An Error Correcting Code (ECC) is used to improve the reliability of the memory device. However, the error correction code of the conventional memory device is not very effective. Generally, the fixed data length and the fixed error correction code rate are used, and the data access is performed in units of error correction units, and if one error corrects the error of the unit data. The bit is particularly large and the error correction code can be corrected to correct the range, so the data cannot be used, even unable to reply and will be lost forever. In view of the fact that traditional memory devices cannot effectively correct errors and prevent data loss, it is imperative to propose a novel memory system and method for effectively improving the reliability of data in the memory device and preventing data loss.

Accordingly, the present invention provides a storage device for improving error correction capability and an access method thereof for the above problems.

An object of the present invention is to provide a storage device and an access method thereof, wherein the complex error correction data is evenly distributed to the plurality of data blocks of the memory device by means of interleaving or mapping, so that the errors are corrected in the data. Errors are evenly spread across the data blocks, which in turn increases the error correction ability of the error correction code.

An object of the present invention is to provide a storage device and an access method thereof, which can improve the error correction capability of an error correction code by changing the storage space ratio of the data block and the spare block in each page.

In order to achieve the above-mentioned various purposes and effects, the present invention discloses a storage device comprising: a memory device for storing a plurality of unit data; and a controller for receiving the plurality of data and encoding the data A plurality of error correction data is generated. The error correction data includes the unit data, and the controller writes the unit data of the error correction data to the memory device in an interleaved manner or according to a mapping address.

The present invention further discloses a method for accessing a storage device, the method comprising: encoding a plurality of data to generate a plurality of error correction data, wherein the error correction data comprises a plurality of unit data; and the unit data of the error correction data is Write to a memory device in an interleaved manner or in accordance with a mapped address.

10‧‧‧ memory device
30‧‧‧ Controller
301‧‧‧Microprocessing unit
303‧‧‧Error correction code circuit
305‧‧‧ mapping circuit
307‧‧‧Transition circuit
309‧‧‧ Buffer memory
50‧‧‧Host
A, B, C‧‧‧ error correction information
A ₁ , A ₂ , A _n , B ₁ , B ₂ , B _n , C ₁ , C ₂ , C _n ‧‧‧ unit data
D, D ₁ , D ₂ , D _n ‧‧‧ data blocks
S‧‧‧ spare block
S10, S20, S30, S40, S50, S70‧‧ steps

Figure 1 is a block diagram of a storage device in accordance with a preferred embodiment of the present invention;
Figure 2 is a flow chart of a writing procedure of a preferred embodiment of the present invention;
Figure 3 is a cross-sectional view showing a writing procedure of a preferred embodiment of the present invention;
Figure 4 is a flow chart showing a writing procedure of another preferred embodiment of the present invention;
FIG. 5A is a schematic diagram showing the ratio of a data block to a spare block according to a preferred embodiment of the present invention;
FIG. 5B is a schematic diagram showing the ratio of a data block to a spare block according to another preferred embodiment of the present invention;
Figure 6 is a flow chart showing a reading procedure of a preferred embodiment of the present invention; and Figure 7 is a schematic diagram showing the mapping of a reading program according to a preferred embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows:

Please refer to FIG. 1 , which is a block diagram of a storage device in accordance with a preferred embodiment of the present invention. As shown, the storage device includes a memory device 10 and a controller 30. The controller 30 is configured to encode the complex data provided by the host 50 to generate complex error correction data, and write the complex unit data included in the error correction data to the memory in an interleaved manner or according to a mapping address. The device 10 reads out the unit data stored in the memory device 10 in an interleaved manner or in accordance with the mapped address, and restores the error correction data, and decodes the error correction data for the host 50 to read. take. After the controller 30 writes the unit data to the memory device 10, the partial space of the plurality of data blocks of the memory device 10 is converted to the data blocks according to the number of errors of the unit data. Corresponding multiple spare blocks.

The controller 30 includes a micro processing unit 301, an error correction code circuit 303, a mapping circuit 305, and a conversion circuit 307. The error correction code circuit 303 is coupled to the micro processing unit 301 and is controlled by the micro processing unit 301. When the data needs to be written to the memory device 10, the error correction code circuit 303 encodes the data transmitted by the host 50 to add an error correction code, and generates the error correction data and transmits the error correction data to the mapping circuit. When the host 50 needs to read the data, the error correction code circuit 305 decodes the error correction data transmitted by the mapping circuit 305, and restores the data to the host 50 for reading.

The mapping circuit 305 is coupled to the micro processing unit 301 and is controlled by the micro processing unit 301. When the data is written, the mapping circuit 305 writes the unit data included in the error correction data output by the error correction code circuit 303 to the memory device 10 in an interleaved manner or according to the mapping address. When the data is read, the mapping circuit 305 reads and restores the unit data stored in the memory device 10 to the error correction data in an interleaved manner or according to the mapping address, and transmits the error correction data to the error correction code circuit 303.

The conversion circuit 307 is coupled to the micro processing unit 301 and controlled by the micro processing unit 301. Before the data is written, the micro processing unit 301 first controls the error correction data output by the error correction code circuit 303. To the memory device 10 (this portion is preferably written in such a manner that the mapping circuit 305 is controlled by the micro processing unit 301 to correct the error data, and can be written into the memory device 10 without interleaving, but the present invention does not The memory device 10 is detected by the host device 50 or the micro processing unit 301 to learn that the error correction data written to the memory device 10 is generated in the data blocks of the memory device 10. The number of errors, that is, the number of errors in which the errors correct the data. The micro-processing unit 301 then causes the conversion circuit 307 to control the partial space of the data blocks of the memory device 10 to be converted to the spare blocks corresponding to the data blocks according to the error correction of the errors. . After the conversion is completed, the error correction data outputted by the error correction code circuit 303 is written and stored in the data blocks of the memory device 10 (divided into the data by the mapping circuit 305 in an interleaved manner according to the mapping address). The unit data is written or written in a non-interlaced manner.

In addition, the controller 30 further includes a buffer memory 309 coupled between the host 50 and the error correction code circuit 303 for temporarily storing the data transmitted or read by the host 50, but the buffer memory 309 is not intended to limit the invention.

In addition, the controller 30 of the present invention may also include only one of the mapping circuit 305 or the conversion circuit 307, and only one of the functions is not limited, and the mapping circuit 305 and the conversion circuit 307 are not limited.

Please refer to FIG. 2, which is a flow chart of a writing procedure according to a preferred embodiment of the present invention. As shown, when writing a program, the host 50 transmits a plurality of data to the controller 30, and first performs step S10, and the error correction code circuit 303 encodes the data to add an error correction code to generate a complex error correction. The data is transmitted to the mapping circuit 305. Then, in step S70, the mapping circuit 305 writes the unit data included in the error correction data to the data blocks of the memory device 10 in an interleaved manner or according to the mapping address.

Please refer to FIG. 3, which is a cross-sectional view of a write program according to a preferred embodiment of the present invention. As shown in the figure, when there are three pieces of data to be written into the storage device, the mapping circuit 305 corrects the unit data included in the data A, B, and C according to the interleaving manner transmitted by the micro processing unit 301. A ₁ , A ₂ -A _n , B ₁ , B ₂ -B _n , C ₁ , C ₂ -C _{n are} written into the complex data blocks D ₁ , D ₂ -D _{n in} one of the pages of the memory device 10, At the same time, the unit data A ₁ , A ₂ -A _n , B ₁ , B ₂ -B _n , C ₁ , C ₂ -C _n already contain the data in the error correction data A, B, C and the error correction. Code, without more explanation.

In addition, the foregoing is to write the data blocks D ₁ , D ₂ -D _n in an interleaved manner, but the present invention may also follow the mapping address without the need to follow the above-mentioned writing order or staggered position. The data A ₁ , A ₂ -A _n , B ₁ , B ₂ -B _n , C ₁ , C ₂ -C _{n are} written into the data blocks D ₁ , D ₂ -D _n , and there are many ways to map The manner of mapping is not intended to limit the present invention, and therefore, the description will not be repeated, as long as the errors are corrected for the unit data A ₁ , A ₂ -A _n , B ₁ , B ₂ included in the data A, B, and C. B _n , C ₁ , C ₂ -C _n are evenly distributed to the data blocks D ₁ , D ₂ -D _{n in} an interleaved manner or a mapped address, which is in accordance with the spirit of the present invention.

Please refer to FIG. 4, which is a flow chart of a writing process according to another preferred embodiment of the present invention. As shown in the figure, in this embodiment, steps S30 and S50 are further included between steps S10 and S70. Before the error correction data is stored in the memory device 10, step S30 is performed first, and the micro processing unit 301 first corrects the error. The error correction data outputted by the code circuit 303 is written to the memory device 10, and the number of errors of the error correction data is detected by the host 50 or the micro processing unit 301 (as illustrated in FIG. 1). Next, in step S50, the conversion circuit 307 converts the partial space of the data blocks of the memory device 10 to the data areas according to the number of errors of the error correction data detected by the host 50 or the micro processing unit 301. The spare blocks corresponding to the block.

Then, in step S70, the mapping circuit 305 writes the unit data included in the error correction data to the data blocks of the memory device 10 in an interleaved manner or according to the mapping address. Moreover, the mapping circuit 305 in this embodiment may also be controlled by the micro processing unit 301 to determine an interleaving manner or a mapping address according to the number of errors in the error correction data to better interleave the unit data. The mode or mapping address is written to the data blocks.

Please refer to FIG. 5A and FIG. 5B together, FIG. 5A is a schematic diagram of a ratio of a data block to a spare block according to a preferred embodiment of the present invention, and FIG. 5B is a data area of another preferred embodiment of the present invention. Schematic diagram of the block-to-spare block.

As shown in FIG. 5A, if the storage space occupied by the original data block D and the spare block S is 8K bytes and 1K bytes, respectively, the conversion circuit 307 determines that the number of errors in the error correction data is low. At a threshold, the conversion circuit 307 controls the memory device 10 to convert the storage space of the 0.5K byte in the data block D to the spare block S, so that the storage space occupied by the data block D and the spare block S It becomes 7.5K bytes and 1.5K bytes. In this way, the amount of data stored in the data block D can be reduced, and the space in which the error correction code can be used can be improved, thereby effectively improving the error correction capability of the error correction code.

In addition, as shown in FIG. 5B, when the conversion circuit 307 determines that the number of errors in the error correction data is higher than the threshold value, the conversion circuit 307 controls the memory device 10 to store the storage space of the 1K byte in the data block D. The conversion to the spare block S causes the storage space occupied by the data block D and the spare block S to become 7K bytes and 2K bytes. In this way, the correction ability of the error correction code is further improved.

In this embodiment, only one data block D and one spare block S are used for description. However, if the unit data is to be interleaved and stored in the plurality of data blocks, the conversion circuit 307 of the present invention controls the same. The storage space ratio of the data block and its corresponding spare block.

Please refer to FIG. 6, which is a flow chart of a reading procedure according to a preferred embodiment of the present invention. As shown in the figure, when the program is read, step S20 is first executed, and the mapping circuit 305 reads and restores the unit data stored in the data blocks of the memory device 10 to the plurality of data blocks according to the interleaving manner or the mapping address. The error correction data is output to the error correction code circuit 305. Next, in step S40, the error correction code circuit 305 decodes the error correction data transmitted by the mapping circuit 305, and restores the data to the host 50 for reading.

Please refer to FIG. 7, which is a schematic diagram of mapping of a reading program according to a preferred embodiment of the present invention. As shown in the figure, when the data needs to be read, the mapping circuit 305 compares the data blocks D ₁ and D ₂ -D of the memory device 10 according to the interleaving manner or mapping address transmitted by the micro processing unit 301. _n stored in the plurality of data units _{a 1, a 2 -A n,} B 1, B 2 -B n, C 1, C 2 -C n readout restore some error correction information a, B, C that, And transmitted to the error correction code circuit 303, the error correction code circuit 303 decodes the error correction data A, B, C, and generates the data that the host 50 can read, and transmits the data to the host 50 (or to the host 50 first) Buffer memory 309 is temporarily stored).

Wherein, although the unit data stored in each data block (for example, D ₁ ) of the present invention has only three A ₁ , B ₁ , and C ₁ , this is only a schematic diagram. In fact, in each data block It may include the complex unit data in the error correction data A, the complex unit data in the error correction data B, and the complex unit data in the error correction data C, that is, the units stored in the data blocks D ₁ , D _{2 -} D _n The number of data A ₁ , A ₂ -A _n , B ₁ , B ₂ -B _n , C ₁ , C ₂ -C _{n and} the order of writing, mapping address or interleaving are not limited, and can be done as needed Appropriate adjustment, and the size of each unit of data is not limited, it can be one-bit, complex, one-tuple or complex.

In summary, the storage device of the present invention and the access method thereof are distributed to the data blocks of the memory device by the error correction data, so that the errors in the error correction data are evenly dispersed. Up to the data blocks, or when reading, the data blocks and the unit data stored in the spare blocks and the error correction codes are restored to the error correction data according to the above manner, so that the data blocks are Errors in the data block are evenly spread to the error correction data. In addition, by changing the storage space ratio of the data block and the spare block in each page, the error correction ability of the error correction code is improved. In this way, it is possible to avoid errors in correcting the data or the fact that the data blocks contain errors that exceed their error correction capabilities, resulting in an inability to correct and thus loss of data.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

10‧‧‧ memory device

30‧‧‧ Controller

301‧‧‧Microprocessing unit

303‧‧‧Error correction code circuit

305‧‧‧ mapping circuit

307‧‧‧Transition circuit

309‧‧‧ Buffer memory

50‧‧‧Host

Claims (15)

A storage device comprising:
a memory device for storing a plurality of unit data; and a controller for receiving the plurality of data and encoding the data to generate a plurality of error correction data, the error correction data including the unit data, the controller The unit data of the error correction data is written to the memory device in an interleaved manner or according to a mapped address. The storage device of claim 1, wherein the controller reads the unit data stored in the memory device in the interleaving manner or according to the mapping address as the error correction data. The storage device of claim 2, wherein the controller comprises:
a mapping circuit controlled by a micro processing unit, and the unit data is written to the memory device in the interleaving manner or according to the mapping address, or the unit data stored in the memory device The error correction data is read out in the interleaving manner or in accordance with the mapping address. The storage device of claim 3, wherein the controller further comprises:
An error correction code circuit coupled to the micro processing unit and the mapping circuit, and controlled by the micro processing unit to encode the data to add a complex error correction code to generate the error correction data, or The error correction data is decoded to generate the data. The storage device of claim 1, wherein the controller first writes the error correction data to the plurality of data blocks of the memory device to detect the number of errors of the error correction data, and The partial space of the plurality of data blocks controlling the memory device is converted to the plurality of spare blocks corresponding to the data blocks according to the error correction errors of the data. The storage device of claim 5, wherein the controller comprises:
a conversion circuit controlled by a micro processing unit, and according to the error correction number of errors of the data, controlling a partial space of the data blocks of the memory device to be converted to the spares corresponding to the data blocks Block. The storage device of claim 1, wherein the controller divides the unit data in each of the error correction data evenly into the plurality of data blocks of the memory device in the interleaving manner. The storage device of claim 1, wherein the unit data is a single element, a complex number of bits, a one-dimensional group or a complex number of bytes. A storage device access method, the steps comprising:
The complex data is encoded to generate complex error correction data, the error correction data includes a plurality of unit data; and the unit data of the error correction data is written to a memory device in an interleaved manner or according to a mapping address. The access method of claim 9, further comprising: reading the unit data stored by the memory device in the interleaving manner or according to the mapping address as the error correction data. The access method of claim 9, wherein the step of encoding the complex data to generate the complex error correction data comprises: encoding the data to add a complex error correction code, and generating the error correction data. The access method of claim 9, further comprising: decoding the error correction data to generate the data. For example, the access method described in claim 9 further includes:
Writing the error correction data to the plurality of data blocks of the memory device to detect the number of errors of the error correction data; and correcting the number of errors of the data according to the errors, and multiplexing the memory device A portion of the data block is converted to a plurality of spare blocks corresponding to the data blocks. The access method of claim 9, wherein the step of writing the unit data in an interleaved manner or according to a mapping address to a memory device comprises: each of the interleaving manners The unit data in the error correction data are evenly dispersed and written into the plurality of data blocks of the memory device. The access method of claim 9, wherein the unit data is a single element, a complex number of bits, a one-dimensional group or a complex byte.