TW201521119A - Method of fabricating semiconductor device - Google Patents

Abstract

Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided, wherein a plurality of gates are formed on the substrate and a gap exists between two adjacent gates. A first material layer covering the gates and filling into the gaps is formed on the substrate. A portion of the first material layer is removed to form a patterned layer on the substrate, wherein the patterned layer includes a plurality of islands in one of the gaps. A protection layer is formed on a sidewall of each of the islands. A second material layer surrounding the patterned layer is formed on the substrate. The patterned layer is removed to form a plurality of openings in the second material layer. A conductive material is filled into each of the openings.

Description

Semiconductor component manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a memory device.

In general, as the size of the memory shrinks, in order to overcome the increasingly smaller line width and prevent misalignment of the contact window, a self-aligned contact (SAC) process is used. .

In the self-aligned contact window process, the thickness of the spacers on the sidewalls of the gates affects the size of the contact windows formed between the gates. However, since the memory element includes the memory cell region and the peripheral region, and the components of the memory cell region and the peripheral region have different requirements for the thickness of the spacer, the complexity of the process is increased. Generally, spacers are formed on the gate sidewalls of the memory cell region and the peripheral region at the same time, and then, in order to form the source and drain regions of the peripheral region, the gate walls of the peripheral region are usually formed again. Second spacer. Wherein, the second spacer material simultaneously fills the opening between the gates of the memory cell region, and after the source and drain regions are formed in the substrate of the peripheral region, the second spacer of the peripheral region is removed together And a second spacer material between the gates of the memory cells. However, since the opening between the gates of the memory cell region has a large aspect ratio, it is not easy to remove the second spacer material between the gates, and may be damaged during the removal process. To remember Recall the gaps in the cell area. As a result, it may result in the gap wall not providing good electrical insulation for the gate and affecting the size of the contact window formed by the subsequent use of the spacer.

The present invention provides a method of fabricating a semiconductor device that solves the problem of plug disconnection that is common in similar processes.

The method of manufacturing a semiconductor device of the present invention includes the following steps. A substrate is provided on which a plurality of gates have been formed, with gaps between adjacent two gates. A first material layer covering the gate and filling the gap is formed on the substrate. A portion of the first material layer is removed to form a pattern layer on the substrate, the pattern layer including a plurality of island regions located in a certain gap. A protective layer is formed on the sidewalls of the island area, respectively. A second material layer surrounding the pattern layer is formed on the substrate. The pattern layer is removed to form a plurality of openings in the second material layer. A conductive material is filled in each opening.

In an embodiment of the invention, the pattern layer further comprises a strip region located in the other gap.

In an embodiment of the invention, the method of forming a protective layer on the sidewall of the island region comprises the following steps. A third material layer is conformally formed on the substrate and the island region. A tilt implant step is performed to dope the third material layer on the sidewalls of the island region. An undoped third material layer between the island regions on the substrate is removed.

In an embodiment of the invention, the tilting step of the oblique implanting step is between 0 and 20 degrees.

In an embodiment of the invention, the method of removing the undoped third material layer is a wet etching process.

In an embodiment of the invention, after forming the third material layer, before performing the oblique implantation step, further comprising removing the third material layer on the gate.

In an embodiment of the invention, the material of the first material layer is polycrystalline germanium.

In an embodiment of the invention, the material of the protective layer is amorphous germanium.

In an embodiment of the invention, the substrate includes a memory cell region and a peripheral region, the gate electrode and the first material layer are formed on the memory cell region, and after the forming the first material layer, the manufacturing method of the semiconductor device further includes the substrate A barrier layer is formed overlying the peripheral region and the first material layer.

In an embodiment of the invention, after the barrier layer is formed, the method of fabricating the semiconductor device further includes forming another material layer on the peripheral region to cover the barrier layer on the peripheral region.

Based on the above, the manufacturing method of the semiconductor of the present invention covers the respective island regions between the gates with a protective layer, and these island regions are replaced by conductive materials to form plugs, which are covered by the protective layer to prevent entry of the impurity materials. Holes inevitably formed in the island area, so that the island area can be successfully removed in subsequent processes.

The above described features and advantages of the present invention will be more apparent from the following description.

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ memory area

103‧‧‧Active Area

104‧‧‧The surrounding area

110, 120‧‧ ‧ gate

112, 122, 124‧‧ ‧ spacers

114‧‧‧ gap

126‧‧‧Source and bungee area

130, 150, 160‧‧‧ material layers

132, 134, 135‧‧

136‧‧‧Electrical materials

140‧‧‧Barrier layer

161‧‧‧pattern layer

162‧‧‧ Island District

162a‧‧‧ side wall

163‧‧‧Protective material layer

Section 163a, 163b‧‧‧

164‧‧‧ District

165‧‧‧protection layer

200, 202‧‧‧ implant steps

1A to 1N are flowcharts showing a method of fabricating a semiconductor device according to a first embodiment of the present invention.

2A and 2B are top views of Figs. 1A and 1F, respectively.

1A to FIG. 1N are schematic cross-sectional views showing a process of fabricating a semiconductor device according to a first embodiment of the present invention. In order to clearly show the three-dimensional structure of each stage in the manufacturing process, a top view of a partial area of FIGS. 1A and 1F is additionally presented in FIGS. 2A and 2B.

Referring to FIG. 1A, first, a substrate 100 is provided. The substrate 100 includes a memory cell region 102. And the peripheral region 104, a plurality of gates 110 on the memory cell region 102 and a gate electrode 120 on the peripheral region 104 have been formed on the substrate 100, and spacers 112 are formed on the sidewalls of the gate electrodes 110, 120, respectively. 122. The adjacent two gates 110 are separated by a gap 114.

The substrate 100 may be a semiconductor substrate such as an N-type germanium substrate, a P-type germanium substrate, or a tri-five semiconductor substrate. Gate 110 is depicted as a single layer structure in FIG. 1A, and gate 110 in this example may contain doped polysilicon. Alternatively, in other embodiments, the gate 110 can also be a stacked structure of oxide/nitride/oxide (ONO) plus doped polysilicon. As for the material of the gate 120, it may also be doped polysilicon. The material of the spacers 112, 122 is, for example, tantalum nitride.

Referring to FIG. 1B, a material layer 130 is formed on the substrate 100. The material layer 130 completely covers the memory cell region 102 and the peripheral region 104 and fills the gap 114. The material layer 130 contains, for example, polycrystalline germanium, and the formation method thereof is, for example, a chemical vapor deposition method. In the present embodiment, the formation of the material layer 130 further includes performing a planarization process such as a chemical mechanical polishing (CMP) on the polycrystalline germanium layer after the polycrystalline germanium is formed by chemical vapor deposition.

Referring to FIG. 1C, material layer 130 covering peripheral region 104 is then removed to expose gate 120 and spacer 122. A method of removing a portion of the material layer 130 is, for example, a reactive ion etch (RIE).

Referring to FIG. 1D, a spacer 124 is formed on the spacer 122. The spacer 124 is formed by, for example, forming a layer of spacer material (not shown) on the substrate 100 by chemical vapor deposition, and then performing an anisotropic etching process to remove a portion of the spacer material layer in the gap. A spacer structure is formed on the wall 122. Wherein, the material of the spacers 124 is, for example, tantalum nitride, and the method of removing a portion of the spacer material layer to form the spacers 124 is, for example, reactive ion etching.

Then, using the spacers 124 as a mask, an implantation process is performed, which is formed on both sides of the gate 120. The source and the bungee area are 126. It should be noted that after the source and drain regions 126 are formed on both sides of the gate 120, the spacers 124 may or may not be removed. In the present embodiment, the spacers 124 are not removed. In short, the step of removing the spacers 124 is an optional step.

It is worth noting here that, in general, when the spacers 124 are formed, the spacer material is simultaneously formed on the memory cell region 102, filled in the gaps 114, and removed when the spacers 124 are removed. The spacer material in the gap 114. However, in the present embodiment, since the material layer 130 covers and protects the gate 110 and the spacer 112 of the memory cell region 102, the formation or removal process of the spacer 124 (including deposition or etching processes) does not occur. Damage is caused to the gate 110 or the spacer 112, so that the spacer 112 can maintain a good structure. In other words, the material layer 130 is adapted to protect the memory cell region 102 from damage that may be caused by any processing process performed by the peripheral region 104.

Referring to FIG. 1E, a barrier layer 140 is formed on the substrate 100 to cover the material layer 130 and the peripheral region 104. The material of the barrier layer 140 is, for example, tantalum nitride, and the formation method thereof is, for example, a chemical vapor deposition method. In the present embodiment, the barrier layer 140 covers the gate 120, the spacers 122, and the spacers 124 on the peripheral region 104, while also covering the material layer 130 on the memory cell region 102.

Next, a material layer 150 is formed over the peripheral region 104 to cover the barrier layer 140 on the peripheral region 104. In the present embodiment, the material layer 150 includes bismuth borate glass or ruthenium oxide, and the formation method thereof is, for example, a chemical vapor deposition method. The material layer 150 is formed, for example, by forming a material layer (not shown) covering the peripheral region 104 and the memory cell region 102 on the substrate 100, and then planarizing the material layer with the barrier layer 140 as a termination layer. The material layer 150 is obtained by the process. Finally, the top surface of the material layer 150 is substantially in the same plane as the top surface of the barrier layer 140. Among them, the planarization process is, for example, a chemical mechanical polishing process.

In general, if the barrier layer 140 is not formed on the material layer 130, then the material is When the material layer 150 is subjected to a planarization process, the material layer 130 is used as a termination layer. As a result, the material layer 150 may have an overetching problem and may cause the material layer 130 to have a surface depression phenomenon. However, in the present embodiment, since the material layer 130 is covered with the barrier layer 140, when the material layer 150 is planarized, the barrier layer 140 can be used as the termination layer, and since the barrier layer 140 usually has The higher density allows the above problems to occur with the material layer 150 and the material layer 130.

Referring to FIG. 1F, a portion of the barrier layer 140 and the portion of the material layer 130 on the memory cell region 102 are removed to form a pattern layer 161 and an opening 132 exposing the gate 110 on the substrate 100. In the present embodiment, the method of removing a portion of the barrier layer 140 and the material layer 130 may be a reactive ion etching method.

In order to further understand the three-dimensional structure of the pattern layer 161, please refer to FIG. 2B together, which is a top view of the memory cell region 102 when the fabrication of the semiconductor proceeds to FIG. 1F. The spacers 112 are omitted in FIG. 2B to present the relationship between the pattern layer 161 and the gate 110. 2B, the pattern layer 161 includes a plurality of island regions 162 located in a certain gap 114 and strip regions 164 located in other gaps 114.

In addition, FIG. 1G is a cross-sectional view taken along line BB' of FIG. 2B when the fabrication of the semiconductor proceeds to the step illustrated in FIG. 1F. Referring to FIG. 1F, FIG. 1G and FIG. 2B together, in this cross section, it can be seen that the substrate 100 is divided into a plurality of active regions (AA) 103 by a plurality of isolation structures 101, wherein the isolation structure 101 is, for example, The material is a shallow trench isolation (STI) of yttrium oxide. In FIG. 1G, the height of the island region 162 is, for example, between 2000 Å and 7000 Å; the spacing of adjacent island regions 162 is, for example, between 100 Å and 500 Å.

Referring to FIG. 1H, a protective material layer 163 is conformally formed on the substrate 100 and the island region 162. The thickness of the protective material layer 163 is, for example, between 50 Å and 300 Å. Protective material The material of layer 163 may be the same as island 162, or both may have similar etch rates in a particular etchant. For example, in the case where the material of the island region 162 is polycrystalline germanium, the material of the protective material layer 163 may be amorphous germanium, and the forming method thereof is, for example, a chemical vapor deposition method using disilane as a precursor. Furthermore, as can be seen from FIG. 1H, the protective material layer 163 can be divided into a portion 163a on the surface (including the side surface and the top surface) of the island region 162, and between the adjacent two island regions 162, disposed in Portion 163b on substrate 100.

Referring to FIG. 1I, next, an oblique implantation step is performed to dope the portion 163a of the protective material layer 163. Here, the tilt implant step can be further subdivided into implant steps 200 and 202. The former is implanted at an angle of plus x degrees with respect to the normal direction of the surface of the substrate 100 to dope the portion 163a on the left side wall of the island region 162 in the drawing; the implant angle of the latter is a corresponding negative x degree Doping the portion 163a on the right side wall of the island region 162, where x is between 0 and 20 degrees. Furthermore, the two implantation steps can have a heavy doping concentration (for example between 2 x 10 ¹⁵ and 4 x 10 ¹⁶ ) and a shallow doping depth (for example between 50 Å and 300 Å).

The main purpose of the implantation is to change the properties of the portion 163a of the protective material layer 163 such that its etching rate in the same etching liquid is different from that of the other portion 163b, for example, much lower than the portion 163b. For this purpose, in the example in which the protective material layer 163 is composed of amorphous germanium, the dopant is, for example, an element such as BF ₂ , P or As.

Referring to FIG. 1J, then, the portion 163b is removed, that is, the undoped protective material layer 163 on the substrate 100 between the adjacent two island regions 162 is removed, thereby forming the coated island region 162. The sidewalls and the top protective layer 165. Since the etching rate of the portion 163a and the portion 163b is different for the specific etching liquid through the aforementioned implantation processing, the method of removing the portion 163b may be a wet etching method, for example, a solution such as NH ₄ OH, DHF, BOE, HNO ₃ or the like. It is an etchant.

Referring to FIG. 1K, a material layer 160 is then formed on the substrate 100, and the material layer 160 covers the substrate 100 and surrounds the island region 162. The material layer 160 may include tantalum nitride, hafnium oxide or boron germanium. Borosilicate glass. Of course, the method of forming the material layer 160 may include a chemical vapor deposition process and a subsequent chemical mechanical polishing process.

In a subsequent process, island regions 162 (and protective layer 165 and barrier layer 140) are removed such that openings are formed in the remaining material layer 160. A conductive material is then filled into the opening to form a plug. In order not to damage other structures on the substrate 100, the aforementioned removal process may use etching to select a very high etchant (or RIE), in other words, almost only the island region 162 is etched.

On the other hand, the inventors have found that during the formation of the island region 162, voids may be generated therein for various reasons. For example, the foregoing has exemplified that the material of the island region 162 (material layer 130) may be polycrystalline germanium, and the deposition of polycrystalline germanium may be performed in a high temperature furnace tube. If the temperature is high enough, the polycrystalline germanium material may be recrystallized or crystallized. The phenomenon of growth may cause holes in the island area 162 due to the movement of helium atoms. The phenomenon of such hole formation is more pronounced as the size is smaller, the aspect ratio of the gap 114 is larger, or the contour of the gate 110 is closer to vertical.

A hole may be formed in a central portion of the island region 162 or formed in a portion close to the side wall 162a to form an opening as shown by the dotted circular wire frame in Fig. 1K. Once the holes are formed on the side walls 162a, foreign matter may enter therein during subsequent processes. For example, when the material layer 160 is formed, constituent atoms of the material layer 160 may be filled into the holes. The material filled in the holes may be unaffected by the etching process when the island region 162 is removed (as described above, if an etching solution is used in the process, the etching solution is selected to be very high; if RIE is used, Between the different materials, the selection ratio will also change drastically) and remain, which hinders the subsequent filling of the conductive material. In severe cases, it may cause an open circuit.

The formation of the protective layer 165 is a concept in response to the above problems. Due to the presence of the protective layer 165, when the material layer 160 is subsequently formed, even if holes are actually formed in the island region 162, the source Impurity atoms from other process gases are also blocked by the protective layer 165 outside the pores. Therefore, the island area 162 can be removed smoothly and completely thereafter without residual matter.

It should also be noted that in FIGS. 1J and 1K, the protective layer 165 is depicted as completely covering the island region 162. However, the inventors have found that the formation of holes tends to concentrate in the middle portion of the island region 162, as shown by the dotted square wire frame in Fig. 1K, and therefore, the protective layer 165 may be formed only on the corresponding side wall portion. That is, the protective material layer 163 formed at the uppermost end portion and the lowermost end portion of the side wall 162a may also be removed. Of course, which portions of the protective material layer 163 are to be removed can be accomplished by adjusting the angles of the implantation steps 200 and 202.

FIG. 1L is a cross-sectional view in the other direction (the same cross-section as FIGS. 1A to 1F, FIG. 1M to FIG. 1N) when the fabrication of the semiconductor proceeds to the step illustrated in FIG. 1K. It should be noted here that there is no protective layer 165 on the top of the gate 110. This can be accomplished by forming a protective material layer 163, performing a reactive ion etching step, removing the protective material layer 163 on the gate 110, and then performing the aforementioned implantation step, removing portion 163b. And the step of forming material layer 160.

Referring to FIG. 1M, the protective layer 165, the barrier layer 140 on the memory cell region 102, and the pattern layer 161 (including the island region 162 and the strip region 164) are removed to form a plurality of openings 134 in the memory cell region 102. . The method of removing the foregoing structure is, for example, a dry etching method or a wet etching method. Then, a mask pattern (not shown) is defined on the peripheral region 104, and a portion of the material layer 150 located in the peripheral region 104 is removed through the mask pattern to form an opening 135 in the peripheral region 104, wherein the opening 135 is exposed. Source and drain regions 126. The method of removing the material layer 150 is, for example, a dry etching method or a wet etching method.

Referring to FIG. 1N, conductive material 136 is then filled in openings 134, 135 to form plugs or wires between adjacent spacers 112 and to form plugs or wires in peripheral region 104. Conductive material 136 is, for example, tungsten, copper, aluminum, or other suitable metal.

In summary, the semiconductor manufacturing method of the present invention first covers the components of the memory cell region with the material layer. Therefore, when the peripheral region is deposited and etched, the components of the memory cell region are not damaged, and the memory cell region is The spacers on the sidewalls of the gates maintain a good structure. In this way, the spacer can provide good electrical insulation for the gate, and can form a self-aligned contact window between two adjacent spacers, so that the memory has good component characteristics.

In addition, the semiconductor manufacturing method of the present invention further covers each island region between the gates with a protective layer, and these island regions are replaced by conductive materials to form plugs, which are covered by the protective layer to prevent entry of impurity materials. The holes that are inevitably formed in the island area can be smoothly removed in the subsequent process, which solves the plug disconnection problem commonly found in such processes.

Although the present invention has been described above by way of examples, it is not intended to limit the invention. Any changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of this application is subject to the definition of the scope of the patent application attached.

100‧‧‧Base

101‧‧‧Isolation structure

103‧‧‧Active Area

140‧‧‧Barrier layer

162‧‧‧ Island District

162a‧‧‧ side wall

165‧‧‧protection layer

Claims (10)

A method of fabricating a semiconductor device, comprising: providing a substrate on which a plurality of gates have been formed, wherein a gap is formed between two adjacent gates; forming a gate on the substrate and filling the gates a first material layer of the gap; removing a portion of the first material layer to form a pattern layer on the substrate, the pattern layer comprising a plurality of island regions located in a gap; respectively forming sidewalls of the island regions a protective layer; a second material layer surrounding the pattern layer is formed on the substrate; the pattern layer is removed to form a plurality of openings in the second material layer; and a conductive material is filled in each of the openings. The method of fabricating a semiconductor device according to claim 1, wherein the pattern layer further comprises a strip region located in another gap. The method of fabricating a semiconductor device according to claim 1, wherein the method of forming the protective layers on the sidewalls of the island regions comprises conformally forming a surface on the substrate and the island regions a three-material layer; performing a tilt implantation step to dope the third material layer on the sidewalls of the island regions; and removing undoped on the substrate between the island regions The third material layer. The method of manufacturing a semiconductor device according to claim 3, wherein the oblique implantation step has an inclination angle of between 0 and 20 degrees. The method of manufacturing a semiconductor device according to claim 3, wherein the method of removing the undoped third material layer is a wet etching method. A method of manufacturing a semiconductor device according to claim 3, wherein the method of forming After the third material layer, before performing the oblique implantation step, further comprising removing the third material layer on the gates. The method of manufacturing a semiconductor device according to claim 1, wherein the first material layer contains polysilicon. The method of producing a semiconductor device according to claim 7, wherein the protective layer contains an amorphous germanium. The method of fabricating a semiconductor device according to claim 1, wherein the substrate comprises a memory cell region and a peripheral region, the gate electrodes and the first material layer are formed on the memory cell region, and the first After the material layer is formed, the method further includes: forming a barrier layer on the substrate to cover the peripheral region and the first material layer. The method of manufacturing a semiconductor device according to claim 9, wherein after the barrier layer is formed, the method further comprises: forming a third material layer on the peripheral region to cover the barrier layer on the peripheral region .