TW201515153A - Static random access memory cell - Google Patents

Abstract

A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly.

Description

Static random access memory unit

The invention discloses a static random access memory unit, and more particularly to a static random access memory unit coupled to an auxiliary capacitor through an auxiliary switch at a storage node.

Static Random Access Memory (SRAM) has been widely used in processors because of its high access speed, low power consumption, simple control circuit, and inability to disappear when memory data is continuously supplied. Take (CPU cache) and hard disk buffer memory (buffer cache) and other purposes. In the prior art, regardless of the 6T or 8T SRAM cell (hereinafter referred to as SRAM cell), the core part is a latch circuit composed of two inverter circuits, when a bit is 0. After 1 or 1 is written, the value is locked by the latch circuit. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art 6T SRAM cell 100. When the SRAM cell 100 stores 1, the storage node NA is latched at a high potential 1, and the storage node NB Is latched to a low potential of zero. When the SRAM cell 100 stores 0, the storage node NA is latched to a low potential of 0, and the storage node NB is latched at a high potential of one. The voltages of the storage node NA and the storage node NB are written or read through the first bit line BL and the second bit line BLB, respectively.

Please refer to FIG. 2 , which is a schematic diagram of a static noise margin (SNM) curve corresponding to the SRAM cell 100 . The static noise boundary curve is a characteristic curve used in the field to evaluate the SRAM cell. The interpretation method is a square side length framed by a butterfly curve in the measurement chart. The longer the side length, the more it is called The larger the SNM, the less likely the data stored in the SRAM cell (0 or 1 of a bit) to be rewritten. Due to the SRAM unit The operation of reading and writing is similar, so the SRAM unit has the risk of being mistakenly written when reading is performed. A large SRAM unit of SNM indicates that the stored data is relatively stable and is not easily miswritten. As can be seen from Figure 2, the SRAM cell 100 corresponds to a square side length of only about 0.2 volts.

Please refer to FIG. 3 again. FIG. 3 is a schematic diagram corresponding to the write boundary (Write Margin; WRM) curve of the SRAM cell 100. The write boundary curve is also used in the art to evaluate a characteristic curve of the SRAM cell, which can be interpreted by observing the voltage of the transition point. For example, the solid line part in FIG. 3 is the voltage of the storage node NA of the SRAM cell 100. V _NA , the dotted line is the voltage V _NB of the storage node NB of the SRAM cell 100. When the voltage value V _BL supplied through the first bit line BL is continuously decreased along the horizontal axis, the V _{BL is} reduced to about 3 by the third figure. At 0.45 volts, V _NA occurs from the original 1.2 volt output high voltage VOH (operating voltage, also corresponding to logic 1) to an output low voltage VOL (corresponding to logic 0) of less than 0.2 volts, that is, say, V _NA occur down to a logic 1 becomes logic 0 is transited 0.45 volts at the time of V _BL. The output high voltage VOH is a high voltage output of one of the SRAM cells 100, which can be, for example, 1.2 volts and is used to represent a high potential logic 1 when outputting; and the output low voltage VOL is a low voltage output of the SRAM cell 100. It can be, for example, 0.2 volts and is used to represent a logic 0 of low potential at the time of output. The write boundary WRM is defined as V _BL when the voltage V _{NA of the} storage node NA is equal to the average of the output high voltage VOH and the output low voltage VOL. The lower the write boundary WRM, the lower the potential of V _BL that causes V _NA to transition when _{VBL is} gradually lowered. The lower the WRM of the SRAM cell, the more stable the data it stores and the easier it is to be rewritten. As can be seen from FIG. 3, the WRAM of the SRAM cell 100 is as high as 0.45 volts.

Please refer to FIG. 4, which is a schematic diagram showing the change of the minimum operable voltage (Vcc_min) of the prior art SRAM cell 100 after the High Temperature Operating Life (HTOL) test. The high temperature operating life test is a reliability test for placing the SRAM unit in a high temperature environment for rapid aging. Vcc_min is the smallest of an SRAM cell The operable operating voltage, the smaller the value, indicates that the SRAM cell is healthier and more stable. As can be seen from Fig. 4, after the high-temperature operation life test, the Vcc_min of the SRAM cell 100 is shifted upward, and it is understood that the reliability of the prior art SRAM cell 100 against high temperature operation needs to be improved.

The prior art, such as the architecture of the SRAM cell 100, can latch data, but it only relies on the parasitic capacitance of the storage nodes NA and NB to store data, and when it is subjected to high-speed access on a daily basis, placed in a high temperature environment, the stability is lowered, or long-term acceptance is accepted. When the cosmic ray α-particle collides, the value of 0 or 1 stored in the SRAM cell 100 is prone to erroneous data inversion. Therefore, there is a need in the art for a solution to improve the stability and controllability of prior art SRAM cells.

An embodiment of the invention discloses an SRAM cell comprising a first P-type MOS transistor, a first N-type MOS transistor, a second P-type MOS transistor, and a second N-type. A gold-oxide semi-transistor, a third switch, a fourth switch, a first switch and a first capacitor. The gate of the first N-type MOS transistor is coupled to the gate of the first P-type MOS transistor, and the source of the first P-type MOS transistor is coupled to the gate a source of the second P-type MOS transistor, the gate of the second N-type MOS transistor is coupled to the gate of the second P-type MOS transistor, the first N-type gold oxide The source of the second transistor is coupled to the source of the second N-type MOS transistor, and the first end of the third switch is coupled to the drain of the first P-type MOS transistor. a drain of the first N-type MOS transistor and a gate of the second P-type MOS transistor, the first end of the fourth switch being coupled to the second P-type MOS transistor a drain, a drain of the second N-type MOS transistor, and a gate of the first P-type MOS transistor, the first end of the first switch is coupled to the first P-type gold The first end of the first capacitor is coupled to the second end of the first switch.

Another embodiment of the present invention discloses a method for operating an SRAM cell. The SRAM cell includes a first inverter, a second inverter coupled to the first inverter, a first capacitor, and a first capacitor. The first switch is coupled between the first inverter and the first capacitor. The method includes When the data writing is to be performed on the SRAM cell, the first switch is turned off.

The SRAM unit disclosed in the embodiment of the present invention can simultaneously consider the high-speed access and data stability of the SRAM unit, and the controllability after mass production.

100, 200, 300‧‧‧ SRAM units

NA, NB‧‧‧ storage node

210‧‧‧First P-type MOS semi-transistor

220‧‧‧First N-type gold oxide semi-transistor

230‧‧‧Second P-type gold oxide semi-transistor

240‧‧‧Second N-type oxy-oxygen semiconductor

250‧‧‧third switch

260‧‧‧fourth switch

270‧‧‧ first switch

280‧‧‧second switch

Ca‧‧‧first capacitor

Cb‧‧‧second capacitor

C _NA ‧‧‧Parasitic capacitance

BL‧‧‧first bit line

BLB‧‧‧ second bit line

WL‧‧‧ character line

CL‧‧‧ control signal line

V _BL ‧‧‧The voltage value of the first bit line BL

Vcc_min‧‧‧ minimum operable voltage

Vcc‧‧‧ operating voltage source

V _NA ‧‧‧Storage node NA voltage

V _NB ‧‧‧Storage node NB voltage

VOH‧‧‧ output high voltage

VOL‧‧‧ output low voltage

1110, 1120, 1310, 1320‧‧ steps

Figure 1 is a schematic diagram of a prior art SRAM cell.

Figure 2 is a schematic diagram of the static noise boundary curve of the prior art SRAM cell.

3 is a schematic diagram of a write boundary curve of a prior art SRAM cell. FIG. 4 is a schematic diagram showing a change in minimum operable voltage of a prior art SRAM cell after a high temperature operational lifetime test.

Fig. 5 is a schematic view showing an SRAM cell of the first embodiment of the present invention.

Figure 6 is a schematic diagram of the single-sided equivalent capacitance of the SRAM cell of Figure 5.

Figure 7 is a schematic diagram of the static noise boundary of the SRAM cell of Figure 5.

Figure 8 is a schematic diagram of the write boundary curve of the SRAM cell of Figure 5.

Figure 9 is a schematic diagram of the minimum operable voltage change of the SRAM cell after the high temperature operational lifetime test in Figure 5.

Figure 10 is a timing diagram of the word line and the control signal line of the SRAM cell of Figure 5.

Figure 11 is a flow chart showing the method of reading and writing SRAM cells in Figure 5.

Figure 12 is a schematic diagram of an SRAM cell in accordance with a second embodiment of the present invention.

Figure 13 is a flow chart showing the method of reading and writing SRAM cells in Fig. 12.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of the SRAM unit 200 according to the first embodiment of the present invention. As shown in FIG. 5, the SRAM cell 200 includes a first P-type MOS transistor 210, a first N-type MOS transistor 220, a second P-type MOS transistor 230, and a second N-type gold oxide. a half transistor 240, a third switch 250, a fourth switch 260, a first switch 270, a second switch 280, The first capacitor Ca and the second capacitor Cb. The gate of the first N-type MOS transistor 220 is coupled to the gate of the first P-type MOS transistor 210, and the source of the first P-type MOS transistor 210 is coupled to the second The source of the P-type MOS transistor 230 is coupled to the operating voltage source Vcc, and the gate of the second N-type MOS transistor 240 is coupled to the gate of the second P-type MOS transistor 230. The first N-type MOS transistor 220 is coupled to the source of the second N-type MOS transistor 240, and the first end of the third switch 250 is coupled to the first P-type gold. The drain of the oxygen semiconductor 210, the drain of the first N-type MOS transistor 220, and the gate of the second P-type MOS transistor 230, the first end of the fourth switch 260 is coupled to the first The drain of the second P-type MOS transistor 230, the drain of the second N-type MOS transistor 240, and the gate of the first P-type MOS transistor 210. Therefore, the first P-type MOS transistor 210 and the first N-type MOS transistor 220 form a first inverter, the second P-type MOS transistor 230 and the second N-type MOS. The crystal 240 forms a second inverter, and the first inverter is coupled to the second inverter system in an alternating manner.

The first end of the first switch 270 is coupled to the first end of the first P-type MOS transistor 210. The first end of the first capacitor Ca is coupled to the second end of the first switch 270, and the second switch The first end of the 280 is coupled to the drain of the second P-type MOS transistor 230, and the first end of the second capacitor Cb is coupled to the second end of the second switch 280. The node at the drain of the first P-type MOS transistor 210 is the first storage node NA, and the node at the drain of the second P-type MOS transistor 230 is the second storage node NB. Comparing the SRAM unit 200 with the SRAM unit 100 of the prior art of FIG. 1 , the SRAM unit 200 disclosed in the present invention differs from the prior art SRAM unit 100 in that the SRAM unit 200 transmits the first through the first storage node NA. The switch 270 is coupled to the first capacitor Ca and coupled to the second capacitor Cb through the second switch 280 at the second storage node NB. In addition, the second end of the third switch 250 is coupled to a first bit line BL, and the second end of the fourth switch 260 is coupled to a second bit line BLB. The third switch 250 and the fourth switch 260 are controlled to be turned on or off by a word line WL, and the first switch 270 and the second switch 280 are controlled to be turned on by the control signal line CL. Or close. First bit line BL and second The bit line BLB is used to supply data written to the SRAM cell 200 or to read data stored in the SRAM cell 200. The second end of the first capacitor Ca and the second end of the second capacitor Cb may be connected to, for example, a ground terminal, a system voltage source, or another metal layer or the like.

The SRAM cell 100 of the prior art is logically a latch circuit composed of two inverters latching 0 or 1 of one bit to be stored, which relies on the parasitic capacitance of the storage nodes NA, NB for storage. The one-digit 0 or 1 data. If the parasitic capacitance of the storage nodes NA and NB is larger, the stability of the stored data is higher. Referring to FIG. 5 together with FIG. 6, FIG. 6 is a schematic diagram of a single-sided equivalent capacitance of the SRAM cell 200 according to the first embodiment of the present invention, wherein the parasitic capacitance C _NA is parasitic on the storage node NA of the SRAM cell 200. capacitance. When the first switch 270 of the SRAM cell 200 is turned on, the equivalent capacitance on the first storage node NA can be regarded as shown in FIG. 6 , which is a parallel connection of the parasitic capacitance C _NA and the first capacitor Ca, and the first storage node NA The equivalent capacitance is: C _NA(new) = C _NA + Ca, that is, the sum of the parasitic capacitance C _NA and the first capacitance Ca, which is greater than the parasitic capacitance C _NA on the original storage node _NA .

Please refer to FIG. 7 in conjunction with FIG. 2, which is a schematic diagram of the static noise boundary of the SRAM cell according to the first embodiment of the present invention. As can be seen from FIG. 7, when the first switch 270 and the second switch 280 are both turned on, the square side length in the SNM graph of the SRAM cell 200 is about 0.35 volts, which is higher than the SNM of the SRAM cell 100 in FIG. The square side length in the graph is long, so that the information stored in the SRAM cell 200 is more stable than the prior art SRAM cell and is not easily rewritten when the first switch 270 and the second switch 280 are both turned on.

Referring to FIG. 3 with reference to FIG. 8, FIG. 8 is a schematic diagram of a write boundary (Write Margin; WRM) curve of the SRAM cell 200 according to the first embodiment of the present invention. In Fig. 8, the solid line portion is the voltage V _NA of the storage node NA, and the broken line portion is the voltage V _NB of the storage node NB, and the voltage value V _BL supplied through the first bit line BL is continuously decreased along the horizontal axis. When it is seen from Fig. 8 that V _BL drops to about 0.4 volts, V _NA is reduced from an output high voltage VOH of 1.2 volts (operating voltage, also corresponding to logic 1) to an output low voltage VOL of less than 0.2 volts (corresponding to logic The transition curve of 0) spans the average of the high voltage VOH and the low voltage VOL, that is, when V _BL drops to 0.4 volts, the transition of V _NA from logic 1 to logic 0 is valid. Therefore, as can be seen from Fig. 8, the write boundary WRM of the SRAM cell 200 is 0.4 volt. It can be seen that the SRAM cell 200 of the first embodiment of the present invention is written when the first switch 270 and the second switch 280 are turned on, compared to the write boundary WRM of the SRAM cell 100 in the prior art. The boundary WRM is lower. Therefore, compared with the prior art, when the first switch 270 and the second switch 280 are turned on, the internal data of the SRAM unit 200 is less easily rewritten.

Please refer to Figure 9 in Figure 4. Fig. 9 is a view showing the change of the minimum operable voltage Vcc_min of the SRAM cell 200 of the first embodiment of the present invention after the high-temperature operation life test. After the comparison, the VRAM_min is increased, that is, the stability is decreased after the high-temperature operation life test of the SRAM cell 100 in the prior art. However, after the high-temperature operation life test of the SRAM cell 200 of the first embodiment of the present invention, the first The influence of the capacitance Ca and the second capacitance Cb, Vcc_min is slightly lowered, so that the Vcc_min characteristic of the SRAM cell 200 is also improved after the first capacitance Ca and the second capacitance Cb are coupled.

Referring to Figures 2 to 4, it can be seen from Figures 7 to 9 that when the first switch 270 and the second switch 280 are turned on, the SRAM cell 200 is relatively stable and difficult to be stored compared to the prior art SRAM cell 100. The advantages of rewriting. However, since the SRAM unit is a readable and writable memory unit, the storage data is stable and difficult to rewrite, and the like is an advantage in reading, but it is a disadvantage when writing, because the stored data is too stable. It also causes the write speed to drop. Referring to FIG. 5 with reference to FIG. 10, FIG. 10 is a timing diagram of the word line WL and the control signal line CL of the SRAM cell 200 according to the first embodiment of the present invention. In the SRAM unit 200 disclosed in the first embodiment of the present invention, the user can control the control signal line CL to convert the first switch 270 and the second switch 280 into Off, so that the storage nodes NA and NB of the SRAM cell 200 are no longer coupled to the first capacitor Ca and the second capacitor Cb, so that the difficulty of writing is reduced, thereby improving the pair of SRAM cells 200. The speed at which data is written. Since the characteristics of each batch of actually produced SRAM cells are different after mass production, the R&D personnel can produce a batch of SRAM cells, according to the actual measurement and statistics, in order to get the batch of SRAM cells to be successfully written, the most appropriate The clock of the signal line CL is controlled, and the programmable control circuit is matched with the software to control the clock of the control signal line CL in the system. As shown in FIG. 10, the clock of the control signal line CL and the clock of the word line WL can be independent of each other. Therefore, the SRAM unit 200 disclosed in the first embodiment of the present invention can also control the write characteristics of the SRAM unit and the adjustability after mass production by controlling the first switch 270 and the second switch 280.

Please refer to the SRAM unit 200 of Figure 5, refer to Figure 11. Figure 11 is a flow chart of the method of reading and writing the SRAM cell 200. The steps of the method are as follows, but are not limited to the following sequence: Step 1110: When the data is to be written into the SRAM cell 200 via the first bit line BL and the second bit line BLB, the first signal is turned off by the control signal line CL. The switch 270 and the second switch 280; Step 1120: After the data is written into the SRAM unit 200, the first switch 270 and the second switch 280 are turned on by the control signal line CL.

Since the writing speed is fast when the storage nodes NA and NB are not coupled to the auxiliary capacitors Ca and Cb, the step 1110 can turn the first switch 270 and the second switch 280 to be off when the data writing is to be performed. Since the storage stability is high when the storage nodes NA and NB are coupled to the first capacitor Ca and the second capacitor Cb, the step 1120 can be performed after the data is written into the SRAM unit 200, and then the first switch 270 is turned on. The second switch 280. In addition, the control signal line CL coupled to the first switch 270 and the second switch 280 may be two different signal lines, which are respectively given the same or phase as the first switch 270 and the second switch 280 in accordance with the requirements of the operation. Different conduction period.

Please refer to Figure 5 and refer to Figure 12. Figure 12 is a schematic diagram of an SRAM cell 300 in a third embodiment of the present invention. As shown in FIG. 12, the difference between the SRAM cell 300 and the SRAM cell 200 of FIG. 5 is that the SRAM cell 300 does not include the fourth switch 280 and the second capacitor Cb, that is, the storage node NB of the SRAM cell 300. It is not coupled to the second capacitor Cb through the fourth switch 280. Therefore, compared to the SRAM cell 200 of FIG. 5, the SRAM cell 300 has only a single-sided storage node NA coupled to the first capacitor Ca through the first switch 270. Although the SRAM cell 300 is coupled to the first capacitor Ca through the first switch 370 only on one side, compared to the SRAM cell 200, the memory characteristics such as storage stability and write speed are improved, but the saving is achieved. The layout area of the memory.

Please refer to the SRAM unit 300 of Fig. 12, refer to Fig. 13. Figure 13 is a flow chart of the method of reading and writing the SRAM cell 300. The steps of the method are as follows, but are not limited to the following sequence: Step 1310: When the data is to be written into the SRAM cell 300 via the first bit line BL and the second bit line BLB, the first signal is turned off by the control signal line CL. Switch 270; Step 1320: After the data is written into the SRAM cell 300, the first switch 270 is turned on by the control signal line CL.

As the access speed of SRAM memory increases and the application level develops, SRAM memory is now often used in many electronic devices exposed to the atmosphere, such as telecom equipment or observation equipment installed outdoors. However, in recent years, cosmic ray α-particle penetration system packaging often hits the storage node in the SRAM cell, causing the electronic hole to change, which causes unintended data reversal in the SRAM cell. This is called α-particle acceleration. The problem of α-particle Accelerated Soft Error Rate (α-particle ASER). Such problems are more likely to occur in high-speed operation of SRAM cells, and have been an urgent issue in the field in recent years. The SRAM unit disclosed in the present invention helps to resist the α-particle acceleration soft failure because it is not easy to generate unintended data inversion. rate.

In summary, the SRAM unit disclosed in the embodiment of the present invention can simultaneously consider the high-speed access of the SRAM unit, the stability of the stored data in the SRAM unit, and the adjustability and controllability after mass production. In the prior art, the present invention has improved the subject matter to be solved in the art.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200‧‧‧SRAM unit

NA, NB‧‧‧ storage node

210‧‧‧First P-type MOS semi-transistor

220‧‧‧First N-type gold oxide semi-transistor

230‧‧‧Second P-type gold oxide semi-transistor

240‧‧‧Second N-type oxy-oxygen semiconductor

250‧‧‧third switch

260‧‧‧fourth switch

270‧‧‧ first switch

280‧‧‧second switch

Ca‧‧‧first capacitor

Cb‧‧‧second capacitor

BL‧‧‧first bit line

BLB‧‧‧ second bit line

WL‧‧‧ character line

CL‧‧‧ control signal line

Vcc‧‧‧ operating voltage

Claims (14)

A static random access memory (SRAM) unit includes: a first P-type MOS transistor; a first N-type MOS transistor, the first N-type MOS a gate of the crystal is coupled to the gate of the first P-type MOS transistor; a second P-type MOS transistor, the source of the first P-type MOS transistor is coupled to a source of the second P-type MOS transistor; a second N-type MOS transistor, the gate of the second N-type MOS transistor is coupled to the second P-type MOS a gate of the transistor, a source of the first N-type MOS transistor is coupled to a source of the second N-type MOS transistor; a first switch, a first end of the first switch The first P-type MOS transistor is coupled to the first P-type MOS transistor; and a first capacitor is coupled to the second end of the first switch. The static random access memory unit of claim 1, further comprising: a third switch, the first end of the third switch is coupled to the drain of the first P-type MOS transistor, a drain of the first N-type MOS transistor and a gate of the second P-type MOS transistor; and a fourth switch, the first end of the fourth switch is coupled to the second P-type a drain of the MOS transistor, a drain of the second N-type MOS transistor, and a gate of the first P-type MOS transistor. The static random access memory unit of claim 2, wherein the control end of the third switch is coupled to a word line, and the second end of the third switch is coupled to a bit Yuan line The control terminal of the fourth switch is coupled to the word line, and the second end of the fourth switch is coupled to a bit line bar. The static random access memory cell of claim 3, wherein the third open relationship is a third N-type MOS transistor, and the control terminal of the third switch is the third N-type MOS half. The gate of the transistor, the fourth open relationship is a fourth N-type MOS transistor, and the control terminal of the fourth switch is the gate of the fourth N-type MOS transistor. The static random access memory cell of claim 1, wherein the first open relationship is an N-type MOS transistor or a P-type MOS transistor. The SRAM unit of claim 1, wherein the source of the first P-type MOS transistor is coupled to a voltage source, the source of the first N-type MOS transistor The system is coupled to the ground. The SRAM cell of claim 6, wherein the second end of the first capacitor is coupled to a ground or the voltage source. The static random access memory unit of claim 6, further comprising: a second switch, the first end of the second switch being coupled to the drain of the second P-type MOS transistor; a second capacitor is coupled to the second end of the second switch. The static random access memory cell of claim 8, wherein the second end of the second capacitor is coupled to the ground or the voltage source. The static random access memory unit of claim 8, wherein the second open relationship is an N type Gold oxide semi-transistor or a P-type gold oxide semi-transistor. A method for operating a static random access memory (SRAM) unit, the static random access memory unit comprising a first inverter coupled to the first inverter and a second An inverter, a first capacitor, and a first switch coupled between the first inverter and the first capacitor, the method comprising: performing data writing on the static random access memory unit When the time is up, the first switch is turned off. The method of claim 11, further comprising turning on the first switch after performing data writing to the static random access memory unit. The method of claim 11, wherein the SRAM cell further includes a second capacitor, and a second switch coupled between the second inverter and the second capacitor, the method In addition, when the data writing is to be performed on the static random access memory unit, the second switch is turned off. The method of claim 13, further comprising turning on the second switch after performing data writing to the static random access memory unit.