TW201515097A - Etch process for reducing directed self assembly pattern defectivity using direct current superpositioning - Google Patents

Abstract

A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process.

Description

Etching procedure to reduce the state of the self-assembled pattern using DC overlap

The present invention relates to a method of forming a pattern in a layered article, and a layered article formed thereof; and more particularly, to reducing pattern collapse and other pattern defects in a directed self-assembly application using direct current overlap. Method related.

In the production of semiconductor components, the need to maintain cost and performance competitiveness has resulted in a continuous increase in component density of integrated circuits. In order to achieve higher integration and miniaturization in semiconductor integrated circuits, it is also necessary to achieve miniaturization of circuit patterns formed on semiconductor wafers.

Light lithography is a standard technique used to fabricate semiconductor integrated circuits by transferring the geometry and pattern on the mask to the surface of the semiconductor wafer. However, the most advanced photolithography tools currently allow the minimum feature size to drop to approximately 25 nm. Therefore, new methods are needed to form smaller features.

Self-assembly of block copolymers (BCPs) has been recognized as a potential tool that can increase the resolution to better values than those obtained using conventional lithography techniques alone. Block copolymers are useful compounds in nanofabrication because they can undergo order-disorder transitions when cooled below a certain temperature (order-disorder transition temperature TOD), which can result in different chemistry The phase separation of the copolymer blocks of the nature forms different regions of order and chemistry which are tens of nanometers or even less than 10 nm in size. The size and shape of the regions can be controlled by manipulating the molecular weight and composition of the different block types of the copolymer. The interface between the regions may have a width on the order of 1 nm to 5 nm and can be manipulated by adjustment of the chemical composition of the copolymer block.

The many different phases that a block copolymer can form upon self-assembly, depending on the volume fraction of the block, the degree of polymerization of each block type (ie: each individual type of each individual block) The number of monomers), the selective use of solvents, and surface interactions. When applied to a film, geometric constraints can create additional boundary conditions that may limit the number of phases. In general, spherical (eg, cubic), cylindrical (eg, tetragonal or hexagonal), and lamellar phases (ie, having cubic, hexagonal, or layer) are actually observed in the film of the self-assembling block copolymer. The space fills the symmetrical self-assembled phase, and the phase types observed may depend on the relative volume fraction of the different polymer blocks. Self-assembled polymer phases can be oriented parallel or perpendicular to the axis of symmetry of the substrate, while layered and cylindrical shapes are compelling for lithographic applications because they can form lines and spaces, and arrays of holes, respectively. Good contrast can be formed when a region type is subsequently etched.

Two methods for directing or directing the self-assembly of the block copolymer onto the surface are the patterning epitaxy method and the chemical pre-patterning method (also known as chemical epitaxy). In the pattern epitaxy process, the self-organization of the block copolymer is guided by a topographical pre-patterning of the substrate. The self-aligned block copolymers can form a parallel linear pattern with adjacent lines of different polymer block regions in the trench defined by the patterned substrate. For example, if the block copolymer is a "diblock copolymer with A and B blocks" in the polymer chain, in which A is hydrophilic in nature and B is hydrophobic, then A block can be assembled. It is "a region formed adjacent to the sidewall of the trench" (provided the sidewall is also hydrophilic in nature). The resolution is improved to better than the resolution of the patterned substrate by subdividing the pre-pattern spaced block copolymer pattern on the substrate.

In chemical epitaxy, the self-assembly of the block copolymer regions is guided by chemical patterns on the substrate (ie, chemical templates). The chemical affinity between the chemical pattern and at least one of the copolymer block types in the block copolymer chain can result in the precise placement of one of the region types (also referred to herein as pinning). One of the chemical patterns on the substrate corresponds to a region above it. For example, if the block copolymer is a diblock copolymer having A and B blocks, wherein A is hydrophilic in nature and B is hydrophobic, and the chemical pattern is composed of a hydrophobic region (the region is adjacent to A and The surface composition of the region of B, which is neutral, may be preferentially assembled onto the hydrophobic region, thus facilitating the alignment of the subsequent A and B blocks on the neutral region. As with the alignment method of the pattern epitaxy, the resolution can be improved to be better than that of the patterned substrate by subdividing the block copolymer pattern (also referred to as density or frequency multiplication) of the pre-patterned features on the substrate. degree. However, the chemical epitaxy method is not limited to a linear pre-pattern; for example, the pre-pattern may be a 2-D dot array pattern suitable as a pattern for use with the "block copolymer forming a cylindrical phase". For example, the patterning epitaxy method and the chemical epitaxial method can be used to guide the self-organization of a layered or cylindrical phase in which the types of different regions are arranged side by side on the surface of the substrate.

Therefore, in order to take advantage of the advantages provided by the patterned epitaxial and chemical epitaxial methods of block copolymers, new lithographic patterning and directed self-assembly techniques must be utilized. However, conventional etching techniques are used when the phase-separated PMMA layer removes polystyrene-b-poly(methyl methacrylate) (PMMA) leaving a polystyrene (PS) pattern. Pattern defects, such as line edge roughness/line width roughness (LER / LWR), are unacceptable. In extreme cases, the defects of the PS can be catastrophic due to pattern collapse, which will be discussed in more detail below. Controlled etching techniques and processes are required to produce acceptable results.

The present invention provides a method for preparing a patterned oriented self-assembled layer that uses DC overlap to reduce the degree of defect in the oriented self-assembled pattern. Providing a substrate having a block copolymer layer covering an intermediate layer, the block copolymer layer comprising: a first phase separation polymer defining a layer in the block copolymer layer a first pattern; and a second phase separated polymer defining a second pattern in the layer of the block copolymer. Performing a first plasma etch using a plasma formed from the first process composition to selectively remove the second phase separated polymer leaving the first phase separated polymer on the surface of the substrate The first pattern; and performing a second plasma etching process using a plasma formed of a second process composition containing a halogen-containing gas to at least partially transfer the first pattern to the intermediate layer. In an embodiment, the first phase separated polymer is exposed to an electron beam. The exposure of the first phase separation polymer to the electron beam is performed before, during, or after the first plasma etching process, or before, or during, the second plasma etching process.

Disclosed in various embodiments are materials and methods for forming a layered substrate comprising a self-assembling material. It will be appreciated by those skilled in the art, however, that various embodiments may be practiced without one or more specific details, or other alternatives and/or additional methods, materials, or components. On the other hand, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the various embodiments of the present invention.

Also, the specific quantities, materials, and configurations are set forth in order to explain the invention. Nevertheless, the invention may be practiced without these specific details. In addition, the various embodiments shown in the drawings are intended to be illustrative and not necessarily to scale. In the drawings, like numerals indicate like parts throughout.

The phrase "an embodiment" or "an embodiment" or variations thereof as used throughout this specification means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. In the examples, it is not meant to be present in every embodiment. Thus, the appearances of the various aspects of the present invention, such as "in an embodiment" or "in an embodiment" are not necessarily referring to the same embodiments of the invention. Further, the particular features, structures, materials, or characteristics may be combined in any of the various embodiments in any suitable manner. Various additional layers and/or structures may be included in other embodiments, and/or features may be omitted.

Apart from this, we understand that "one" or "one" may mean "one or more" unless expressly stated otherwise.

Various different operations will be described as sequential multiple individual operations in a manner that is most helpful in understanding the invention. However, the order of the description should not be construed as implying that the operations must be in the order. In particular, such operations need not be performed in the order recited. The operations described may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and/or the operations described may be omitted.

As used herein, the term "radiation-sensitive material" means and includes a light-sensitive material such as a photoresist.

As used herein, the term "polymer block" means and encompasses a plurality of monomer units comprising a single type (ie, a homopolymer block) or a complex type (ie, a copolymer block) as a unit. A continuous polymer chain of length that forms part of a larger polymer of longer length and exhibits a cN value sufficient for phase separation to occur with polymer blocks of other different monomer types. c is the Flory-Huggins interaction parameter and N is the total degree of polymerization of the block copolymer. According to an embodiment of the invention, the cN value of one polymer block and at least one other polymer block in the larger copolymer may be greater than or equal to about 10.5.

As used herein, the term "block copolymer" means and encompasses a polymer composed of a plurality of chains, wherein each chain comprises two or more polymer blocks as defined above, and at least the blocks Both have a separation strength sufficient to separate the blocks (e.g., cN > 10.5). Many different block polymers are contemplated herein, comprising a diblock copolymer (ie, a polymer (AB) comprising a dipolymer block), a triblock copolymer (ie, comprising a tripolymer block) Polymer (ABA or ABC)), multi-block copolymer (ie, a polymer comprising more than three polymer blocks (ABCD, etc.)), and combinations thereof.

As used herein, the term "substrate" means and includes a substrate or structure on which a material is formed. It can be understood that the substrate may comprise: a single material, a plurality of layers of different materials, one or more layers of regions having different materials or different structures, and the like. The materials may comprise: a semiconductor, an insulator, a conductor, or a combination of the above. For example, the substrate can be a semiconductor substrate; a base semiconductor layer on the support structure; a metal electrode or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate can be a conventional germanium substrate or other host substrate comprising a layer of semiconducting material. As used herein, the term "bulk substrate" means not only and includes germanium wafers, but also includes and includes germanium insulator (SOI) substrates (eg, sapphire (SOS) substrates, and germanium glass (SOG). a substrate, a germanium epitaxial layer on the base of the base semiconductor, and other semiconductor or optoelectronic materials (eg, germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). The substrate can be doped or undoped.

As used herein, the terms "microphase separation" and "microphase separation" mean and include the property of a homogeneous block comprising a block copolymer to agglomerate with each other and a heteroblock to separate into different regions. In the host, the block copolymer can self-assemble into an ordered morphology having a spherical, cylindrical, layered, bicontinuous helical tetrahedron, or miktoarm star microdomain, wherein The molecular weight of the block copolymer determines the size of the microdomains formed.

The area size or pitch period (L ₀ ) of the self-assembled block copolymer morphology can be used as a basis for designing the critical dimensions of the patterned structure. Similarly, the structural period (L _s ) can be used to design the basis of the critical dimensions of the patterned structure, the structural period being the characteristic portion left after selectively etching one of the polymer blocks of the block copolymer. size of. For the size of the regions formed by the polymer blocks of these block copolymers, the length of each polymer block constituting the block copolymer can be an inherent limitation. For example, each polymer block can be selected to have a length that promotes self-assembly into a desired pattern of regions, while shorter and/or longer copolymers may not self-assemble as desired.

The term "annealing step" or "annealing" as used herein means and the treatment comprising a block copolymer to promote sufficient microphase separation between two or more different polymerizable block components of the block copolymer to form An ordered pattern defined by repeating the structural units formed by the polymer blocks. Annealing of the block copolymers of the present invention can be accomplished by a variety of different methods of the prior art, including but not limited to: thermal annealing (in vacuum or in an inert atmosphere such as nitrogen or argon), Solvent vapor assisted annealing, supercritical fluid assisted annealing, or absorption-based annealing (eg, optical baking) at room temperature or above room temperature. As a specific example, thermal annealing of the block copolymer can be carried out by exposing the block copolymer to an elevated temperature, which is higher than the glass transition temperature of the block copolymer ( _Tg ), but below the degradation temperature (T _d ) of the block copolymer, which will be discussed in more detail below. Other conventional annealing methods not described herein may also be used.

The self-organization ability of the block copolymer can be used to form a mask pattern. The block copolymer is formed of two or more different blocks. For example, each block can be formed from a different monomer. The blocks are immiscible or thermodynamically incompatible, such as: one block can be polar and the other blocks can be non-polar. Due to thermodynamic effects, the copolymer will self-organize in solution to minimize the overall energy of the system; in general, the situation causes the copolymers to move relative to each other such that, for example, similar blocks are brought together to form a block containing each An alternate region of type or species. For example, if the copolymer is formed from polar blocks (eg, organic metal-containing polymers) and non-polar blocks (eg, hydrocarbon polymers), the blocks are separated such that the non-polar blocks are Non-polar blocks aggregate while polar blocks aggregate with other polar blocks. Since the block can be patterned by moving without actively applying an external force to guide the movement of a particular individual molecule (although heat can be applied to increase the overall rate of movement of the molecular population), it is understood that the block copolymer can be described as Self-assembling materials.

In addition to the interaction between polymer block species, the self-assembly of the block copolymer can also be affected by topographical features (e.g., steps or guides extending perpendicularly from the horizontal surface on which the block copolymer is deposited). For example, a diblock copolymer (which is a copolymer formed from two different polymer block species) can form a plurality of alternating regions (or regions) each having substantially different polymer blocks. Species formation. When the self-assembly of the polymer block species occurs in the region between the vertical walls of the step or the guide, the steps or guides can interact with the polymer block such that, for example, each of the blocks is formed The alternating regions form a regular spacing pattern having features oriented substantially parallel to the walls and the horizontal surface.

Such self-assembly can be useful for forming a mask that patterns features during a semiconductor fabrication process. For example, one of the alternating regions can be removed, thereby leaving material forming other regions to act as a mask. The mask can be used to pattern features such as electronic components in the underlying semiconductor substrate. U.S. Patent No. 7, 579, 278, U.S. Patent No. 7, 723, 009, and U.S. Patent Application Serial No. 13/830,859, entitled "Chemi-Epitaxy in directed self", filed on March 14, 2013, to Sommervell et al. A method of forming a block copolymer mask is disclosed in -assembly applications Using Photo-Decomposable AGENTS", the contents of which are incorporated herein by reference in its entirety.

Figure 1 shows a substrate having a layer of block copolymer patterned using directed self-assembly (DSA) techniques. Referring to Figure 1, a layer of block copolymer 180 is applied and allowed to self-assemble into a mask pattern on the exposed portions of exposed first material layer 120 and radiation sensitive material 160. The block copolymer comprises at least two polymer blocks which are selectively etchable with respect to each other, ie the block copolymer has a number greater than 2 under the first set of etching conditions Etching selectivity. Again, the block copolymer can self-organize in a desired and predictable manner, for example, the polymer block is immiscible under appropriate conditions and will separate to form a region comprising predominantly single block species.

The block copolymer can be deposited by a variety of different methods including, for example, spin coating, spin casting, brush coating, or vapor deposition. For example, the block copolymer can be used as a solution in a carrier solvent such as an organic solvent such as toluene. The block copolymer solution can be applied to the layered substrate, and then the carrier solvent is removed to form a 180 layer of the block copolymer. While the invention is not limited by theory, it will be understood that in a process similar to phase separation of materials, different block species should be understood to self-aggregate due to thermodynamic considerations. The self-organization is guided by the physical interface of the mask feature and the chemical affinity between at least one of the chemical species of the first material layer 120 and the polymer block in the block copolymer chain. Thus, the constituent blocks of the block copolymer can self-orient along the length of the cross-linking portion of the radiation-sensitive material 160 due to interface interaction and chemical affinity.

With continued reference to FIG. 1, the layer block copolymer 180 is exposed to annealing conditions to promote self-assembly of the block copolymer into a plurality of alternating regions 190, 195 that are cross-linked in the radiation-sensitive material 160. The parts are aligned side by side. In this exemplary embodiment shown in FIG. 1, the layer of self-assembling block copolymer 180 has regions 190, 195 that are aligned, wherein the first material layer 120 has chemical affinity for the copolymer block comprising region 195. . Thus, the chemical affinity between one of the polymer blocks of the block copolymer and the first material layer 120 will cause the region 195 to be pinned to the features. Conversely, if the chemical affinity between the cross-linking portion of the radiation-sensitive material 160 and the polymer block of the block copolymer is neutral, the regions 190, 195 may self-organize throughout the neutral surface, such It will be advantageous to form a frequency multiplication. In the embodiment shown in Figure 1, the frequency multiplication of 3X is shown. We should understand that other frequency doublings in the 1X-10X range are available. In the case of a frequency multiplication of 1X, the neutral layer can also be made chemically attractive to the block containing the region 190, thus further increasing the chemical driving force for assembly.

It should be appreciated that the size of the needle zone (i.e.: Example feature size in this embodiment) may be designed with a self-assembled block copolymer morphology associated L _0. If the pinning zone is about L ₀ /2, it will effectively match the size of one of the block copolymer blocks. A needled zone of about 3 L ₀ /2 is also effective for use in one of the pinned block copolymer blocks. Thus, in accordance with an embodiment of the present invention, the method also includes preparing a feature having a size ranging from about 0.30 L ₀ to about 0.9 L ₀ , or from about 1.25 L ₀ to about 1.6 L ₀ .

Self-organization can be accelerated or promoted by annealing the layered structure 105 shown in FIG. A sufficiently low annealing process temperature can be selected to avoid adversely affecting the block copolymer or layered structure. In some embodiments, the annealing can be performed at a temperature of less than about 150 ° C, less than about 300 ° C, less than about 250 ° C, less than about 200 ° C, or about 180 ° C. According to another embodiment, the annealing process can include a solvent anneal that substantially reduces the temperature of the anneal. A conventional solvent annealing method can be used, and the newer technology disclosed in, for example, U.S. Patent Application Serial No. 13/843,122, filed on Mar. -SELF ASSEMBLY APPLICATIONS", attorney reference number: CT-107, the contents of which are incorporated herein by reference in its entirety.

According to one embodiment, in order to promote a faster annealing time without oxidizing or burning the organic polymer block of the block copolymer, an annealing temperature of greater than about 250 ° C can be achieved in an annealing time of less than about 1 hour. Annealing is carried out in a low oxygen atmosphere. When used herein, the low oxygen atmosphere contains less than about 50 ppm oxygen. For example, the low oxygen atmosphere can comprise: less than about 45 ppm oxygen, less than about 40 ppm oxygen, less than about 35 ppm oxygen, less than about 30 ppm oxygen, less than about 25 ppm oxygen, less than about 20 ppm oxygen, or between the above concentrations. Range of oxygen. In addition, the low oxygen atmosphere annealing method can be accompanied by a thermal quenching method. An exemplary hypoxic atmosphere annealing and thermal quenching annealing method is disclosed in U.S. Patent Application Serial No. 61/793,204, the entire disclosure of which is incorporated herein by reference. DIRECTED SELF-ASSEMBLY LITHOGRAPHY CONTROL, attorney reference number: CT-106, the contents of which are incorporated herein by reference in its entirety.

The annealing time can range from about several hours to about one minute. For example, the annealing time above 250 ° C can range from about 1 hour to about 2 minutes, from about 30 minutes to about 2 minutes, or from about 5 minutes to about 2 minutes. According to an embodiment, the annealing temperature may range from about 260 °C to about 350 °C, wherein the low oxygen atmosphere comprises less than about 40 ppm oxygen. For example, the layer block copolymer 180 can be exposed to less than about 40 ppm oxygen in an annealing condition at 310 ° C for about 2 minutes to about 5 minutes.

Thus, the annealing step of the layer block copolymer forms a layer of self-assembling block polymer 180 having a first region 190 formed by one polymer block and sandwiched by another block Between the regions 195 where the polymer is formed. Again, based on the intrinsic etch selectivity provided by the appropriate polymer block selection, it is understood that one of the regions can be selectively removed in a single step by a single etch chemistry, or by different etch chemistries. The article is removed using multiple etches.

For example, in the case where the region 190 is formed of polystyrene (PS) and the region 195 is formed of polymethyl methacrylate (PMMA), the PMMA region 195 can be removed by performing selective oxygen plasma etching. This also partially oxidizes the remaining PS region 190 features. It is understood that the size of the features produced may vary depending on the size of the copolymer used and the process conditions. It is to be further understood that a phase phase other than the lamellar phase shown in Fig. 1 can also be envisaged, and thus the invention is not limited thereto.

As described above, conventional etching techniques can produce unacceptable pattern defects (eg, line edge roughness/line width roughness (LER / LWR)), and in extreme cases, due to pattern collapse, PS defects It is catastrophic. 2A depicts simplified schematic diagrams 200 and 220 of a patterned DSA layer with structural defects produced by prior art etching processes. 2A includes a side view 200 and a top view 220 after a conventional etching process for a PS oriented self-assembly pattern. The side view 200 depicts the substrate 208 with some features 216 showing a substantial line edge roughness, and wherein adjacent features 212 are in contact with each other, and thus the display causes more damage to the sidewalls of the features 212. The top view 220 of the pattern depicts two adjacent features 212 that are in contact at points in the dashed circle 224; the contact of two or more adjacent features is also referred to as bridging.

2B shows a simplified schematic 240 and 260 of a patterned DSA layer with structural pattern collapses produced by prior art methods of the etching process. Side view 240 depicts substrate 246 in which two or more adjacent features 242 are damaged and the features are not individually distinguishable (ie, the pattern collapses). The top view 260 depicts the features mixed together in a manner that would render the pattern unusable for its intended purpose.

3 is a flow diagram 300 illustrating an exemplary method for reducing defects in a block copolymer layer oriented self-assembly pattern in accordance with an embodiment of the present invention. In operation 310, a substrate is provided having a block copolymer layer on a surface thereof, the block copolymer layer comprising: a first phase separation polymer which will be in the block copolymer layer Defining a first pattern; and a second phase separation polymer defining a second pattern in the block copolymer layer. The substrate can be fabricated in accordance with the process described in relation to FIG. The block copolymer may comprise: a diblock copolymer, a triblock copolymer, or a tetrablock copolymer. As described above, in one embodiment, the block copolymer layer comprises polystyrene-b-poly(methyl methacrylate). Other block copolymer layers can also be used.

Still referring to FIG. 3, in operation 310, the first phase separation polymer can be polystyrene (PS), and the second phase separation polymer can be poly(methyl methacrylate) (PMMA). Other polymers can also be used. The glass transition temperature and substrate temperature of the first phase separated polymer are key factors in controlling the etching process results. In one embodiment, the first phase separation polymer comprises polystyrene and the second phase separation polymer comprises poly(methyl methacrylate). The glass transition temperature can be adjusted by controlling more than one operating parameter used to fabricate the copolymer, such that a glass transition temperature within the target glass transition temperature range is generated, wherein more than one of the operating parameters is selected from the group consisting of: The cooling rate or heating rate of the substrate, the degree of crosslinking, the degree of copolymerization, the molecular size of the copolymer, the percentage of plasticizer in the copolymer, the annealing temperature, or the pressure used in the manufacture of the copolymer. Controlling more than one glass transition temperature parameter to produce a substrate having a numerical or numerical range of acceptable glass transition temperatures for copolymer application. In one embodiment, the first phase separation polymer has a glass transition temperature greater than 50 ° C, in the range of from about 50 ° C to about 100 ° C, or from about 80 ° C to about 100 ° C.

In operation 320, an etching process is performed to selectively remove the second phase separated polymer while leaving a first pattern of the first phase separated polymer on the surface of the substrate, the etching process being at about 20 ° C or less. The substrate temperature is advanced. In an embodiment, the substrate temperature may be less than or equal to about 10 °C. In another embodiment, the step of performing the etching process comprises forming a plasma from a process composition comprising an oxygen-containing gas and a noble gas. In yet another embodiment, a plasma is formed from a process composition comprising an oxygen-containing gas and argon. A process composition comprising O ₂ and Ar can be provided at a flow rate ratio of O ₂ to Ar of from about 0.08 to about 0.10.

Still referring to operation 320, the etching process further includes exposing the first phase separated polymer to an electron beam. In another embodiment, the etching process is performed wherein the electron beam exposure is performed during the etching process, or after the etching process, or both. In another embodiment, the etching process includes: forming a plasma between the lower electrode on which the substrate is placed and the upper electrode disposed opposite the lower electrode; and coupling a negative DC voltage to the upper electrode.

The degree of defect is measured in terms of pattern collapse metrics and pattern roughness metrics. Measurements of pattern collapse metrics and pattern roughness metrics may be performed after or during the etch process using optical metrology tools and/or process metrology tools. The pattern collapse metric can be a percentage of the collapse feature in a measurement area. The pattern defect degree may also include a line edge roughness of one or more edges of a feature in the pattern. The line edge roughness of a first edge can be measured using an optical metrology tool such as a reflectometer, ellipsometer, scanning electron microscope (SEM), etc. (eg, line edge roughness-right (LERR) and Line edge roughness-left (LERL). Operation 320 can include a process step wherein the proceeding of the etch process includes control of pattern defectivity, the pattern defect including a measure of the pattern roughness of the first pattern. Such a measurement may be a measure of the roughness of the pattern, which may include: an average of the line width roughness, a line width roughness of the first edge of the first pattern, and a line edge roughness of the second edge of the first pattern . For example, the average value of the line width roughness may be 3.0 nm or less, the left-line width roughness may be 3.5 nm or less, and the right-line width roughness may be 3.5 nm or less.

4 is a flow chart illustrating another method for reducing the defectivity of a directed self-assembled pattern of a block copolymer layer in accordance with an embodiment of the present invention. After operations 310 and 320 in FIG. 3, in operation 430 of FIG. 4, a substrate holder for supporting a substrate is provided, wherein the substrate holder has a first temperature for controlling a first temperature at a central region of the substrate a control element and a second temperature control element for controlling a second temperature at an edge region of the substrate. In operation 440, in an embodiment, the first temperature may be at about 20 ° C, or below 20 ° C, and the second temperature may be set at about 10 ° C, or below 10 ° C. In another embodiment, the first temperature control element controls the first temperature at the central region of the substrate, and the second temperature control element controls the second temperature at the edge region of the substrate; the target value of the first temperature Set at about 10 ° C or below about 10 ° C; set the target value for the second temperature to about 0 ° C or less than about 0 ° C.

FIG. 5 is a simplified schematic diagram of a substrate holder 500 in accordance with an embodiment of the present invention. Referring to FIG. 5, the temperature controlled substrate holder 500 for use in an etching system is configured to be used in operation 430 of FIG. 4 described above. The substrate holder 500 includes a substrate support portion 530 having a first temperature for supporting the substrate 510, and a temperature control support base 520 located below the substrate support portion 530 and set at a second temperature lower than the first temperature. (for example, lower than the desired temperature of the substrate 510); and a thermal insulating portion 540 disposed between the substrate supporting portion 530 and the temperature-controlled support base 520. In addition, the substrate support portion 530 includes a central heating element 533 (located at a substantial central region below the substrate 510) and an edge heating element 531 (located at a substantial edge or surrounding area below the substrate 510), the heating elements The system is coupled to the substrate supporting portion 530 for raising the temperature of the substrate supporting portion 530. In addition, the support base 520 includes one or more cooling elements 521 coupled to the support base 520 for removing heat from the substrate support portion 530 through the thermal insulation portion 540. The temperature of the substrate supporting portion 530 is lowered.

As shown in FIG. 5, central heating element 533 and edge heating element 531 are coupled to heating element control unit 532. Heating element control unit 532 is used to provide dependency or independent control of each heating element and to exchange information with controller 550. Central heating element 533 and edge heating element 531 can include at least one of a heating fluid channel, a resistive heating element, or a thermoelectric element that is biased to transfer heat to the wafer.

For example, central heating element 533 and edge heating element 531 can include: more than one heating channel that can allow fluids such as water, FLUORINERT, GALDEN HT-135, etc. to flow therethrough to provide conductive-convection heating, Wherein the fluid temperature is raised via a heat exchanger. For example, fluid flow rate and fluid temperature can be set, monitored, adjusted, and controlled by heating element control unit 532.

Alternatively, for example, central heating element 533 and edge heating element 531 can comprise: more than one resistive heating element, such as a filament of tungsten, nickel-chromium alloy, aluminum-iron alloy, aluminum nitride, or the like. Examples of commercially available materials for making resistive heating elements include: Kanthal, Nikrothal, Akrothal, which is a registered trade name of a metal alloy produced by Kanthal Corporation of Bethel, CT. The Kanthal family contains: ferrite alloys (FeCrAl), while the Nikrothal family contains: austenitic alloys (NiCr, NiCrFe). For example, the heating element can comprise: a cast-in heater available from Watlow (1310 Kingsland Dr., Batavia, IL, 60510) and having a maximum operating temperature of 400 to 450 ° C; or A film heater for aluminum nitride material, also available from Watlow, can operate at temperatures up to 300 ° C and power densities up to 23.25 W/cm ² . Further, for example, the heating element can comprise an anthrone rubber heater (1.0 mm thick) having a power of 1400 W (or a power density of 5 W/in ² ). When current flows through the filament, the power is dissipated as heat, and thus, the heating element control unit 532 can, for example, include a controllable DC power source. Another heater suitable for lower temperature and power density is selected as a Kapton heater consisting of a filament embedded in a Kapton (eg, polyimine) sheet and by Minneapolis, MN Minco, Inc. ., Sales.

Alternatively, for example, central heating element 533 and edge heating element 531 can comprise an array of thermoelectric elements that can heat or cool the substrate in accordance with the direction of current flow through the various elements. Thus, although the central heating element 533 and the edge heating element 531 are referred to simply as "heating elements," these elements may include a cooling function to provide a rapid transition between temperatures. Again, the heating and cooling functions may be provided by separate components within the substrate support 530. An example of a thermoelectric element is available from Advanced Thermoelectric, Model ST-127-1.4-8.5M (40 mm × 40 mm × 3.4 mm thermoelectric unit, which has a maximum heat transfer power of 72 W). Thus, heating element control unit 532 can, for example, comprise a controllable current source.

More than one cooling element 521 can include at least one of a cooling passage or a thermoelectric element. Further, more than one cooling element 521 is coupled to the cooling element control unit 522. Cooling element control unit 522 is used to provide dependent or independent control of each cooling element 521 and to exchange information with controller 550.

For example, more than one cooling element 521 can include more than one cooling passage that can allow fluids such as water, FLUORINERT, GALDEN HT-135, etc. to flow therethrough to provide conduction-convection cooling, via heat exchange The device lowers the temperature of the fluid. For example, the fluid flow rate and fluid temperature can be set, monitored, adjusted, and controlled by the cooling element control unit 522. Alternatively, for example, during heating, the temperature of the fluid flowing through more than one cooling element 521 may be increased by the central heating element 533 and the edge heating element 531 to assist in the heating step. Still alternatively, the temperature of the fluid flowing through more than one cooling element 521 can be reduced, for example during cooling.

Alternatively, for example, more than one cooling element 521 can include an array of thermoelectric elements that can heat or cool the substrate in accordance with the direction of current flow through the elements. Thus, although elements 521 are referred to as "cooling elements," these elements may include a heating function to provide a rapid transition between temperatures. Again, the heating and cooling functions can be provided by separate components within the temperature controlled support pedestal 520. An example of a thermoelectric element is available from Advanced Thermoelectric Model Model ST-127-1.4-8.5M (40 mm × 40 mm × 3.4 mm thermoelectric unit with a maximum heat transfer power of 72 W). Thus, cooling element control unit 522 can, for example, comprise a controllable current source.

In addition, as shown in FIG. 5 , the substrate holder 500 may further include an electrostatic chuck (ESC) including one or more clamping electrodes 535 embedded in the substrate supporting portion 530 . The ESC further includes a high voltage (HV) DC voltage source 534 coupled to the clamping electrode 535 via an electrical connection. This type of clamping design and implementation is well known to those skilled in the art of electrostatic clamping systems. In addition, the high voltage DC voltage source 534 is coupled to the controller 550 and is used to exchange information with the controller 550.

In addition, the substrate holder 500 may further include: a back side gas supply system 536 that transmits heat to the gas via at least two of the two gas supply lines and the plurality of orifices and channels (not shown) (eg, including: An inert gas of argon, helium or neon, a process gas, or other gas (including oxygen, nitrogen, or hydrogen) is supplied to the back side central region and the edge region of the substrate 510. As shown, the backside gas supply system 536 includes a two-segment (center/edge) system in which the backside pressure can vary radially from the center to the edge. In addition, the backside gas supply system 536 is coupled to the controller 550 and is used to exchange information with the controller 550.

Moreover, as shown in FIG. 5, the substrate holder 500 further includes: a center temperature sensor 562 for measuring a temperature at a substantial central region below the substrate 510; and an edge temperature sensor 564 for measuring the substrate The temperature at the substantial edge region below 510. Center and edge temperature sensors 562, 564 are coupled to temperature monitoring system 560.

The temperature sensor can include: an optical fiber thermometer, an optical pyrometer, a band-edge temperature measurement system as described in U.S. Patent No. 6,891,124, the disclosure of which is incorporated herein by reference. Incorporate the disclosure of this case, or a thermocouple such as a K-type thermocouple (as indicated by the dashed line). Examples of optical thermometers include: optical fiber thermometers available from Advanced Energies, Inc., model OR2000F; optical fiber thermometers available from Luxtron Corporation, model M600; or optical fiber thermometers available from Takaoka Electric Mfg., model number FT-1420.

Temperature monitoring system 560 can provide sensor information to controller 550 to adjust at least one of a heating element, a cooling element, a backside gas supply system, or an ESC high voltage DC voltage source before, during, or after processing .

The controller 550 includes: a microprocessor, a memory, and a digital I/O port (which may include a D/A and/or an A/D converter) that generates a control voltage sufficient for transmission and activation to substrate holding The input of the device 500 and monitors the output from the substrate holder 500. As shown in FIG. 5, the controller 550 can be coupled to and exchanged with the heating element control unit 532, the cooling element control unit 522, the high voltage DC voltage source 534, the back side gas supply system 536, and the temperature monitoring system 560. News. A program stored in the memory for interacting with the components of the substrate holder 500 in accordance with a stored process recipe.

The controller 550 can be implemented by a general purpose computer, a processor, a digital signal processor, etc., which can cause the substrate holder to perform some or all of the processing steps of the present invention in response to executing one of the computer readable media One or more sequences of controllers 550 of the above instructions. A computer readable medium or memory system for accommodating instructions programmed in accordance with the teachings of the present invention, and may include: a data structure, table, record, or other material as described herein. Examples of computer readable media are: CD, hard drive, floppy disk, magnetic tape, magneto-optical disk, PROM (EPROM, EEPROM, flash EPROM), DRAM, SRAM, SDRAM, or any other magnetic media, CD (such as CD -ROM), or any other optical medium, punch card, tape, or other physical medium with a hole pattern, carrier wave, or any other medium from which a computer can read.

The controller 550 can be placed in close proximity relative to the substrate holder 500, or it can be placed remotely relative to the substrate holder 500 via an internet or intranet. Thus, controller 550 can exchange information with substrate holder 500 using at least one of a direct connection, an intranet, or an internet. The controller 550 can be coupled to an intranet of a customer location (ie, device manufacturer, etc.) or can be coupled to an intranet of a vendor location (ie, device manufacturer). In addition, another computer (ie, controller, server, etc.) can exchange data via at least one of the direct connection, the intranet, or the Internet access controller 550.

Optionally, the substrate holder 500 can include an electrode via which the RF power is coupled to the plasma in the processing region above the substrate 510. For example, support base 520 can be electrically biased to a radio frequency voltage by transmitting RF power from the RF generator to substrate holder 500 via an impedance matching network. This RF bias can be used to heat electrons to form and maintain plasma, or to bias substrate 510 to control ion energy incident on substrate 510, or both. In this configuration, the system can operate as a reactive ion etching (RIE) reactor in which the chamber and the upper gas injection electrode system serve as a grounded surface. Typical frequencies for RF bias can range from 1 MHz to 100 MHz, and preferably 13.56 MHz.

Alternatively, RF power can be applied to the substrate holder electrode at multiple frequencies. In addition, an impedance matching network can be used to maximize the RF power delivered to the plasma in the processing chamber by minimizing the reflected power. Various matching network topologies (eg, L-type, pi-type, T-type, etc.) and automatic control methods are available.

U.S. Patent Application Publication No. 2008/0083723, U.S. Patent Application Publication No. 2010/0078424, U.S. Patent Application Publication No. 2008/0083724, U.S. Patent Application Publication No. 2008/0073335, U.S. Patent No. 7,297,894 Additional details of the design of a temperature controlled substrate holder for fast and uniform control of substrate temperature are provided in U.S. Patent No. 7,557,328, and U.S. Patent Application Publication No. 2009/0266809.

In an embodiment, the first, second, and/or third etch process can include a process parameter space comprising: a chamber pressure of up to about 1000 mtorr (eg, up to about 100 mTorr, or up to about 10 to 30 mTorr); process gas flow rate up to about 2000 sccm (standard cubic centimeters per minute) (eg, up to about 1000 sccm, or about 1 sccm to about 100 sccm, or about 1 sccm to about 20 sccm, or about 15 sccm); up to about 2000 sccm Add gas process gas flow rate (eg, up to about 1000 sccm, or about 1 sccm to about 20 sccm, or about 10 sccm); up to about 2000 W (watts) of upper electrode RF bias (eg, up to about 1000 W, Or up to about 500 W); and a lower electrode RF bias of up to about 1000 W (eg, up to about 600 W). Also, the upper electrode bias frequency can range from about 0.1 MHz to about 200 MHz, such as about 60 MHz. Additionally, the lower electrode bias frequency can range from about 0.1 MHz to about 100 MHz, such as about 2 MHz.

In another alternative embodiment, RF power is supplied to the upper electrode instead of the lower electrode. In another alternative embodiment, RF power is supplied to the lower electrode instead of the upper electrode. The duration of the particular etching process can be determined using experimental design (DOE) techniques or prior experience; however, it can also be determined using endpoint detection. One possible endpoint detection method is to monitor a portion of the emitted light spectrum from the plasma region that indicates when a change in the plasma chemical occurs due to a change in a particular material layer or substantially completely removed from the substrate. Caused by contact with the underlying film. After the emission level corresponding to the monitored wavelength crosses a certain threshold (eg, drops to substantially zero, falls below a certain level, or increases above a certain level), it can be considered as reaching the end point. Various wavelengths can be used for the etch chemistry being used, and the layer of material being etched. In addition, the etch time can be extended to include an over etch period that constitutes a fraction of the time between the beginning of the etch process and the end point detection time (ie, 1 to 100%).

More than one etching process can be performed using a plasma etching system. In addition, more than one etch process can be performed using a temperature controlled substrate holder in a plasma etch system (such as that shown in FIG. 5). However, the methods discussed are not limited in scope to this exemplary presentation.

6 is an exemplary simplified architectural diagram 600 of a manufacturing process associated with a manufacturing sequence in an embodiment of the present invention. As discussed above and with reference to Figure 6, the process of providing a substrate having a block copolymer layer can be performed in two different processing sequences, i.e., a first processing sequence 604 of coating the substrate with a block copolymer, and A second processing sequence 608 of annealing the substrate is discussed in relation to operation 310 of FIG. The first processing sequence 604 includes coating a first phase separation polymer (which defines a first pattern in the block copolymer layer), and a second phase separated polymer (which is defined in the block copolymer layer) a second pattern). A second processing sequence 608 includes exposing the block copolymer to annealing conditions to promote self-assembly of the block copolymer into a plurality of alternating regions 190 aligned side by side between spaced apart cross-linking portions of the radiation-sensitive material. 195, as shown in Figure 1. The third processing sequence 612 includes: performing an etching process to selectively remove the second phase separated polymer while leaving a first pattern of the first phase separated polymer on the surface of the substrate, the etching process using, for example, a pattern The substrate holder of 5 is carried out at a selected low temperature range.

Figure 7 is a simplified schematic diagram 700 of a substrate after an etching process in accordance with an embodiment of the present invention. The etching process utilizes techniques to reduce the defectivity of the block copolymer layer. Figure 7 includes a simplified side view 700 of the substrate, and a simplified top view 720 in which techniques for reducing the defectivity of the block copolymer layer are used during the etching process. The inventors have found that the block copolymer layer structure 708 does not undergo pattern collapse, based on tests performed using these techniques to control the temperature of the substrate 704 during the etching process. As described above, pattern collapse is a typical situation that would have a very severe effect on the etched substrate and would substantially render the substrate unusable.

Measurements made during testing using an optical metrology tool such as an ellipsometer, reflectometer, interferometer, scanning electron microscope (SEM), etc. indicate a number of increases in line edge roughness at the left and right upper edges of the feature. However, as the substrate is further cooled to a relatively low temperature, and the temperature range of the substrate is more strictly controlled using the substrate holder shown in FIG. 5 and/or the control system shown in FIG. 8, the line edge roughness is increased. Will be within the acceptable target range of less than 3.5nm. In addition, the present inventors further found that the glass transition temperature (T _g ) is related to the degree of pattern defect. T _g in the range from 50 to 100 deg.] C, and preferably the T _g is in the range of 80 to 100 deg.] C, the case where no pattern collapse, and the line edge roughness of 3.5nm or less less acceptable Within the target range. The glass transition temperature can be adjusted by controlling more than one operating parameter used to make the copolymer, thereby causing the glass transition temperature to be within the target glass transition temperature range, wherein one or more of the operating parameters are selected from the group consisting of: The rate of cooling or heating, the degree of crosslinking, the degree of copolymerization, the molecular size of the copolymer, the percentage of plasticizer in the copolymer, the annealing temperature, or the pressure used in the manufacture of the copolymer.

Figure 8 is a simplified schematic diagram of one of the control systems used in the processing sequence, in the embodiment of the invention, the system is used to reduce the defect level of the block copolymer layer and control one in more than one processing sequence. The above operating parameters. An etching processing system 800 for performing the above determined process conditions is shown in FIG. 8, the system comprising: a plasma processing chamber 810; a substrate holder 820 to which the substrate 825 to be processed is held; and a vacuum pump system 850 . The substrate 825 can be a semiconductor substrate, a wafer, a flat panel display device, or a liquid crystal display device. The plasma processing chamber 810 can be configured to facilitate the generation of plasma in the plasma processing region 845 in an adjacent region of the surface of the substrate 825. The ionizable gas or process gas mixture is introduced via a gas distribution system 840. The process pressure is adjusted using a vacuum pump system 850 for a particular process gas stream. The plasma can be utilized to create a material for a predetermined material process and/or to help remove material from the exposed side of the substrate 825. The plasma processing system 800 can be used to process substrates of any desired size, such as a 200 mm substrate, a 300 mm substrate, or larger.

The substrate 825 can be secured to the substrate holder 820 by a clamping system 828, such as a mechanical clamping system or an electrical clamping system (eg, an electrostatic clamping system). In addition, the substrate holder 820 can include a heating system (not shown) or a cooling system (not shown) for adjusting and/or controlling the temperature of the substrate holder 820 and the substrate 825. The heating system or cooling system can include a reflow of heat transfer fluid that receives heat from the substrate holder 820 and transfers the heat to the heat exchanger system (not shown) upon cooling, or heat exchange by heat upon heating The system is transferred to the substrate holder 820. In other embodiments, heating/cooling elements such as resistive heating elements or thermoelectric heaters/coolers may be included in the substrate holder 820, and the chamber walls of the plasma processing chamber 810, and in plasma processing Among any other components within system 800.

Additionally, heat transfer gas may be delivered to the back side of substrate 825 via backside gas supply system 826 to enhance gas gap heat transfer between substrate 825 and substrate holder 820. Such a system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, the backside gas supply system can include a two-zone gas distribution system in which the helium gas gap pressure can be independently varied between the center and the edge of the substrate 825.

In the embodiment shown in FIG. 8, substrate holder 820 can include an electrode 822 via which RF power is coupled to the processing plasma in plasma processing region 845. For example, the substrate holder 820 can be electrically biased to a RF voltage by transmitting RF power from the RF generator 830 to the substrate holder 820 via an optional impedance matching network 832. The RF bias can be used to heat electrons to form and maintain plasma. In this configuration, the system can operate as a reactive ion etching (RIE) reactor in which the chamber and the upper gas injection electrode system serve as a grounded surface. The typical frequency of the RF bias can range from about 0.1 MHz to about 100 MHz. Plasma systems for plasma processing are well known to those skilled in the art.

Additionally, the electrical bias of the electrode 822 at a radio frequency voltage can be pulsed by the pulsed bias signal controller 831. For example, the RF power output from the RF generator 830 can be pulsed between an off state and an on state. Alternatively, RF power can be applied to the substrate holder electrodes at multiple frequencies. In addition, the impedance matching network 832 can enhance the transfer of radio frequency power to the plasma in the plasma processing chamber 810 by reducing the reflected power. Matching network topologies (e.g., L-type, pi-type, T-type, etc.) and automatic control methods are well known to those skilled in the art.

Gas distribution system 840 can include a showerhead design for introducing a process gas mixture. Alternatively, gas distribution system 840 can include a multi-zone showerhead design for introducing a process gas mixture and adjusting a process gas mixture distribution over substrate 825. For example, the multi-zone showerhead design can adjust the process gas flow or composition flowing to substantially the surrounding area above the substrate 825 relative to the amount of process gas flow or composition flowing to a substantially central region above the substrate 825.

The vacuum pump system 850 can include a turbomolecular vacuum pump (TMP) capable of pump speeds up to about 8,000 liters per second (or greater), and a gate valve to regulate chamber pressure. In a conventional plasma processing apparatus for dry plasma etching, TMP of 1000 to 3000 liters per second can be used. TMP is useful for low pressure processing typically less than about 50 mTorr. For high pressure processing (ie, greater than about 100 mTorr), mechanical boost pumps and dry rough pumps can be used. Additionally, means for monitoring chamber pressure (not shown) may be coupled to the plasma processing chamber 810.

As noted above, the controller 855 can include a microprocessor, a memory, and a digital I/O port capable of generating a control voltage sufficient to transmit and initiate input to the plasma processing system 800, and to monitor from The output of the plasma processing system 800. In addition, the controller 855 can be coupled to the RF generator 830, the pulsed bias signal controller 831, the impedance matching network 832, the gas distribution system 840, the vacuum pump system 850, and the substrate heating/cooling system (not shown), back Side gas supply system 826, and/or electrostatic clamping system 828, and exchanges information with the above. For example, the program stored in the memory can be used to initiate the input of the aforementioned components of the plasma processing system 800 in accordance with a process recipe to perform a plasma assisted process, such as a plasma etch process, on the substrate 825.

Other etch processing systems may include: a fixed, or mechanical or electrical rotating magnetic field system to increase plasma density and/or improve plasma processing uniformity, the system comprising: an upper electrode from an RF generator RF power can be coupled to the upper electrode via an optional impedance matching network; a direct current (DC) power source coupled to the upper electrode opposite the substrate; an inductive coil, RF power routed to the RF generator via an optional impedance matching network An induction coil coupled to the induction coil as a "spiral" coil or a "flat wound" coil, which communicates with the plasma processing region from above in a transformer coupled plasma (TCP) reactor; surface wave plasma (SWP) ) Source and so on. In order to explain the plasma processing and etching system in more detail, please refer to the application No. 13/589,096, filed on Aug. 18, 2012, the disclosure of which is hereby incorporated by reference.

9 is an exemplary flow diagram 900 illustrating an exemplary method of reducing DCA pattern defectivity of a block copolymer layer using DC overlap. In operation 910, a substrate having a block copolymer layer covering a first intermediate layer on a surface of the substrate, the block copolymer layer comprising: a first phase separation polymer, A first pattern is defined in the block copolymer layer; and a second phase separated polymer defining a second pattern in the block copolymer layer. As described above, the block copolymer may include a diblock copolymer, a triblock copolymer, or a tetrablock copolymer. The block copolymer layer may comprise polystyrene-b-poly(methyl methacrylate). Other block copolymer layers can also be used. The first phase separation polymer may be polystyrene (PS) and the second phase separation polymer may be poly(methyl methacrylate) (PMMA). Other polymers can also be used. The glass transition temperature and substrate temperature of the first phase separated polymer are key factors in controlling the results of the etching process. In one embodiment, the first phase separation polymer comprises polystyrene and the second phase separation polymer comprises poly(methyl methacrylate). As also noted above, for this application, one or more of the glass transition temperature parameters of the copolymer can be controlled to produce a substrate having an acceptable range of glass transition temperature values or glass transition temperature values.

In one embodiment, the first phase separation polymer has a glass transition temperature of greater than 50 °C, from about 50 °C to about 100 °C, or from about 80 °C to about 100 °C. The block copolymer layer may include a diblock copolymer, a triblock copolymer, or a tetrablock copolymer or the like. The block copolymer layer may comprise polystyrene-b-poly(methyl methacrylate). The first intermediate layer can include an anti-reflective coating, and the first intermediate layer includes a ruthenium-containing anti-reflective coating. The substrate may further include: a second intermediate layer positioned below the first intermediate layer, wherein the second intermediate layer may include an organic planarization layer. The first phase separation polymer may comprise polystyrene and other polymers.

In operation 920, a first plasma etching process is performed using a plasma formed from the first process composition to selectively remove the second phase separated polymer leaving the first phase on the surface of the substrate The first pattern of the polymer is separated. In operation 930, a second plasma etch process is performed using a plasma formed from a second process composition containing a halogen-containing gas to at least partially transfer the first pattern to the first intermediate layer. In one embodiment, the first plasma etch process is performed at a substrate temperature of about 20 ° C or less. In another embodiment, the halogen-containing gas comprises: SF ₆ . In still another embodiment, the second process composition further comprises: a gas containing CxFyHz, a gas containing CxFy; or the second process composition further comprises C ₄ F ₈ , or SF ₆ , or C ₄ F ₈ and Optional inert gas. In another embodiment, the second plasma etching process comprises: forming a plasma from a process composition comprising an oxygen-containing gas and an inert gas. In still another embodiment, the performing of the second plasma etching process comprises: forming a plasma from a process composition comprising O ₂ and Ar. The process of the second plasma etch process will be described in detail below and in connection with FIG.

10 is another exemplary flow diagram 1000 illustrating further exemplary method operations for reducing DCA pattern defects of a block copolymer layer using DC overlap. The operation of the method of setting the substrate (1010), performing the first plasma etching process (1020), and performing the second plasma etching process (1030) of FIG. 10 is similar to the method of FIG. 9: setting the substrate (910) And performing a first plasma etching process (920) and performing a second plasma etching process (930). In operation 1040, the first phase separated polymer is exposed to an electron beam. In the presence of the plasma generated in the previous first or second plasma etching process sequence, the electron beam may be a ballistic electron beam generated by a DC power supply. The exposing of the electron beam may be performed during the first plasma etching process, or after the first plasma etching process and before the second plasma etching process, or in the second plasma etching process It is carried out during the period. As described above, the second plasma etching process includes: forming a plasma between a lower electrode on which the substrate is placed and an upper electrode disposed opposite to the lower electrode; and coupling a negative DC voltage to the Upper electrode.

The inventors have found that by operating using the above methods and in the process sequence described below, the directional self-assembly defect of the substrate can be controlled and within the tolerances sought. For example, achieving a line width roughness (LWR) of the first pattern less than 2.60 after the first plasma etch process, achieving a line edge roughness (LERL) on the first edge (eg, the left edge) of the first pattern of less than 3.00 And achieving a line edge roughness (LERR) on the second edge of the first pattern (eg, the right edge) of less than 3.10.

11 is an exemplary structural diagram 1100 of a fabrication process that includes a fabrication sequence including DC overlap to reduce pattern defects. The first branch of the processing sequence includes a process of providing a substrate having a block copolymer layer, which can be performed in two different processing sequences, that is, a first processing sequence 1104 of coating the substrate with a block copolymer, And a second processing sequence 1108 of annealing the substrate, as discussed in connection with operation 310 of FIG. The third processing sequence 1112 includes: performing an etching process to selectively remove the second phase separated polymer leaving a first pattern of the first phase separated polymer on the surface of the substrate, the etching process using, for example, FIG. The substrate holder is operated at a selected low temperature range. Processing sequences 1104, 1108, and 1112 are similar to the processing sequence described in relation to FIG.

The second branch of the processing sequence comprises: (1120) arranging a substrate having a block copolymer layer covering an intermediate layer on the surface of the substrate, the block copolymer layer comprising a first phase separation polymer (which is a first pattern is defined in the block copolymer layer) and a second phase separated polymer (which defines a second pattern in the block copolymer layer); (1124) using a plasma formed from the first process composition Performing a first plasma etching process to selectively remove the second phase separation polymer leaving the first pattern of the first phase separation polymer on the surface of the substrate; (1128) used by containing halogen a plasma formed by the second process composition of the gas is subjected to a second plasma etching process to at least partially transfer the first pattern to the intermediate layer; and (1132) exposing the first phase separation polymer to electrons bundle. As described above, the electron beam exposure (1132) may be performed during the first plasma etching process, or after the first plasma etching process and before the second plasma etching process, or The second plasma etching process is performed during the process.

12 is an exemplary simplified schematic diagram of another control system for use in a processing sequence to reduce the defectivity of a block copolymer layer and to control one or more operating parameters of more than one processing sequence using DC overlap. In the embodiment shown in FIG. 12, the plasma processing system 1200 can be similar to the embodiment depicted in FIG. 7, and can further include a DC (DC) power supply 1290 coupled to the substrate 1225 The upper electrode 1270 is opposed. The upper electrode 1270 can include an electrode plate. The electrode plate may comprise a ruthenium containing electrode plate. Further, the electrode plate may contain a doped ytterbium electrode plate. The DC power supply 1290 can include a variable DC power supply. Additionally, the DC power supply 1290 can include a bipolar DC power supply. The DC power supply 1290 can further include a system for monitoring, adjusting, or controlling at least one of the polarity, current, voltage, or on/off state of the DC power supply 1290. Once the plasma is formed, the DC power supply 1290 promotes the formation of a ballistic electron beam. An electronic filter (not shown) may be utilized to decouple the RF power from the DC power supply 1290.

For example, the DC voltage applied by the DC power supply 1290 to the upper electrode 1270 can range from about -2000 volts (V) to about 1000V. The absolute value of the direct current voltage preferably has a value of about 100 V or more, and the absolute value of the direct current voltage is more preferably a value of about 1300 V or more. In addition, we expect the DC voltage to have a negative polarity. Furthermore, it is desirable for the DC voltage to be a negative voltage having an absolute value greater than the self-bias generated on the surface of the upper electrode 1270. The upper electrode surface facing the substrate holder 1220 may be composed of a ruthenium-containing material.

The present invention has been described by way of a description of the embodiments of the invention, and the description of the invention is not limited by the scope of the appended claims. Those skilled in the art will be able to clarify other advantages and modifications without difficulty. Moreover, based on the intrinsic etch selectivity provided by the appropriate polymer block selection, it is understood that one of the regions can be selectively removed in a single step using a single etch chemistry, or by different etch chemistries. Remove using multiple etches. The invention in its broader aspects is therefore not limited to the specific details of Therefore, changes may be made from such details without departing from the general inventive concept.

105‧‧‧Layered structure
120‧‧‧Material layer
160‧‧‧radiation sensitive materials
180‧‧‧ block copolymer (block polymer)
190‧‧‧ area
195‧‧‧Area
200‧‧‧ Schematic
208‧‧‧Substrate
212‧‧‧Characteristic Department
216‧‧‧ Characteristic Department
220‧‧‧ Schematic
224‧‧‧dotted circle
240‧‧‧ Schematic (side view)
242‧‧‧Characteristic Department
246‧‧‧Substrate
260‧‧‧ Schematic (top view)
300‧‧‧ Flowchart
310‧‧‧ operation
320‧‧‧ operations
430‧‧‧ operation
440‧‧‧ operation
500‧‧‧Substrate Holder
510‧‧‧Substrate
520‧‧‧Support base
521‧‧‧Cooling elements (components)
522‧‧‧Control unit
530‧‧‧Substrate support
531‧‧‧Edge heating element
532‧‧‧Heating element control unit
533‧‧‧Center heating element
534‧‧‧DC voltage source
535‧‧‧Clamping electrode
536‧‧‧Backside gas supply system
540‧‧‧ Thermal insulation
550‧‧‧ controller
560‧‧‧ Temperature Monitoring System
562‧‧‧Center temperature sensor
564‧‧‧Edge temperature sensor
600‧‧‧Architectural map
604‧‧‧First processing sequence
608‧‧‧second processing sequence
612‧‧‧ Third processing sequence
700‧‧‧ side view
704‧‧‧Substrate
708‧‧‧ block copolymer layer structure
720‧‧‧ top view
80‧‧‧Processing system
810‧‧‧ Plasma processing chamber
820‧‧‧Sheet holder
822‧‧‧electrode
825‧‧‧Substrate
826‧‧‧Backside gas supply system
828‧‧‧Clamping system
830‧‧‧RF generator
831‧‧‧pulse bias signal controller
832‧‧‧ impedance matching network
840‧‧‧Gas distribution system
845‧‧‧ Plasma processing area
850‧‧‧vacuum pump system
855‧‧‧ Controller
900‧‧‧Flowchart
910‧‧‧ operation
920‧‧‧ operations
930‧‧‧ operation
1000‧‧‧flow chart
1010‧‧‧ operation
1020‧‧‧ operation
1030‧‧‧ operation
1040‧‧‧ operation
1100‧‧‧Structure
1104‧‧‧Processing order
1108‧‧‧Processing order
1112‧‧‧Processing order
1120‧‧‧Processing order
1124‧‧‧Processing order
1128‧‧‧Processing order
1132‧‧‧Processing order
1200‧‧‧ Plasma Processing System
1220‧‧‧Substrate Holder
1225‧‧‧Substrate
1270‧‧‧ upper electrode
1290‧‧‧Power supply

The present invention is described with reference to the accompanying drawings, and the claims

Figure 1 shows a substrate having a block copolymer layer patterned using directed self-assembly (DSA) techniques;

2A and 2B are simplified schematic illustrations of a patterned copolymer layer having structural defects produced by an etching process of the prior art;

3 is a flow chart illustrating an example of a method for reducing the defect of a directed self-assembly pattern of a block copolymer layer in accordance with an embodiment of the present invention;

4 is a flow chart further illustrating a method operation for reducing the degree of defect in a directed self-assembly pattern of a block copolymer layer in accordance with an embodiment of the present invention;

Figure 5 is a simplified schematic diagram of a substrate holder in accordance with an embodiment of the present invention;

6 is an exemplary architectural diagram of a manufacturing process of a manufacturing sequence included in an embodiment of the present invention;

7 is a simplified schematic diagram of a substrate after an etching process, in which the technique utilized in the etching process can reduce the defect degree of the block copolymer layer;

Figure 8 is a simplified schematic diagram of one of the control systems used in the processing sequence, in the embodiment of the invention, the system is used to reduce the defect level of the block copolymer layer and control one in more than one processing sequence. The above operating parameters;

Figure 9 is a flow chart further illustrating the method of operation for reducing the DSA pattern defect degree of the block copolymer layer using DC superposition;

Figure 10 is another flow diagram further illustrating the method of using a DC stack to reduce the DSA pattern defect of the block copolymer layer;

Figure 11 is an exemplary structural diagram of a fabrication process included in a fabrication sequence including DC overlap to reduce pattern defects.

Figure 12 is a simplified schematic diagram of another control system used in a processing sequence for reducing the defectivity of a block copolymer layer and controlling more than one of more than one processing sequence in an embodiment of the invention. Operating parameters.

300‧‧‧ Flowchart

310‧‧‧ operation

320‧‧‧ operations

Claims (20)

A method of preparing a patterned directed self-assembled (DSA) layer, the method comprising: a substrate setting step of disposing a substrate having a block copolymer layer covering a surface of one of the substrates a first intermediate layer, the block copolymer layer comprising a first phase separation polymer and a second phase separation polymer, the first phase separation polymer defining a first pattern in the block copolymer layer, The second phase separation polymer defines a second pattern in the block copolymer layer; a first plasma etching process performing step of performing a first plasma etching using a plasma formed by a first process composition a process for selectively removing the second phase separation polymer leaving the first pattern of the first phase separation polymer on the surface of the substrate; and an exposing step of separately separating the first phase The object is exposed to an electron beam. A method of preparing a patterned directed self-assembly (DSA) layer according to claim 1, wherein the exposing step is performed before, during, or after the first plasma etching process execution step. The method of preparing a patterned directed self-assembly (DSA) layer according to claim 1, wherein the exposing step comprises: forming a plasma between the lower electrode and an upper electrode, wherein the substrate is placed on the lower electrode Upper, the upper electrode is disposed relative to the lower electrode; and a negative DC voltage is coupled to the upper electrode. A method of preparing a patterned directed self-assembly (DSA) layer according to claim 3, wherein the exposing step is performed in a processing system identical to the processing system of the first plasma etching process execution step, or wherein The processing step of the first plasma etching process execution step performs the exposure step in a different processing system. The method for preparing a patterned directed self-assembly (DSA) layer according to claim 1, wherein the first plasma etching process execution step comprises: forming a plasma between the lower electrode and an upper electrode, the substrate system Placed on the lower electrode, the upper electrode is disposed relative to the lower electrode; and a negative DC voltage is coupled to the upper electrode. The method for preparing a patterned directed self-assembly (DSA) layer according to claim 1, further comprising: a second plasma etching process execution step of performing a second electricity using a plasma formed by a second process composition A plasma etching process to at least partially transfer the first pattern to the first intermediate layer. A method of preparing a patterned directed self-assembly (DSA) layer according to claim 6 wherein: the exposing step is performed during the first plasma etching process execution step; or the exposing step is performed in the first electric Executing after the slurry etching process execution step and before the second plasma etching process execution step; or the exposing step is performed during the second plasma etching process execution step. The method for preparing a patterned directed self-assembly (DSA) layer according to claim 6, wherein the second plasma etching process execution step comprises: forming a plasma between the lower electrode and an upper electrode, the substrate system Placed on the lower electrode, the upper electrode is disposed relative to the lower electrode; and a negative DC voltage is coupled to the upper electrode. A method of preparing a patterned directed self-assembly (DSA) layer according to claim 1, wherein the first plasma etching process execution step is performed at a substrate temperature of about 20 ° C or less. The scope of the patent patterned orientation, Paragraph 6 Preparation of self - assembly (DSA) layer, wherein the second process composition comprising: a halogen-containing gas comprising the SF _6. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 10, wherein the second process composition further comprises a gas containing C _X F _Y H _Z , and wherein x and y are greater than 0, and The z system is greater than or equal to zero. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 10, wherein the second process composition further comprises C ₄ F ₈ . A method of preparing a patterned directed self-assembled (DSA) layer according to claim 10, wherein the second process composition consists of SF ₆ , C ₄ F ₈ , and a selective rare gas. A method of preparing a patterned oriented self-assembled (DSA) layer according to claim 1, wherein the block copolymer layer comprises: a diblock copolymer, a triblock copolymer, or a tetrablock copolymer. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 1, wherein the block copolymer layer comprises: polystyrene-b-poly(methyl methacrylate). The method of preparing a patterned directed self-assembled (DSA) layer according to claim 15 , wherein a line width roughness (LWR) of the first pattern after the first plasma etching process is less than 2.60, the first The line edge roughness (LERL) on the first edge of a pattern is less than 3.00, and the line edge roughness (LERR) on the second edge of the first pattern is less than 3.10. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 1, wherein the first intermediate layer comprises: a antimony-containing antireflective coating. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 1, wherein the first phase separation polymer comprises: polystyrene. A method of preparing a patterned directed self-assembled (DSA) layer, the method comprising: a substrate setting step of disposing a substrate having a block copolymer layer covering a surface of one of the substrates An intermediate layer, the block copolymer layer comprising a first phase separation polymer and a second phase separation polymer, the first phase separation polymer defining a first pattern in the block copolymer layer, and the The second phase separation polymer defines a second pattern in the block copolymer layer; the first plasma etching process performs the step of performing a first plasma etching using the plasma formed by the first process composition, Selectively removing the second phase separation polymer leaving the first pattern of the first phase separation polymer on the surface of the substrate; and the second plasma etching process execution step, using a plasma formed by a second process composition of a halogen-containing gas performs a second plasma etching process to at least partially transfer the first pattern to the plasma Floor. A method of preparing a patterned directed self-assembled (DSA) layer according to claim 19, wherein the second process composition is composed of SF ₆ , C ₄ F ₈ , and a selective rare gas.