TW201514720A - A server system - Google Patents

Abstract

A server system comprises a central processing module, a complex programmable logic device (CPLD), a basic input/output system (BIOS) chip, a plurality of system chips and a baseboard management controller(BMC). When BMC receives a renew firmware instruction and when the serve system is in a standby state, the BMC is switched to be a host and the CPLD and the system chips are switched to be a slave of a Serial Peripheral Interface (SPI) bus. Then, the firmware of the system chips is renewed by the BMC and the firmware of the BIOS chip is renewed through the CPLD by the BMC.

Description

Server system

The present invention relates to a server system, and more particularly to a server system that can perform firmware update using a serial data transmission interface bus.

Firmware is a program that needs to be executed when many electronic devices operate, and is generally stored in a specific storage device inside the electronic device. In order to solve the problems caused by the operation of the electronic device, change the hardware settings of the electronic device or provide new functions, the manufacturer will provide a new version of the firmware code for updating.

In the case of firmware update, the general electronic device writes a new version of the firmware code to the specific storage device to replace the old version of the code. Some electronic devices cannot be offlined if they are going to be firmware-updated. They can only use online update (online), and some can be updated in the standby state. After the electronic device is turned on, it can be performed. At the same time, different storage devices may need to use different corresponding tools for firmware update. For the user, the corresponding tools must be re-learned, so that the update party The style is not convenient, and there is room for further improvement.

In view of the inconvenience of the above firmware update, the present invention provides a server system for firmware update of a selected read-only memory through a serial data transmission interface bus by a substrate management controller.

One aspect of the present invention is to provide a server system. The server system has at least one central processing unit module, complex programmable logic elements, a basic input/output system chip, a plurality of system chips, and a substrate management controller. The complex programmable logic component is coupled to the central processing unit module. A basic input/output system chip is coupled to the complex programmable logic element. The substrate management controller couples the complex programmable logic components and the system chips through a serial data transmission interface bus. When the baseboard management controller receives a firmware update command, when the server is in a power-on state, an indication signal is sent to the complex programmable logic component, and the complex programmable logic component subsequently sends a first switching signal. Switching the baseboard management controller to the master device of the serial data transmission interface bus, switching the complex programmable logic component and the system chips to the slave device of the serial data transmission interface bus, and then The baseboard management controller performs a firmware update operation on the system chips, and performs a firmware update operation on the basic input/output system through the complex programmable logic component. When the booting operation is performed, the complex programmable logic component switches the basic The input/output system chip is coupled to the at least one central processing unit module for starting the system.

In an embodiment, when the baseboard management controller receives the When the firmware update command is first, the working state of the server system is first determined. If the server system is in the working state, the baseboard management controller sends a shutdown command to shut down the server system and enter the state to be turned on. The indication signal is sent to the complex programmable logic element.

In an embodiment, after the substrate management controller completes the firmware update operation, a boot command is sent to the server system to enable the server system to boot.

In one embodiment, the substrate management controller has a first switching signal 埠, and the first switching signal 电 is electrically connected to the complex programmable logic element and the system chips for transmitting the first switching signal.

In an embodiment, the system wafer includes: a memory aggregator; and at least one network card.

In an embodiment, the server system further includes at least one first read-only memory coupled to the storage aggregator, and at least one second read-only memory coupled to the at least one network card, a third read-only memory The body is coupled to the baseboard management controller. a switch between the at least one network card and the at least one second read-only memory, the baseboard management controller controlling the switch to switch the at least one second read-only memory and the at least one network card Coupling or switching the at least one second read-only memory to be coupled to the serial data transmission interface bus.

In an embodiment, the substrate management controller further includes a second switching signal 埠, and transmits a second switching signal to the third read-only memory, and updates the firmware of the substrate management controller itself to the third Read only memory.

In summary, the present invention couples the read-only memory and the substrate management controller to the serial data transmission interface bus, and selects the read-only memory to be updated by the substrate management controller. At this time, the substrate management controller can perform the firmware update operation on the selected read-only memory via the serial data transmission interface bus, and does not need to be updated by the specific update device, which is quite convenient in use.

100‧‧‧Server system

101‧‧‧Complex programmable logic components

102‧‧‧Central Processing Unit Module

103‧‧‧Storage Collector

104‧‧‧Network card

105‧‧‧Switcher

106‧‧‧Baseboard Management Controller

107‧‧‧Listed data transmission interface bus

1011‧‧‧Basic Input/Output System Wafer

1031‧‧‧First read-only memory

1041‧‧‧Second read-only memory

1064‧‧‧ Third read-only memory

1061‧‧‧First switching signal埠

1062‧‧‧Second switching signal埠

1063‧‧‧Listed data transmission interface埠

FIG. 1 is a diagram showing a server system for firmware update using a serial data transmission interface bus according to an embodiment of the invention.

The following description of the preferred embodiments of the invention is in the

1 is a diagram showing a server system for firmware update using a serial data transmission interface bus according to an embodiment of the invention. The server system 100 includes at least one central processing unit 102, a Complex Programmable Logic Device (CPLD) 101, and a basic input/output system (BIOS) 1011. The system chip and a Baseboard Management Controller (BMC) 106. In an embodiment The system chips further include a storage aggregator 103 and at least one network interface card 104. However, in other embodiments, the system chip is not limited to the above. The complex programmable logic component 101 is coupled to the central processing module 102. The basic input/output system chip 101 is coupled to the complex programmable logic element 101. The Serial Peripheral Interface (SPI) 1063 of the Baseboard Management Controller 106 is coupled to the Complex Programmable Logic Element 101, the Storage Aggregator 103, and the Network Card 104 via a serial data transmission interface bus 107. connection. The central processing unit 102 manages the corresponding network card 104 and the storage aggregator 103 through the complex programmable logic element 101 to connect the network and access the storage device.

The CPU module 102 accesses the BIOS firmware stored in the basic input/output system chip 1011 through the complex programmable logic component 101 for booting and shutting down. The storage concentrator 103 has a first read-only memory 1031 for storing firmware required for accessing the storage device. When the central processing unit 102 is to access the storage device through the storage concentrator 103, the storage concentrator 103 is stored. The reading of the first read-only memory 1031 is performed to complete the access operation of the data. The network card 104 has a second read-only memory 1041 for storing the firmware required for the connection network. When the central processing unit 102 wants to connect to the network through the corresponding network card 104, the network The road card 104 accesses the second read-only memory 1041 to take out the desired firmware for connection. The substrate management controller 106 has a third read-only memory 1064. On the other hand, the server system 100 further has a switch 105 disposed between the network card 104 and the second read-only memory 1041. Among them, the substrate tube The controller 106 can control the switch 105 to switch to couple the second read-only memory 1041 with the network card 104, or to couple the second read-only memory 1041 with the serial data transmission interface bus 107. For firmware update. It should be noted that only a single CPU module 102 and a network card 104 and a storage aggregator 103 are depicted in the drawings, but the number is not limited. For example, there may be four central processing units 102 associated with four network cards 104, which in this case will have four second read-only memory 1041. Furthermore, the number of the first read-only memory 1031 of the storage aggregator 103 is not limited to one, and may also have a plurality of first read-only memories 1031.

When the substrate management controller 106 receives a firmware update command, the baseboard management controller 106 first determines the operating state of the server system 100. The firmware update command is an instruction to update the basic input/output system chip 1011, the first read-only memory 1031, the second read-only memory 1041, and the third read-only memory 1064. If the server system 100 is in the working state, the baseboard management controller 106 first sends a shutdown command to cause the server system 100 to shut down and enter the state to be turned on, and then send an indication signal to the complex programmable logic component 101. Perform subsequent firmware update operations. That is to say, the firmware update operation is performed only when the server system 100 is in the standby state. When the server 100 is in the standby state, the baseboard management controller 106, the complex programmable logic component 101 and the at least one network card 104 are in an active state, and the storage aggregator 103 is in an inoperative state.

When the complex programmable logic component 101 receives the indication signal sent by the baseboard management controller 106, the complex programmable logic component 101 will send A first switching signal CS1 is generated, thereby switching the substrate management controller 106 to the master device of the serial data transmission interface bus 107, and switching the complex programmable logic component 101, the storage aggregator 103 and the network card 104 into a string. The slave device management interface 106 performs a firmware update operation on the storage aggregator 103 and the network card 104, that is, the first read-only memory 1031 and the second read-only memory. The firmware stored in the memory 1041 is updated. In addition, the substrate management controller 106 also performs an update operation on the firmware in the basic input/output system chip 1011 through the complex programmable logic element 101. When the baseboard management controller 106 completes the firmware update operation, it sends a power-on command to the server system 100 to enable the server 100 to boot. When the server 100 is powered on, the complex programmable logic component 101 switches the basic input/output system chip 101 and the central processing module 102 to be coupled for booting of the server system 100.

In addition, the substrate management controller 106 further has a first switching signal 埠 1061 and a second switching signal 埠 1062. The first switching signal 埠1061 is electrically connected to the complex programmable logic component 101, the storage concentrator 103 and the network card 104, for transmitting the first switching signal CS1, and switching the substrate management controller 106 to the serial data transmission interface. The master device of the bus bar 107 switches the complex programmable logic component 101, the storage aggregator 103, and the network card 104 to slave devices of the serial data transmission interface bus. The second switching signal 埠 1062 is configured to transmit a second switching signal CS2 to the third read-only memory 1064 of the substrate management controller 106, and update the firmware of the substrate management controller 106 itself to the third read-only memory 1064. .

Accordingly, the present invention transmits the serial data through the substrate management controller. The material transfer interface bus performs a firmware update operation on the selected read-only memory. Since it is not necessary to use an additional specific update device, it is quite convenient to use.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Server system

101‧‧‧Complex programmable logic components

102‧‧‧Central Processing Unit Module

103‧‧‧Storage Collector

104‧‧‧Network card

105‧‧‧Switcher

106‧‧‧Baseboard Management Controller

107‧‧‧Listed data transmission interface bus

1011‧‧‧Basic Input/Output System Wafer

1031‧‧‧First read-only memory

1041‧‧‧Second read-only memory

1064‧‧‧ Third read-only memory

1061‧‧‧First switching signal埠

1062‧‧‧Second switching signal埠

1063‧‧‧Listed data transmission interface埠

Claims (10)

A server system comprising: at least one central processing unit module; a complex programmable logic element coupled to the central processing unit module; a basic input/output system chip coupled to the complex programmable logic element; And a substrate management controller coupled to the complex programmable logic component and the system chip through a serial data transmission interface bus; wherein, when the substrate management controller receives a firmware update command Sending an indication signal to the complex programmable logic component when the server is in a power-on state, the complex programmable logic component subsequently issuing a first switching signal, and switching the baseboard management controller to the serial data transmission a master device of the interface bus, switching the complex programmable logic component and the system chips to the slave devices of the serial data transmission interface bus, and then performing firmware update operations on the system chips by the baseboard management controller And performing a firmware update operation on the basic input/output system through the complex programmable logic element. When as the complexity of the switching element Programmable Logic basic input output system coupled to the wafer at least one central processor module for system startup. The server system of claim 1, wherein when the substrate management controller receives the firmware update command, first determining an operating state of the server system, if the server system is in an active state, The baseboard management controller sends a shutdown command to make the server system After the system is shut down and enters the state to be turned on, the indication signal is sent to the complex programmable logic element. The server system of claim 1, wherein the substrate management controller sends a power-on command to the server system after the firmware update operation is completed, so that the server system is powered on. The server system of claim 1, wherein the substrate management controller has a first switching signal 埠, the first switching signal 电 is electrically connected to the complex programmable logic element and the system chips, For transmitting the first switching signal. The server system of claim 4, wherein the system chips comprise: a storage aggregator; and at least one network card. The server system of claim 5, wherein the baseboard management controller, the complex programmable logic component, and the at least one network card are in an active state when the server is in a power-on state, the one The storage aggregator is not working. The server system of claim 5, further comprising at least one first read-only memory coupled to the storage aggregator, the at least one second read-only memory coupled to the at least one network card, The three read-only memory is coupled to the baseboard management controller. The server system of claim 7, further comprising a switch disposed between the at least one network card and the at least one second read-only memory, the baseboard management controller controlling the switchover The at least one second read-only memory is coupled to the at least one network card, or the at least one second read-only memory is coupled to the serial data transmission interface bus. The server system of claim 8, wherein the substrate management controller further includes a second switching signal 埠, and transmits a second switching signal to the third read-only memory, and the substrate management The controller's own firmware is updated to the third read-only memory. The server system of claim 7, wherein the firmware update command includes the basic input/output system chip, the at least one first read only memory, and the at least one second read only memory. And an update instruction of the third read-only memory.