TW201513298A - Semiconductor device - Google Patents

Abstract

To optimize a balance between signal line remedy and transmission speed in a layered semiconductor device. An interface chip (IF) comprises a plurality of driver circuits (30). Each core chip (CC) comprises a plurality of receiver circuits (40). The interface chip (IF) and the plurality of core chips (CC) are connected by through-silicon vias (TSV). A first driver circuit (30) is connected to a second receiver circuit (40) by way of a first TSV. A second driver circuit (30) is connected to a second receiver circuit (40) by way of a second TSV. A signal (F1) among various signals is inputted into both the first and second driver circuits (30), and is outputted from both the first and second receiver circuits (40).

Description

Semiconductor device

The present invention relates to a stacked semiconductor device including a plurality of semiconductor wafers electrically connected by through electrodes.

The memory capacity required for a semiconductor device such as a DRAM (Dynamic Random Access Memory) is increasing. In order to satisfy this requirement, in recent years, a method of electrically connecting a plurality of memory wafers via a through electrode provided on a ruthenium substrate has been proposed (refer to Patent Documents 1 and 2).

In particular, in a semiconductor device in which an interface wafer at an end portion such as an interface circuit or an integrated body having a memory core or the like is laminated, a memory device is formed from a memory core. The read data read in parallel is directly supplied to the interface wafer without serial conversion, and therefore requires a large number of through electrodes (generally about 1,000). However, as long as there is one defect in the through electrode, the entire wafer becomes defective, and after lamination, all the wafers become non- good. Therefore, in such a semiconductor device, in order to prevent a failure due to a failure of the through electrode, a preliminary through electrode may be provided.

In the semiconductor device described in Patent Document 1, a predetermined through electrode is allocated to a group of a plurality of through electrodes (for example, eight through electrodes). On the other hand, when a defect occurs in one of the through electrodes, a preliminary through electrode is used instead of the through electrode, and the defect is remedied (hereinafter referred to as "replacement method"). Further, Patent Document 2 discloses a defective remedy for doubling the through electrode itself (hereinafter referred to as "partial parallel method").

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open No. 2011-081887

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2007-158237

The interface chip and the core chip are subjected to various types of signals. One of the signals is necessary for higher speed transmission than other signals. Compared with the control method which is complicated, the transmission speed of the signal in the case of partial parallel mode is faster. However, in a partially parallel approach, the system is accompanied by multiple paths. The unique transmission delay.

The semiconductor device of the present invention includes: a first semiconductor wafer including a plurality of driving circuits; and a second semiconductor wafer including a plurality of receiving circuits; and a plurality of through electrodes, the first semiconductor wafer and the second semiconductor wafer The semiconductor wafer is connected. The first drive circuit is connected to the first receiving circuit via the first through electrode. The second drive circuit is connected to the second receiving circuit via the second through electrode. The first signal transmitted from the first semiconductor wafer to the second semiconductor wafer is input to both the first and second drive circuits, and is output from both the first and second receiving circuits.

A semiconductor device according to another aspect of the present invention includes: a first semiconductor wafer including a plurality of driving circuits; and a second semiconductor wafer including a plurality of receiving circuits; and a plurality of through electrodes for the first semiconductor wafer It is connected to the second semiconductor wafer. The first drive circuit is connected to the first receiving circuit via the first through electrode. The third drive circuit is connected to the third receiving circuit via the third and fourth through electrodes. The first signal transmitted from the first semiconductor wafer to the second semiconductor wafer is input to the first drive circuit, and is output from the first receiving circuit only via the first through electrode. The second signal transmitted from the first semiconductor wafer to the second semiconductor wafer is input to the third driving circuit, and is output from the third receiving circuit via both the third and fourth through electrodes.

According to the present invention, in a stacked semiconductor device capable of using a plurality of through electrodes, it is easy to achieve an optimum balance between the remedy of the defective signal line and the transmission speed of the signal.

10‧‧‧Semiconductor device

20‧‧‧Terminal joints

30‧‧‧Drive circuit

40‧‧‧ receiving circuit

50, 52‧‧‧ output control circuit

60, 62‧‧‧ input control circuit

70‧‧‧Selection circuit

72‧‧‧Selection circuit

90‧‧‧ layer decision circuit

91‧‧‧Electrode

92‧‧‧through hole electrode

93‧‧‧Rewiring layer

94‧‧‧NCF

95‧‧‧ lead frame

96‧‧‧Bottom filler

97‧‧‧ Sealing resin

98‧‧‧NOR gate

CC‧‧‧ core chip

IF‧‧ interface chip

IP‧‧‧Intermediary

SB‧‧‧External terminals

TSV‧‧‧through electrode

SW‧‧ switch

R‧‧‧ Path

FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device.

Fig. 2 is a cross-sectional view showing the connection relationship of the semiconductor device in the first embodiment.

[Fig. 3] is a schematic diagram of a partially parallel mode.

[Fig. 4] is a circuit diagram in a partially parallel manner.

[Fig. 5] is a schematic diagram of the replacement method.

[Fig. 6] is a circuit diagram in the replacement mode.

[Fig. 7] is a schematic diagram of a completely parallel mode.

[Fig. 8] is a circuit diagram in a completely parallel manner.

Fig. 9 is a cross-sectional view showing the connection relationship of the semiconductor device in the second embodiment.

[Fig. 10] is a schematic diagram of a non-remediation mode.

[Fig. 11] is a circuit diagram in a non-remediation mode.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a schematic cross-sectional view for explaining the configuration of the semiconductor device 10.

As shown in FIG. 1, the semiconductor device 10 of the present embodiment is generally provided with eight core wafers CC0 to CC7 having the same structure and one interface wafer IF and one interposer IP. The structure of the stratification is made. The core wafers CC0 to CC7 and the interface wafer IF are semiconductor wafers using a germanium substrate, and are all connected to the wafers adjacent to each other by a plurality of through electrodes TSV (Through Silicon Via) passing through the germanium substrate. Electrical connection. On the other hand, the interposer IP is a circuit board made of a resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb.

The core wafers CC0 to CC7 are semiconductor wafers in which a so-called front end portion for interconnecting an external interface in a circuit block included in an SDRAM (Synchronous Dynamic Random Access Memory) is removed. In other words, it is a semiconductor wafer in which only the circuit blocks belonging to the rear end portion are integrated. As the circuit block included in the front end portion, a parallel sequence conversion circuit (data latch circuit) for performing parallel/sequence conversion of input and output data between the memory cell array and the data input/output terminal or It is a DLL (Delay Locked Loop) circuit that controls the input/output timing of data. In the core chips CC0 to CC7, since the circuit does not include such a circuit belonging to the front end portion, there is no other than the test operation. The method causes the core wafers CC0 to CC7 to operate as a single unit. In order to operate the core wafers CC0 to CC7, an interface wafer IF is required.

In the core chips CC0 to CC7, in addition to the memory cells, a circuit for temporarily holding data of the memory cells and a part of its control circuit (sense amplifier or address decoder, operation test) are mounted. Use the circuit, etc.). The interface chip IF transmits external signals to the core chips CC0 to CC7, and outputs signals from the core chips CC0 to CC7 to the outside.

The interface wafer IF functions as a common front end with respect to the eight core chips CC0 to CC7. Therefore, all accesses from the outside are performed via the interface wafer IF, and data input and output are also performed via the interface wafer IF. In the present embodiment, the interface wafer IF is disposed between the interposer IP and the core wafers CC0 to CC7. However, the position of the interposer wafer IF is not particularly limited, and may be disposed on the core wafer CC0. ~CC7 and higher, can also be placed on the back IPb of the intermediary IP. When the interface wafer IF is disposed above the core wafers CC0 to CC7 or at the back IPb of the interposer IP, it is not necessary to provide the TSV at the interface wafer IF.

The interposer IP functions as a rewiring substrate for securing the mechanical strength of the semiconductor device 10 and for expanding the electrode pitch. That is, the electrode 91 to be formed on the upper surface IPa of the interposer IP is pulled out to the back surface IPb by the via electrode 92, and is provided by the rewiring layer 93 provided at the back surface IPb. The pitch of the external terminal SB is enlarged. In FIG. 1, only two external terminals SB are shown, but The system is provided with a large number of external terminals. The semiconductor device 10 can be treated as one SDRAM from an external controller.

As shown in FIG. 1, generally, the uppermost core wafer CC0 is covered by a (Non-Conductive Film) 94 and a lead frame 95, and the core wafers CC0 to CC7 and the side of the interface wafer IF are borrowed. It is covered by the underfill material 96 and the sealing resin 97. Thereby, each wafer is protected by crop rationality.

[First Embodiment]

Fig. 2 is a cross-sectional view showing the connection relationship of the semiconductor device 10 in the first embodiment. In the first embodiment, in addition to the replacement method and the partial parallel method, the interface wafer IF is connected to each core wafer CC in a new "completely parallel manner".

The through electrodes TSV are formed on the interface wafer IF and the core wafer CC, and are connected to each other via the terminal bonding portion 20. The number of TSVs included in the interface wafer IF and the core wafer CC may also be in the order of thousands. If there is a defect in the TSV or a connection failure in the terminal bonding portion 20, the signal cannot be transmitted (hereinafter, the signal line in which such a defect occurs is referred to as a "bad signal line"). In general, since a plurality of defective signal lines are generated in one semiconductor device 10, and one or two defective signal lines are generated, the semiconductor device 10 is discarded as a defective product as long as one defective signal line is included. The practice is not realistic.

In Figure 2, signal S1 is partially parallelized. Transmission, signals D1~D4 are transmitted by replacement. Also, the signal F1 is transmitted in a completely parallel manner. Hereinafter, each transmission method will be described in order.

Figure 3 is a schematic diagram of a partially parallel mode. The signal S1 (second signal) is first input to the drive circuit 30 (third drive circuit). The signal S1 is further input to the receiving circuit 40 (third receiving circuit) via each of the TSV 1 (third through electrode) and the TSV 2 (fourth through electrode). Thereafter, the signal S1 is output from the receiving circuit 40. Even if one of TSV1 and 2 becomes unreachable, the signal will be transmitted from the other party. Both TSV1 and 2 have a low probability of being unreasonable.

Figure 4 is a circuit diagram in a partially parallel manner. The signal S1 is input to the drive circuit 30-1, and after passing through the two TSVs, is wired and input to the receiving circuit 40-1. The driving circuit 30-1 includes a 3-state inverter and controls the input of the signal S1 by a control signal (high start) from the output control circuit 50. When the control signal is at the Low level, the output of the 3-state inverter is in a high impedance state, and the signal S1 is not supplied to the through electrode TSV.

The receiving circuit 40-1 includes a 3-state inverter and is controlled by the receiving circuit 40. When the control signal of the input control circuit 60 is at the Low level, the S1 signal that has passed through the through electrode TSV passes through the receiving circuit 40-1. The other signals S2~S4 are also the same.

Figure 5 is a schematic diagram of the replacement mode. Signal D1, It is input to one of the drive circuit 30-1 or the drive circuit 30-2 (fourth drive circuit) by the control of the switch circuit 1 of the selection circuit 70. The drive circuit 30-1 is connected to the receiving circuit 40-1 via the through electrode TSV1, and is connected to the receiving circuit 40-1 by the control of the switch SW2 of the selection circuit 72. The drive circuit 30-2 is connected to the reception circuit 40-2 or the reception circuit 40-3 (fourth reception circuit) via the through electrode TSV2 (the fifth through electrode). The connection target of the through electrode TSV2 is selected by the control of the switch SW2 of the selection circuit 72.

Similarly, the signal D2 is input to the drive circuit 30-2 or the drive circuit 30-3 (the fifth drive circuit). The drive circuit 30-3 is connected to one of the receiving circuit 40-4 (the fifth receiving circuit) or the receiving circuit 40-5 via the through electrode TSV3 (the sixth through electrode).

Since the selection circuit 70 of the interface wafer IF and the selection circuit 72 of the core wafer CC need to cooperate with each other, setting information for avoiding the defective through electrode TSV is also sent from the interface wafer IF to the core wafer CC (details) Please refer to Patent Document 1).

When the through electrodes TSV1 and TSV2 are normal, the signal D1 is transmitted via the drive circuit 30-1, the through electrode TSV1, and the receiving circuit 40-1. The signal D2 is via the drive circuit 30-2, the through electrode TSV2, and the receiving circuit 40. -3 is transmitted. When the through electrode TSV1 is defective, the signal D1 is transmitted via the driving circuit 30-2, the through electrode TSV2, and the receiving circuit 40-2, and the signal D2 is via the driving circuit 30-3. It is transmitted through the through electrode TSV3 and the receiving circuit 40-4.

In FIG. 2, signals D1 to D4 are transmitted via paths R1 to R5, but it is assumed that a defect occurs in path R2. In this case, the signal D1 is transmitted from the path R1, and the signals D2 to D4 are transmitted via the paths R3 to R5. The path R4 is a path prepared when a failure occurs.

Figure 6 is a circuit diagram in a replacement mode. The output control circuit 52 of FIG. 6 includes the function of the selection circuit 70 of FIG. 5, and the input control circuit 62 includes the function of the selection circuit 72. The signal D1 is supplied to both the drive circuit 30-1 and the drive circuit 30-2, but the input target is selected by the output control circuit 52.

It is assumed that the through electrode TSV2 is defective. At this time, the output control circuit 52 sets the input target of the signal D1 as the drive circuit 30-1, sets the input target of the signal D2 as the drive circuit 30-3, and sets the input target of the signal D3 as the drive circuit 30-4. . The input control circuit 62 connects the through electrode TSV1 and the receiving circuit 40-1, connects the through electrode TSV3 and the receiving circuit 40-4, and connects the through electrode TSV4 and the receiving circuit 40-6. The receiving circuit 40 in this embodiment is a so-called 3-state buffer. In this way, the output control circuit 52 and the input control circuit 62 not only control whether the signal passes, but also select the input target or output target of the signal.

In the replacement method, the number of through electrodes TSV required is relatively small compared to the partial parallel mode. In the case of generalization, for n signals D1 to Dn, it is only necessary to prepare n+1 or more through electrodes. TSV can be. Usually, as n, it is intended to be 16 degrees. However, in the replacement method, since the drive circuit 30 and the reception circuit 40 are complicated, the circuit area is increased. And, the control is also complicated. Therefore, the wiring load is large, and the delay amount of signal transmission is large.

On the other hand, in the partial parallel mode, although the number of the through electrodes TSV is increased, since the control system is simple, the circuit area can be suppressed, and the signal transmission is also relatively high speed. Therefore, in general, a small number of signals, such as control signals, which are required for high-speed transmission, are transmitted by path parallelism, and most of the information signals are transmitted by replacement.

In particular, those who need high-speed transmission are the chip selection signals. The chip selection signal is used by the interface chip IF to specify a signal for the core chip CC of the access target. Each core chip CC has an inherent chip address. The interface chip IF is a transmission chip selection signal, and the chip address specified by the chip selection signal is a core chip CC which is consistent with its own wafer address, and is a signal transmitted by the subsequent signals transmitted by the message. . When the core chip CC is four, the chip address is two bits, and if it is eight, it is three bits. The chip select signal is input from the outside simultaneously with the action command. Generally, it is specified by the upper address or the memory address area.

After the motion command is input, the memory cell selection or writing and reading operations are performed. When a plurality of core chips CC are stacked as in the semiconductor device 10 in general, if the core wafer CC of the access target is not determined first, the operation command cannot be sent. Based on this theory Since the wafer selection signal system is particularly required to have a high transmission speed, it is more desirable in a partially parallel manner than the replacement method. However, even in a partially parallel manner, the unique delay caused by the presence of the prepared through electrodes cannot be avoided.

In the case of the partial parallel mode, since the drive circuit 30 needs to send signals to the two through electrodes TSV1 and 2, in order to maintain the signal transmission speed, it is necessary to at least the size of the transistor included in the drive circuit 30. Set to 2 times. The through electrodes TSV each have a capacity of 60 to 100 fF. Further, in consideration of the connection capacity required for connecting the two through electrodes TSV and the diffusion capacity of the transistor, the size of the transistor of the drive circuit 30 is actually required to be twice or more. However, there is still a limit in increasing the signal transmission speed by increasing the size of the drive circuit 30. Therefore, in the first embodiment, signals which are required to be transmitted at a high speed as in the case of the wafer selection signal are transmitted in a completely parallel manner as follows.

Figure 7 is a schematic diagram of a completely parallel mode. The signal F1 (first signal) is input to both the drive circuit 30-1 (first drive circuit) and the drive circuit 30-2 (second drive circuit). The drive circuit 30-1 is connected to the reception circuit 40-1 (first reception circuit) via the through electrode TSV1 (first through electrode), and the drive circuit 30-2 passes through the through electrode TSV2 (second through electrode) ) is connected to the receiving circuit 40-2 (second receiving circuit). The output of the receiving circuit 40-1 and the output of the receiving circuit 40-2 are logically summed by the NOR gate 98. It can also be the logical sum caused by the OR gate.

The partially parallel method is a method in which only the through electrode TSV is multiplexed. However, in the completely parallel manner, not only the through electrode TSV is multiplexed, but also the drive circuit 30 and the receiving circuit 40 are multiplexed. The signal F1 is input by the drive circuits 30-1 and 30-2, respectively, and the drive circuits 30-1 and 30-2 transmit the signal F1 from the through electrodes TSV1 and 2, respectively. Since the problem of a decrease in the transmission speed due to the provision of the through-electrode TSV is not caused, the completely parallel mode is higher in speed than the partially parallel mode. According to the simulation by the present inventors, the TSV passage time of the signal of the completely parallel mode can be shortened by about 50 psec compared to the partial parallel mode. Therefore, it is easy to ensure a margin of time for latching the signal at the core wafer CC.

Of course, even if a defect occurs in one of the through electrodes TSV1, 2, the signal F1 is transmitted via the through electrode TSV on the normal side. Further, the signal F1 that has passed through both of the through electrodes TSV is logically summed by the NOR gate 98.

Figure 8 is a circuit diagram in a completely parallel manner. The signal F1 is input to both of the drive circuits 30-1, 30-2. The output control circuit 50 activates all of the drive circuits 30 simultaneously by a control signal (high start). The signal F1 after the drive circuit 30-1 is received by the receiving circuit 40-1, and the signal F1 after the drive circuit 30-2 is received by the receiving circuit 40-2. The output signals of the receiving circuits 40-1, 40-2 are logically summed by the NOR gate 98-1 and are received by the layer decision circuit 90-1. The layer determining circuit 90 is configured to determine whether the chip address specified by the chip selection signal is a designated chip bit. The circuit for determining the address. The receiving circuit 40 is a 3-state buffer and is activated by the control signal (low start) of the output control circuit 52. The signal F2 is also the same and is received by the layer decision circuit 90-2.

Since each of the drive circuits 30 is associated with one of the through electrodes TSV and one of the receiving circuits 40, even if it does not have a large capacity as the drive circuit 30 of the partially parallel type, it can be high speed. Transmit the signal.

In the case of the above-described content, in the partial parallel mode, although the number of the through electrodes TSV is increased, the signal transmission speed is moderate, and the circuit scale of the drive circuit 30 or the like can be reduced. In the replacement method, although the circuit area is increased and the signal transmission speed is also slow, the number of the through electrodes TSV is small. In the completely parallel mode, although the number of the through electrodes TSV is increased, the signal transmission speed is fast. It is only necessary to select the transmission mode of various signals based on the characteristics of each of these transmission modes. In particular, for a signal that is as high priority as a wafer selection signal, it is most suitable in a completely parallel manner.

[Second Embodiment]

Fig. 9 is a cross-sectional view showing the connection relationship of the semiconductor device 10 in the second embodiment. In the second embodiment, in addition to the replacement method and the partial parallel method, the interface wafer IF is connected to each core wafer CC in a new "non-remedy manner".

In Fig. 9, the signal S1 is transmitted in a partially parallel manner, and the signals D1 to D4 are transmitted by the replacement method. Also, the signal F is transmitted by a non-remediation method. Regarding the replacement method and the partial parallel method, it is as described above.

Figure 10 is a schematic diagram of a non-remediation mode. The signal F1 (first signal) is first input to the drive circuit 30 (first drive circuit). The signal F1 is further input to the receiving circuit 40 (first receiving circuit) via the TSV 1 (first through electrode). Thereafter, the signal F1 is output from the receiving circuit 40.

In the non-remedy manner, the remedy of the bad signal line caused by the prepared TSV is not performed. Since the remedy caused by the prepared TSV is not performed, the signal transmission speed is fast. However, if the through electrode TSV of any of the transmission signals F1 becomes a defective signal line, it is necessary to discard the entire semiconductor device 10.

In recent years, the manufacturing technology of laminated semiconductor devices has progressed, and the incidence of defective signal lines has also decreased. Moreover, most of the signals are data signals. As for the chip selection signals, the signals that need to be transmitted at high speed are only a small part of the whole. Therefore, it is conceivable that one part of the chip selection signal is required. The probability of a bad signal in the signal line is low. Therefore, by not providing a remedy for all signal lines, a high-speed signal line that is not a remedial method that does not remedy the bad signal line can be used to speed up the transmission speed and the stability of the product. Balance.

Figure 11 is a circuit diagram in a non-remedy manner. Signal F1 is output from the drive circuit 30-1 and is received by the receiving circuit 40-1. If there is a defect in the through electrode TSV, there is a risk that the transmission of the signal F1 cannot be performed. However, since the remedy of the defective signal line is not performed, there is no such a problem in the transmission speed or the circuit area. The problem of creating an excessive burden.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit and scope of the invention. These are also included in the scope of the present invention.

In the present embodiment, the signal transmission to the core wafer CC from the interface wafer IF is described. However, the signal transmission from the core wafer CC to the interface wafer IF is also applicable. this invention.

10‧‧‧Semiconductor device

20‧‧‧Terminal joints

30‧‧‧Drive circuit

40‧‧‧ receiving circuit

CC0~CC3‧‧‧ core chip

F1‧‧‧ signal

IF‧‧ interface chip

D1~D4‧‧‧ signal

S1‧‧‧ signal

R1~R5‧‧‧ Path

TSV‧‧‧through electrode

Claims (10)

A semiconductor device comprising: a first semiconductor wafer having a plurality of driving circuits including first and second driving circuits; and a second semiconductor wafer having plural numbers including first and second receiving circuits a receiving circuit; and a plurality of through electrodes for connecting the first semiconductor wafer and the second semiconductor wafer, wherein the first driving circuit is connected to the first receiving circuit via a first through electrode, The second drive circuit is connected to the second receiving circuit via the second through electrode, and the first signal transmitted from the first semiconductor wafer to the second semiconductor wafer is input to the first signal. And both of the second drive circuits are output from both the first and second receiving circuits. The semiconductor device according to the first aspect of the invention, wherein the second semiconductor wafer is synthesized by combining signals output from the first and second receiving circuits, and is received as the first signal. . The semiconductor device according to claim 1, wherein the plurality of second semiconductor wafers are provided, and the first signal is for the plurality of second semiconductor wafers The second semiconductor wafer that should be the target of the transmission is designated as the signal. The semiconductor device according to the first aspect of the invention, wherein the first semiconductor wafer includes a third driving circuit, the second semiconductor wafer includes a third receiving circuit, and the third driving circuit is via a third The fourth through electrode is connected to the third receiving circuit, and the second signal sent from the first semiconductor wafer to the second semiconductor wafer is input to the third driving circuit, and The third and fourth through electrodes are output from the third receiving circuit. The semiconductor device according to claim 1, wherein the first semiconductor wafer further includes a selection circuit, and the first semiconductor wafer includes fourth and fifth driving circuits, and the second semiconductor wafer The fourth and fifth receiving circuits are connected to the fourth receiving circuit via the fifth through electrode, and the fifth driving circuit is connected to the fourth through electrode via the sixth through electrode. The fifth receiving circuit is connected to transmit the first semiconductor wafer to the second semiconductor wafer The third signal is input to the drive circuit selected by the selection circuit in the fourth and fifth drive circuits, and is output from one of the fourth and fifth receiving circuits. . The semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor wafer and the plurality of second semiconductor wafers are stacked, and the through electrode is provided in the plural The second semiconductor wafer. The semiconductor device according to any one of claims 1 to 5, wherein one of the first and second semiconductor wafers is an interface wafer, and the other one is a core wafer. A semiconductor device comprising: a first semiconductor wafer having a plurality of driving circuits including first and third driving circuits; and a second semiconductor wafer having plural numbers including first and third receiving circuits a receiving circuit; and a plurality of through electrodes for connecting the first semiconductor wafer and the second semiconductor wafer, wherein the first driving circuit is connected to the first receiving circuit via a first through electrode, The third driving circuit is connected to the third receiving circuit via the third and fourth through electrodes, and the first signal sent from the first semiconductor wafer to the second semiconductor wafer is input to The first drive circuit is output from the first receiving circuit only via the first through electrode. The second signal transmitted from the first semiconductor wafer to the second semiconductor wafer is input to the third driving circuit, and is received from the third via the third and fourth through electrodes. The circuit is output. The semiconductor device according to claim 8, wherein the plurality of second semiconductor wafers are provided, and the first signal is the aforementioned one of the plurality of second semiconductor wafers to be a target of the communication. The second semiconductor wafer is designated as a signal. The semiconductor device according to claim 8 or 9, wherein the first semiconductor wafer further includes a selection circuit, and the first semiconductor wafer has fourth and fifth drive circuits, and the The second semiconductor wafer includes fourth and fifth receiving circuits, and the fourth driving circuit is connected to the fourth receiving circuit via a fifth through electrode, and the fifth driving circuit passes through the sixth through electrode. And being connected to the fifth receiving circuit, the third signal sent from the first semiconductor wafer to the second semiconductor wafer is input to the fourth and fifth driving circuits by the selection The circuit is selected by the driver circuit, and from the aforementioned 4 and one of the fifth receiving circuits are output.