TW201513185A - Semiconductor substrate to define reticle-free bit line trenches and method for fabricating the same - Google Patents

Abstract

The present invention relates to a fabricating method of semiconductor substrate to define reticle-free BL trenches, comprising the following steps. The first step is to form a plurality of insulating structures on a substrate structure. Specially, each of the insulating structures includes a protrusion above the substrate structure, and there is a BL area between two adjacent protrusions. The next step is to form a sacrificial layer covering the protrusions and the BL areas, wherein the sacrificial layer defines a plurality of openings. The next step is to form a plurality of shielding structures in the openings respectively. The last step is to selectively remove a portion of the sacrificial layer and a portion of the substrate structure by using the insulating structures and the shielding structures as hard masks to form two BL trenches in each of the BL areas with no reticle. The present invention further relates a semiconductor substrate to define reticle-free BL trenches.

Description

Semiconductor substrate for defining bit line trenches in a mask-free manner and method of fabricating the same

The present invention relates to a semiconductor process technology, and more particularly to a semiconductor substrate that can be applied to a memory device to define a bit line trench in a reticle-free manner and a method of fabricating the same.

Memory, as the name suggests, is a semiconductor component used to store data/data. Generally, in the storage of digital data, it is customary to use Bit to represent the capacity of the memory, and each unit in the memory for storing data is called Memory cell. As the functions of computer microprocessors become more and more complex, the computing operations of software programs are becoming more and more large. Therefore, the memory technology has become one of the important technologies that the semiconductor industry cannot ignore. Dynamic Random Access Memory (DRAM) is a kind of volatile memory, which is composed of multiple memory cells. Each memory cell contains a transistor and a capacitor, and each memory cell borrows It is electrically connected to each other by a word line (WL line) and a bit line (Bit Line, BL).

With the complication of semiconductor structure design rules, optical micro-etching technology is bound to develop toward smaller line widths. For today's lithography processes, the alignment accuracy is becoming higher and higher with the increase in component density (increased pattern complexity) and the sharp reduction in line width and line pitch in the same wafer area. The conventional lithography process forms a photoresist layer on the material layer to be etched, and then uses a projection exposure method. (Projection), the pattern on the photo mask is transferred to the wafer in a step and repeat or step and scan manner.

However, although the pattern formed by the above process has better resolution, the lithography process has high complexity and is subject to the reticle alignment position, Magnification error, stepper. The correct alignment of the scanner and the matching between the mechanical devices have caused the process window to become tighter, which increases the difficulty of alignment and even the process. Defect.

In addition, metal-insulator-metal (MIM) capacitors are commonly used in many types of capacitors, but MIM capacitors usually require more than three layers of masks and complicated processes, making it easy to process. Rates have an adverse effect (because complex processes are one of the potential causes of yield reduction). Therefore, there is an urgent need for reducing the use of the mask for the process of the MIM capacitor.

The present invention is directed to the absence of the prior art, and proposes a semiconductor substrate for defining a bit line trench in a mask-free manner and a method of fabricating the same, which can reduce the number of required masks and avoid misalignment of the mask (Mis- Alignment) causes the area of the predetermined molding area of the capacitor to be too small or offset.

In order to achieve the above object and effect, the present invention adopts the following technical solution: a method for manufacturing a semiconductor substrate for defining a bit line trench in a mask-free manner, comprising the steps of: firstly, providing a semiconductor substrate having a plurality of deep trenches; Then, a plurality of insulating structures are formed on the semiconductor substrate, each of the insulating structures has a partition portion and a protrusion portion, and the partition portions are located in the deep trenches, and the protrusion portions are located on the plurality of isolation portions and overflow Partially covering the semiconductor substrate, wherein a single-element region is defined between two adjacent protrusions; then, a sacrificial layer is formed on the protrusions and the bit line regions, and the sacrificial layer has a plurality of Opening; afterwards, forming a complex a plurality of shielding structures are disposed in the openings; and finally, the shielding structures are self-aligned masks, and a portion of the sacrificial layer and the semiconductor substrate are selectively removed to form two in each bit line region Bit line groove.

Based on the above method, the present invention also provides a semiconductor substrate for defining a bit line trench in a mask-free manner, comprising a semiconductor substrate, a plurality of insulating structures, a sacrificial layer and a plurality of shielding structures. The semiconductor substrate has a plurality of deep trenches; the insulating structures are disposed on the semiconductor substrate in parallel, each insulating structure has a partition and a protrusion, and the spacers are located in the deep trenches. The protrusions are located on the spacers and the overflow portion covers the semiconductor substrate, wherein a bit line region is defined between the adjacent two protrusions; the sacrificial layer covers the protrusions and the bits In the line region, the sacrificial layer has a plurality of openings; the shielding structures are located within the openings.

The manufacturing method can accurately define the active region and the bit line trenches, capacitors and bit line contact window predetermined molding areas without using a mask, thereby reducing the need for the mask to save process cost. Furthermore, since the protruding portion of the insulating structure and the shielding structure can be used together as a self-aligning mask, it is possible to further prevent a predetermined molding area such as a capacitor or a bit line contact window from being displaced due to misalignment of the mask. Too small, which can effectively improve the process yield and contribute to the miniaturization of memory components.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the principles of the present invention, and provide further explanation of the scope of the patent application of the present invention.

10‧‧‧Semiconductor substrate

DT‧‧ deep trench

11‧‧‧Base

12‧‧‧Oxide layer

13‧‧‧hard mask layer

ST‧‧‧ shallow trench

14‧‧‧ patterned photoresist layer

20‧‧‧Insulation structure

21‧‧‧Isolation Department

22‧‧‧Protruding

22a‧‧‧Inside

22b‧‧‧Outside

220b‧‧‧Slope structure

23‧‧‧ bit line area

30‧‧‧sacrificial layer

31‧‧‧ openings

40‧‧‧Shielding structure

50‧‧‧ bit line trench

AA‧‧‧active area

C‧‧‧Capacitor intended molding area

BLC‧‧‧ bit line contact window intended molding area

1 is a schematic flow chart of a method for fabricating a semiconductor substrate in which a bit line trench is defined in a mask-free manner according to the present invention.

2 to 8 are schematic diagrams showing the process of fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner according to the present invention.

The present disclosure proposes a method for fabricating a semiconductor substrate in which a bit line trench is defined in a mask-free manner, which can form a plurality of isolation structures and bits extending in the same direction on a semiconductor substrate by a self-alignment mechanism through a special process design. The element line trenches do not require the use of a reticle. It is worth mentioning that the method of the present invention can further define a predetermined molding area of a capacitor (capacitor) and a bit line contact window (BL contact) while forming a bit line trench, thereby preventing a predetermined molding area from being blocked. The cover is misaligned and the position is shifted and the area is too small.

Please refer to FIG. 1 , which is a schematic flow chart of a method for manufacturing a semiconductor substrate for defining a bit line trench in a mask-free manner according to the present invention, and referring to FIG. 2 to FIG. 7 respectively, which are respectively corresponding to the steps of the manufacturing method. Process schematic. The manufacturing method of the present invention will be described in detail below with reference to a preferred embodiment and the accompanying drawings.

First, step S10 is performed to provide a semiconductor substrate 10 having a plurality of deep trenches DT (shown in FIG. 2), wherein the adjacent two deep trenches DT are separated by a predetermined distance, providing a subsequent step to define the active region AA ( Active area). In the present embodiment, the predetermined distance is between about 1000 and 1500 Å, but the invention is not limited thereto, and the predetermined distance may be adjusted according to the process requirements.

Specifically, the semiconductor substrate 10 is sequentially formed by stacking a substrate 11, a pad layer 12, a hard mask layer 13, and a patterned photoresist layer 14. The method for forming the deep trench DT includes the following steps: A substrate 11 is provided, then a pad layer 12 is formed on the substrate 11, a hard mask layer 13 is formed on the pad layer 12, and a patterned photoresist layer 14 is formed on the hard mask layer 13, and then unpatterned light is removed. The portion of the resist layer 14 that is shielded. In this embodiment, the substrate 11 is, for example, a polysilicon substrate, and the pad layer 12 is, for example, a pad oxide or a pad nitride. The material of the hard mask layer 13 may include ruthenium oxide and nitridation.矽 or a combination thereof, but the invention is not limited thereto, and the material of each layer of the stacked structure can be adjusted according to the etching selectivity.

Next, step S12 is performed to form a plurality of insulating structures 20 (shown in FIG. 5) on the semiconductor substrate 10. Each of the insulating structures 20 has a partition 21 and a protrusion. The portion 22, wherein the spacers 21 are located in the deep trenches DT, the protrusions 22 are located on the spacers 21, and the overflow portion covers the semiconductor substrate 10; it is worth noting that adjacent A one-dimensional line region 23 may be defined between the two protrusions 22 to facilitate the fabrication of bit line trenches (not shown) in a mask-free manner in a subsequent step.

Specifically, the insulating structures 20 are formed by a self-aligned method, and the method includes the steps of first removing the patterned photoresist layer 14 remaining in step S10, and then selectively etching the hard mask layer. 13 is patterned (as shown in FIG. 3) to form a plurality of shallow trenches ST corresponding to the deep trenches DT, respectively, and the inner diameter of the shallow trenches ST is larger than the inner deep trenches DT The via is then filled with an insulating material in each deep trench DT and its corresponding deep trench DT (as shown in FIG. 4), and finally the patterned hard mask layer 13 is removed (as shown in FIG. 5). In the present embodiment, the insulating material is, for example, an oxide or an oxynitride, but the invention is not limited thereto.

In more detail, the protruding portion 22 of each of the insulating structures 20 can be further divided into an inner end portion 22a and at least one outer end portion 22b, wherein the inner end portion 22a is formed by the partition portion 21 extending away from the semiconductor substrate 10 The outer end portion 22b is located on at least one side of the inner end portion 22a to cover a portion of the semiconductor substrate 10 on at least one side of the partition portion 21. Thereby, the present invention also defines a predetermined molding area C of the capacitor while forming the insulating structure 20 by self-alignment.

Then, steps S14 and S16 are performed to deposit a sacrificial layer 30 on the insulating structures 20 and the bit line regions 23, and the sacrificial layer 30 can define a plurality of exposures between the insulating structures 20. The opening 31 (shown in FIG. 6) further forms a plurality of shielding structures 40 in the openings 31 (as shown in FIG. 7). Specifically, the sacrificial layer 30 is formed by Atomic layer deposition (ALD), which has an advantage in that the thickness of the sacrificial layer 30 can be controlled at Å level and the uniformity is excellent. Further, in order to make the sacrificial layer 30 conformally cover the outer surface of the insulating structure 20 to ensure that the opening 31 has a cubic shape, a gentle slope structure 220b may be formed on the outer end portion 22b of each insulating structure 20 (as shown in FIG. 6a). Shown).

In this embodiment, the material of the sacrificial layer 30 is, for example, tantalum nitride, but the invention is not limited thereto; it should be noted that the sacrificial layer 30 must be selected as a material rich in germanium at the same time as the substrate 11 to facilitate Both are removed simultaneously in the same etching step, and the shielding structure 40 must be selected as an oxide-rich material simultaneously with the insulating structure 20 to facilitate blocking in the etching step. However, in a variant embodiment, the sacrificial layer 30 can also be selected as an oxide-rich material simultaneously with the substrate 11, and the shielding structure 40 can be selected as a germanium-rich material simultaneously with the insulating structure 20.

Finally, step S18 is performed to etch the insulating structures 20 and the shielding structures 40 together as a self-aligning mask (as shown in FIG. 8) to form a plurality of bit line trenches 50. Specifically, the etching method used in this step is an anisotropic etching, such as plasma etching or reactive ion etching, but the invention is not limited thereto.

Further, the etching reaction gas may be selected from a mixed gas containing hydrogen bromide (HBr) gas and oxygen-containing (O ₂ ) gas. The reason is that the hydrogen bromide-containing gas has a good selectivity to the polycrystalline germanium substrate 11 and the tantalum nitride-based sacrificial layer 30, thereby reducing the influence on other layers during the etching process. Accordingly, the sacrificial layer 30 and the substrate 11 not covered by the insulating structure 20 and the shielding structure 40 can be sequentially removed to form the two-dimensional line trench 50 in each of the bit line regions 23 in a reticle manner.

Referring to FIGS. 2, 5 and 8, the technical features of the method for fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner are as described above. Based on the manufacturing method, a memory element can be fabricated. The semiconductor substrate includes a semiconductor substrate 10, a plurality of insulating structures 20, a sacrificial layer 30, and a plurality of shielding structures 40 (shown in FIG. 7).

Specifically, the semiconductor substrate 10 has a plurality of deep trenches DT, and the insulating structures 20 are disposed on the semiconductor substrate 10 in parallel, and each of the insulating structures 20 has a partition portion 21 and a protruding portion 22. In particular, the spacers 21 are respectively located in the deep trenches DT, and a plurality of active regions pre-AA are defined on the semiconductor substrate 10; the protrusions 22 are respectively located on the spacers 21, Overflow The portion covers a portion of the semiconductor substrate 10 such that a single line region 23 is defined between the adjacent two protrusions 22, and the overflow portion can define a plurality of capacitors to form a predetermined molding region C; the sacrificial layer 30 is located (covered) The protrusions 22 and the bit line regions 23, and the sacrificial layer 30 can define a plurality of openings 31 above the bit line regions 23, and the shielding structures 40 are respectively located in the openings 31.

Obviously, with the semiconductor substrate of the present invention, since the protruding portion 22 of the insulating structure 20 and the shielding structure 40 can be used as a self-aligning mask in the etching process, the active region can be accurately defined without using a mask. The bit line contact window between the AA and the two-element trench 50 and the two-element trench 50 is intended to form a molding region BLC between the bit line trench 50 and the spacer trench portion 50 and the isolation portion 21.

It should be further noted that the manufacturing method of the present invention can be adjusted by the self-alignment except that the bit line trench 50, the bit line contact window predetermined forming area BLC and the capacitor predetermined forming area C can be defined in a mask-free manner. a mask to adjust the dimensions and/or depth of the regions; specifically, the size of the predetermined line forming region BLC of the bit line contact window can be adjusted via the width of the shielding structure 40, the predetermined molding area of the capacitor The size of C can be adjusted via the width of the outer end 22b of the protrusion 22, and the size of the bit line groove 50 can be simultaneously adjusted by the width of the shielding structure 40 and the width of the outer end 22b, and all the bit lines The depths of the grooves 50 are all equal. Thereby, the process efficiency and reliability can be greatly improved.

Therefore, the manufacturing method of the semiconductor substrate of the present invention for defining the bit line trenches in a mask-free manner has at least the following advantages compared to the conventional process of defining a bit line trench by using a photomask:

1. The manufacturing method of the present invention can accurately define the active region and the bit line trenches, capacitors and bit line contact window predetermined forming regions without using a mask, thereby reducing the need for the mask to save Process cost.

2. The manufacturing method proposed by the invention can be regarded as a self-aligning mask by the protruding portion of the insulating structure and the shielding structure, so that in addition to the simple process, the predetermined molding area such as the capacitor and the bit line contact window can be prevented because of the light. The cover is misaligned and the position is biased The shift and the area are too small, which can effectively improve the process yield and contribute to the miniaturization of the memory components.

3. The semiconductor substrate of the present invention is used as a self-aligned mask by the protruding portion of the insulating structure and the shielding structure, so that it is easy to adjust the process parameters to control a predetermined molding region such as a capacitor and a bit line contact window. The area, and thus the capacitors, bit line contact windows and the like made by the subsequent steps have good consistency.

In summary, the present invention has been met with the requirements of the new patent, and the application is made according to law. However, the above disclosure is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus the equivalent changes or modifications made in the scope of the present application are still covered by the present application.

10‧‧‧Semiconductor substrate

30‧‧‧sacrificial layer

31‧‧‧ openings

40‧‧‧Shielding structure

Claims (10)

A method of fabricating a semiconductor substrate for defining a trench of a bit line in a mask-free manner, comprising the steps of: providing a semiconductor substrate having a plurality of deep trenches; forming a plurality of insulating structures on the semiconductor substrate, each insulating structure Having a spacer portion and a protrusion portion, the spacer portions are located in the deep trenches, the protrusion portions are located on the spacer portions and the overflow portion covers the semiconductor substrate, wherein the adjacent two protrusion portions are defined a plurality of element regions; a sacrificial layer is formed on the protrusions and the bit line regions, the sacrificial layer has a plurality of openings; a plurality of shielding structures are formed in the openings; and the shielding structures are A self-aligned mask selectively removes a portion of the sacrificial layer and the semiconductor substrate to form a two-dimensional line trench in each bit line region. The method for manufacturing a semiconductor substrate in which a bit line trench is defined in a mask-free manner according to claim 1, wherein the step of providing a semiconductor substrate further comprises the steps of: providing a substrate; forming a pad layer on the substrate Forming a hard mask layer on the underlayer; forming a patterned photoresist layer on the hard mask layer; and etching the hard mask layer not covered by the patterned photoresist layer, the mat layer And a portion of the substrate to form the deep trenches. The method for fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner according to claim 2, wherein the step of forming the plurality of insulating structures on the semiconductor substrate further comprises the step of: removing the patterning a photoresist layer; patterning the hard mask layer to form a plurality of shallow trenches respectively corresponding to the deep trenches, wherein the inner diameter of each shallow trench is larger than the corresponding deep trench a fill material; filling the insulating material in each of the deep trenches and the corresponding deep trenches; and removing the patterned hard mask layer to form the insulating structures. A method of fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner as described in claim 1, wherein each of the protrusions has an inner end structure and at least one outer end structure on a side of the inner end structure, The inner end structures respectively correspond to the plurality of partitions and define a plurality of active regions on the semiconductor substrate, the outer end structures defining a plurality of capacitor predetermined forming regions on the semiconductor substrate, The masking structure defines a plurality of contact window predetermined forming regions on the semiconductor substrate. A method of fabricating a semiconductor substrate for defining a bit line trench in a mask-free manner as described in claim 4, wherein the edge of the protruding portion of each insulating structure further forms a gentle slope structure. A semiconductor substrate for defining a trench of a bit line in a mask-free manner, comprising: a semiconductor substrate having a plurality of deep trenches; a plurality of insulating structures disposed in parallel on the semiconductor substrate, each insulating structure having a a spacer portion and a protrusion portion, the spacer portions are located in the deep trenches, the protrusion portions are located on the spacer portions and the overflow portion covers the semiconductor substrate, wherein a space is defined between the adjacent two protrusion portions a sacrificial layer covering the protrusions and the bit line regions, the sacrificial layer having a plurality of openings; and a plurality of shielding structures located in the openings. The semiconductor substrate of claim 6, wherein the outer diameter of each of the protrusions is larger than the outer diameter of the corresponding spacer. The semiconductor substrate of claim 7, wherein each of the protrusions has an inner end structure and at least one outer end structure on a side of the inner end structure, the inner ends The structures respectively correspond to the spacers and a plurality of active regions may be defined on the semiconductor substrate, and the outer structures may be The semiconductor substrate defines a plurality of capacitor predetermined forming regions, and the shielding structures define a plurality of contact window predetermined forming regions on the semiconductor substrate. A semiconductor substrate for defining a bit line trench in a mask-free manner as described in claim 8, wherein the edge of each of the protrusions further forms a gentle slope structure. The semiconductor substrate of claim 6, wherein the sacrificial layer and the substrate are germanium-rich materials, and the insulating structures and the shielding structures are oxide-rich. Material.