TW201511334A - Nanowire LED structure with decreased leakage and method of making same - Google Patents

Abstract

A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores extending from portions of a surface of a support exposed through openings in a mask layer, and a plurality of semiconductor shells extending over the nanowire cores. Each semiconductor shell includes at least one semiconductor interior shell extending around the respective nanowire cores, and a second conductivity type semiconductor outer shell extending around the interior shell. A first electrode layer contacts the second conductivity type semiconductor outer shell and extends into spaces between the semiconductor shells. The semiconductor interior shell includes a semiconductor foot portion which extends under the first electrode and under the respective second conductivity type semiconductor outer shell on the insulating masking layer in the spaces between the semiconductor shells. Semiconductor devices and methods including an insulating layer located between an insulating mask layer and a first electrode in the spaces between semiconductor shells.

Description

Nanowire light-emitting diode structure with reduced leakage and manufacturing method thereof Related application

This application claims the benefit of priority to U.S. Provisional Application No. 61/832,309, filed on Jun. 7, 2013, and U.S. Provisional Application No. 61/832,350, filed on Jun. 7, 2013. The entire contents of all of these applications are hereby incorporated by reference.

Embodiments of the present invention generally relate to semiconductor devices, such as nanowire light emitting diodes (LEDs), and in particular to an additional insulating layer at the base of the nanowire for reducing leakage current. Nano line LED.

Nanowire light-emitting diodes (LEDs) are becoming more and more attractive as an alternative to planar LEDs. Compared to LEDs produced by conventional planar technology, nanowire LEDs offer unique properties due to one-dimensional nature of the nanowires, provide improved flexibility of material combinations due to fewer lattice matching limitations, and are provided for use in The opportunity to process on a larger substrate.

In one aspect, a semiconductor device includes: a plurality of first conductivity type semiconductor nanowire cores positioned over a support member and exposed from an opening of one of the support members through an opening in the insulating mask layer a portion of the extension; and a plurality of semiconductor shells extending over the respective nanowire cores. Each of the plurality of semiconductor shell layers And comprising: at least one semiconductor inner shell extending around each of the plurality of nanowire cores; and a second conductivity type semiconductor outer layer extending around the at least one semiconductor inner shell. A first electrode layer contacts the second conductivity type semiconductor outer casing layer of the plurality of semiconductor shell layers and extends into a space between the semiconductor shell layers. The semiconductor inner casing layer includes a semiconductor foot portion on the insulating mask layer over the plurality of semiconductor shell layers under the first electrode and the respective second conductivity type semiconductor shell layers The space between them extends.

In a further aspect, a semiconductor device includes: a plurality of first conductivity type semiconductor nanowire cores over a support member; an insulating mask layer over the support member, wherein the nanometers The wire core includes a portion of the epitaxially extending semiconductor nanowire exposed from the semiconductor surface of the support member through the opening in the insulating mask layer; and a plurality of second conductive type semiconductor shell layers in the respective a nanowire core extending over and surrounding the respective nanowire cores; a first electrode layer contacting the second conductivity type semiconductor shell layers and extending into a space between the semiconductor shell layers; An insulating layer between the insulating mask layer and the first electrode in the spaces between the semiconductor shell layers.

1‧‧‧Nano-line light-emitting diode/other nanowire light-emitting diode structure/nano line Light-emitting diode structure / nanowire

2‧‧‧n type nanowire core/nano core/core/n core/first conductivity type core/first conductivity type (for example, n type) semiconductor nanowire core/first conductivity Type semiconductor nanowire core

2A‧‧‧ root

3‧‧‧p-type shell/shell/shell/semiconductor shell/second conductivity type semiconductor shell/semiconductor shell sidewall

3A‧‧‧Inner/Shell Sublayer/Shell/Inner AlGaN Shell/First p-AlGaN Inner Shell/p-AlGaN Inner Shell/AlGaN Shell/Layer/p-AlGaN Shell/No Two Conductive Type Shell/Crystal Part/Bottom Barrier Layer/Crystalline AlGaN/Semiconductor Shell/Substantial Single Crystal AlGaN Inner Shell/Substantial Single Crystal p-AlGaN Inner Shell/Substantial Single Crystal Inner Shell

3B‧‧‧Sheath/shell sublayer/outer GaN shell/outer p-GaN shell/shell/p-GaN shell/substantial single crystal p-GaN shell/p-GaN shell

3C‧‧‧Intermediate Shell/p-AlGaN Intermediate Shell/AlGaN Shell/Shell/Second Conductive Type Shell/Bottom Barrier/Crystal AlGaN/Semiconductor Shell/Substantial Single Crystal AlGaN Inner Shell

4‧‧‧Intermediate zone/action zone/action zone shell/quantum well shell/quantum well/semiconductor active zone

5‧‧‧Growth substrate/substrate/Si substrate

6‧‧‧Growth mask/dielectric mask layer/mask/mask layer/tantalum nitride mask layer/tantalum nitride mask/insulation mask layer

7‧‧‧Semiconductor buffer layer/GaN and/or AlGaN buffer layer/buffer layer/n-type semiconductor buffer layer

8‧‧‧ openings

9‧‧‧electrode/first electrode/p-side electrode/upper electrode/top electrode/top (example) For example, p side) electrode layer

10‧‧‧foot area/base area

11‧‧‧ Space

13‧‧‧Semiconductor Foot/Bottom/Polycrystalline p-AlGaN Foot/AlGaN Foot/Foot Part/n-AlGaN Foot/Bottom Barrier/Polycrystalline AlGaN Foot/ Relative High Resistivity Semiconductor AlGaN Foot/semiconductor foot portion/polycrystalline p-AlGaN foot portion/polycrystalline semiconductor foot portion/p-AlGaN foot portion/polycrystalline semiconductor foot

13A‧‧‧foot/polycrystalline foot/p-n diode foot/foot barrier

13B‧‧‧foot/polycrystalline foot/p-n diode foot/foot barrier

15‧‧‧Insulation/Layer/Spin-on Dielectric/Spin-on Insulation/Dense-Spin-On Glass/Spin-On Glass Insulation

15A‧‧‧Thicker part/thick part/thick-coated glass layer thicker part

15B‧‧‧ thinner part

15C‧‧‧Medium thickness/thinner part

17‧‧‧Second electrode layer/electrode/second electrode

23‧‧‧Pure or n-doped AlGaN shell/AlGaN shell/first conductivity type (eg n-type) AlGaN shell/shell/crystal part/foot barrier/crystalline AlGaN/semiconductor Shell/n-type shell/substantially single crystal AlGaN inner shell/inner n-AlGaN shell

25‧‧‧n-GaN shell/shell

313‧‧‧Bottom barrier/layer/barrier

Section 313C‧‧‧

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing one of the foundations of one of the nanowire LEDs according to an embodiment of the present invention.

Figure 2 is a schematic cross-sectional view showing one of the nanowire LED structures on a buffer layer in accordance with an embodiment of the present invention.

3A, 3B, 3C, 3D, 4A, and 4B schematically illustrate side cross-sectional views of a nanowire LED in accordance with an embodiment of the present invention.

3E, 3F, 3G, and 3H schematically illustrate side cross-sectional views of the steps of a method of fabricating a nanowire LED in accordance with an embodiment of the present invention.

5A, 5B, 5C, and 5D schematically illustrate the implementation in accordance with the present invention A side cross-sectional view of one of the nanowire LEDs.

6A, 6B, 6C, and 6D are SEM micrographs showing the steps of a method of fabricating a nanowire LED in accordance with an embodiment of the present invention. 6A and 6B are micrographs showing the formation of the base regions of Figs. 3A and 3B, respectively. Figure 6C is a micrograph of the SOG layer after deposition, drying and annealing. Figure 6D is a micrograph after partially etching the SOG layer by hydrofluoric acid (HF) solution.

Figure 7 is a plot of the probability of current at +2V for about 500 devices consisting of nanowire LEDs with and without the SOG layer.

In the technical field of nanotechnology, the nanowire is usually interpreted as having a lateral dimension of one of the nanometer or nanometer dimensions (eg, the diameter of a cylindrical nanowire or the width of a pyramid or hexagonal nanowire). Nanostructure, while its longitudinal size is not limited. These nanostructures are also commonly referred to as nanobes, one-dimensional nanocomponents, nanorods, nanotubes, and the like. The nanowires can have a diameter or width of up to about 2 microns. The small size of the nanowire provides unique physical, optical and electronic properties. For example, such properties can be used to form devices using quantum mechanical effects (eg, using quantum wires) or to form heterostructures of different materials that are typically not combined due to large lattice mismatches. As the term nanowire implies, a one-dimensional nature can be associated with an elongated shape. Since the nanowires can have various cross-sectional shapes, the diameter is intended to mean the effective diameter. Reference is made to the effective diameter, which means the average of the long and short axes of the profile of the structure.

All references to upper, top, lower, downward, etc. are made by considering the substrate as being at the bottom and the nanowire as extending upward from the substrate. Vertical means a direction perpendicular to one of the planes formed by the substrate, and horizontal means a direction parallel to one of the planes formed by the substrate. This nomenclature was introduced for ease of understanding only and should not be considered as limiting to a particular assembly orientation or the like.

Any suitable nanowire LED known in the art can be used in the method of the present invention. structure. Nanowire LEDs are typically based on one or more pn junctions or p-i-n junctions. The difference between a pn junction and a p-i-n junction is that the p-i-n mask has a wider area of action. A wider area of action allows for a higher probability of one of the reorganizations in the i-area. Each nanowire includes a first conductivity type (eg, n-type) nanowire core and a packaged portion for forming one of pn or pin junctions for operation of light generation A two conductivity type (eg, p-type) shell layer. While the first conductivity type of the core is described herein as an n-type semiconductor core and the second conductivity type shell is described herein as a p-type semiconductor shell, it should be understood that the conductivity type can be reversed.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of the basis of a modified nanowire LED structure in accordance with an embodiment of the present invention. In principle, a single nanowire is sufficient to form a nanowire LED, but due to its small size, the nanowire is preferably configured to include hundreds, thousands, tens of thousands or more of side-by-side layers used to form the LED structure. An array of rice noodles. For illustrative purposes, individual nanowire LED devices are described herein as having a p-shell having an n-type nanowire core 2 and at least partially encapsulating the nanowire core 2 and an intermediate active region 4. Forming the nanowire LED 1 of layer 3, the intermediate active region may comprise a single pure or lightly doped (eg, doped level below 10 ¹⁶ cm ^-3 ) semiconductor layer or a plurality of different band gaps One or more quantum wells of the semiconductor layer, such as 3 to 10 quantum wells. However, for the purpose of embodiments of the present invention, the nanowire LED is not limited thereto. For example, the nanowire core 2, the active region 4, and the p-type shell layer 3 may be composed of a plurality of layers or segments. In an alternate embodiment, only the core 2 may comprise a nanostructure or a nanowire by having a width or diameter less than 2 microns, and the shell 3 may have a width or diameter greater than one micron.

III-V semiconductors are of particular interest for their ability to promote high speed and low power electronic devices and optoelectronic devices such as lasers and LEDs. The nanowires may include any semiconductor material, and suitable materials for the nanowires include, but are not limited to, GaAs (p), InAs, Ge, ZnO, InN, GaInN, GaN, AlGaInN, BN, InP, InAsP, GaInP, InGaP: Si, InGaP: Zn, GaInAs, AlInP, GaAlInP, GaAlInAsP, GaInSb, InSb, Si. Possible donor dopants for, for example, GaP are Si, Sn, Te, Se, S, etc., and acceptor dopants for the same material are Zn, Fe, Mg, Be, Cd, and the like. It should be noted that the nanowire technology makes it possible to use nitrides such as GaN, InN, and AlN, which facilitates the fabrication of LEDs that emit light in wavelength regions that are not readily available by conventional techniques. Other combinations of particular commercial interest include, but are not limited to, GaAs, GaInP, GaAlInP, GaP systems. Typical doping levels range from 10 ¹⁸ cm ^-3 to 10 ²⁰ cm ^-3 . Those skilled in the art are familiar with these and other materials and recognize that other materials and combinations of materials are possible.

Preferred materials for the nanowire LED are III-V semiconductors such as a Group III nitride semiconductor (e.g., GaN, AlInGaN, AlGaN, InGaN, etc.) or other semiconductors (e.g., InP, GaAs). To act as an LED, the n-side and p-side of each nanowire LED 1 have to be contacted, and the present invention provides methods and compositions relating to contacting the n-side and the p-side of the nanowire in an LED structure.

Although the exemplary fabrication method set forth herein preferably utilizes a nanowire core to grow a semiconductor shell on the core to form a core shell nanowire, such as, for example, for a nanowire fabrication process. The teachings are set forth in U.S. Patent No. 7,829,443, the disclosure of which is incorporated herein by reference. For example, in an alternate embodiment, only the core may also constitute a nanostructure (eg, a nanowire), and the shell may optionally be larger than the size of a typical nanowire shell. In addition, the device can be shaped to include a plurality of end faces and control the area ratio between different types of end faces. This is illustrated by the "pyramid" end face and the vertical side wall end face. The LED can be fabricated such that the emissive layer is formed on a template having a dominant pyramid end face or sidewall end face. The same is true for the contact layer except for the shape of the emissive layer.

Figure 2 illustrates an exemplary structure for providing one of the supports for a nanowire. By using a growth mask or dielectric mask layer 6 (eg, a nitride layer, such as a tantalum nitride dielectric mask layer) as appropriate to define the position and determine the bottom interface region of the nanowires in a growth A nanowire is grown on the substrate 5, and the substrate 5 serves as a carrier for the nanowire protruding from the substrate 5 at least during processing. The bottom interface region of the nanowire includes a root region of the core 2 inside each opening in the dielectric mask layer 6. Substrate 5 may comprise different materials such as III-V or II-VI semiconductors, Si, Ge, Al ₂ O ₃ , SiC, quartz, glass, etc., as in Swedish patent application SE 1050700-2 (assigned to GLO AB) The Swedish patent application is hereby incorporated by reference in its entirety. Other suitable materials for the substrate include, but are not limited to, GaAs, GaP, GaP: Zn, GaAs, InAs, InP, GaN, GaSb, ZnO, InSb, SOI (on-insulator), CdS, ZnSe, CdTe. In one embodiment, the nanowire core 2 is grown directly on the growth substrate 5.

Preferably, the substrate 5 is also adapted to act as a current transport layer connected to the n-side of each nanowire LED 1. This can be achieved by having a substrate 5 comprising a semiconductor buffer layer 7 disposed on the surface of the substrate 5 facing the nanowire LED 1, as shown in FIG. 2, by way of example, a III-nitride A layer such as a GaN and/or AlGaN buffer layer 7 on a Si substrate 5. The buffer layer 7 is typically matched to the desired nanowire material and thus acts as a growth template in the fabrication process. For an n-type core 2, the buffer layer 7 is preferably also doped n-type. The buffer layer 7 may include a single layer (eg, GaN), a plurality of sub-layers (eg, GaN and AlGaN), or a graded layer of AlGaN or GaN that is tapered from a high Al content of AlGaN to a lower Al content. The growth of the nanowires can be achieved by the methods described in U.S. Patent Nos. 7,396,696, 7,335,908 and 7,829,443, and WO201014032, WO2008048704, and WO 2007102781, all of which are incorporated herein by reference.

It should be noted that the nanowire LED 1 may include several different materials (eg, a GaN core, a plurality of quantum well active regions of GaN/InGaN, and an AlGaN shell layer having an In to Ga ratio different from the active region). In general, substrate 5 and/or buffer layer 7 are referred to herein as one of the support members or a support layer for the nanowire. In some embodiments, instead of or in addition to the substrate 5 and/or the buffer layer 7, a conductive layer (eg, a mirror or transparent contact) Point) can be used as a support. Thus, the term "support layer" or "support" can encompass any one or more of these elements.

The use of a sequential (eg, shell) layer gives that the final individual device (eg, a pn or pin device) can have a pyramid or tapered shape (ie, narrower at the top or tip and at the base) A shape that is wider than a cylinder (e.g., about the same width at the tip and base) with a circular or hexagonal or other polygonal cross-section perpendicular to the long axis of the device. Thus, individual devices having a complete shell can have a variety of sizes. For example, the size can vary, wherein the substrate width is in the range of 100 nm to several (eg, 5) μm, such as 100 nm to less than 2 microns, and the height is between several hundred nm to several (eg, 10) μm. Within the scope.

The above description of one exemplary embodiment of an LED structure will serve as a basis for the description of the methods and compositions of the present invention; however, it will be appreciated that any suitable nanowire LED structure or Others are suitable for the nanowire structure, and any modifications will be apparent to those skilled in the art without departing from the invention.

LED radiation (eg, visible, UV, or IR) emissions can be reduced by unintentional leakage of current in the diode. A leaky power source has been identified by its physical location as being at the "foot" or base region 10 of the nanowire LED, as shown in Figure 3A. The foot or base region 10 is located above the mask 6 between the shell 3 and the nanowire core 2. This substrate leakage exhibits a relatively high current at <2V, which is lower than the "on" of the diode at 2.5 volts to 3.5 volts.

The first embodiment of the present invention provides a structure and method for reducing this leakage current by reducing contamination of the mask layer 6 during growth of the group III nitride semiconductor layer.

Without wishing to be bound by a particular theory, it is believed that in a binary, ternary, quaternary III-nitride semiconductor layer (such as an (Al)(In)GaN layer (ie, AlGaN, InGaN, and/or Decomposition of the tantalum nitride mask layer 6 may occur during high temperature growth of the InAlGaN action and/or the shell layer (e.g., at a temperature of at least 850 °C). The mask layer 6 is continuously exposed during the growth of the (Al)(In)GaN layer because the (Al)(In)GaN is easily nitrided from the tantalum nitride layer 6 at a high temperature. The surface is released. Contamination from the growth of the Group III nitride semiconductor of the tantalum nitride mask layer may result in leakage currents of one of the devices or worsening leakage currents.

In one aspect of the first embodiment, the inventors have discovered that the substrate leakage can be reduced by the formation of a portion of the semiconductor leg 13 of the shell 3, and the portion of the semiconductor leg 13 is exposed to the mask 6 The surface between the rice cores 2 extends away from the shell, as shown in Figures 3A, 3B, 4A and 4B. The foot 13 protects the mask layer 6 from contamination during the growth of other Group III nitride layers and thus can reduce leakage current.

In particular, the shell layer 3 may comprise a plurality of sub-layers, such as an inner shell layer 3A above the active region 4 and one outer shell layer 3B above the inner shell layer. If the nanowire core 2 comprises an n-type Group III nitride semiconductor, such as n-type GaN, the shell sub-layers 3A, 3B may comprise a p-type Group III nitride semiconductor sub-layer having a different composition. For example, the inner shell layer 3A may include p-AlGaN, and the outer shell layer 3B may include p-GaN.

In an embodiment of the present invention, a portion of the polycrystalline p-AlGaN foot 13 of the inner shell layer 3A may be formed in the inner layer 3A during growth of the tantalum nitride mask 6 at the nanowire core 2 and the shell layer. 3 above the exposed part. The foot 13 portion can, for example, be selected to result in a growth temperature (for example, a growth temperature of less than 850 ° C) and/or a CVD precursor gas flow that results in the formation of the polycrystalline p-AlGaN foot 13 portion. The ratio (for example, a ratio of one of Al gas to ammonia gas and/or a ratio of nitrogen to ammonia) is formed. Other growth conditions or parameters can also be used.

The resistivity of the AlGaN layer increases as the Al concentration increases. Thus, the AlGaN foot 13 portion containing at least 5 atomic percent aluminum has a relatively high resistivity to reduce leakage current. The foot 13 portion also provides a chemical resistant layer to protect the mask layer 6 during processing of the device and may also behave as a getter for oxygen impurities due to strong atomic bonding of oxygen to Al.

In particular, portions of the AlGaN foot 13 can be deposited directly on the tantalum nitride mask layer 6. The AlGaN layer can be deposited at any time during the growth of the device. For example, the AlGaN layer can include an inner shell layer 3A that forms a portion of the foot 13 on the mask layer 6 during growth, as shown in Figure 3A. The combination of the shell layer 3A containing a foot portion 13 can also be referred to as a foot block Floor.

Alternatively, the AlGaN layer can include an intermediate shell 3C between the inner AlGaN shell 3A and the outer GaN shell 3B, as shown in Figure 3B. Therefore, a first p-AlGaN inner shell layer 3A can be grown as an electron barrier after the growth of the quantum well in the active region 4. In an embodiment, the p-AlGaN inner shell layer 3A may contain less than 10 atom% Al (such as 2 atom% to 5 atom% Al) to provide a higher conductivity.

This inner shell layer 3A does not form a portion of the foot portion 13. Then, the p-AlGaN intermediate shell layer 3C is grown on the inner shell layer 3A having more than 5 at% Al, such as at least 10 at% Al. The intermediate shell 3C forms a portion of the foot 13 on the mask layer 6, as shown in Figure 3B. The outer p-GaN shell layer 3B is grown on the intermediate shell layer 3C and on the leg portion 13.

Alternatively, the AlGaN shell layer 3C may be grown over the active region 4 prior to growth of the AlGaN shell layer 3A. In this case, the portion of the foot 13 is formed before the growth of the AlGaN shell layer.

Preferably, the shell layers 3A, 3B and optionally 3C are grown by MOCVD with a p-type dopant source (eg, a Mg-containing metal organic gas such as (Cp) ₂ Mg) contained in the precursor stream. However, the AlGaN shell layer (for example, the shell layer 3A in FIG. 3A or the shell layer 3C in FIG. 3B) can also be grown without intentional doping. In this way, the AlGaN shell and foot regions are pure rather than p-doped.

In another alternative of the first embodiment, the foot 13 region is formed prior to the formation of the active region 4. In this aspect as shown in FIG. 3C, an optional n-GaN shell layer 25 is formed around the nanowire core 2. Then, a pure or n-doped AlGaN shell layer 23 (for example, Si-doped n-AlGaN) is formed to have Al of more than 5 atomic percent. The AlGaN shell layer 23 growth step also forms an n-AlGaN foot 13 portion on the mask layer 6. An active region 4 (for example, a GaN/InGaN quantum well) and an outer shell layer 3 (which may include a p-AlGaN shell layer 3A and a p-GaN shell layer 3B) are then formed on the region of the foot 13.

In another embodiment, the two legs 13A, 13B are partially disposed on the dielectric mask layer 6 Above, as shown in Figure 3D. The structure of Fig. 3D is combined with one of the structures of Fig. 3C and Fig. 3A. As shown in FIG. 3D, a first conductivity type (eg, n-type) AlGaN shell layer 23 having a portion of the foot 13A is formed over the first conductivity type core 2 and optionally at least one of the first conductivity types. On one shell 25. The portion of the shell layer 23 of the first conductivity type foot barrier layer formed on the shell layer 25 has a single crystal structure, and the portion of the foot 13A of the first conductivity type barrier layer is formed on the dielectric mask layer 6. One of the polycrystalline structures. The first conductivity type foot barrier layer includes a dopant that provides a first conductivity type of a group III nitride semiconductor (such as Si for an n-type semiconductor) such that the first bottom The conductivity type of the crystal portion 23 of the foot barrier layer has the same conductivity type as the first conductivity type of the core 2 and the shell layer 25.

A second conductivity type (e.g., p-type) AlGaN foot barrier layer is then formed after formation of the active region 4, as shown in Figure 3D. The second conductivity type (eg, p-type) AlGaN foot barrier layer can include a second conductivity type shell layer 3A having a portion of the second conductivity type foot 13B, similar to the foot shown in FIG. 3A Barrier layer. Alternatively, the second conductivity type (eg, p-type) AlGaN foot barrier layer can include a second conductivity type shell layer 3C having a portion of the second conductivity type foot 13B, similar to that in FIG. 3B The foot barrier shown.

The portion of the shell layer 3A of the second conductivity type foot barrier layer formed on the active region 4 (or another shell layer such as 3C) has a single crystal structure, and the bottom portion 13B of the second conductivity type barrier layer A portion has a polycrystalline structure formed on a portion of the polycrystalline foot 13A of the first conductivity type barrier layer. The second conductivity type foot barrier layer includes one of a second conductivity type one of a group III nitride semiconductor (such as Mg for a p-type semiconductor) such that the second foot barrier layer The conductivity type of the crystal portion 3A has the same conductivity type as the outer shell layer 3B (for example, a p-GaN shell layer). Thus, the device shown in Figure 3D contains two polycrystalline foot (e.g., 13A, 13B) portions of opposite conductivity types that are positioned one above the other. This forms a p-n diode foot 13A/13B portion, this The contamination of the mask layer 6 is further reduced or prevented and the leakage current from the electrodes 9 to 2 shown in Figures 4A and 4B is prevented or reduced.

In another alternative embodiment shown in FIGS. 3E and 3F, the foot barrier layer 313 is deposited on the dielectric mask layer 6 prior to the formation of the opening 8 in the mask layer 6. As shown in FIG. 3E, a foot barrier layer 313 is deposited on the mask layer 6. The foot barrier layer 313 can include one of the p-type or n-type AlGaN layers described above. Preferably, layer 313 has a conductivity type (e.g., p-type) that is opposite to the conductivity type (e.g., n-type) of core 2 to reduce leakage current. Then, as shown in FIG. 3F, an opening 8 is formed through the foot barrier layer 313 and the mask layer 6 using any suitable lithography and etching process to expose the buffer layer 7 (or another portion of the support). The core 2 and the remaining nanowire LED structures 1 comprising a core and a shell are then formed, as set forth above with respect to Figures 1 and 2.

In another embodiment, shown in Figures 3G and 3H, the foot barrier layer 313 is deposited on the dielectric mask layer 6 after the opening 8 has been formed in the mask layer. As shown in Figure 3G, an opening 8 is first formed in the mask layer 6 using any suitable lithography and etching process to expose the buffer layer 7 (or another portion of the support). Then, as shown in FIG. 3H, a foot barrier layer 313 is then formed over the mask layer 6. The foot barrier layer 313 can include the p-type or n-type AlGaN layer as explained above. Thus, a portion 313C of the foot barrier layer 313 will be formed in the opening 8 on the buffer layer 7 (or the support member exposed to another portion of the opening 8). Portion 313C of foot barrier layer 313 can be removed from opening 8 by another etching step prior to forming core 2. Alternatively, the core 2 can be formed directly on the portion 313C of the barrier layer, in which case the core 2 and the barrier layer 313 preferably have the same conductivity type (e.g., n-type). A nanowire LED structure 1 comprising a shell layer is then formed over the core 2. Additional foot 13 portions may be formed on the foot barrier layer 313, as set forth above and as shown in Figures 3A-3D.

In summary, the foot barrier layer (eg, the entire layer 313 or portions thereof) can be formed on the mask layer 6 before and/or after forming the core 2, as in Figures 3E-3H and 3A-3D. Shown separately. The foot barrier layer 23/13 may be formed on the core 2 before forming the active region 4. Above the square and at least one of the shell layers 25, as shown in Figure 3C. Alternatively, the foot barrier layer 3A/13 or 3C/13 may be formed over the active area 4 after forming the active area 4, as shown in Figures 3A and 3B. Alternatively, the LED device can include a plurality of foot barrier layers (eg, 23/13A and 3A/13B) of the same or opposite conductivity type formed before and/or after forming the active region, as in FIG. 3D. Shown.

The foot barrier layer preferably includes one or more of Al, Ga, In, B, Si, Mg, N, such as a Group III nitride semiconductor, wherein Si and/or Mg are doped as n-type and p-type Add as a dose. In an embodiment, the foot barrier layer comprises AlGaN and has a polycrystalline structure in a region (eg, 13, 313) formed on the dielectric mask layer 6. The region (for example, the shell layer 3A, 3C, 23), the core or the shell layer formed on a single crystal layer may have a single crystal structure. The foot barrier layer can be deposited by any of several methods, such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), electricity. Pulp-assisted molecular beam epitaxy (PAMBE) or reactive sputtering deposition. Other methods can also be used. In a preferred embodiment, the foot barrier layer comprises a polycrystalline AlGaN foot 13 portion on the dielectric mask layer 6 and a crystalline AlGaN 3A, 3C or 23 shell layer over a single crystal semiconductor nanowire shell layer. And formed by MOCVD.

The thickness of the polycrystalline foot barrier layer (e.g., foot portion 13) above the mask layer 6 can vary across the area between adjacent cores 2 such that the thickness is minimal closest to the core and between two adjacent cores The midpoint is the largest, as shown in Figures 3A through 3D. Alternatively, the foot barrier layer 313 can have a uniform thickness as shown in Figures 3E, 3F, and 3H. The thickness of the portion of the AlGaN foot 13 on the tantalum nitride mask layer 6 is preferably greater than 10 nm to achieve good surface coverage, but less than 100 nm so as not to interfere with the growth of the outer shell layer 3B. For example, the AlGaN foot 13 portion or layer 313 can be 20 nm to 80 nm thick and contain at least 10 atomic percent Al, such as 10 to 15 atomic percent. However, other thicknesses can be used.

As shown in Figures 4A and 4B, a first (e.g., top or p-side) electrode 9 is then formed over the outer shell layer 3B of the LED and in the space 11 between the LEDs. The p-side electrode 9 contacts the far The relatively high resistivity semiconductor AlGaN foot 13 shown in FIGS. 3A through 3C of the lift electrode 9 is lifted away from the base region 10, which can be reduced to the undesired current leakage path of the nanowire core 2.

A second embodiment of the present invention provides a structure and method for reducing leakage current by electrically isolating leakage current from the base region 10 and the upper electrode 9 and the remainder of the device.

Specifically, as shown in FIGS. 5A and 5B, an insulating layer 15 is formed between the insulating mask layer 6 and the top electrode 9 in the space 11 between the semiconductor shell layers 3 to prevent or reduce the substrate region 10 Leakage current. Figure 5A illustrates a semiconductor device, such as an LED device, comprising a plurality of first conductivity type (e.g., n-type) semiconductor nanowire cores 2 over a support. The insulating mask layer 6 is located above the support. As explained above, the nanowire core 2 includes a portion of the epitaxially-extending semiconductor nanowire that is exposed through the opening in the insulating mask layer 6 from one of the semiconductor surfaces of the support (e.g., the surface of the buffer layer 7). A plurality of second conductivity type semiconductor shell layers 3 extend over the respective nanowire cores 2 and around the respective nanowire cores 2. The top (e.g., p-side) electrode layer 9 contacts the second conductive type semiconductor shell layer 3 and extends into the space 11 between the semiconductor shell layers.

Preferably, as set forth above, the LED device also includes an active region shell 4 surrounding each of the plurality of nanowire cores 2. In one embodiment, the active region shell layer includes at least one quantum well, and the second conductivity type semiconductor shell layer 3 surrounds at least one quantum well to surround each nanowire core 2 surrounded by at least one quantum well shell layer 4. A luminescent pin junction is formed at the location.

As explained above, the semiconductor shell layer 3A, 3C or 23 optionally includes a portion of the semiconductor foot 13 of the first embodiment, and a portion of the semiconductor foot 13 portion on the insulating mask layer 6 between the semiconductor shell layers 11 Extended in the middle. As shown in FIGS. 5B and 5C, the insulating layer 15 is located on the portion of the semiconductor leg 13 such that the top electrode 9 contacts the insulating layer 15 and does not contact the foot portion 13 in the space 11. The portion of the foot 13 in Fig. 5B is formed as part of the p-type shell layer 3 (e.g., the shell layer 3A or 3C of Fig. 3A or Fig. 3B), and the foot portion of Fig. 5C is formed as the n type shell layer of Fig. 3C. Part of 23. Therefore, the insulating layer prevents or reduces the flow through the top electrode 9 and The leakage current of the foot portion 13 between the nanowire cores 2.

As also explained above, the second conductivity type semiconductor shell layer 3 preferably comprises one of substantially single crystal AlGaN inner shell layers 3A, 3C or 23 having greater than 5 atomic percent aluminum and a substantially single crystal p-GaN outer shell. Layer 3B. The semiconductor foot portion 13 includes a polycrystalline AlGaN foot portion of one of the inner shell layers of AlGaN. The polycrystalline p-AlGaN foot portion 13 is connected under the p-GaN outer layer 3B to the substantially single crystal AlGaN inner shell layer 3A, 3C or 23. As used herein, substantially single crystal means that it may have certain defects (such as poor row and/or stacking errors) and/or several grain boundaries (but lacking in the layers and layers of polycrystalline materials). One of more than ten crystal grains). In particular, in the embodiment shown in FIG. 5C, the insulating layer 15 prevents a pn junction between the n-AlGaN foot 13 portion and the p-type shell layer 3 (eg, the p-GaN shell layer 3B). form.

In another aspect of the second embodiment shown in Figure 5D, the insulating layer 15 is used in a device that lacks one of the legs 13 portions. In this device, the insulating layer 15 is located above the mask layer 6. Thus, layer 15 protects mask layer 6 and raises electrode 9 away from substrate portion 10 of the device in which leakage current occurs.

The insulating layer 15 may comprise any suitable insulating layer such as hafnium oxide, tantalum nitride, high-k dielectric (eg, alumina, hafnium oxide, organic dielectric, etc.). Preferably, the insulating layer 15 comprises a spin-on dielectric, such as a spin-on glass or another suitable spin-on dielectric.

One of the second electrode layers 17 (for example, the n-side electrode) shown in FIG. 5A is electrically connected to the n-type nanowire core 2. If the substrate 5 is a semiconductor (for example, germanium or GaN) or a conductive substrate, the electrode 17 may be formed on the bottom of the substrate 5. Alternatively, the second electrode 17 may contact the n-type semiconductor buffer layer 7 on the substrate 5 from the top side in a region in which the nanowire 1 and the top electrode 9 have been removed.

As explained above, in a preferred embodiment, the buffer layer 7 comprises an n-GaN or n-AlGaN layer, the nanowire core 2 comprises n-GaN nanowires, and at least one quantum well 4 comprises a plurality of InGaN/ a GaN quantum well, and the top electrode 9 comprises a transparent conductive oxide (TCO), such as Indium tin oxide or aluminum zinc oxide. Electrode 17 can comprise any suitable electrical conductor, such as a metal.

6A, 6B, 6C, and 6D are SEM micrographs illustrating one method of fabricating the apparatus of Figs. 5A and 5B. First, as explained above, a plurality of first conductivity type semiconductor nanowire cores 2 are passed through a semiconductor surface (for example, buffer layer 7) of a support member through an opening in one of the insulating mask layers 6 on the support member. The exposed part of the epitaxial growth. The core layers 23, 25 and the active regions (e.g., quantum wells) 4 of Figure 3C are then formed around the core 2. A plurality of second conductivity type semiconductor shell layers 3 extending over the respective nanowire cores 2 and extending around the respective nanowire cores 2 are then formed.

As explained above, the step of forming the semiconductor shell layer 3 includes forming (eg, epitaxial growth by CVD) during the same CVD growth step over the respective nanowire cores 2 and extending around the respective nanowire cores 2 The substantially single crystal semiconductor shell portion (for example, inner shell layer 3A, outer shell layer 3B, and intermediate shell layer 3C) and, as the case may be, horizontally extend in space 11 between semiconductor shell layers 3 on insulating mask layer 6. The polycrystalline semiconductor foot portion 13. For example, a substantially single crystal p-AlGaN inner shell layer 3A or an intermediate shell layer 3C having 5% or more aluminum is epitaxially grown by CVD over a semiconductor active region 4 (for example, a quantum well) while being nitrided. A polycrystalline p-AlGaN foot portion 13 is selected for growth on the germanium mask layer 6. Then, substantially, the single crystal p-GaN outer shell layer 3B is epitaxially grown on the substantially single crystal inner shell layer 3A (or the intermediate shell layer 3C) instead of the foot portion 13.

Without being bound by a particular theory, it is believed that the outer shell layer 3B does not grow horizontally on the foot portion 13 (i.e., has a thickness that is less than one of the length and width along the horizontal plane in the vertical direction). Therefore, as shown in FIG. 6A, the p-AlGaN foot portion 13 can be connected to the p-AlGaN inner shell layer 3A under the p-GaN outer shell layer 3B. Alternatively, as shown in Figure 6B, the p-AlGaN foot portion 13 can be attached to the p-AlGaN intermediate shell 3C under the p-GaN outer shell layer 3B (or to the n- shown in Figure 3C). AlGaN shell layer 23). Alternatively, the foot portion 13 may not be physically connected to any of the shell layers.

Then, as shown in FIG. 6C, an insulating layer 15 is formed over the insulating mask layer 6 at In the space 11 between the semiconductor shell layers 3, the tips and sidewalls of the semiconductor shell layer 3 are exposed in the insulating layer 15. If the foot portion 13 is present, the insulating layer 15 is formed on the foot portion 13 in the space 11. The insulating layer 15 prevents or reduces the current leakage path in the base region 10 between the outer shell layer 3B and the root 2A of the nanowire core 2.

Preferably, the step of forming the insulating layer 15 comprises spin coating a spin-on dielectric layer. The spin coating process forms an insulating layer 15 having a thicker portion 15A in the space 11 between the semiconductor shell layers on the insulating mask layer 6 and a thinner portion 15B on the upper sidewall of the semiconductor shell layer 3, As shown in Figure 6C. The upper surface of the insulating layer is curved, wherein the thick portion 15A is adjacent to the shell layer in the space 11 and the thickness portion 15C of the space 11 is away from the shell layer 3.

In one non-limiting example, the spin-on dielectric layer 15 is a spin on glass (SOG). SOG is formed by providing a solution of a citrate dissolved or suspended in a solvent. This solution is deposited on top of the nanowire and on the shell containing the substrate, which is spin coated at high revolutions per minute. The spin coating action uniformly distributes the SOG above the shell layer 3 and into the space 11 on the substrate. After the deposition, the SOG slowly changes. For example, the SOG can first be enthalpy at one of 75 ° C, then at 150 ° C and finally at 250 ° C. The drying procedure removes the solvent leaving the phthalate. After drying, the substrate with spin-on tantalate is annealed at a higher temperature (typically 400 ° C to 700 ° C), which densifies the niobate to a SiO ₂ web. The dense SiO ₂ is a dielectric film having low leakage.

Then, as shown in FIG. 6D, the insulating layer 15 is isotropically partially etched. This etching step removes the thinner portion 15B of the insulating layer 15 from at least the upper portion of the sidewall of the semiconductor shell 3 and exposes at least the upper portion of the sidewall 3 of the semiconductor shell. However, the thick portion 15A of the spin-on insulating layer 15 remains in the space 11 between the semiconductor shell layers 3 after the partial etching, but the total insulating layer thickness is reduced in the space 11. The thicker portion 15A adjacent to the shell layer and the thinner portion 15C remote from the shell layer remain on the curved surface.

For example, the etch can include any suitable wet etching of SOG, such as isotropic wet etching by dilute hydrofluoric acid (HF) via dense SOG layer 15. This etching can be from the shell layer 3 The sidewalls and the thinner portion 15B of the tip removal layer are in electrical contact to one of the sidewalls of the shell layer 3, while leaving a thicker portion 15A of the SOG layer where it provides electrical insulation in the substrate region 10.

As shown in Figures 5A-5D, a top electrode layer 9 is then formed over the device shown in Figure 6D. The top electrode layer 9 contacts the exposed tip and sidewall of the semiconductor shell 3. The top electrode layer 9 also contacts the insulating layer 15 in the space 11 between the semiconductor shell layers 3. Preferably, the top electrode layer 9 is formed on the exposed top end of the semiconductor shell layer 3 and on at least the upper portion of the sidewall (for example, on the outer shell layer 3B) and the insulating layer 15 in the space 11 between the semiconductor shell layers 3. One of the continuous layers is such that the top electrode layer does not contact the portion of the polycrystalline semiconductor foot 13 if it is present.

Figure 7 is a plot of the probability of current at +2V for about 500 devices consisting of nanowire LEDs with and without the SOG insulating layer 15 at the substrate or foot region 10. As can be seen from this figure, for LEDs with SOG layers, the current distribution is much tighter and the leakage current is lower compared to without the SOG layer.

Although the invention has been described in terms of contact with a nanowire LED, it should be understood that semiconductor devices based on other nanowires (such as field effect transistors, diodes, and especially those involving light absorption or light generation (such as light detection) , solar cells, lasers, etc.) can be implemented on any nanowire structure.

All publications and patents cited in the specification are hereby incorporated by reference in their entirety as if the disclosure The methods and/or materials are disclosed and described herein together and incorporated by reference. The disclosure of any publication is for its disclosure prior to the filing date and is not to be construed as an admission that the invention is not limited by the prior invention. In addition, the date of the publication provided may be different from the actual publication date, which may require independent confirmation.

2‧‧‧n type nanowire core/nano core/core/n core/first conductivity type core/first conductivity type (for example, n type) semiconductor nanowire core/first conductivity Type semiconductor nanowire core

3‧‧‧p-type shell/shell/shell/semiconductor shell/second conductivity type semiconductor shell/semiconductor shell sidewall

3A‧‧‧Inner/Shell Sublayer/Shell/Inner AlGaN Shell/First p-AlGaN Inner Shell/p-AlGaN Inner Shell/AlGaN Shell/Layer/p-AlGaN Shell/No Two Conductive Type Shell/Crystal Part/Bottom Barrier Layer/Crystalline AlGaN/Semiconductor Shell/Substantial Single Crystal AlGaN Inner Shell/Substantial Single Crystal p-AlGaN Inner Shell/Substantial Single Crystal Inner Shell

3B‧‧‧Sheath/shell sublayer/outer GaN shell/outer p-GaN shell/shell/p-GaN shell/substantial single crystal p-GaN shell/p-GaN shell

4‧‧‧Intermediate zone/action zone/action zone shell/quantum well shell/quantum well/semiconductor active zone

6‧‧‧Growth mask/dielectric mask layer/mask/mask layer/tantalum nitride mask layer/tantalum nitride mask/insulation mask layer

7‧‧‧Semiconductor buffer layer/GaN and/or AlGaN buffer layer/buffer layer/n-type semiconductor buffer layer

10‧‧‧foot area/base area

13‧‧‧Semiconductor Foot/Bottom/Polycrystalline p-AlGaN Foot/AlGaN Foot/Foot Part/n-AlGaN Foot/Bottom Barrier/Polycrystalline AlGaN Foot/ Relative High Resistivity Semiconductor AlGaN Foot/semiconductor foot portion/polycrystalline p-AlGaN foot portion/polycrystalline semiconductor foot portion/p-AlGaN foot portion/polycrystalline semiconductor foot

Claims (58)

A semiconductor device comprising: a plurality of first conductivity type semiconductor nanowire cores over a support member; an insulating mask layer over the support member, wherein the nanowire cores comprise a portion of the epitaxially extending semiconductor nanowire exposed by the semiconductor surface of the support member through the opening in the insulating mask layer; a plurality of semiconductor shell layers extending over the respective nanowire cores, wherein the plurality Each of the plurality of semiconductor shell layers includes at least one semiconductor inner shell layer extending around each of the plurality of first conductivity type nanowire cores and a second one extending around the at least one semiconductor inner shell layer a conductive type semiconductor outer casing layer; a first electrode layer contacting the second conductive type semiconductor outer casing layer of the plurality of semiconductor shell layers and extending into a space between the semiconductor shell layers; and the at least one semiconductor An inner shell layer and a semiconductor foot portion, the semiconductor foot portion being under the first electrode and the respective second conductivity type semiconductor shell layer Upper layer extends to the spaces between the plurality of semiconductor shell layer. A device as claimed in claim 1, wherein the device comprises a light emitting diode (LED) device. The device of claim 2, further comprising a zone shell surrounding each of the plurality of nanowire cores. The device of claim 3, wherein the active region shell comprises at least one quantum well, and the second conductivity type semiconductor outer layer surrounds the at least one quantum well to surround each nanometer surrounded by at least one quantum well shell layer A luminescent pin junction is formed at the core. The device of claim 4, further comprising an insulating layer between the insulating mask layer and the first electrode between the plurality of semiconductor shell layers, wherein the insulating layer is located in the semiconductor The semiconductor foot portions of the shell layer are such that the first electrode contacts the insulating layer and does not contact the semiconductor foot portion. The device of claim 5, wherein the insulating layer comprises a spin-on dielectric. The device of claim 6 wherein the spin-on dielectric comprises a spin-on glass layer having a curved upper surface. The device of claim 3, wherein each of the semiconductor inner shell layers comprises a second conductivity type semiconductor inner shell layer between the active region shell layer and the second conductive type outer shell layer, and the at least one semiconductor interior A shell layer is attached to the semiconductor foot portion. The device of claim 8, wherein: each of the second conductivity type semiconductor inner shell layers comprises one p-AlGaN inner shell layer having more than 5% aluminum; each second conductivity type semiconductor outer shell layer comprises a p-GaN layer a semiconductor layer portion including a p-AlGaN foot portion of the p-AlGaN inner shell layer; and the p-AlGaN foot portion is connected to the p-AlGaN inner shell layer under the p-GaN outer shell layer . The device of claim 8, wherein: each of the second conductivity type semiconductor inner shell layers comprises a p-AlGaN inner shell layer having 5% or less aluminum and one p-AlGaN inner layer having more than 5% aluminum a shell layer; each second conductivity type semiconductor shell layer comprises a p-GaN outer shell layer; each p-AlGaN intermediate shell layer is located on the p-GaN outer shell layer and the p-AlGaN inner shell layer or the active region shell layer Between one of the semiconductor legs; the semiconductor foot portion includes one of the p-AlGaN intermediate shell p-AlGaN feet a portion; and the p-AlGaN foot portion is connected to the p-AlGaN intermediate layer under the p-GaN outer layer. The device of claim 3, wherein each of the semiconductor inner shell layers comprises a first conductivity type between the active region shell layer and one of the plurality of first conductivity type semiconductor nanowire cores The inner shell of the semiconductor. The device of claim 11, wherein: each first conductivity type semiconductor inner shell layer comprises one n-AlGaN shell layer having more than 5% aluminum; and the semiconductor foot portion includes one of the n-AlGaN shell layers n- An AlGaN foot portion; each second conductivity type semiconductor outer layer includes a p-GaN outer layer; and the n-AlGaN foot portion is connected to the n- under the p-GaN outer layer and the active region shell AlGaN shell layer. The device of claim 4, wherein the first conductivity type comprises an n-type, the second conductivity type comprises a p-type, and the first electrode layer comprises a p-electrode layer. The device of claim 13, further comprising a second electrode layer electrically connected to one of the n-type nanowire cores. The device of claim 14, wherein the support comprises an n-type semiconductor buffer layer on a substrate. The device of claim 15, wherein the buffer layer comprises an n-GaN or n-AlGaN layer, the nanowire core comprises an n-GaN nanowire, the at least one quantum well comprises an InGaN/GaN quantum well, and The first electrode includes a transparent conductive oxide (TCO). A method of fabricating a semiconductor device, comprising: transmitting an insulating mask layer from a semiconductor surface of a support member through the support member a portion of the epitaxially exposed portion of the epitaxially grown plurality of first conductivity type semiconductor nanowire cores; forming a plurality of semiconductor shell layers extending around the respective nanowire cores, wherein the plurality of semiconductor shell layers are formed Each of the plurality of semiconductor inner shell layers and a semiconductor foot portion extending over the insulating mask layer in a space between the plurality of semiconductor shell layers; and forming around the at least one semiconductor inner shell a layer extending a second conductivity type semiconductor outer casing layer; and forming a first electrode layer, wherein the first electrode layer contacts at least an upper portion of the exposed tip and sidewall of the second conductivity type semiconductor outer casing layer, and The first electrode layer extends over the foot portion of each of the semiconductor inner shell layers in the spaces between the plurality of semiconductor shell layers. The method of claim 17, wherein forming the at least one semiconductor inner shell layer comprises forming at least one substantially single crystal semiconductor inner shell layer having the semiconductor foot portion in the same CVD growth step. The method of claim 18, further comprising forming an insulating layer over the insulating mask layer in the spaces between the plurality of semiconductor shell layers such that the second conductive type semiconductor shell layers At least the upper portion of the tip and the sidewall are exposed to the insulating layer. The method of claim 19, wherein the step of forming the insulating layer comprises spin coating a spin-on dielectric layer. The method of claim 20, wherein the spin-on dielectric layer thickness is above the insulating mask layer in the spaces between the second conductive type semiconductor outer skin layers than in the second conductive types The sidewalls of the semiconductor outer layer are large. The method of claim 21, further comprising isotropically partially etching the spin-on dielectric layer from the at least one of the second conductivity type semiconductor outer skin layers Portion partially removing the spin-on dielectric and exposing at least the upper portions of the sidewalls of the second conductivity type semiconductor cap layers, and in the spaces between the second conductivity type semiconductor cap layers The spin-on dielectric layer is retained. The method of claim 19, wherein the first electrode layer contacts the insulating layer and does not contact the polycrystalline semiconductor foot portion of each of the semiconductor inner shell layers. The method of claim 18, wherein the first electrode layer contacts the polycrystalline semiconductor foot portion of each of the semiconductor inner shell layers. The method of claim 18, further comprising forming an active region shell surrounding each of the plurality of nanowire cores, wherein the device comprises a light emitting diode (LED) device. The method of claim 25, wherein the first conductivity type comprises an n-type, the second conductivity type comprises a p-type, and the first electrode layer comprises a p-electrode layer. The method of claim 26, further comprising electrically connecting to one of the second electrode layers of the n-type nanowire core. The method of claim 27, wherein the support comprises an n-type semiconductor buffer layer on the substrate, the buffer layer comprising an n-GaN or n-AlGaN layer, the nanowire core comprising an n-GaN nanowire The active region shell layer includes an InGaN/GaN quantum well, and the first electrode includes a transparent conductive oxide (TCO). The method of claim 25, wherein each of the semiconductor inner shell layers comprises a second conductivity type semiconductor inner shell layer between the active region shell layer and the second conductivity type semiconductor outer shell layer. The method of claim 29, wherein: forming each of the second conductivity type semiconductor inner shell layers comprises forming a p-AlGaN inner shell layer having one greater than 5% aluminum at a temperature lower than 850 ° C; forming each The second conductive type semiconductor outer layer includes a p-GaN outer layer formed at a temperature higher than 850 ° C; Forming the semiconductor foot portion includes forming a p-AlGaN foot portion of the p-AlGaN inner shell layer; and the p-AlGaN foot portion is connected to the p-AlGaN inner shell layer below the p-GaN outer shell layer. The method of claim 29, wherein: forming each of the second conductivity type semiconductor inner shell layers comprises forming a p-AlGaN inner shell layer having 5% or less of aluminum at a temperature lower than 850 ° C, And forming a p-AlGaN intermediate shell layer having more than 5% aluminum at a temperature higher than 850 ° C; forming each second conductivity type semiconductor outer shell layer includes forming a p-GaN outer shell layer; each p-AlGaN An intermediate shell layer is located between the p-GaN outer shell layer and one of the p-AlGaN inner shell layer or the active region shell layer; forming the semiconductor foot portion includes forming one of the p-AlGaN intermediate shell layers p- An AlGaN foot portion; and the p-AlGaN foot portion is connected to the p-AlGaN intermediate layer under the p-GaN outer layer. The method of claim 25, wherein each of the semiconductor inner shell layers comprises a first conductivity type semiconductor inner shell layer between the active region shell layer and the first conductivity type semiconductor core. The method of claim 32, wherein: forming each of the first conductivity type semiconductor inner shell layers comprises forming an n-AlGaN shell layer having one of greater than 5% aluminum at a temperature lower than 850 ° C; forming the semiconductor foot Part comprising forming an n-AlGaN foot portion of the n-AlGaN shell layer; forming each second conductivity type semiconductor shell layer comprises forming a p-GaN shell layer; The n-AlGaN foot portion is connected to the n-AlGaN shell layer under the p-GaN outer shell layer and the active region shell layer. A semiconductor device comprising: a plurality of first conductivity type semiconductor nanowire cores over a support member; an insulating mask layer over the support member, wherein the nanowire cores comprise a portion of the epitaxially extending semiconductor nanowire exposed by the semiconductor surface of the support member through the opening in the insulating mask layer; a plurality of second conductivity type semiconductor shell layers above the respective nanowire cores And extending around the respective nanowire cores; a first electrode layer contacting the second conductivity type semiconductor shell layers and extending into a space between the semiconductor shell layers; and an insulating layer Located between the insulating mask layer and the first electrode in the spaces between the semiconductor shell layers. The device of claim 34, wherein the device comprises a light emitting diode (LED) device. The device of claim 35, further comprising a zone shell surrounding each of the plurality of nanowire cores. The device of claim 36, wherein the active region shell comprises at least one quantum well, and the second conductivity type semiconductor shell surrounds the at least one quantum well to surround each nanometer surrounded by at least one quantum well shell layer A luminescent pin junction is formed at the core. The device of claim 37, wherein: each of the semiconductor shell layers comprises a semiconductor foot portion extending over the insulating mask layer in the spaces between the semiconductor shell layers; An insulating layer is on the semiconductor foot portion such that the first electrode contacts the insulating layer and does not contact the foot portion. The device of claim 38, wherein: the second conductivity type semiconductor shell layer comprises a p-AlGaN inner shell layer having more than 5% aluminum, and a p-GaN outer shell layer; the semiconductor foot portion including the p-AlGaN layer One p-AlGaN foot portion of the inner shell layer; and the p-AlGaN foot portion is connected to the p-AlGaN inner shell layer below the p-GaN outer shell layer. The device of claim 37, further comprising a first conductivity type AlGaN shell layer having greater than 5% aluminum, wherein: the first conductivity type AlGaN shell layer is located in the active region shell layer and the plurality of nanowire lines Between each of the cores; the first conductivity type AlGaN shell layer includes one of the first in the space between the second conductivity type semiconductor shell layers on the insulating mask layer a conductive type AlGaN foot portion; the insulating layer is on the first conductive type AlGaN foot portion such that the first electrode contacts the insulating layer and does not contact the first conductive type AlGaN foot portion; the second The conductive type semiconductor shell layer includes a second conductive type GaN outer shell layer; and the first conductive type AlGaN foot portion is connected to the first under the second conductive type GaN outer shell layer and the active region shell layer Conductive type AlGaN shell layer. The device of claim 34, wherein the insulating layer comprises a spin-on dielectric. The device of claim 41, wherein the spin-on dielectric comprises a spin-on glass layer having a curved upper surface. The device of claim 40, wherein the first conductivity type comprises an n-type, the second guide The electrical type includes a p-type, and the first electrode layer includes a p-electrode layer. The device of claim 43, further comprising a second electrode layer electrically coupled to one of the n-type nanowire cores. The device of claim 44, wherein the support comprises an n-type semiconductor buffer layer on a substrate. The device of claim 45, wherein the buffer layer comprises an n-GaN or n-AlGaN layer, the nanowire core comprises an n-GaN nanowire, the at least one quantum well comprising an InGaN/GaN quantum well, and The first electrode includes a transparent conductive oxide (TCO). A method of fabricating a semiconductor device, comprising: partially epitaxially growing a plurality of first conductivity type semiconductor nanoparticles from a semiconductor surface of a support member through an opening in an insulating mask layer of the support member a core; a plurality of second conductivity type semiconductor shells formed over the individual nanowire cores and extending around the respective nanowire cores; the semiconductor shell layers over the insulating mask layer Forming an insulating layer in a space between the tips and sidewalls of the semiconductor shells exposed to the insulating layer; and forming a first electrode layer, wherein the first electrode layer contacts the semiconductor shell layer The at least upper portions of the tips and sidewalls are exposed, and the first electrode layer contacts the insulating layer in the spaces between the semiconductor shell layers. The method of claim 47, wherein the step of forming the insulating layer comprises spin coating a spin-on dielectric layer. The method of claim 48, wherein the thickness of the spin-on dielectric layer is greater above the insulating mask layer in the spaces between the semiconductor shell layers than on the sidewalls of the semiconductor shell layers. The method of claim 49, further comprising isotropically partially etching the spin-on dielectric layer to remove the spin-on dielectric from the at least upper portions of the sidewalls of the semiconductor shells and exposing the same The at least upper portions of the sidewalls of the semiconductor shell retain the spin-on dielectric layer in the spaces between the semiconductor shell layers. The method of claim 50, wherein the step of forming the plurality of second conductivity type semiconductor shell layers comprises forming substantially over the respective nanowire cores and extending around the respective nanowire cores a single crystal semiconductor shell portion and a polycrystalline semiconductor foot portion extending over the insulating mask layer in the spaces between the semiconductor shell layers; and the step of forming the first electrode layer includes Forming a continuous first electrode layer on the exposed tip of the semiconductor shell and at least the upper portion of the sidewalls and the insulating layer in the spaces between the semiconductor shells such that the first An electrode layer does not contact the polycrystalline semiconductor foot portions. The method of claim 51, wherein the step of forming the plurality of second conductivity type semiconductor shell layers each comprises forming a p-AlGaN inner shell layer having greater than 5% aluminum at a temperature lower than 850 ° C and Forming a p-GaN outer shell layer at a temperature higher than 850 ° C; the polycrystalline semiconductor foot portions including one of the p-AlGaN inner shell layers of polycrystalline p-AlGaN foot portions; and the p-GaN A cap layer is formed over the p-AlGaN inner cap layer and the p-AlGaN leg portions such that the p-AlGaN leg portions are connected to the respective p under the respective p-GaN cap layers -AlGaN inner shell layer. The method of claim 50, further comprising forming a first conductivity type AlGaN shell layer having greater than 5% aluminum between the shell layers of the respective active regions and the nanowire cores at a temperature lower than 850 °C. ,among them: The step of forming the first conductivity type AlGaN shell layer includes forming a portion of the substantially single crystal AlGaN shell layer over the respective nanowire cores and extending around the respective nanowire cores and at the insulation a first conductivity type polycrystalline AlGaN foot portion extending over the spaces between the second conductivity type semiconductor shell layers on the mask layer; and the step of forming the first electrode layer is included in the Forming the exposed tips of the second conductive type semiconductor shell layer and the at least upper portions of the sidewalls and the insulating layer in the spaces between the second conductive type semiconductor shell layers a continuous first electrode layer such that the first electrode layer does not contact the polycrystalline AlGaN foot portions; and the first conductive type polycrystalline AlGaN foot portions are in the respective second conductivity type shell layers And below the shell layers of the respective active regions are connected to the respective first conductive type AlGaN shell layers. The method of claim 50, wherein the insulating layer comprises a spin-on glass layer having a curved upper surface. The method of claim 54, further comprising forming an active region shell around each of the plurality of nanowire cores, wherein the device comprises a light emitting diode (LED) device. The method of claim 55, wherein the first conductivity type comprises an n-type, the second conductivity type comprises a p-type, and the first electrode layer comprises a p-electrode layer. The method of claim 56, further comprising electrically connecting to one of the second electrode layers of the n-type nanowire core. The method of claim 57, wherein the support comprises an n-type semiconductor buffer layer on the substrate, the buffer layer comprising an n-GaN or n-AlGaN layer, the nanowire core comprising an n-GaN nanowire The at least active region shell layer includes an InGaN/GaN quantum well, and the first electrode includes a transparent conductive oxide (TCO).