TW201507224A - Noble metal/non-noble metal electrode for RRAM applications - Google Patents

Abstract

A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Description

Precious metal/non-precious metal electrode for variable resistance memory [related application]

The present application claims priority to US Non-Provisional Patent Application No. 13/585,759, entitled "NOBLE METAL/NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS", which is incorporated by reference. All incorporated.

The present invention relates to a noble metal/non-precious metal electrode for use in a variable resistance memory.

The inventors of the present invention have recognized that the success of semiconductor devices is primarily achieved by a centralized transistor miniaturization process. However, when field effect transistors (FETs) are close to size less than 100 nm, physical problems such as short channel effects begin to interfere with normal device operation. For transistor-based memories, such as the well-known flash memory, other performance impairments or problems may occur as the device size becomes smaller. For flash memory, high voltages are often required for such memory programming, however, as device sizes become smaller, high programming voltages can cause dielectric breakdown and other problems. Similar problems can occur with other types of non-volatile memory devices other than flash memory.

The inventors of the present invention have recognized that many other types of non-volatile random access memory devices have been developed as next-generation memory devices, such as ferroelectric random access memory, magnetoresistive random access memory, organic Random access memory, phase change random access memory, and others.

A common disadvantage of these memory devices involves new materials that they typically need to be incompatible with conventional CMOS processes. For example, organic random access memories require organic compounds that are currently incompatible with large-scale, germanium-based manufacturing techniques and manufacturing. Other materials such as ferroelectric random access memory and magnetoresistive random access memory typically require materials that use a high temperature annealing step, and such devices are generally not integrated with large size germanium based fabrication techniques.

An additional disadvantage of these devices is that such memory cells typically lack the key characteristics required for one or more non-volatile memories. For example, ferroelectric random access memory and magnetoresistive random access memory generally have fast switching (ie, "0" to "1") characteristics and good programming tolerance. However, such memory is difficult to use. Shrinked to a small size. Taking an organic random access memory device as an example, the reliability of such a memory is generally poor. As another example, phase change random access memory typically includes Joule heating and undesirably requires high energy losses.

Based on the above, new semiconductor device structures and integrations are required.

The present invention relates to an impedance switching device. More specifically, embodiments are directed to methods and apparatus for controlling oxygen levels in impedance switching devices in accordance with embodiments of the present invention. Embodiments in accordance with the present invention may be used in non-volatile memory devices but it will be appreciated that the invention may have a broader range of applications.

In a specific embodiment, a method for forming a non-volatile memory device includes forming a bottom metal electrode; forming a bonding layer in electrical contact with a bottom metal electrode, the conductive layer containing a conductive material (eg, p-doped a heteropolycrystalline germanium, a p-doped germanium germanium, or the like; and a switching layer formed on the bonding layer having an undoped amorphous germanium-containing material (eg, undoped amorphous germanium, undoped SiOx, SixGeyOz, wherein x, y, and z are integers, etc.) In a particular embodiment, a non-precious metal material (eg, titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, tungsten nitride, nitride) a barrier layer of aluminum, copper, copper alloy, or the like is formed on the switching layer; an active layer containing a noble metal material such as silver, gold, platinum, palladium, or the like is formed on the barrier layer; Another barrier layer (top layer) is formed on the active layer. Thereafter, a top metal electrode is formed in electrical contact with the top layer and the active layer.

In various embodiments, the just-plated or newly formed layer is arranged to receive oxygen and oxygen Chemical. As an example, the non-noble metal material used for this layer is titanium, and when titanium receives oxygen, it is converted to titanium dioxide, or other titanium oxidation state. Oxygen used to oxidize titanium may be directed from the switching layer, the active layer, or from any other source (eg, from the atmosphere) via diffusion through the switching layer, the active layer, or the like. In the oxidized state, the layer can have a thickness ranging from about 2 nm to about 3 nm.

In accordance with an aspect of the invention, a method of forming a non-volatile memory device is described. A process comprising depositing a bonding layer comprising a doped germanium-containing material in electrical contact with a first conductive material; and forming a switching layer comprising an undoped amorphous germanium-containing material in at least one of the bonding layers Part of it. A technique includes disposing a barrier layer comprising a non-precious metal material over at least a portion of the switching layer and disposing an active metal layer comprising a noble metal material over at least a portion of the barrier layer. A method can include forming an additional barrier layer on top of the active metal layer and subsequently electrically contacting the second conductive material with the active metal layer.

According to another aspect of the invention, a non-volatile memory device is described. A device may include a bonding layer containing a doped germanium-containing material in electrical contact with a first conductive material; and a switching layer containing an undoped amorphous germanium-containing material formed on the bonding layer Part of it. A memory may include a first layer comprising a precious metal disposed on at least a portion of the switching layer, a second conductive material electrically coupled to the first layer, and a layer comprising an oxidized state comprising a non-noble metal material. Between at least a portion of the first layer and at least a portion of the switching layer.

Many benefits can be achieved by the means of the present invention. For example, embodiments in accordance with the present invention provide a method for increasing the performance of a non-volatile memory device, such as device reliability, device off state current consistency, device thickness uniformity, device retention, and the like. This method uses conventional semiconductor devices and techniques without adjustment. According to an embodiment, one or more of these advantages can be achieved. Other variations, adjustments, and alternatives will be apparent to those skilled in the art.

102‧‧‧Semiconductor substrate

104‧‧‧Surface area

202‧‧‧Semiconductor substrate

302‧‧‧First wiring material

304‧‧‧First Adhesive Material

306‧‧‧Diffuse barrier material

402‧‧‧Material materials

502‧‧‧ Impedance switching material

600‧‧ layers

602‧‧‧Active conductive materials

702‧‧‧Diffuse barrier material

802‧‧‧hard mask material

902‧‧‧pattern layer

1202‧‧‧column structure

1302‧‧‧ dielectric materials

1304‧‧‧Surface area

1306‧‧‧Flat surface

1402‧‧‧Second wiring material

For a more complete understanding of the invention, reference is made to the accompanying drawings. It should be understood that such figures are not necessarily to scale and are not considered as limiting. The 30 embodiments described and the invention can be best understood by using the following illustrations by means of additional details, wherein: 1 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 2 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 3 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 5 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 6 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; The figure shows program steps in accordance with various embodiments of the present invention; Figure 8 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 9 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 10 is a simplified diagram display The program steps are in accordance with various embodiments of the present invention; Figure 11 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 12 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; and Figure 13 is a diagram showing performance data. According to various embodiments of the invention.

The impedance switching device is guided according to an embodiment of the invention. More specifically, methods are provided in accordance with embodiments of the present invention to form a silver structure for impedance switching devices. This method is applied to the fabrication of non-volatile memory devices, but it will be appreciated that embodiments in accordance with the present invention may have a broader range. application.

For an impedance switching device using amorphous germanium as a switching material, a metal material is used as an electrode of at least one of them. The impedance of the amorphous germanium material is changed. According to one or more conductor particles derived from the conductor electrode, the voltage difference between the electrodes is shown in FIGS. 1 to 12, which shows an impedance switching device for forming a memory device according to various embodiments of the present invention. method. As shown in FIG. 1, a semiconductor substrate 102 having a surface region 104 is provided. The semiconductor substrate 102 may be a single crystal germanium wafer, a germanium material, or a germanium on insulator (commonly referred to as SOI), depending on the embodiment. In a particular embodiment, semiconductor substrate 202 can have one or more MOS devices formed thereon or therein. The one or more MOS devices may be control circuits for impedance switching devices, or the like, in some embodiments.

As shown in FIG. 2, an embodiment of the method includes depositing a first dielectric material 202 on a semiconductor substrate 102. The first dielectric material 202 can be a dielectric stack of selected layers of hafnium oxide, tantalum nitride, hafnium oxide, and tantalum nitride (eg, an ONO stack), low K dielectric, high K dielectric, or a combination thereof, And others, depending on the application. The first dielectric material 202 can be deposited using techniques such as chemical vapor deposition, including low pressure chemical weather deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, atomic layer deposition (ALD). ), physical vapor deposition techniques, including any combination of these, and others.

As shown in FIG. 3, an embodiment of the method includes depositing a first wiring material 302 on the first dielectric material. The first wiring material 302 can be a suitable metal material comprising a metal alloy, or a semiconductor material having suitable conductive properties. In some embodiments, the metallic material can be tungsten, aluminum, copper, or silver, among others. In various embodiments, these metallic materials can be deposited using physical vapor deposition procedures, chemical vapor deposition procedures, electroplating, or electroless deposition processes, any combination of these, and others. In some embodiments, the semiconductor material can be, for example, a p-type doped germanium material, a conductive polysilicon, or the like.

In a particular embodiment, a first adhesive material 304 is first formed on the first dielectric material 202 prior to deposition of the first wiring material 302 to optimize adhesion of the first wiring material 302 to the first dielectric material 202. In a particular embodiment, a diffusion barrier material 306 can also be formed over the first wiring material 302 to prevent, for example, conductive materials, metallic materials, gases, oxygen, or the like from contaminating other portions of the device.

As shown in FIG. 4, the method includes forming a bonding material 402 on at least the first wiring material 302 (or the first diffusion barrier material 306, if used). In a particular embodiment, the first bonding material 402 can be a p-doped germanium-containing material (eg, p++ polycrystalline germanium, p-doped germanium, or the like). The p++ polycrystalline germanium can be formed by using a deposition procedure such as low pressure chemical weather deposition, plasma enhanced chemical vapor deposition depending on the application using methane or dioxane or a suitable chlorodecane. Alternatively, the first tantalum material can be deposited using a physical vapor deposition process from a suitable tantalum target. The deposition temperature can range from about 380 ° C to about 450 ° C, and preferably does not exceed 440 ° C. In a particular embodiment, the p++ polysilicon material is deposited using a low pressure chemical vapor deposition process using a decane at a deposition temperature of between about 400 °C and about 460 °C.

As shown in FIG. 5, the method deposits an impedance switching material 502 at the bonding material. 402. The impedance bonding material 502 can be a germanium material. The tantalum material may be an amorphous tantalum material or a polycrystalline germanium material and the like, by way of example. In a particular embodiment, the impedance switching material 502 comprises an amorphous germanium material. The switching material is defined by a state, for example, an impedance state is attached to an electric field in the switching material. In a particular embodiment, the switching material is an amorphous germanium material. Impedance switching material 502 has substantially true semiconductor characteristics in a particular embodiment and is not intended to be doped. In various embodiments, amorphous germanium is also referred to as amorphous germanium. The amorphous 矽 non-volatile impedance switching device can be fabricated using existing CMOS technology.

Deposition techniques may include chemical vapor deposition procedures, physical vapor deposition procedures, atomic layer vapor deposition procedures, and others. Chemical vapor deposition can be low pressure chemical weather deposition, plasma enhanced chemical vapor deposition, use of precursors such as methane or dioxane or suitable chlorodecane in a reducing environment, combinations thereof, or others. The deposition temperature can range from 250 °C to about 500 °C. In some cases, the deposition temperature ranges from about 400 °C to about 440 °C and no more than about 450 °C. In an exemplary procedure, monodecane (45 sccm) and ruthenium (500 sccm) were used to form an a-Si layer by a deposition rate of 80 nm per minute in a PECVD process (temperature 260 ° C, pressure 600 mTorr). In another exemplary procedure, decane (190 sccm) and ruthenium (100 sccm) were used to form an a-Si layer by a deposition rate of 2.8 A per minute in a PECVD process (temperature 380 ° C, pressure 2.2 Torr) ). In another exemplary procedure, decane (80 sccm) or dioxane was used to form an a-Si layer by a deposition rate of 2.8 nm per minute in a LPCVD procedure (temperature 585 ° C, pressure 100 mTorr). Part of the polycrystalline germanium particles can be formed in the LPCVD process and cause an amorphous polycrystalline germanium. In various embodiments, no p-type, n-type, or metal impurities are intentionally added to the deposition chamber when forming an amorphous germanium material. Accordingly, the amorphous germanium material does not substantially have any p-type, n-type, or metal impurities during deposition, that is, the amorphous germanium material is undoped.

In various embodiments, the thickness of the amorphous germanium material is typically in the range of from about 10 nm to about 30 nm. In other embodiments, other thicknesses may be employed depending on the particular performance characteristics desired (eg, switching voltage, retention characteristics, current, or the like).

In another embodiment, the impedance switching material 502 can form an upper region of the bonding material 402 (eg, a p+ poly germanium containing layer) (eg, away from the first wiring layer 302). In various embodiments, the exposed surface of bonding material 402 is plasma etched using argon, helium, oxygen, Or a combination thereof to affect the amorphization of the bonding material 402 and the upper region. In some examples, plasma etching can use a bias voltage ranging from approximately 30 watts to approximately 120 watts to convert an upper region of bonding material 402 into impedance switching material 502.

In some specific cases, when the bonding material 402 is a doped polysilicon material, the amorphization process creates an SiOx material for the impedance switching material 502. In other specific cases, when the bonding material 402 is a doped germanium material, the amorphization process creates a SixGeyOz (x, y, z is an integer) material for the impedance switching material 502. In some examples, the resulting impedance switching material 502 can have a thickness ranging from approximately 2 nm to approximately 5 nm. In other embodiments, other thicknesses are considered, depending on the particular engineering requirements.

As shown in FIG. 6, in various embodiments, the method includes depositing a layer 600, which may be a barrier layer, on the impedance switching material 502. In various embodiments, the barrier layer 600 can be specifically a non-noble metal such as titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, tungsten nitride, aluminum nitride, copper, copper alloy, or the like. By. Non-noble metals are used to oxidize, absorb and lock oxygen. As an example, if layer 600 is titanium, titanium is oxidized to form titanium oxide, or other non-conductive layer.

In some embodiments, layer 600 can have a thickness that is just deposited ranging from approximately 1 nm to approximately 5 nm, and after oxidation, layer 600 can have a slightly greater thickness. As an example, layer 600 can be increased from a 2.5 nm just deposited thickness to a 3 nm oxidized thickness.

In various embodiments, the source of oxygen may be from any number of sources, including atmospheric oxygen after formation of layer 600; oxygen is present in impedance switching material 502 during or after formation; oxygen is present after formation of impedance switching material 502 Active conductive material 602 (described below); oxygen diffuses through active conductive material 602 formed after impedance switching material 502; or the like.

In some embodiments, oxidation of barrier layer 600 does not necessarily occur at any particular time in the process. Conversely, in various embodiments, when oxygen from any source reaches layer 600, the non-precious metal may oxidize. Thus, as an example, in a manufacturing lot, if a long delay is formed after layer 600 is formed until a subsequent layer is formed, oxidation may occur during this delay; in another manufacturing lot, if there is a long delay in the continuation Active conductive material 602 is formed over layer 600 and when a diffusion barrier material 702 (described below) is formed, oxidation may occur during this delay; or Like.

In various embodiments, it is presently believed that once the non-noble metal material in layer 600 is oxidized, it provides additional protection for subsequent diffusion of oxygen down to switching material 502. For example, if layer 600 is originally a titanium nitride material, the oxynitride material prevents oxygen from diffusing from active conductive material 602 into switching material 502 after oxidation.

In some embodiments, these oxide layers may be detrimental to preventing diffusion of the conductive material of the active conductive material 602, as described below, to the impedance switching material 502.

As shown in FIG. 6, in some embodiments, the method includes depositing an active conductive material 602 on layer 600. The active conductive material 602 may be a noble metal material such as silver, gold, platinum, palladium, alloys thereof, or others. The active conductive material 602 is specific to a particular embodiment in which an appropriate electric field exists in the impedance switching material in an electric field. For the amorphous germanium material as the impedance switching material 502, the metal material may be silver or a silver alloy. In some examples, the silver alloy contains at least 80% silver.

In some embodiments, the active conductive material 602 is silver, the silver metal pierces the layer 600 and forms a silver region in the portion of the switching material 502 (eg, amorphous germanium material, SiOx, SixGeyO, or the like) in the electric field. Do it. The silver region comprises a plurality of silver particles comprising silver ions, silver clusters, silver atoms, or a combination thereof. In a particular embodiment a plurality of silver particles are formed at the defect location of the switching material. The silver region further comprises a silver filamentous structure extending from the source of metal (active conductive material 602), such as silver/silver ions, to the first wiring material 302.

In various embodiments, the filamentary structure is specified to be long, the distance between the silver particles, and the distance between the filamentary structure and the first electrode structure. In a particular embodiment, the impedance switching material 502 (eg, amorphous germanium material, SiOx, SixGeyOz) is specifically characterized by an impedance based at least on a length, a length between silver particles, and a filamentary structure and first electrode structure (first The length between the wiring materials 302). In some cases, the missing density is high in the interface region formed from the amorphous germanium material (eg, switching material 502) and the first wiring material (eg, first wiring material 302) due to material mismatch, which may cause a short circuit . In a particular embodiment, the bonding layer (e.g., bonding material 402) (e.g., p+ complex crystalline germanium material) controls the defect density of the interface for proper switching performance of the impedance switching device.

In some embodiments, the silver material is in direct contact with the particular embodiment as The amorphous material of the impedance switching material. In other embodiments, a thin layer of material, such as an oxide, a nitride, is formed prior to deposition of the silver material on top of the amorphous germanium as the impedance switching material. A thin layer of the inserted material may be naturally or intentionally grown or formed. In some embodiments, one or more etching operations (eg, HF etching, argon etching) can help control the thickness of this layer. In some embodiments, the thickness of the material (eg, oxide, nitride) prior to deposition of the silver material can range from about 20 A to about 50 A; in other embodiments, the thickness can range from about 30 A to about 40 A; Similar.

In some embodiments, an additional layer of amorphous germanium may be disposed on top of a thin layer (eg, oxide, nitride) prior to deposition of the silver material. An additional layer of this amorphous germanium (unintentionally doped) can be used to help secure the silver material to a thin layer of material (eg, oxides, nitrides, barriers). In some embodiments, the thickness can be between 20 and 50 amps. In one example, the order of the layers can be: undoped amorphous germanium used as an impedance switching material, a thin layer of a material (eg, oxide, nitride, barrier), an amorphous tantalum, and silver material.

In another embodiment, layer 600 and active conductive material 602 can be formed in the same deposition step. For example, a mixture of precious metal or non-precious metal materials can be deposited in a single step, alternating layers of precious metal and non-precious metal materials can be deposited in a plurality of steps, or the like. In various embodiments, the percentage of non-noble metal relative to the precious metal material may vary, for example, the percentage may vary from about 0.1% to about 10%, or the like. It is believed that the non-precious metal material will also be oxidized in this mixture and reduce the amount of oxygen reaching or presenting the switching material 502.

As shown in FIG. 7, the method includes forming a second diffusion barrier material 702 on the active conductive material 602. For silver as the active conductive material 602, the second diffusion barrier layer 702 can be a non-noble metal such as titanium, titanium nitride material, tungsten, or the like. The second diffusion barrier material 702 can form a titanium or tungsten target material by a physical vapor deposition process. A nitride material can be formed using a physical vapor deposition process, or a chemical vapor deposition process or an atomic layer deposition process or by reacting nitrogen with a titanium material.

In various embodiments, the second diffusion barrier material 702 is formed a short time after the travel of the active conductive material 602. As an example, this short time can be less than 10 minutes, 20 minutes, 1 hour, 4 hours or the like. In some examples, this short time is defined as less than or equal to one day. At a specific short time, atmospheric oxygen is prevented from being absorbed into the active conductive material. Material 602 and/or moved to impedance switching material 502, layer 600 (eg, interface between active conductive material 602 level impedance switching material 502), or the like.

In other embodiments, to reduce the amount of oxygen absorbed or contained by the impedance switching material 502 or the active conductive material 602, the partially completed device is placed in an oxygen reducing environment (eg, substantially oxygen free) for a brief period of time. After the active conductive material 602 is deposited. In some embodiments, this brief time can be less than 15 minutes, 30 minutes, 2 hours, 4 hours, or the like. In some examples, this short time is defined as less than or equal to one day. In various embodiments, the partially completed device is placed in an oxygen reducing environment (e.g., substantially oxygen free) until the second diffusion barrier (cover) material 702 is deposited. In a particular embodiment, the method includes forming a hard masking material 802 on the second diffusion barrier material 702 as shown in FIG. The hard mask material 802 can be a dielectric material, a metal material, a semiconductor material, or the like, depending on the application. In a particular embodiment, the hard mask material can be a dielectric material such as tantalum oxide, tantalum nitride, tantalum oxide, and tantalum nitride dielectric stack (eg, ONO stack), high K dielectric, low K dielectric ,and others.

In various embodiments, the hard dielectric material 802 is used in a first patterning and etching process to form a pattern layer 902 as shown in FIG. The first patterning and etching process can include depositing a photoresist layer on the hard mask material, patterning the photoresist material, and etching the hard mask material using the patterned photoresist material. In other embodiments, Other conventional forms of etching are expected.

As shown in FIG. 10, the method includes using the hard mask 902 as a mask layer to perform one or more stacks of materials including the diffusion barrier material 702, the active conductive material 602, the layer 600, the impedance switching material 502, the bonding material 402, and the like. The etching process is performed to form a columnar structure 1202. In various embodiments, the impedance memory device is formed from active conductive material 602, layer 600, impedance switching material 502, and bonding material 402.

The method then removes the dielectric hard mask material remaining after the aforementioned etching process and forms a dielectric material 1302 on each of the first structures and fills the gap between the first structures as shown in FIG. Dielectric material 1302 can be a dielectric stack of hafnium oxide, tantalum nitride, hafnium oxide, and tantalum nitride (eg, an ONO stack), a high K dielectric, a low K dielectric, and others. The dielectric material 1302 can be deposited using, for example, a chemical vapor deposition process, including a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, and the like, Depending on the application. Dielectric material 1302 can be further planarized to expose the barrier (or A surface region 1304 of the material (e.g., 702) is covered to isolate each of the first structures and form a planarized surface 1306, as shown in FIG.

As shown in FIG. 12, a second wiring material 1402 is formed over the planarized surface and surface region 1304 of the dielectric material 1302, or the like. The second wiring material 1402 may be a metal material such as copper, tungsten, aluminum, and others. The second wiring material 1402 can also be a suitably doped semiconductor material such as a doped flip chip material and the like, depending on the application.

A second wiring material 1402 is used for the patterning and etching process to form one or more second wiring structures. The one or more second wiring structures are elongated in shape and shaped to extend in a first direction orthogonal to the first direction of the first wiring structure. Moreover, in a particular embodiment at least the impedance switching unit is formed in an intersection region of the first wiring structure and the second wiring structure. The method can further include forming a passivation layer and a ball interconnect for the memory device, among others to complete the device.

In other embodiments, other configurations and structures are contemplated for non-volatile memory structures. In one example, a layer of tantalum is deposited followed by a layer of germanium dioxide. An opening is then opened and the upper surface of the crucible is amorphized to form an amorphous layer. In some embodiments, this layer has a thickness of approximately 2 to approximately 3 nm. In some embodiments, for example, the process can be performed in a single argon plasma etch step. In other embodiments, the upper surface of the crucible can be amorphized prior to the deposition of the hafnium oxide. Subsequently, layers of titanium, silver, and/or tungsten are deposited. At some time during the process, or otherwise, the bottom titanium layer absorbs oxygen and oxidizes to titanium oxide, or other non-conductive layers. In some embodiments, the oxide layer has a thickness of approximately 3 to approximately 4 nm.

Figure 13 shows a representation of performance data in accordance with various embodiments of the present invention. More specifically, Figure 13 shows some of the advantages of the formed non-volatile memory device after multiple side-by-side procedures and elimination cycles. A particular advantage is the consistent stability of this memory device over a number of different cycles.

As another example, in an embodiment, the bonding layer 402 and the switching layer 502 may be formed such that the columnar structure is surrounded by the oxide layer. Subsequently, layer 600, active conductive material 602, and the like are deposited and contact the upper surface of the columnar structure.

While the foregoing description and drawings have disclosed the preferred embodiments of the invention The spirit and scope of the principles of the invention as defined by the appended claims. Modifications of many forms, structures, arrangements, ratios, materials, components and components can be made by those skilled in the art to which the invention pertains. Therefore, the embodiments disclosed herein are to be considered as illustrative and not restrictive. The scope of the present invention is defined by the scope of the appended claims, and the legal equivalents thereof are not limited to the foregoing description.

102‧‧‧Semiconductor substrate

202‧‧‧Semiconductor substrate

302‧‧‧First wiring material

304‧‧‧First Adhesive Material

306‧‧‧Diffuse barrier material

1302‧‧‧ dielectric materials

1402‧‧‧Second wiring material

Claims (20)

A method of generating a non-volatile memory device, comprising: depositing a bonding layer comprising a doped germanium-containing material, electrically contacting a first conductive material; forming an undoped amorphous germanium-containing material The switching layer is over at least a portion of the bonding layer; a layer comprising a non-precious metal material is disposed over at least a portion of the switching layer; and an active metal layer comprising a noble metal material is disposed on the layer a portion above; and forming a second conductive material in electrical contact with the active metal layer. The method of claim 1, wherein the non-precious metal material is selected from the group consisting of titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, tungsten nitride, aluminum nitride, copper, copper alloy or a composition thereof. Things. The method of claim 1, wherein the precious metal material is selected from the group consisting of silver, gold, platinum, palladium or a composition thereof. The method of claim 1 wherein the layer comprises an adhesive layer having a thickness ranging from about 2 nm to about 4 nm. The method of claim 1, wherein at least a portion of the non-precious metal material is oxidized to an oxidation state of the non-precious metal material to form an oxide layer after the active metal layer is disposed over the layer. The method of claim 5, wherein the oxide layer has a thickness ranging from about 2 nm to about 3 nm. The method of claim 5, wherein the oxygen used to oxidize a portion of the non-precious metal material is derived from the active metal layer. The method of claim 5, wherein the non-precious metal material comprises a titanium-containing material; wherein the oxidation state of the non-precious metal material comprises titanium oxide; and wherein the noble metal comprises a silver-containing material. The method of claim 1, wherein the doped germanium-containing material comprises a p-doped polysilicon material; and wherein forming the switching layer comprises forming an undoped amorphous germanium-containing material in the p-doped polysilicon material Part of the top. The method of claim 9, wherein the switching layer has a thickness ranging from about 10 nm to about 30 nm. The method of claim 1, wherein the bonding layer comprises an upper region; and wherein the method further comprises the upper region of the bonding layer An amorphization process is performed to form the undoped amorphous germanium-containing material. The method of claim 11, wherein the switching layer has a thickness ranging from about 2 nm to about 5 nm. The method of claim 12, wherein the doped germanium-containing material is selected from the group consisting of doped telluride telluride, doped polysilicon, p-doped germanium telluride, p-doped polysilicon or a composition thereof. A non-volatile memory device formed according to the method of claim 13. A non-volatile memory device comprising: a bonding layer comprising a doped germanium-containing material electrically contacting a first conductive material; and a switching layer comprising an undoped amorphous germanium-containing material formed in Overlying at least a portion of the bonding layer; a first layer comprising a precious metal material over at least a portion of the switching layer; a second conductive material in electrical contact with the first layer; and a A layer of a non-noble metal material in an oxidized state is formed between at least a portion of the first layer and at least a portion of the switching layer. The non-volatile memory device of claim 15 wherein the oxidation state of the non-noble metal material is deposited as a non-oxidized state of the non-noble metal material on the switching layer. The non-volatile metal material according to claim 15, wherein the non-precious metal material comprises an adhesive material; wherein the non-precious metal material is selected from the group consisting of titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, and nitrogen. Tungsten, aluminum nitride, copper, copper alloy or a composition thereof. The non-volatile memory device of claim 15, wherein the precious metal material is selected from the group consisting of silver, gold, platinum, palladium or a composition thereof. The non-volatile memory device of claim 15, wherein the undoped amorphous germanium-containing material is selected from the group consisting of SiOx, SixGeyOz, or a composition thereof, wherein x, y, and z are integers; and wherein the switching layer has A thickness ranges from about 2 nm to about 5 nm. The non-volatile memory device of claim 15 wherein the layer has a thickness ranging from about 2 nm to about 3 nm.