TW201506938A - Data storage device and voltage protection method thereof - Google Patents
Data storage device and voltage protection method thereof Download PDFInfo
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- TW201506938A TW201506938A TW102148612A TW102148612A TW201506938A TW 201506938 A TW201506938 A TW 201506938A TW 102148612 A TW102148612 A TW 102148612A TW 102148612 A TW102148612 A TW 102148612A TW 201506938 A TW201506938 A TW 201506938A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
Description
本發明係關於一種記憶體裝置之電壓保護方法；特別係關於一種根據供應電壓進行電壓保護的方法。 The present invention relates to a voltage protection method for a memory device; and more particularly to a method for voltage protection based on a supply voltage.
快閃記憶體為一種普遍的非揮發性資料儲存裝置，係以電性方式抹除與程式化。以非及閘型的快閃記憶體(即NAND FLASH)為例，常用作記憶卡(memory card)、通用序列匯流排閃存裝置(USB flash device)、固態硬碟(SSD)、嵌入式快閃記憶體模組(eMMC)…等使用。 Flash memory is a popular non-volatile data storage device that is electrically erased and programmed. For example, NAND FLASH, which is not a gate type, is often used as a memory card, a universal flash memory device, a solid state drive (SSD), and an embedded flash. Memory module (eMMC)...etc.
快閃記憶體(如，NAND FLASH)的儲存陣列包括複數個區塊(blocks)，其中浮置閘極電晶體可用以構成快閃記憶體。浮置閘極電晶體中之浮置閘極，可捕捉的電荷以儲存資料。然而，儲存於浮置閘極之電荷會由於快閃記憶體之操作以及各種環境參數，自浮置閘極流失，造成資料讀取或者寫入的錯誤。 A flash memory (eg, NAND FLASH) storage array includes a plurality of blocks, wherein a floating gate transistor can be used to form a flash memory. A floating gate in a floating gate transistor that captures charge to store data. However, the charge stored in the floating gate may be lost from the floating gate due to the operation of the flash memory and various environmental parameters, resulting in errors in data reading or writing.
本發明提供一種資料儲存裝置包括一快閃記憶體、一電壓判斷裝置以及一控制器。快閃記憶體用以儲存資料。電壓判斷裝置用以偵測資料儲存裝置所接收的一供應電壓。控制器用以接收來自一主機用以致使控制器對快閃記憶體 進行寫入之一寫入命令，以及當供應電壓超過一既定範圍時，執行一限制模式，其中在限制模式中，控制器禁能所有自主機接收的寫入命令。在另一實施例中，控制器更用以接收來自主機用以致使控制器對快閃記憶體進行讀取之一讀取命令，以及在限制模式中，控制器禁能所有自主機接收的讀取命令。 The invention provides a data storage device comprising a flash memory, a voltage judging device and a controller. Flash memory is used to store data. The voltage determining device is configured to detect a supply voltage received by the data storage device. The controller is configured to receive from a host to cause the controller to flash the memory A write command is written, and when the supply voltage exceeds a predetermined range, a limit mode is executed, wherein in the limit mode, the controller disables all write commands received from the host. In another embodiment, the controller is further configured to receive a read command from the host to cause the controller to read the flash memory, and in the restricted mode, the controller disables all reads received from the host Take the command.
另外，當供應電壓超過既定範圍時，控制器更用以產生一警告訊號，並將警告訊號傳送至主機，以表示禁止對快閃記憶體進行存取之資訊。在一實施例中，控制器更用以每隔一既定週期，讀取電壓判斷裝置以獲得相應於當下之供應電壓。控制器更用以當所讀取之供應電壓超過既定範圍時，啟動限制模式，並且用以當所讀取之供應電壓在既定範圍內時，關閉限制模式。 In addition, when the supply voltage exceeds the predetermined range, the controller is further configured to generate a warning signal and transmit the warning signal to the host to indicate that the access to the flash memory is prohibited. In an embodiment, the controller is further configured to read the voltage determining means to obtain a current supply voltage corresponding to the current cycle. The controller is further configured to activate the limit mode when the read supply voltage exceeds a predetermined range, and to turn off the limit mode when the read supply voltage is within a predetermined range.
本發明亦提供一種電壓保護方法，適用於具有一快閃記憶體之一資料儲存裝置。存取方法包括：判斷資料儲存裝置所接收之一供應電壓是否超過一既定範圍；以及當供應電壓超過既定範圍時，開啟一限制模式，以禁能所有自一主機接收用以對快閃記憶體進行寫入的至少一寫入命令。在另一實施例中，電壓保護方法更包括在限制模式中，禁能所有自主機接收用以對快閃記憶體進行讀取的至少一讀取命令。在另一實施例中，電壓保護方法更包括每隔一既定週期，讀取一電壓判斷裝置以獲得相應於當下之供應電壓；當供應電壓超過既定範圍時，產生一警告訊號；以及將警告訊號傳送至主機，以表示禁止對快閃記憶體進行存取之資訊，其中當所讀取之供應電壓在既定範圍內時，關閉限制模式。 The invention also provides a voltage protection method suitable for a data storage device having a flash memory. The access method includes: determining whether a supply voltage received by the data storage device exceeds a predetermined range; and when the supply voltage exceeds a predetermined range, opening a limit mode to disable all receiving from a host for flash memory At least one write command to write. In another embodiment, the voltage protection method further includes disabling, in the restricted mode, all at least one read command received from the host to read the flash memory. In another embodiment, the voltage protection method further includes: reading a voltage judging device to obtain a corresponding supply voltage every other predetermined period; generating a warning signal when the supply voltage exceeds a predetermined range; and applying a warning signal Transferred to the host to indicate that access to the flash memory is prohibited, wherein the limited mode is turned off when the read supply voltage is within a predetermined range.
100‧‧‧電子系統 100‧‧‧Electronic system
120‧‧‧主機 120‧‧‧Host
140‧‧‧資料儲存裝置 140‧‧‧Data storage device
160‧‧‧控制器 160‧‧‧ Controller
162‧‧‧運算單元 162‧‧‧ arithmetic unit
164‧‧‧永久記憶體 164‧‧‧Permanent memory
165‧‧‧隨機存取記憶體 165‧‧‧ random access memory
180‧‧‧快閃記憶體 180‧‧‧Flash memory
190‧‧‧電壓判斷裝置 190‧‧‧Voltage judging device
S202~S212‧‧‧步驟 S202~S212‧‧‧Steps
第1圖係本發明之一種實施例之電子系統之方塊圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an electronic system in accordance with one embodiment of the present invention.
第2圖係本發明之一種實施例之電壓保護方法之流程圖。 2 is a flow chart of a voltage protection method of an embodiment of the present invention.
以下將詳細討論本發明各種實施例之裝置及使用方法。然而值得注意的是，本發明所提供之許多可行的發明概念可實施在各種特定範圍中。這些特定實施例僅用於舉例說明本發明之裝置及使用方法，但非用於限定本發明之範圍。 The apparatus and method of use of various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are only intended to illustrate the apparatus and methods of use of the present invention, but are not intended to limit the scope of the invention.
第1圖係本發明之一種實施例之電子系統之方塊圖。電子系統100包括一主機120以及一資料儲存裝置140。資料儲存裝置140包括一控制器160、一快閃記憶體180以及一電壓判斷裝置190，且可根據主機120所下達的命令操作。控制器160包括一運算單元162、一永久記憶體(如，唯讀記憶體ROM)164以及一隨機存取記憶體165。永久記憶體164與所載之程式碼、資料組成韌體(firmware)，由運算單元162執行，使控制器160基於該韌體控制該快閃記憶體180。舉例而言，控制器160可根據主機120之命令執行對快閃記憶體180進行存取，以及自動執行本發明所揭露之電壓保護方法。快閃記憶體180具有複數區塊，每一區塊具有複數頁面。值得注意的是，在其他實施例中，控制器160更可包括一計時裝置(未圖示)，計算時間，但本發明不限於此。舉例而言，控制器160亦可根據所接收或者自己產生之時脈計算時間。電壓判斷裝置190用以偵測供應電壓VDD，以產生隨著供應電壓VDD變化之電壓參數。值 得注意的是，在本實施例中，電壓判斷裝置190系用以偵測提供至快閃記憶體180之供應電壓VDD。換言之，快閃記憶體180的電源係由供應電壓VDD所提供的，並且快閃記憶體180係藉由供應電壓VDD對資料進行存取，但本發明不限於此。在其他實施例中，電壓判斷裝置190亦可以偵測提供至控制器160之供應電壓VDD。換言之，控制器160的電源係由供應電壓VDD所提供的，並且控制器160係藉由供應電壓VDD致使快閃記憶體180對資料進行存取。在本發明之另一實施例中，電壓判斷裝置190亦可同時分別偵測提供至快閃記憶體180以及控制器160之供應電壓VDD，其中快閃記憶體180以及控制器160之供應電壓VDD可為不同之電壓源，並具有不同之既定範圍。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an electronic system in accordance with one embodiment of the present invention. The electronic system 100 includes a host 120 and a data storage device 140. The data storage device 140 includes a controller 160, a flash memory 180, and a voltage determining device 190, and is operable according to commands issued by the host 120. The controller 160 includes an arithmetic unit 162, a permanent memory (e.g., read only memory ROM) 164, and a random access memory 165. The permanent memory 164 and the stored code and data constitute a firmware, which is executed by the operation unit 162, so that the controller 160 controls the flash memory 180 based on the firmware. For example, the controller 160 can perform access to the flash memory 180 according to the command of the host 120, and automatically perform the voltage protection method disclosed in the present invention. Flash memory 180 has a plurality of blocks, each block having a plurality of pages. It should be noted that in other embodiments, the controller 160 may further include a timing device (not shown) to calculate the time, but the invention is not limited thereto. For example, the controller 160 can also calculate the time based on the received or self-generated clock. The voltage determining device 190 is configured to detect the supply voltage VDD to generate a voltage parameter that varies with the supply voltage VDD. value It should be noted that in the present embodiment, the voltage determining device 190 is configured to detect the supply voltage VDD supplied to the flash memory 180. In other words, the power of the flash memory 180 is supplied from the supply voltage VDD, and the flash memory 180 accesses the material by the supply voltage VDD, but the present invention is not limited thereto. In other embodiments, the voltage determining device 190 can also detect the supply voltage VDD supplied to the controller 160. In other words, the power of the controller 160 is provided by the supply voltage VDD, and the controller 160 causes the flash memory 180 to access the data by supplying the voltage VDD. In another embodiment of the present invention, the voltage determining device 190 can also detect the supply voltage VDD supplied to the flash memory 180 and the controller 160, respectively, wherein the flash memory 180 and the supply voltage VDD of the controller 160 are respectively. Can be different voltage sources and have different established ranges.
另外，快閃記憶體180更用以儲存相應於電壓值之至少一既定範圍的參數，其中相應於電壓值之既定範圍系快閃記憶體180可正常對資料進行讀寫的電壓範圍，但本發明不限於此。在另一實施例中，相應於電壓值之既定範圍系控制器160可正常致使快閃記憶體180對資料進行讀寫的電壓範圍。在其他實施例中，快閃記憶體180更包括相應於電壓之複數組既定範圍的參數，其中控制器160可根據使用者所輸入之一金鑰或者一識別碼，選取複數組既定範圍中之一既定範圍，以作為電壓保護方法的既定範圍。本領域之技術人員可根據本發明之揭示，根據不同之快閃記憶體的資料在不同供應電壓VDD下寫入或者讀取資料的錯誤率，設計既定範圍。值得注意的是，在一實施例中，不同的廠商或者客戶具有不同之金鑰或者識別碼。 In addition, the flash memory 180 is further configured to store a parameter corresponding to at least a predetermined range of the voltage value, wherein the predetermined range corresponding to the voltage value is a voltage range in which the flash memory 180 can normally read and write data, but The invention is not limited to this. In another embodiment, the predetermined range corresponding to the voltage value is a range of voltages that the controller 160 can normally cause the flash memory 180 to read and write data. In other embodiments, the flash memory 180 further includes a parameter corresponding to a predetermined range of the complex array of voltages, wherein the controller 160 may select a complex array according to a key or an identification code input by the user. A defined range as a defined range of voltage protection methods. According to the disclosure of the present invention, a person skilled in the art can design a predetermined range according to the error rate of writing or reading data under different supply voltages VDD according to different flash memory data. It is worth noting that in an embodiment, different vendors or customers have different keys or identifiers.
在一實施例中，控制器160可根據供應電壓VDD啟 動一限制模式，以禁能主機120對快閃記憶體180進行寫入或者讀取。舉例而言，控制器160係用以接收來自主機120之讀取命令或者寫入命令，並當供應電壓VDD超過一既定範圍時執行一限制模式，其中讀取命令係用以致使控制器160對快閃記憶體180中之資料進行讀取，寫入命令係用以致使控制器160對快閃記憶體180中之資料進行寫入。在限制模式中，控制器160禁能所有自主機120所接收的寫入命令，但本發明不限於此。在另一實施例中，在限制模式中，控制器160更用以禁能(忽略)所有自主機120所接收的讀取命令。在一實施例中，當供應電壓VDD超過(高於或者低於)既定範圍時，控制器160更用以產生一警告訊號，並將警告訊號傳送至主機120，以表示禁止對快閃記憶體180進行存取之資訊，但本發明不限於此。在另一實施例中，當控制器160系在限制模式中接收到寫入命令或者讀取命令時，產生警告訊號，並將警告訊號傳送至主機120，以表示禁止對快閃記憶體180進行存取之資訊。舉例而言，控制器160可在供應電壓VDD超過既定範圍時(即在限制模式中)，啟動Write Protect Mode(Pull WP)以禁止資料寫入快閃記憶體180中。另外，控制器160亦可在供應電壓VDD超過既定範圍時(即在限制模式中)，忽略來自主機之讀取命令。 In an embodiment, the controller 160 can be activated according to the supply voltage VDD. In the limit mode, the host 120 is disabled to write or read the flash memory 180. For example, the controller 160 is configured to receive a read command or a write command from the host 120 and perform a limit mode when the supply voltage VDD exceeds a predetermined range, wherein the read command is used to cause the controller 160 to The data in the flash memory 180 is read, and the write command is used to cause the controller 160 to write the data in the flash memory 180. In the restricted mode, the controller 160 disables all write commands received from the host 120, but the invention is not limited thereto. In another embodiment, in the restricted mode, the controller 160 is further configured to disable (ignore) all read commands received from the host 120. In an embodiment, when the supply voltage VDD exceeds (above or falls below) a predetermined range, the controller 160 is further configured to generate a warning signal and transmit the warning signal to the host 120 to indicate that the flash memory is disabled. 180 access information, but the invention is not limited thereto. In another embodiment, when the controller 160 receives the write command or the read command in the restricted mode, a warning signal is generated, and the warning signal is transmitted to the host 120 to indicate that the flash memory 180 is prohibited from being performed. Access to information. For example, the controller 160 may initiate a Write Protect Mode (Pull WP) to prohibit data from being written into the flash memory 180 when the supply voltage VDD exceeds a predetermined range (ie, in the limited mode). In addition, the controller 160 may also ignore the read command from the host when the supply voltage VDD exceeds a predetermined range (ie, in the limit mode).
另外，在其他實施例中，寫入之電壓的既定範圍亦可不同於讀取之電壓的既定範圍。舉例而言，在一實施例中，限制模式可包括一讀取限制模式以及一寫入限制模式，並且讀取限制模式與寫入限制模式具有不同之供應電壓VDD的既定範圍。換言之，讀取限制模式與寫入限制模式可根據當下 之供應電壓VDD，在不同的時間點啟動。讀取限制模式系用以禁能主機120對快閃記憶體180進行讀取。寫入限制模式系用以禁能主機120對快閃記憶體180進行寫入。 In addition, in other embodiments, the predetermined range of the written voltage may be different from the predetermined range of the read voltage. For example, in an embodiment, the limit mode may include a read limit mode and a write limit mode, and the read limit mode and the write limit mode have different predetermined ranges of the supply voltage VDD. In other words, the read limit mode and the write limit mode can be based on the current The supply voltage VDD is activated at different points in time. The read limit mode is used to disable the host 120 from reading the flash memory 180. The write limit mode is used to disable the host 120 from writing to the flash memory 180.
詳細而言，控制器160系用以每隔一既定週期，讀取電壓判斷裝置190以獲得相應於當下之供應電壓，並判斷當下之供應電壓是否超過既定範圍，並當當下之供應電壓超過既定範圍時，啟動限制模式。在具有分開之讀取限制模式與寫入限制模式的實施例中，控制器160系用以每隔一既定週期，讀取電壓判斷裝置190以獲得相應於當下之供應電壓VDD，並判斷當下之供應電壓VDD是否超過讀取限制模式所相應之既定範圍及/或超過寫入限制模式的既定範圍，並當當下之供應電壓VDD超過讀取限制模式所相應之既定範圍及/或超過寫入限制模式的既定範圍時，分別啟動寫入限制模式及/或讀取限制模式。另外，在限制模式中，控制器160仍然繼續每隔一既定週期，讀取電壓判斷裝置190以獲得相應於當下之供應電壓VDD，並判斷當下之供應電壓VDD是否超過既定範圍，並當當下之供應電壓VDD未超過既定範圍時，關閉限制模式。在另一實施例中，電壓判斷裝置190更包括一電壓比較器(未圖示)，用以藉由硬體電路比較所接收之供應電壓VDD以及既定範圍的最高電壓值與最低電壓值，並當供應電壓VDD超過既定範圍的最高電壓值或者最低電壓值時，產生一判斷訊號，並將判斷訊號提供至控制器160。當控制器160接收到相應於供應電壓VDD超過既定範圍的最高電壓值或者最低電壓值的判斷訊號時，控制器160啟動限制模式。反之，當控制器160接收到相應於供應 電壓VDD未超過既定範圍的最高電壓值或者最低電壓值的判斷訊號時，控制器160關閉限制模式。 In detail, the controller 160 is configured to read the voltage judging device 190 every other predetermined period to obtain a current supply voltage corresponding to the current supply voltage, and determine whether the current supply voltage exceeds a predetermined range, and when the current supply voltage exceeds the predetermined range. In the range, the limit mode is activated. In an embodiment having separate read limit mode and write limit mode, the controller 160 is configured to read the voltage determining means 190 every other predetermined period to obtain a current supply voltage VDD, and to determine the current state. Whether the supply voltage VDD exceeds a predetermined range corresponding to the read limit mode and/or exceeds a predetermined range of the write limit mode, and when the current supply voltage VDD exceeds a predetermined range corresponding to the read limit mode and/or exceeds a write limit When the mode is within the predetermined range, the write limit mode and/or the read limit mode are respectively activated. In addition, in the limit mode, the controller 160 continues to read the voltage judging device 190 every other predetermined period to obtain the current supply voltage VDD, and determines whether the current supply voltage VDD exceeds a predetermined range, and when the current When the supply voltage VDD does not exceed the specified range, the limit mode is turned off. In another embodiment, the voltage determining device 190 further includes a voltage comparator (not shown) for comparing the received supply voltage VDD and the highest voltage value and the lowest voltage value of the predetermined range by the hardware circuit, and When the supply voltage VDD exceeds the highest voltage value or the lowest voltage value of the predetermined range, a determination signal is generated, and the determination signal is supplied to the controller 160. When the controller 160 receives the determination signal corresponding to the highest voltage value or the lowest voltage value in which the supply voltage VDD exceeds the predetermined range, the controller 160 activates the limit mode. Conversely, when the controller 160 receives the corresponding supply When the voltage VDD does not exceed the determination signal of the highest voltage value or the lowest voltage value of the predetermined range, the controller 160 turns off the limit mode.
第2圖係本發明之一種實施例之電壓保護方法之流程圖。電壓保護方法適用於第1圖所示之資料儲存裝置140。流程開始於步驟S200。 2 is a flow chart of a voltage protection method of an embodiment of the present invention. The voltage protection method is applied to the data storage device 140 shown in FIG. The flow begins in step S200.
在步驟S200中，控制器160讀取電壓判斷裝置190以獲得當下之供應電壓VDD。 In step S200, the controller 160 reads the voltage judging means 190 to obtain the current supply voltage VDD.
接著，在步驟S202中，控制器160判斷當下之供應電壓VDD是否超過既定範圍。當供應電壓VDD超過既定範圍時，流程進行至步驟S204。當供應電壓VDD未超過既定範圍時，流程進行至步驟S208。本領域之技術人員可根據本發明之揭示，根據不同之快閃記憶體的資料在不同供應電壓VDD下寫入或者讀取資料的錯誤率，設計既定範圍。 Next, in step S202, the controller 160 determines whether the current supply voltage VDD exceeds a predetermined range. When the supply voltage VDD exceeds the predetermined range, the flow proceeds to step S204. When the supply voltage VDD does not exceed the predetermined range, the flow proceeds to step S208. According to the disclosure of the present invention, a person skilled in the art can design a predetermined range according to the error rate of writing or reading data under different supply voltages VDD according to different flash memory data.
接著，在步驟S204中，控制器160判斷限制模式是否已啟動。當限制模式已啟動時，流程進行至步驟S208。當限制模式未啟動時，流程進行至步驟S206。 Next, in step S204, the controller 160 determines whether the restriction mode has been activated. When the restriction mode has been started, the flow proceeds to step S208. When the restriction mode is not activated, the flow proceeds to step S206.
接著，在步驟S206中，控制器160開啟限制模式，以禁能所有自主機120接收用以對快閃記憶體180進行寫入的寫入命令。值得注意的是，在另一實施例之限制模式中，當供應電壓VDD超過既定範圍時，控制器160更用以禁能所有自主機120接收用以對快閃記憶體180進行讀取的讀取命令。在一實施例中，當供應電壓VDD超過既定範圍時，控制器160更用以產生一警告訊號，並將警告訊號傳送至主機120，以表示禁止對快閃記憶體180進行存取之資訊，但本發明不限於此。在另 一實施例中，當控制器160系在限制模式中接收到寫入命令或者讀取命令時，產生警告訊號，並將警告訊號傳送至主機120，以表示禁止對快閃記憶體180進行存取之資訊。舉例而言，控制器160可在供應電壓VDD超過既定範圍時(即在限制模式中)，啟動Write Protect Mode(Pull WP)以禁止資料寫入快閃記憶體180中。另外，控制器160亦可在供應電壓VDD超過既定範圍時(即在限制模式中)，忽略來自主機之讀取命令。 Next, in step S206, the controller 160 turns on the limit mode to disable all write commands from the host 120 to write to the flash memory 180. It should be noted that in the limited mode of another embodiment, when the supply voltage VDD exceeds a predetermined range, the controller 160 is further configured to disable all readings from the host 120 for reading the flash memory 180. Take the command. In an embodiment, when the supply voltage VDD exceeds a predetermined range, the controller 160 is further configured to generate a warning signal and transmit the warning signal to the host 120 to indicate that the access to the flash memory 180 is prohibited. However, the invention is not limited thereto. In another In one embodiment, when the controller 160 receives a write command or a read command in the restricted mode, a warning signal is generated, and the warning signal is transmitted to the host 120 to indicate that access to the flash memory 180 is prohibited. Information. For example, the controller 160 may initiate a Write Protect Mode (Pull WP) to prohibit data from being written into the flash memory 180 when the supply voltage VDD exceeds a predetermined range (ie, in the limited mode). In addition, the controller 160 may also ignore the read command from the host when the supply voltage VDD exceeds a predetermined range (ie, in the limit mode).
在步驟S208中，控制器160判斷限制模式是否已啟動。當限制模式已啟動時，流程進行至步驟S210。當限制模式未啟動時，流程進行至步驟S212。 In step S208, the controller 160 determines whether the restriction mode has been activated. When the restriction mode has been started, the flow proceeds to step S210. When the restriction mode is not activated, the flow proceeds to step S212.
在步驟S210中，控制器160關閉限制模式。 In step S210, the controller 160 turns off the restriction mode.
接著，在步驟S212中，控制器160判斷是否超過一既定時間。當超過既定時間時，流程會到步驟S200，控制器160讀取電壓判斷裝置190以獲得相應於當下之供應電壓VDD。當未超過既定時間時，控制器160繼續判斷是否超過既定時間。 Next, in step S212, the controller 160 determines whether or not a predetermined time has elapsed. When the predetermined time is exceeded, the flow proceeds to step S200, and the controller 160 reads the voltage judging means 190 to obtain the supply voltage VDD corresponding to the present. When the predetermined time has not elapsed, the controller 160 continues to judge whether or not the predetermined time is exceeded.
由上述可知，資料儲存裝置140以及電壓保護方法可根據目前之供應電壓VDD對主機120進行限制存取。 As can be seen from the above, the data storage device 140 and the voltage protection method can restrict access to the host 120 according to the current supply voltage VDD.
本發明之方法，或特定型態或其部份，可以以程式碼的型態存在。程式碼可儲存於實體媒體，如軟碟、光碟片、硬碟、或是任何其他機器可讀取(如電腦可讀取)儲存媒體，亦或不限於外在形式之電腦程式產品，其中，當程式碼被機器，如電腦載入且執行時，此機器變成用以參與本發明之裝置。程式碼也可透過一些傳送媒體，如電線或電纜、光纖、或是任何傳輸型態進行傳送，其中，當程式碼被機器，如電腦接收、載 入且執行時，此機器變成用以參與本發明之裝置。當在一般用途處理單元實作時，程式碼結合處理單元提供一操作類似於應用特定邏輯電路之獨特裝置。 The method of the invention, or a particular type or portion thereof, may exist in the form of a code. The code can be stored in a physical medium such as a floppy disk, a CD, a hard disk, or any other machine readable (such as computer readable) storage medium, or is not limited to an external form of computer program product, wherein When the code is loaded and executed by a machine, such as a computer, the machine becomes a device for participating in the present invention. The code can also be transmitted via some transmission medium such as wire or cable, optical fiber, or any transmission type, where the code is received by the machine, such as a computer. Upon entry and execution, the machine becomes a device for participating in the present invention. When implemented in a general purpose processing unit, the code combination processing unit provides a unique means of operation similar to application specific logic.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。另外本發明的任一實施例或申請專利範圍不須達成本發明所揭露之全部目的或優點或特點。此外，摘要部分和標題僅是用來輔助專利文件搜尋之用，並非用來限制本發明之權利範圍。 The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.
100‧‧‧電子系統 100‧‧‧Electronic system
120‧‧‧主機 120‧‧‧Host
140‧‧‧資料儲存裝置 140‧‧‧Data storage device
160‧‧‧控制器 160‧‧‧ Controller
162‧‧‧運算單元 162‧‧‧ arithmetic unit
164‧‧‧永久記憶體 164‧‧‧Permanent memory
165‧‧‧隨機存取記憶體 165‧‧‧ random access memory
180‧‧‧快閃記憶體 180‧‧‧Flash memory
190‧‧‧電壓判斷裝置 190‧‧‧Voltage judging device
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| CN201710127971.6A CN106898381B (en) | 2013-08-09 | 2014-07-10 | Data storage device and voltage protection method thereof |
| CN201910043456.9A CN109767803A (en) | 2013-08-09 | 2014-07-10 | Data memory device and its voltage protection method |
| CN201710127551.8A CN106910522B (en) | 2013-08-09 | 2014-07-10 | data storage device and voltage protection method thereof |
| CN201410327489.3A CN104346296B (en) | 2013-08-09 | 2014-07-10 | Data storage device and voltage protection method thereof |
| CN201910043591.3A CN109767804B (en) | 2013-08-09 | 2014-07-10 | Data storage device and voltage protection method thereof |
| US14/444,429 US9847134B2 (en) | 2013-08-09 | 2014-07-28 | Data storage device and voltage protection method thereof |
| KR1020140101938A KR101595557B1 (en) | 2013-08-09 | 2014-08-07 | Data storage device and voltage protection method thereof |
| JP2014162080A JP5891274B2 (en) | 2013-08-09 | 2014-08-08 | Data storage device and its protection method from abnormal voltage |
| US15/809,542 US9997249B2 (en) | 2013-08-09 | 2017-11-10 | Data storage device and flash memory voltage protection method thereof |
| US15/809,539 US9990999B2 (en) | 2013-08-09 | 2017-11-10 | Data storage device and voltage protection method thereof |
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| TWI740454B (en) * | 2020-04-14 | 2021-09-21 | 慧榮科技股份有限公司 | Method and apparatus for accessing to data in response to a power-supply event |
| CN115497522B (en) * | 2022-11-17 | 2023-03-14 | 合肥康芯威存储技术有限公司 | Storage device and data protection method thereof |
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| JPH1011365A (en) * | 1996-06-20 | 1998-01-16 | Fujitsu General Ltd | Protecting circuit for nonvolatile storage device |
| JP2004178782A (en) * | 2002-10-04 | 2004-06-24 | Sharp Corp | Semiconductor memory, control method for the same, and portable electronic apparatus |
| US6856556B1 (en) * | 2003-04-03 | 2005-02-15 | Siliconsystems, Inc. | Storage subsystem with embedded circuit for protecting against anomalies in power signal from host |
| US7187600B2 (en) * | 2004-09-22 | 2007-03-06 | Freescale Semiconductor, Inc. | Method and apparatus for protecting an integrated circuit from erroneous operation |
| JP2007066232A (en) * | 2005-09-02 | 2007-03-15 | Seiko Epson Corp | Data processor |
| US8605533B2 (en) * | 2009-11-27 | 2013-12-10 | Samsung Electronics Co., Ltd. | Apparatus and method for protecting data in flash memory |
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