TW201506931A - Method for managing a memory apparatus, and associated memory apparatus thereof and associated controller thereof - Google Patents

Abstract

A method for managing a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the volatile memory as received data, and dynamically monitoring the data amount of the received data to determine whether to immediately write the received data into at least one NV memory element; and when a specific signal is received and it is detected that specific data having not been written into a same location in a specific block configured to be an MLC memory block within a specific NV memory element of the at least one NV memory element for a predetermined number of times exists in the received data, immediately writing the specific data into another block in the at least one NV memory element.

Description

Method for managing a memory device and memory device and controller

The present invention relates to the control of flash memory, and more particularly to a method for managing a memory device and its associated memory device and controller.

In recent years, due to the continuous development of flash memory technology, various portable memory devices (for example, memory cards conforming to SD/MMC, CF, MS, and XD standards) have been widely implemented in many applications. Therefore, access control of flash memory in these portable memory devices has become a hot topic.

In the conventional NAND type flash memory, it can be mainly divided into two types of flash memory: single level cell (SLC) and multiple level cell (MLC). Each of the single-order cellular flash memories, which are treated as memory cells (also known as "memory cells"), has only two types of charge values, which are used to represent a logical value of 0 and a logical value of 1, respectively. In addition, the storage capacity of each of the multi-order cellular flash memory, which is treated as a memory cell, is fully utilized and is driven by a higher voltage to record in a transistor through different levels of voltage. Information on multiple bits (eg 00, 01, 11, 10); in theory, the recording density of multi-level cellular flash memory can reach more than twice the recording density of single-order cellular flash memory, It is very good news for industries related to NAND-type flash memory that have encountered bottlenecks in the development process.

Compared to single-order cellular flash memory, multi-order cellular flash memory quickly becomes a market because multi-stage cellular flash memory is cheaper and provides a larger capacity in a limited space. The mainstream of portable memory devices on the competition. According to related technology, due to Some types of multi-order cellular flash memory are complicated to operate, so the traditional memory controller configures a part of the physical blocks in the multi-order cellular flash memory into a single-order cellular memory block for receiving from The data written by the host device (Host Device). However, some problems have arisen. For example, since a part of the physical block in the multi-order cell flash memory is configured as a single-order cell memory block, the number of physical blocks available in the multi-order cell flash memory as a multi-order cell memory block is This has been reduced, resulting in a reduction in the overall storage capacity of conventional memory devices. For example, the traditional memory controller temporarily writes the received data into the single-order cell memory block, and then collects the data from the single-order cell memory block to the multi-order cell memory block, wherein these single-order cell memory regions The storage space of the block is easy to use, so the traditional memory controller needs to erase these single-order cell memory blocks frequently. As a result, the workload of the conventional memory controller has been greatly increased, and these additional operations require additional processing time, which deteriorates the overall performance of the conventional memory device. Therefore, there is a need for a novel method to enhance data access to control flash memory to improve overall performance without side effects (eg, storage data errors).

Accordingly, it is an object of the present invention to provide a method for managing a memory device and associated memory device and controller to solve the above problems.

Another object of the present invention is to provide a method for managing a memory device and its associated memory device and controller to improve the operational efficiency of the memory device.

At least one preferred embodiment of the present invention provides a method for managing a memory device, the memory device including at least one non-volatile (NV) memory component, each non-volatile memory component comprising a plurality of blocks, the method being applied to a controller in the memory device, the controller is for controlling the at least one non-volatile memory component, the method comprising the following steps: receiving a block The data of the host device is temporarily stored in the controller as one of the volatile memory as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least one non- a volatile memory component, wherein at least one write command received from the master device indicates that the master device requires writing of the data; Receiving a specific signal, and detecting that the specific data in the received data has not been written into one of the at least one non-volatile memory element, the specific non-volatile memory element is configured as a multi-order cell (Multiple Level Cell (MLC), when the same location in a particular block of a memory block reaches a predetermined number of times, immediately writes the specific data to another block of the at least one non-volatile memory element to avoid the specific Loss of data, wherein the particular signal indicates that the power supply to the controller is abnormal, or indicates that the memory device is shut down, and the predetermined number of times is greater than one, and the other block is configured as a single-stage cell (Single Level Cell) , SLC) memory block.

While providing the above method, the present invention also correspondingly provides a memory device comprising: at least one non-volatile memory element, each non-volatile memory element comprising a plurality of blocks; and a controller for The at least one non-volatile memory component is controlled, the controller including a processing unit to manage the memory device according to a code embedded in or received from the processing unit. In addition, the controller temporarily stores the data received from a master device in one of the volatile memory of the controller as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data. The at least one non-volatile memory component is received, wherein at least one write command received from the master device indicates that the master device requires writing of the data. In addition, when a specific signal is received, and it is detected that the specific data in the received data has not been written into one of the at least one non-volatile memory element, the plurality of non-volatile memory elements are configured to be multi-order. When the same location in a particular block of the cell memory block reaches a predetermined number of times, the controller immediately writes the specific data to another block of the at least one non-volatile memory element to avoid the specific data. The loss, wherein the particular signal indicates that the power supply to the controller is abnormal, or indicates that the memory device is to be turned off, and the predetermined number of times is greater than one, and the other block is configured as a single-order cellular memory block.

While providing the above method, the present invention also correspondingly provides a controller for a memory device, the memory device comprising at least one non-volatile memory component, each non-volatile memory component comprising a plurality of blocks, the controller The method includes: a processing unit configured to manage the memory device according to a code embedded in the processing unit or received from the processing unit. In addition, the The controller temporarily stores the data received from a master device in the volatile memory of the controller as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least A non-volatile memory component, wherein at least one write command received from the master device indicates that the master device requires writing of the data. In addition, when a specific signal is received, and it is detected that the specific data in the received data has not been written into one of the at least one non-volatile memory element, the plurality of non-volatile memory elements are configured to be multi-order. When the same location in a particular block of the cell memory block reaches a predetermined number of times, the controller immediately writes the specific data to another block of the at least one non-volatile memory element to avoid the specific data. The loss, wherein the particular signal indicates that the power supply to the controller is abnormal, or indicates that the memory device is to be turned off, and the predetermined number of times is greater than one, and the other block is configured as a single-order cellular memory block.

One of the advantages of the present invention is that the method, the memory device, and the controller of the present invention do not have to use a large number of single-order cell memory blocks compared to the related art, so that the above-mentioned large number of single-order cell memory blocks can be saved. Take up storage space to provide more multi-level cell memory blocks. Thus, the present invention provides a higher storage capacity than related art.

Another advantage of the present invention is that the method, memory device, and controller of the present invention can improve overall performance without causing side effects (e.g., storing data errors) as compared to the related art. In particular, the method, the memory device, and the controller of the present invention can substantially save the temporary reception of the received data into the plurality of single-order cellular memory blocks and collect the data from the plurality of single-order cellular memory blocks. By the time of the multi-order cell memory block, the time to frequently erase the above-mentioned large number of single-order cell memory blocks can be saved. Thus, the present invention provides better performance than related techniques.

100‧‧‧ memory device

110‧‧‧Processing unit

120‧‧‧ volatile memory

130‧‧‧Transport interface

140_0,140_1,...,140_N‧‧‧Non-volatile memory components

150‧‧‧ busbar

200‧‧‧Methods for managing a memory device

210,220‧‧ steps

BLK(0), BLK(1), BLK(2),...,BLK(M),BLK(m),BLK(m’)‧‧‧ blocks

CHP(n)‧‧‧flash chip

Data(0), Data(1), Data(2), Data(6), Data(7), Data(8),...‧‧‧Information

Data(3), Data(4), Data(5), Page(0), Page(1), Page(2), Page(3), Page(4), Page(5), Page(6), Page(7), Page(8),..., Page (189), Page (190), Page (191) ‧ ‧ page

SEC(0), SEC(1), SEC(2), SEC(3)‧‧‧ Section

WL0, WL1, WL2, WL3, WL4, WL5, WL6,..., WL63‧‧‧ word line

1 is a schematic view of a memory device in accordance with a first embodiment of the present invention.

2 is a view showing an arrangement of one of the non-volatile memory elements shown in FIG. 1 in an embodiment of the present invention, wherein the non-volatile memory element is a flash chip in this embodiment. .

FIG. 3 is a diagram showing the content arrangement of one of the non-volatile memory elements shown in FIG. 1 in another embodiment of the present invention, wherein the non-volatile memory element is flashed in this embodiment. Wafer.

Figure 4 is a diagram of a method for managing a memory device in accordance with an embodiment of the present invention.

FIG. 5 is a diagram showing the control scheme involved in the method shown in FIG. 4 in an embodiment.

Figure 6 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.

Figure 7 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.

Figure 8 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.

Figure 9 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.

Figure 10 is a diagram showing the control scheme involved in the method shown in Figure 4 in another embodiment.

Please refer to FIG. 1 , which illustrates a schematic diagram of a memory device 100 in accordance with a first embodiment of the present invention. The memory device 100 includes: a processing unit 110, a volatile (Volatile) memory 120, a transmission interface 130, and a plurality of non-volatile (NV) memory elements 140_0, 140_1, ..., and 140_N (The symbol "N" represents a positive integer) such as (N+1) flash chips, and a bus 150. In a typical case, after the transmission interface 130 is coupled to a host device (not shown in FIG. 1), the host device can access the memory device 100 through the transmission interface 130. For example, the primary device can represent a personal computer, such as a laptop or a desktop computer.

The processing unit 110 can manage the memory device 100 in accordance with code (not shown) embedded in or received from the processing unit 110. For example, the code may be a hardware code embedded in the processing unit 110, especially a ROM code. For another example, the code may be a firmware code received from the processing unit 110. In particular, processing unit 110 is used to control volatile memory 120, transmission interface 130, non-volatile memory elements 140_0, 140_1, . . . , and 140_N, and bus bar 150. The processing unit 110 of this embodiment may be a high An Advanced Reduced Instruction Set Computer Machine (Advanced RISC Machine, ARM) processor or an Argonaut RISC Core (ARC) processor. This is for illustrative purposes only and is not a limitation of the invention. According to various variations of this embodiment, processing unit 110 can be other types of processors.

In addition, the volatile memory 120 can be used to store a Global Page Address Linking Table, information accessed by the host device, and other required information for accessing the memory device 100. The volatile memory 120 of this embodiment may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). This is for illustrative purposes only and is not a limitation of the invention. According to various variations of the embodiment, the volatile memory 120 can be other types of volatile memory. For example, the volatile memory 120 can include a static random access memory (SRAM).

According to the embodiment, the transmission interface 130 shown in FIG. 1 is used for transmitting data and instructions between the host device and the memory device 100, wherein the transmission interface 130 conforms to a specific communication standard such as a serial advanced technology accessory (Serial Advanced). Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, or Universal Serial Bus (USB) standard. For example, the memory device 100 is a Solid State Drive (SSD) disposed in the host device, and the specific communication standard may be some typical communication standard used to implement internal communication of the host device, such as serial Advanced Technical Attachment Standard or Parallel Advanced Technical Attachment Standard. For another example, the memory device 100 is a solid state drive and is external to the host device, and the particular communication standard can be some typical communication standard used to implement external communication of the host device, such as a universal serial bus standard. This is for illustrative purposes only and is not a limitation of the invention. According to different variants of the embodiment, the memory device 100 can be a portable memory device such as a memory card, and the specific communication standard can be some typical communication standard for implementing an input/output interface of a memory card. Such as security digital (Secure Digital, SD) standard or Compact Flash (CF) standard.

In addition, the non-volatile memory elements 140_0, 140_1, ..., and 140_N are used to store data, wherein the non-volatile memory elements 140_0, 140_1, ..., and 140_N may be (but are not limited to) NAND type Flash chip. The bus bar 150 is used to couple the processing unit 110, the volatile memory 120, the transmission interface 130, and the non-volatile memory elements 140_0, 140_1, ..., and 140_N, and to communicate therewith. In this embodiment, the parts other than the non-volatile memory elements 140_0, 140_1, ..., and 140_N in the architecture shown in FIG. 1 can be integrated into a controller, especially an integrated circuit (Integrated Circuit, IC), such as a controller chip, wherein the controller is used to control at least one non-volatile memory component such as non-volatile memory components 140_0, 140_1, ..., and 140_N in memory device 100, such that The controller of the memory device 100.

2 is a diagram showing the content arrangement of any one of the non-volatile memory elements 140_0, 140_1, . . . , and 140_N shown in FIG. 1 according to an embodiment of the present invention, wherein The non-volatile memory element 140_n may be referred to as a flash wafer CHP(n) in this embodiment, and the index n may represent any integer falling within the range of the interval [0, N]. As shown in FIG. 2, each of the non-volatile memory elements 140_0, 140_1, ..., and 140_N, such as the flash wafer CHP(n), may include a plurality of blocks. Each of the blocks BLK(0), BLK(1), BLK(2), ..., and BLK(M) (the symbol "M" represents a positive integer) as shown in Fig. 2, each block Multiple pages can be included, and each page can contain a plurality of segments. In this embodiment, a segment can be the minimum read unit. In other words, during a read operation, processing unit 110 can read one segment or a plurality of segments. This is for illustrative purposes only and is not a limitation of the invention.

As shown in FIG. 2, one of the non-volatile memory elements 140_n such as the flash wafer CHP(n) (for example, the block BLK(0)) is configured as a single-level cell (Single Level Cell, SLC). In the case of a memory block, the block, such as block BLK(0), may comprise a predetermined number of pages, such as corresponding to a plurality of word lines (Word-Line) WL0, WL1, WL2, ..., respectively. Pages (0), Page(1), Page(2), ..., and Page(63) with WL63, each page such as Page(0) Sections SEC(0), SEC(1), SEC(2), and SEC(3) may be included. This is for illustrative purposes only and is not a limitation of the invention. According to some variations of this embodiment, such as the embodiment illustrated in FIG. 3, one of the non-volatile memory elements 140_n, such as a flash wafer CHP(n) (eg, block BLK(0)) In the case of being configured as a multiple level cell (MLC) memory block such as a Triple Level Cell (TLC) memory block, the block such as block BLK(0) may contain a predetermined number a plurality of pages, such as respective pages {Page(0), Page(1), Page(2)}, {Page(3) corresponding to the plurality of word lines WL0, WL1, WL2, ..., and WL63, respectively. ), Page(4), Page(5)}, {Page(6), Page(7), Page(8)},..., and {Page(189), Page(190), Page(191) }, where each page such as page Page(0) may contain sections SEC(0), SEC(1), SEC(2), and SEC(3).

Note that each of the at least one non-volatile memory component has a storage capacity greater than one bit per memory cell, wherein the controller selectively selects the block group The single-order cell memory block stores a bit in a memory cell, and can also selectively configure the block into a multi-order cell memory block to store a plurality of bits in one memory cell.

4 is a diagram of a method 200 for managing a memory device in accordance with an embodiment of the present invention. The method can be applied to the memory device 100 shown in FIG. 1 , in particular, the above-mentioned controller (for example, a memory controller that executes the above code through the processing unit 110 ), wherein the controller for executing the above code is used. The at least one non-volatile memory component such as the non-volatile memory components 140_0, 140_1, ..., and 140_N shown in FIG. 1 are controlled. The method is described as follows:

In step 210, the controller temporarily stores the data from the host device in the volatile memory 120 stored in the controller as receiving data, and dynamically monitors the amount of data of the received data to determine whether to immediately The received data is written to the at least one non-volatile memory component, wherein at least one write command received from the master device indicates that the master device requires the data to be written. For example, when the amount of data of the Partial Data in the received data reaches a predetermined data threshold PDDA_TH, the controller immediately writes the partial data to at least one of the above. The non-volatile memory component, in particular, directly writes the portion of the data to at least one multi-level cell memory block, rather than by temporarily writing the received data to a large number of single-order cell memory regions as in the related art. One or more single-order cellular memory blocks in the block indirectly write the received data into the at least one multi-level cellular memory block. Thus, the controller does not have to use a large number of single-order cell memory blocks as described above, so that the problems of the related art can be avoided.

In step 220, when a specific signal is received, and it is detected that the specific data in the received data has not been written into one of the at least one non-volatile memory element, the specific non-volatile memory element is grouped. The state is a multi-order cell memory block (for example, in the embodiment shown in FIG. 3, there is a page of 192 pages of Page(0), Page(1), ..., Page(191)) in a specific block. When the same position reaches a predetermined number of times PDNT_WR, the controller immediately writes the specific data into another block of the at least one non-volatile memory element to avoid loss of the specific data, wherein the specific signal indicates The power supply of the controller is abnormal, or indicates that the memory device 100 will be turned off, and the predetermined number of times PDNT_WR is greater than one, and the other block is configured as a single level cell (SLC) memory block (for example, In the embodiment shown in Fig. 2, there are 64 pages of Page(0), Page(1), ..., Page(63). According to different variants of the embodiment, the specific signal may include at least one of a shutdown command and a power detection signal (eg, the shutdown command; for example, the power detection signal; and, for example, the shutdown The command and the power detection signal are used to indicate the occurrence of any of Power Loss and Power Down of the power source. Examples of the shutdown command may include, but are not limited to, a clear cache instruction from the master device.

In practice, the specific non-volatile memory component can be the flash wafer CHP(n) in the embodiment shown in FIG. 3, and the specific block can be the block {BLK(0), BLK(1). One of the blocks BLK(2), ..., BLK(M)} such as block BLK(m), and the index m may represent any integer falling within the range of the interval [0, M]. In particular, the other block may be any block that is different from the particular block, such as block BIK(m'), and the index m' may represent any of the ranges falling within the interval [0, M] Possible integer. For example, the other block and the specific block can be located on the same flash chip, where index m' Not equal to index m. For another example, the other block and the particular block may be located on different flash chips, wherein the index m' may be any integer falling within the range of the interval [0, M].

According to this embodiment, in a case where one of the memory cells in the specific block is used to store a plurality of bits, the plurality of bits are repeatedly written into the memory cell for a predetermined number of times PDNT_WR to make the memory cell It is correctly programmed among the particular non-volatile memory elements such that each of the plurality of bits is correctly stored in the memory cell for further reading. In practice, the storage capacity of the volatile memory 120 is greater than or equal to a product of a predetermined data threshold PDDA_TH and a predetermined number of PDNT_WR (PDDA_TH * PDNT_WR) to allow at least a portion of the received data to be used for repeated writing of the memory cell. Into the operation. For example, for certain types of multi-level cellular flash memory, the particular block can be configured as a third-order cellular memory block, and the predetermined number of PDNT_WR can be equal to three, and the predetermined data threshold value PDDA_TH can be equal to Among the specific non-volatile memory elements, the storage capacity of one of the memory cells belonging to one word line. This is for illustrative purposes only and is not a limitation of the invention.

Please note that in this embodiment, the controller can directly write the received data to the specific block to ensure that the user data does not have any errors. In particular, under the control of the controller, the received data is written into the specific block for a predetermined number of times PDNT_WR such that a particular group of memory cells belonging to a particular word line in the particular block is in the particular non-volatile The memory elements are correctly programmed so that each bit in the received data is correctly stored in the particular set of memory cells for further reading.

According to some variations of the embodiment, the controller receives the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), respectively, from the master device. Data(5)}, {Data(6), Data(7), Data(8)}, ..., and the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), Data(8)}, ... are temporarily stored in the volatile memory 120, wherein the plural Each group of data in the group data includes a plurality of pages, and the data amount of each group of data in the complex array data is equal to a predetermined data amount threshold PDDA_TH. In particular, the controller is self-contained The volatile memory 120 reads the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6) And at least one set of data of Data (7), Data (8)}, ... to write at least one of the above-mentioned materials directly to the specific block, wherein at least one of the above-mentioned materials is written to the specific block The number of blocks has not reached the predetermined number of times PDNT_WR, and the specific data described in step 220 contains at least one of the above-mentioned materials. This is for illustrative purposes only and is not a limitation of the invention. According to some embodiments of the present invention, the controller reads the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4) from the volatile memory 120. ), Data(5)}, {Data(6), Data(7), Data(8)}, ..., to separate the complex array data {Data(0), Data(1), Data(2 )}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), Data(8)}, ... directly write to the specific block, and more The complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7) The first set of data {Data(0), Data(1), Data(2)} in Data(8)},... is directly written to the specific block, where the first set of data {Data(0) , Data(1), Data(2)} is written to the specific block for a predetermined number of times PDNT_WR such that a particular group of memory cells belonging to a particular word line in the particular block is in the particular non-volatile memory The components are correctly programmed so that each of the first set of data {Data(0), Data(1), Data(2)} is correctly stored in the particular set of memory cells for further reading. .

According to some embodiments of the present invention, the controller may receive the complex array data {Data(0), Data(1), Data(2)}, {Data(3), Data (page by page) from the host device. 4) at least one of at least one of the data of Data(5)}, {Data(6), Data(7), Data(8)}, ... (for example: one or more pages), And storing at least one of the at least one page of the set of data in the volatile memory 120, wherein the specific data includes the at least one page of the set of data, and the total amount of received data in the set of data reaches a predetermined amount of data Before the threshold value PDDA_TH, the data of this group was not written to the specific block. When the crisis condition represented by the specific signal (for example, the power source is abnormal; for example, the memory device 100 is turned off), the controller may read the at least one page of the group of materials from the other block. And storing the at least one page read from the other block temporarily in the volatile memory 120 for writing to the specific block. As such, the controller ensures volatile memory 120 The latest storage information is equivalent to the stored information in the volatile memory 120 when the above-mentioned crisis situation occurs, whereby the controller can continue to operate normally as if the above-mentioned crisis situation has not occurred.

In particular, in a situation where the group of materials has not been completely received (for example, the amount of data of the at least one page in the group of materials is less than the amount of data of the group of materials), the controller may be page by page from the main device. Receiving at least one other page (eg, one or more pages) of the set of materials, and temporarily storing the at least one other page of the set of data in the volatile memory 120 until the total receipt of the set of data The amount of data reaches the predetermined data amount threshold PDDA_TH. When the total received data amount of the group of data reaches the predetermined data amount threshold PDDA_TH (that is, in these embodiments, the group of data has now been completely received), the controller can read from the volatile memory 120. At least a portion of the set of data is taken to write the set of data directly to the particular block.

In addition, in the case that the group of materials has been completely received (for example, the amount of data of the at least one page in the group of materials is equal to the amount of data of the group of materials; for example, the at least one page of the group of materials mentioned above) The amount of data is less than the amount of data of the set of data and the controller further receives the at least one other page of the set of data, the controller may receive the complex array data page by page from the primary device {Data(0), Data (1), Data(2)}, {Data(3), Data(4), Data(5)}, {Data(6), Data(7), Data(8)}, ... a set of data and temporarily storing the other set of data in the volatile memory 120 until the total received data amount of the other set of data reaches a predetermined data amount threshold PDDA_TH, wherein the total receiving of the other set of data Before the amount of data reaches the predetermined data threshold PDDA_TH, the other group of data is not written to the specific block. When the total received data amount of the another set of data reaches a predetermined data amount threshold PDDA_TH, the controller reads at least a portion of the other set of data from the volatile memory 120 to directly write the other set of data. Enter the specific block and write the group data directly to the specific block again. Thus, by writing the set of data directly to the particular block multiple times, each bit of any page of the set of data is correctly stored in the particular block for further reading.

FIG. 5 is a diagram showing a control scheme involved in the method 200 shown in FIG. 4, wherein the data shown in FIG. 5 is Data(0), Data(1), Data(2), Data(3). ), Data(4), Each of Data (5), Data (6), ... can be a page of data. For example, the size of a page of data can be 16KB (Kilobyte, that is, thousands of bytes). This is for illustrative purposes only and is not a limitation of the invention. This specific material contains

According to this embodiment, the controller receives the first group of data {Data(0), Data(1), Data(2)} page by page from the master device and sets the first group of data {Data(0), Data( 1), Data(2)} is temporarily stored in the volatile memory 120, wherein the total amount of received data in the first set of data {Data(0), Data(1), Data(2)} reaches a predetermined data amount threshold. Before the value PDDA_TH, the first set of data {Data(0), Data(1), Data(2)} is not written to the specific block. In practice, a set of data (for example: the first group of data {Data (0), Data (1), Data (2)}; and for example: other group data {Data (3), Data (4), Data ( The total amount of received data of 5)}, {Data(6), Data(7), Data(8)}, ...) can be temporarily stored in the volatility of this group of data. The amount of data of the data of the memory 120. This is for illustrative purposes only and is not a limitation of the invention. As shown in FIG. 5, when the total received data amount of the first group of data {Data(0), Data(1), Data(2)} reaches the predetermined data amount threshold PDDA_TH, the controller is self-volatile memory. 120 reads at least a portion of the first set of data {Data(0), Data(1), Data(2)} to directly direct the first set of data {Data(0), Data(1), Data(2)} This particular block is written, such as block BLK(m). Similarly, the controller performs a similar operation on the second set of data {Data(3), Data(4), Data(5)}.

Please note that the specific data of this embodiment includes the first group of data {Data(0), Data(1), Data(2)} and the second group of data {Data(3), Data(4), Data(5). )}. When the crisis situation represented by the specific signal occurs, because the first group of data {Data(0), Data(1), Data(2)} and the second group of data {Data(3), Data(4), Data (5)} has not been written to the specific block for a predetermined number of times PDNT_WR, so the controller immediately sets the first group of data {Data(0), Data(1), Data(2)} and the second group of data {Data (3), Data(4), Data(5)} writes the other block such as the block BLK(m'), in particular, writes to some pages in the block BLK(m'), respectively (0) ), Page(1), Page(2), Page(3), Page(4), and Page(5).

Figure 6 is a diagram showing the method 200 shown in Figure 4 in another embodiment. Control scheme, in which the data shown in Fig. 6 is Data(0), Data(1), Data(2), Data(3), Data(4), Data(5), Data(6), ... Each of them can be a page of information. For example, the controller has performed the operation in the embodiment shown in FIG. According to this embodiment, when the crisis condition represented by the specific signal is released, the controller reads the first group of data {Data(0), Data(1), Data(2)} and the first block from the other block. Two sets of data {Data(3), Data(4), Data(5)}, and will read the first set of data from the other block {Data(0), Data(1), Data(2) And the second set of data {Data(3), Data(4), Data(5)} is temporarily stored in the volatile memory 120 for writing to the specific block.

FIG. 7 illustrates a control scheme involved in the method 200 shown in FIG. 4 in another embodiment. Compared with the embodiment shown in FIG. 5, the specific data in this embodiment includes a first group of data {Data(0), Data(1), Data(2)}, and a second group of data {Data(3), Data (4), Data (5)}, and data Data (3). In addition, the data Data(3) may be regarded as the above-mentioned at least one page in the aforementioned group of materials, such as the above-mentioned at least one page in the third group of materials {Data(6), Data(7), Data(8)}. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.

FIG. 8 illustrates a control scheme involved in the method 200 shown in FIG. 4 in another embodiment. Compared with the embodiment shown in FIG. 5, the specific data of the embodiment includes the first group of data {Data(0), Data(1), Data(2)} and the data Data(3) and Data(4). . In addition, the data Data(3) and Data(4) may be regarded as the above-mentioned at least one page in the foregoing group of materials, such as the above-mentioned at least in the second group of materials {Data(3), Data(4), Data(5)}. One page. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.

FIG. 9 illustrates a control scheme involved in the method 200 shown in FIG. 4 in another embodiment. Compared with the embodiment shown in FIG. 5, the specific material of this embodiment includes the data Data(0). In addition, the data Data(0) can be regarded as the above-mentioned at least one page in the aforementioned group of materials, such as the above-mentioned at least one page in the first group of materials {Data(0), Data(1), Data(2)}. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.

FIG. 10 illustrates a control scheme involved in the method 200 shown in FIG. 4 in another embodiment. Compared with the embodiment shown in FIG. 5, the specific data of the embodiment includes data Data(0). With Data(1). In addition, the data Data(0) and Data(1) may be regarded as the at least one page in the foregoing group of materials, such as the above-mentioned at least in the first group of materials {Data(0), Data(1), Data(2)}. One page. The description of the embodiment that is similar to the foregoing embodiment/variation will not be repeated.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200‧‧‧Methods for managing a memory device

210,220‧‧ steps

Claims (20)

A method for managing a memory device, the memory device comprising at least one non-volatile (NV) memory component, each non-volatile memory component comprising a plurality of blocks, the method Applying to a controller in the memory device, the controller is for controlling the at least one non-volatile memory component, the method comprising the steps of: temporarily storing data received from a host device (Host Device) One of the volatile memory in the controller acts as the receiving data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least one non-volatile memory component, wherein the receiving is received from the main At least one write command of the device indicates that the master device requests to write the data; and when a specific signal is received, and detecting that the specific data exists in the received data has not been written into the at least one non-volatile memory component One of the specific non-volatile memory elements is configured to be the same position within a particular block of one of the multiple level cell (MLC) memory blocks for a predetermined number of times Immediately writing the specific data to another block of the at least one non-volatile memory element to avoid loss of the specific data, wherein the specific signal indicates that the power supply of the controller is abnormal, or indicates the memory device The shutdown will occur, and the predetermined number of times is greater than one, and the other block is configured as a Single Level Cell (SLC) memory block. The method of claim 1, wherein in the case where one of the memory cells in the specific block is used to store a plurality of bits, the plurality of bits are repeatedly written. The memory cell reaches the predetermined number of times to cause the memory cell to be correctly programmed in the specific non-volatile memory element such that each of the plurality of bits is correctly stored in the memory cell for Read further. The method of claim 2, further comprising: when the amount of data of the Partial Data in the received data reaches a predetermined threshold, the portion of the data is immediately written into the at least a non-volatile memory component; wherein the storage capacity of the volatile memory is greater than or equal to a product of the predetermined data threshold and the predetermined number of times to allow at least a portion of the received data to be used for repeated writing of the memory cell Into the operation. The method of claim 3, wherein the predetermined data threshold is equal to a storage capacity of one of the memory cells belonging to one word line of the particular non-volatile memory component. The method of claim 4, wherein any one of the plurality of blocks comprises a predetermined number of pages; and the method further comprises: receiving the complex array data from the master device, respectively, and The complex array data is temporarily stored in the volatile memory, wherein each of the set of data in the complex array data comprises a plurality of pages, and the data amount of each set of data in the complex array data is equal to the threshold of the predetermined data amount And reading at least one set of the plurality of data from the volatile memory to write the at least one set of data directly to the specific block, wherein the at least one set of data is written to the specific block The number of times has not reached the predetermined number of times; wherein the specific data includes the at least one set of materials. The method of claim 2, wherein any one of the plurality of blocks comprises a predetermined number of pages; and the method further comprises: receiving the plurality of pages from the main device page by page At least one page of a set of data, and the at least one page of the set of data is temporarily stored in the volatile memory, wherein the specific The data includes the at least one page of the set of data, and the set of data is not written to the specific block before the total received data amount of the set of data reaches a predetermined data amount; and from the other area The block reads the at least one page of the set of data and temporarily stores the at least one page read from the other block in the volatile memory for writing to the particular block. The method of claim 6, further comprising: receiving at least one other page of the group of materials from the master device page by page, and temporarily storing the at least one other page in the group of materials The volatile memory; and when the total received data amount of the set of data reaches the predetermined data threshold, at least a portion of the set of data is read from the volatile memory to directly write the set of data to the Specific block. The method of claim 6, further comprising: receiving another set of data comprising a plurality of pages from the main device page by page and temporarily storing the other set of data in the volatile memory until The total amount of received data of the other set of data reaches the predetermined threshold value, wherein the other set of data is not written until the total received data amount of the other set of data reaches the predetermined data threshold The specific block; and when the total received data amount of the another set of data reaches the predetermined data amount threshold, at least a portion of the other set of data is read from the volatile memory to the other group The data is directly written into the specific block, and the group data is written directly to the specific block again; wherein, by directly writing the group data directly to the specific block, any page in the group of materials Each bit of the data is correctly stored in that particular block for further reading. The method of claim 1, wherein the specific signal includes at least one of a shutdown command and a power detection signal, wherein the power detection signal is used to indicate power loss of the power source (Power) Loss) and any of Power Down. The method of claim 1, wherein a memory cell of each of the at least one non-volatile memory component has a storage capacity greater than one bit. A memory device includes: at least one non-volatile (NV) memory component, each non-volatile memory component includes a plurality of blocks; and a controller for controlling the at least a non-volatile memory component, the controller including a processing unit to manage the memory device according to a code embedded in the processing unit or received from the processing unit, wherein the controller will receive the memory device The data of the host device is temporarily stored in the controller as one of the volatile memory as the received data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least one non- a volatile memory component, wherein at least one write command received from the master device indicates that the master device requests to write the data; wherein when a specific signal is received and a specific data is detected in the received data, a specific data has not been written yet One of the specific non-volatile memory elements of the at least one non-volatile memory element is configured as a multi-level cell (MLC) memory block When the same position in the block reaches a predetermined number of times, the controller immediately writes the specific data into another block of the at least one non-volatile memory element to avoid loss of the specific data, wherein the specific signal Indicates that the controller's power supply is abnormal, or indicates that the memory device will be shut down, and the predetermined number of times is greater than one, and the other block is configured as a single-order cell (Single Level Cell, SLC) Memory block. The memory device of claim 11, wherein in the case where one of the memory cells in the specific block is used to store a plurality of bits, the plurality of bits are repeatedly written. Entering the memory cell for the predetermined number of times to cause the memory cell to be correctly programmed in the specific non-volatile memory element such that each of the plurality of bits is correctly stored in the memory cell For further reading. The memory device of claim 12, wherein when the amount of data of the partial data in the received data reaches a predetermined data threshold, the controller immediately writes the partial data to the at least a non-volatile memory component; and a storage capacity of the volatile memory greater than or equal to a product of the predetermined data threshold and the predetermined number of times to allow at least a portion of the received data to be used for repeated writing of the memory cell Into the operation. The memory device of claim 13, wherein the predetermined data threshold is equal to a storage capacity of a memory cell belonging to one word line of the specific non-volatile memory component. The memory device of claim 14, wherein any one of the plurality of blocks comprises a predetermined number of pages; the controller receives the complex array data from the master device, and the plurality of blocks The group data is temporarily stored in the volatile memory, wherein each of the sets of data in the complex array data comprises a plurality of pages, and the data amount of each of the set of data in the complex array data is equal to the threshold of the predetermined data amount; The controller reads at least one set of data in the complex array data from the volatile memory to directly write the at least one set of data to the specific block, wherein the at least one set of data is written into the specific block The number of times has not reached the predetermined number of times; and the specific material contains the at least one set of data. A controller for a memory device, the memory device comprising at least one non-volatile (NV) memory component, each non-volatile memory component comprising a plurality of blocks, the controller comprising: a processing unit for managing the memory device according to a code embedded in the processing unit or received from the processing unit, wherein the controller temporarily stores data received from a host device (Host Device) One of the volatile memory in the controller acts as the receiving data, and dynamically monitors the amount of data of the received data to determine whether to immediately write the received data to the at least one non-volatile memory component, wherein the receiving is received from the main At least one write command of the device indicates that the master device requests to write the data; wherein when a specific signal is received, and it is detected that the specific data in the received data has not been written into the at least one non-volatile memory component One of the specific non-volatile memory elements is configured to be the same position within a particular block of one of the multiple level cell (MLC) memory blocks for a predetermined number of times The controller immediately writes the specific data to another block of the at least one non-volatile memory element to avoid loss of the specific data, wherein the specific signal indicates that the power supply of the controller is abnormal, or indicates The memory device will be turned off, and the predetermined number of times is greater than one, and the other block is configured as a single level cell (SLC) memory block. The controller of claim 16, wherein in the case where one of the memory cells in the specific block is used to store a plurality of bits, the plurality of bits are repeatedly written. Entering the memory cell for the predetermined number of times to cause the memory cell to be correctly programmed in the specific non-volatile memory element such that each of the plurality of bits is correctly stored in the memory cell For further reading. For example, the controller described in claim 17 of the patent application, wherein some of the materials in the receiving data When the amount of data of the Partial Data reaches a predetermined data threshold, the controller immediately writes the portion of the data to the at least one non-volatile memory component; and the storage capacity of the volatile memory is greater than or equal to the The product of the predetermined data threshold and the predetermined number of times to allow at least a portion of the received data to be used for repeated write operations of the memory cell. The controller of claim 18, wherein the predetermined data threshold is equal to a storage capacity of one of the memory cells belonging to one word line of the particular non-volatile memory component. The controller of claim 19, wherein any one of the plurality of blocks comprises a predetermined number of pages; the controller receives the complex array data from the master device, and the plurality of blocks The group data is temporarily stored in the volatile memory, wherein each of the sets of data in the complex array data comprises a plurality of pages, and the data amount of each of the set of data in the complex array data is equal to the threshold of the predetermined data amount; The controller reads at least one set of data in the complex array data from the volatile memory to directly write the at least one set of data to the specific block, wherein the at least one set of data is written into the specific block The number of times has not reached the predetermined number of times; and the specific material contains the at least one set of data.