TW201445002A - Methods for manganese nitride integration - Google Patents

Methods for manganese nitride integration Download PDF

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TW201445002A
TW201445002A TW103116581A TW103116581A TW201445002A TW 201445002 A TW201445002 A TW 201445002A TW 103116581 A TW103116581 A TW 103116581A TW 103116581 A TW103116581 A TW 103116581A TW 201445002 A TW201445002 A TW 201445002A
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layer
depositing
manganese nitride
seed layer
film
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TW103116581A
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TWI609095B (en
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Paul F Ma
Jennifer Meng Tseng
Mei Chang
Annamalai Lakshmanan
Jing Tang
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Applied Materials Inc
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.

Description

用於氮化錳整合之方法 Method for manganese nitride integration

本發明的實施例大體係關於半導體裝置中的阻障層及將之整合到半導體裝置。更特別地,本發明的實施例係關於包含氮化錳的薄膜整合。 Embodiments of the present invention relate to a barrier layer in a semiconductor device and to integrate it into a semiconductor device. More particularly, embodiments of the invention relate to thin film integration comprising manganese nitride.

諸如半導體或積體電路的微電子裝置包括數百萬個電子電路裝置,例如電晶體、電容器等。為進一步提高積體電路上的裝置密度,期有更小的特徵結構尺寸。為達成該等較小特徵結構尺寸,必須縮小導線、通孔與內連線、閘極等。可靠地形成多層內連線結構亦為提高電路密度與品質所需。製造技術的進步已得以將銅用於導線、內連線、通孔和其他結構。然隨著特徵結構尺寸減小及增加銅用於內連線,內連線結構中的電遷移變成難以克服的一大障礙。 Microelectronic devices such as semiconductor or integrated circuits include millions of electronic circuit devices, such as transistors, capacitors, and the like. In order to further increase the device density on the integrated circuit, there is a smaller feature size. In order to achieve these smaller feature sizes, the wires, vias, interconnects, gates, etc. must be reduced. Reliably forming a multilayer interconnect structure is also required to increase circuit density and quality. Advances in manufacturing technology have enabled copper to be used for wires, interconnects, vias, and other structures. However, as the size of the feature structure decreases and copper is used for the interconnect, the electromigration in the interconnect structure becomes a major obstacle that is difficult to overcome.

氮化鉭(TaN)的膜厚大於10埃時係銅阻障層,其中薄膜係連續的。然因Ta原子的直徑係約4埃,故約5埃厚的TaN薄膜並非連續。就需要薄TaN的小節點而言,TaN本身係不連續薄膜,以致限制TaN的銅阻障性。目前方法包括Ta層置於TaN層頂部,Ta層當作銅的濕潤層及提供阻障薄膜的連續性。然對更小的節點(小於32奈米(nm))而言,此 方法將造成更大的線路電阻,因此不是適當的解決方式。 When the film thickness of tantalum nitride (TaN) is more than 10 angstroms, the copper barrier layer is continuous, wherein the film is continuous. Since the diameter of the Ta atom is about 4 angstroms, the TaN film of about 5 angstroms thick is not continuous. For small nodes that require a thin TaN, TaN itself is a discontinuous film that limits the copper barrier of TaN. Current methods include the Ta layer placed on top of the TaN layer, the Ta layer serving as a wet layer of copper and providing continuity of the barrier film. For smaller nodes (less than 32 nanometers (nm)), this The method will result in greater line resistance and is therefore not an appropriate solution.

物理氣相沉積(PVD)氮化鉭(TaN)係用於銅內連線的標準擴散阻障材料。由於銅與TaN的附著性很差,故鉭襯層亦可用於增強內連線結構的耐久性。當銅內連線尺寸縮減成次20nm時,PVD TaN阻障層加上Ta襯層的非共形本性將引發問題,例如銅間隙填充孔洞和高線路電阻。原子層沉積(ALD)TaN用作具更佳共形性的先進技術;然ALD TaN薄膜品質仍需顯著改善。 Physical vapor deposition (PVD) tantalum nitride (TaN) is a standard diffusion barrier material for copper interconnects. Since the adhesion of copper to TaN is poor, the lining layer can also be used to enhance the durability of the interconnect structure. When the copper interconnect size is reduced to 20 nm, the non-conformal nature of the PVD TaN barrier plus the Ta liner will cause problems such as copper gap fill holes and high line resistance. Atomic Layer Deposition (ALD) TaN is used as an advanced technology with better conformality; however, the quality of ALD TaN films still needs to be significantly improved.

因此,此技術領域仍需有效的銅阻障薄層。 Therefore, there is still a need for an effective copper barrier layer in this field of technology.

本發明的一態樣係關於形成半導體裝置的方法,方法包含沉積包含氮化錳的薄膜至介電質上;沉積銅晶種層至薄膜上;及沉積銅填充層至銅晶種層上。以下列出各種實施例。應理解根據本發明的範圍,下列實施例不僅可如下述般結合,還可依其他適合方式結合。 One aspect of the invention is directed to a method of forming a semiconductor device comprising depositing a film comprising manganese nitride onto a dielectric; depositing a copper seed layer onto the film; and depositing a copper fill layer onto the copper seed layer. Various embodiments are listed below. It is to be understood that the following examples can be combined not only in the following, but also in other suitable ways in accordance with the scope of the present invention.

在一或更多實施例中,介電質係低介電常數(k)介電質。在一些實施例中,方法進一步包含在沉積包含氮化錳的薄膜前,沉積孔隙封膠至介電質上。在一或更多實施例中,沉積銅晶種層包含化學氣相沉積、原子層沉積、物理氣相沉積或電化學沉積。在一些實施例中,氮化錳係由原子層沉積沉積而得。在一或更多實施例中,方法進一步包含用氨電漿後處理來處理氮化錳薄膜。在一些實施例中,氮化錳和銅晶種層係在同一腔室中沉積。在一或更多實施例中,氮化錳具有Mn3N2的化學式。 In one or more embodiments, the dielectric is a low dielectric constant (k) dielectric. In some embodiments, the method further comprises depositing a pore sealant onto the dielectric prior to depositing the film comprising the manganese nitride. In one or more embodiments, depositing the copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition, or electrochemical deposition. In some embodiments, manganese nitride is deposited by atomic layer deposition. In one or more embodiments, the method further comprises treating the manganese nitride film with an ammonia plasma post treatment. In some embodiments, the manganese nitride and copper seed layers are deposited in the same chamber. In one or more embodiments, the manganese nitride has a chemical formula of Mn 3 N 2 .

本發明的第二態樣係關於形成半導體裝置的方法,方法包含沉積包含氮化錳的薄膜至介電質上;沉積包含鈷或釕的薄膜至包含氮化錳的薄膜上,或以鈷或釕摻雜氮化錳層;沉積銅晶種層;及沉積銅填充層至銅晶種層上。 A second aspect of the invention relates to a method of forming a semiconductor device comprising depositing a film comprising manganese nitride onto a dielectric; depositing a film comprising cobalt or germanium onto a film comprising manganese nitride, or cobalt or a germanium-doped manganese nitride layer; a copper seed layer deposited; and a copper fill layer deposited onto the copper seed layer.

在一或更多實施例中,介電質係低k介電質。在一些實施例中,方法進一步包含在沉積包含氮化錳的薄膜前,沉積孔隙封膠至低k介電質上。在一或更多實施例中,沉積銅晶種層包含化學氣相沉積、原子層沉積、物理氣相沉積或電化學沉積。在一些實施例中,氮化錳係由原子層沉積沉積而得。在一或更多實施例中,方法進一步包含用氨電漿後處理來處理氮化錳薄膜。在一些實施例中,氮化錳和銅晶種層係在同一腔室中沉積。在一或更多實施例中,沉積氮化錳及沉積包含鈷或釕的薄膜係在不破真空的情況下進行。在一些實施例中,氮化錳具有Mn3N2的化學式。 In one or more embodiments, the dielectric is a low-k dielectric. In some embodiments, the method further comprises depositing a pore sealant onto the low-k dielectric prior to depositing the film comprising the manganese nitride. In one or more embodiments, depositing the copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition, or electrochemical deposition. In some embodiments, manganese nitride is deposited by atomic layer deposition. In one or more embodiments, the method further comprises treating the manganese nitride film with an ammonia plasma post treatment. In some embodiments, the manganese nitride and copper seed layers are deposited in the same chamber. In one or more embodiments, depositing manganese nitride and depositing a film comprising cobalt or ruthenium is performed without breaking the vacuum. In some embodiments, the manganese nitride has a chemical formula of Mn 3 N 2 .

本發明的又一態樣係關於半導體裝置,包含:低k介電質;氮化錳層,位於低k介電質上;晶種層,選自銅晶種層或電化學沉積晶種層,且位於氮化錳層上;銅層,位於銅晶種層上。在一或更多實施例中,半導體裝置進一步包含含鈷或釕層,含鈷或釕層位於氮化錳層上、但在晶種層下。在一些實施例中,晶種層包含銅晶種層。 A further aspect of the invention relates to a semiconductor device comprising: a low-k dielectric; a manganese nitride layer on a low-k dielectric; a seed layer selected from a copper seed layer or an electrochemically deposited seed layer And located on the manganese nitride layer; the copper layer is located on the copper seed layer. In one or more embodiments, the semiconductor device further comprises a cobalt or germanium containing layer on the manganese nitride layer but below the seed layer. In some embodiments, the seed layer comprises a copper seed layer.

100‧‧‧微電子裝置 100‧‧‧Microelectronics

105‧‧‧基板 105‧‧‧Substrate

110‧‧‧介電層 110‧‧‧ dielectric layer

115‧‧‧側壁 115‧‧‧ side wall

120‧‧‧底部 120‧‧‧ bottom

130‧‧‧阻障層 130‧‧‧Barrier layer

140‧‧‧導電填充材料 140‧‧‧Electrical filling material

150‧‧‧溝槽 150‧‧‧ trench

160‧‧‧開口 160‧‧‧ openings

200‧‧‧低k介電質 200‧‧‧Low k dielectric

210‧‧‧孔隙封膠 210‧‧‧Pore sealant

220‧‧‧氮化錳薄膜 220‧‧‧Manganese nitride film

230‧‧‧銅晶種層 230‧‧‧ copper seed layer

240‧‧‧銅填充層 240‧‧‧copper filled layer

為讓本發明的上述概要特徵更明顯易懂,可配合參考實施例說明,部分實施例乃圖示在附圖。然應注意所附圖式僅說明本發明典型實施例,故不宜視為限定本發明範圍, 因為本發明可接納其他等效實施例。 In order to make the above summary of the present invention more obvious and understood, the description may be made in conjunction with the reference embodiments. It is to be understood that the appended drawings are merely illustrative of exemplary embodiments of the invention Because the invention is susceptible to other equivalent embodiments.

第1A圖及第1B圖圖示根據本發明一或更多實施例,沉積阻障層與導電填充材料前、後的介電層;及第2圖圖示根據本發明一或更多實施例的半導體裝置。 1A and 1B illustrate a dielectric layer before and after deposition of a barrier layer and a conductive filler material in accordance with one or more embodiments of the present invention; and FIG. 2 illustrates one or more embodiments in accordance with the present invention. Semiconductor device.

在描述本發明數個示例性實施例前,應理解本發明不限於以下提及的構造或製程步驟細節。本發明當能以各種方式實踐或實行其他實施例。 Before describing several exemplary embodiments of the present invention, it is understood that the invention is not limited to the details of the construction or process steps mentioned below. The invention can be practiced or carried out in various ways.

本發明的實施例係關於包含氮化錳的薄膜整合,以供後段內連線製程用。此薄膜可用作製造半導體裝置期間的銅阻障及/或銅濕潤材料。 Embodiments of the present invention relate to thin film integration comprising manganese nitride for use in a post-end interconnect process. This film can be used as a copper barrier and/or copper wetting material during the fabrication of semiconductor devices.

因此,本發明的一態樣係關於形成半導體裝置的方法,方法包含:沉積包含氮化錳的薄膜至介電質上;沉積銅晶種層至薄膜上;及沉積銅填充層至銅晶種層上。上述方法的數個變體將描述於後。 Accordingly, an aspect of the present invention is directed to a method of forming a semiconductor device, the method comprising: depositing a film comprising manganese nitride onto a dielectric; depositing a copper seed layer onto the film; and depositing a copper filled layer to the copper seed On the floor. Several variations of the above methods will be described later.

氮化錳沉積在介電材料上。介電層可由此技術已知方法提供。介電層可依需求鋪在其他層上面。在一或更多實施例中,介電質包含低k介電質。在此所用「低k介電質」一詞係指k值小於約4的介電材料。低k介電質的實例包括氟化矽酸鹽玻璃(FSG)(k=3.5)、Black Diamond I(k=3.0)、Black Diamond IIx(k=2.6)、Black Diamond III(k=2.2),但不以此為限。在一些實施例中,介電質係多孔的。在此實施例中,方法進一步包含在沉積包含氮化錳的薄膜前,沉積 孔隙封膠至介電質上。 Manganese nitride is deposited on the dielectric material. The dielectric layer can be provided by methods known in the art. The dielectric layer can be placed on top of other layers as needed. In one or more embodiments, the dielectric comprises a low-k dielectric. The term "low-k dielectric" as used herein refers to a dielectric material having a k value of less than about 4. Examples of low-k dielectrics include fluorinated silicate glass (FSG) (k=3.5), Black Diamond I (k=3.0), Black Diamond IIx (k=2.6), Black Diamond III (k=2.2), But not limited to this. In some embodiments, the dielectric is porous. In this embodiment, the method further comprises depositing before depositing a film comprising manganese nitride The pores are encapsulated onto the dielectric.

在一或更多實施例中,在此所用「氮化錳」可表示成「MnNx」。沉積包含氮化錳的薄膜可以任何適合方法進行。沉積方法可為原子層沉積(ALD)或化學氣相沉積(CVD)。錳對氮化物的量可表示為比率。在一或更多實施例中,Mn:N的原子比為約90:10至約20:80。適合的氮化錳薄膜相實例包括Mn4N、Mn3N2、Mn6N5,但不以此為限。在進一步實施例中,Mn:N比為約60:40,及/或相為Mn3N2In one or more embodiments, "manganese nitride" as used herein may be referred to as "MnN x ". Depositing a film comprising manganese nitride can be carried out by any suitable method. The deposition method may be atomic layer deposition (ALD) or chemical vapor deposition (CVD). The amount of manganese to nitride can be expressed as a ratio. In one or more embodiments, the atomic ratio of Mn:N is from about 90:10 to about 20:80. Examples of suitable manganese nitride thin film phases include Mn 4 N, Mn 3 N 2 , and Mn 6 N 5 , but are not limited thereto. In a further embodiment, Mn: N ratio of about 60:40, and / or phase Mn 3 N 2.

可以任何適當的沉積製程形成氮化錳層。例如,錳層可由交替層沉積(ALD)製程或電漿加強原子層沉積(PEALD)沉積而得。接著可利用化學氣相沉積(CVD)、物理氣相沉積(PVD)或ALD來沉積摻質。接著使摻質擴散到含錳層內,以形成整合的含錳摻質層。可利用不同製程,包括電漿處理或加熱,使摻質擴散到含錳層內。 The manganese nitride layer can be formed by any suitable deposition process. For example, the manganese layer can be deposited by alternating layer deposition (ALD) processes or plasma enhanced atomic layer deposition (PEALD) deposition. The dopant can then be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD) or ALD. The dopant is then diffused into the manganese-containing layer to form an integrated manganese-containing dopant layer. Different processes, including plasma treatment or heating, can be used to diffuse the dopant into the manganese containing layer.

在一些實施例中,使用有機金屬前驅物來沉積MnNx。在一些實施例中,避免具含氧配體的前驅物係有益的,因含氧配體會導致MnOx形成。形成於銅表面的氧化錳很難移除,以致將提高通孔電阻。一些前驅物具有極低的蒸汽壓和反應速率,此在腔室設計方面深具挑戰性且ALD沉積期間的薄膜形貌很差。一些前驅物實施例可利用CVD來產生高純度錳薄膜,及利用ALD產生高純度MnNx薄膜並具平滑形貌。 In some embodiments, the organometallic precursor is deposited MnN x. In some embodiments, to avoid having the precursor of the oxygen-containing ligands useful, because the oxygen-containing ligands may lead to formation of MnO x. The manganese oxide formed on the copper surface is difficult to remove, so that the via resistance will be increased. Some precursors have very low vapor pressures and reaction rates, which are challenging in chamber design and poor film morphology during ALD deposition. Some precursor embodiments can utilize CVD to produce high purity manganese films, and ALD to produce high purity MnN x films with a smooth topography.

有機金屬前驅物可包括矽基醯胺基錳錯合物。在一些實施例中,在標準ALD腔室中,由三甲基矽基醯胺基錳錯合物ALD MnNxThe organometallic precursor can include a mercaptoguanamine manganese complex. In some embodiments, in a standard ALD chamber, the trimethyl decyl guanamine manganese complex ALD MnN x .

在一些實施例中,使基板接觸第一前驅物和反應物。如在CVD反應中,可實質同時接觸該等前驅物,或者如在ALD反應中,可為相繼接觸。在特定實施例中,利用ALD來沉積氮化錳。本說明書與後附申請專利範圍所用「實質同時」一詞意指前驅物和反應物氣體一起流入腔室而與彼此和基板表面反應。熟諳此技術者將理解可能有基板區域只短暫接觸前驅物與反應物氣體之一,直到其他擴散到相同區域。 In some embodiments, the substrate is brought into contact with the first precursor and the reactants. As in the CVD reaction, the precursors may be substantially simultaneously contacted, or as in the ALD reaction, may be in sequential contact. In a particular embodiment, ALD is used to deposit manganese nitride. The term "substantially simultaneous" as used in this specification and the appended claims means that the precursor and reactant gases flow into the chamber to react with each other and the substrate surface. Those skilled in the art will appreciate that there may be a substrate area that only briefly contacts one of the precursor and reactant gases until the other diffuses into the same area.

在一些實施例中,含錳的有機金屬化合物具下列化學式: In some embodiments, the manganese-containing organometallic compound has the following chemical formula:

A個別選自碳或矽,R個別選自氫、甲基、取代或未取代烷烴、支鏈或非支鏈烷烴、取代或未取代烯烴、支鏈或非支鏈烯烴、取代或未取代炔烴、支鏈或非支鏈炔烴、或取代或未取代芳烴。錳的氧化態可為任何適於與基板或反應物反應的氧化態。在一些實施例中,錳係Mn(II)或Mn(III)。 A is individually selected from carbon or hydrazine, and R is each selected from hydrogen, methyl, substituted or unsubstituted alkane, branched or unbranched alkane, substituted or unsubstituted olefin, branched or unbranched olefin, substituted or unsubstituted alkyne A hydrocarbon, a branched or unbranched alkyne, or a substituted or unsubstituted aromatic hydrocarbon. The oxidation state of manganese can be any oxidation state suitable for reaction with a substrate or reactant. In some embodiments, the manganese is Mn(II) or Mn(III).

可在裸基板表面或存於基板表面的薄膜上沉積含錳薄膜。例如,含錳薄膜可沉積在存於表面的介電薄膜上。介電薄膜可具有各種具頂部、底部和側壁的結構(例如溝槽)形成於內。在一些實施例中,介電薄膜具有至少一溝槽,溝槽具有側壁和底部。底部可為介電質或介電質底下的表面(例如裸基板或其他材料)。可就不同表面選擇性沉積含錳薄膜。 在一些實施例中,就介電層或下層選擇性沉積含錳薄膜。 A manganese-containing film can be deposited on the surface of the bare substrate or on the film deposited on the surface of the substrate. For example, a manganese-containing film can be deposited on a dielectric film deposited on a surface. The dielectric film can have various structures (e.g., trenches) with top, bottom, and sidewalls formed therein. In some embodiments, the dielectric film has at least one trench having a sidewall and a bottom. The bottom portion can be a dielectric or dielectric underlying surface (eg, a bare substrate or other material). Manganese-containing films can be selectively deposited on different surfaces. In some embodiments, a manganese-containing film is selectively deposited in the dielectric layer or underlying layer.

在一些實施例中,A係氮原子。在一或更多實施例中,R基團係甲基。在一些實施例中,含錳的有機金屬化合物包含雙[雙(三甲基矽基)醯胺]錳。在一些實施例中,反應物係一或更多氨。儘管不侷限於任何特定操作理論,咸信在薄膜形成期間,Mn-N會斷鍵。故舉例來說,若使用氨,則可形成氮化錳薄膜。 In some embodiments, A is a nitrogen atom. In one or more embodiments, the R group is a methyl group. In some embodiments, the manganese-containing organometallic compound comprises bis[bis(trimethyldecyl)decylamine]manganese. In some embodiments, the reactant is one or more ammonia. Although not limited to any particular theory of operation, it is believed that Mn-N will break bonds during film formation. For example, if ammonia is used, a manganese nitride film can be formed.

在一些實施例中,介電質係多孔的,且需要孔隙封膠。適合的方法實例包括ALD SiO2及接觸N2O電漿。 In some embodiments, the dielectric is porous and requires a pore seal. Examples of suitable methods include ALD SiO 2 and contacting N 2 O plasma.

可利用此技術已知方法,沉積銅晶種層至包含氮化錳的薄膜上。方法包括化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)及/或電化學沉積(ECD),但不以此為限。 A copper seed layer can be deposited onto a film comprising manganese nitride using methods known in the art. Methods include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and/or electrochemical deposition (ECD).

視特定沉積模式而定,在同一腔室中進行一個以上的製程係有利的。在一或更多實施例中,氮化錳和銅晶種層係在同一腔室中沉積。在進一步實施例中,此類腔室含有至少二安瓿供沉積期間所需的不同化學品用。在替代實施例中,氮化錳和銅晶種層係在不同腔室中沉積。在一或更多實施例中,沉積氮化錳及沉積包含鈷或釕的薄膜係在不破真空的情況下進行。 Depending on the particular deposition mode, it may be advantageous to perform more than one process in the same chamber. In one or more embodiments, the manganese nitride and copper seed layers are deposited in the same chamber. In a further embodiment, such a chamber contains at least two ampoules for different chemicals required during deposition. In an alternate embodiment, the manganese nitride and copper seed layers are deposited in different chambers. In one or more embodiments, depositing manganese nitride and depositing a film comprising cobalt or ruthenium is performed without breaking the vacuum.

沉積銅晶種層後,沉積銅填充層至銅晶種層上。此可利用此技術已知方法進行,包括化學氣相沉積和物理氣相沉積,但不以此為限。 After depositing the copper seed layer, a copper fill layer is deposited onto the copper seed layer. This can be done using methods known in the art, including, but not limited to, chemical vapor deposition and physical vapor deposition.

在一或更多實施例中,所述方法進一步包含用氨 (NH3)電漿後處理來處理氮化錳薄膜。沉積銅填充層後,需研磨基板的表面。用含氨電漿後處理有助於避免施行化學機械研磨技術時裂化。在NH3後處理期間,將Mn:N比調整成富含氮的比率。增加MnN中的氮含量有助於避免CMP腐蝕。 In one or more embodiments, the method further comprises using an ammonia (NH 3) plasma treatment process after manganese nitride film. After depositing the copper fill layer, the surface of the substrate needs to be polished. Post-treatment with ammonia-containing plasma helps to avoid cracking when performing chemical mechanical polishing techniques. The Mn:N ratio was adjusted to a nitrogen-rich ratio during the NH 3 post treatment. Increasing the nitrogen content of MnN helps to avoid CMP corrosion.

可就特定薄膜、所用前驅物等選擇適合氨電漿處理的條件。接觸電漿期間的適合溫度大致為約150℃至約300℃。壓力大致為約0.5托耳至10托耳。間距大致為約100密耳至約500密耳。在40兆赫(MHz)下的射頻(RF)功率大致為約100瓦(W)至約1000W。NH3流率大致為約500至約5000sccm。稀有氣體電漿亦可用於製程。例如,可依約500至約5000sccm的流率流入氬。 The conditions suitable for the treatment of the ammonia plasma can be selected for the specific film, the precursor used, and the like. Suitable temperatures during contact with the plasma are from about 150 ° C to about 300 ° C. The pressure is approximately from about 0.5 Torr to 10 Torr. The spacing is generally from about 100 mils to about 500 mils. The radio frequency (RF) power at 40 megahertz (MHz) is approximately 100 watts (W) to approximately 1000 W. The NH 3 flow rate is approximately from about 500 to about 5000 sccm. Rare gas plasma can also be used in the process. For example, argon can be introduced at a flow rate of from about 500 to about 5000 sccm.

在一或更多實施例中,所述方法進一步包含沉積包含鈷或釕的薄膜至包含氮化錳的薄膜上。此可由此技術已知方法達成。 In one or more embodiments, the method further comprises depositing a film comprising cobalt or ruthenium onto the film comprising manganese nitride. This can be achieved by methods known in the art.

或者,鈷或釕可不為分離的不同層,而是氮化錳薄膜中的摻質。根據此態樣的一或更多實施例,阻障層包含氮化錳與選自錳(Mn)、鈷(Co)、釕(Ru)、鉭(Ta)、鋁(Al)、鎂(Mg)、鉻(Cr)、鈮(Nb)、鈦(Ti)和釩(V)的摻質。或者,錳和摻質可沉積於交替層。根據此實施例,第一含錳層(例如錳單層)沉積在介電薄膜上。雖然在此係描述介電薄膜做為沉積含錳薄膜的下層,但應理解下層可為任何適合層,包括金屬層或基底基板,但不以此為限。第一摻質層(例如摻質、摻質合金或其他含摻質化合物層)接著沉積在第一含錳層的頂部。此第一摻質層亦可為單層。第二 含錳層接著沉積在第一摻質層的頂部。反覆進行此製程,直到製造預定厚度的摻雜含錳薄膜為止。含錳層與摻質層可按任何適合比率結合,且不限於1:1。例如,可就每一摻質層沉積十個含錳層。 Alternatively, cobalt or ruthenium may not be a separate layer of separation, but a dopant in the manganese nitride film. According to one or more embodiments of this aspect, the barrier layer comprises manganese nitride and is selected from the group consisting of manganese (Mn), cobalt (Co), ruthenium (Ru), tantalum (Ta), aluminum (Al), and magnesium (Mg). ), a dopant of chromium (Cr), niobium (Nb), titanium (Ti), and vanadium (V). Alternatively, manganese and dopants can be deposited in alternating layers. According to this embodiment, a first manganese-containing layer (e.g., a manganese monolayer) is deposited on the dielectric film. Although a dielectric film is described herein as a lower layer for depositing a manganese-containing film, it should be understood that the lower layer may be any suitable layer, including a metal layer or a base substrate, but is not limited thereto. A first dopant layer (eg, a dopant, a dopant alloy, or other dopant-containing compound layer) is then deposited on top of the first manganese-containing layer. The first dopant layer may also be a single layer. second A manganese containing layer is then deposited on top of the first dopant layer. This process is repeated until a predetermined thickness of the doped manganese-containing film is produced. The manganese-containing layer and the dopant layer may be combined in any suitable ratio and are not limited to 1:1. For example, ten manganese-containing layers can be deposited for each dopant layer.

在一些實施例中,有一個以上的前驅氣體同時或分別流入處理腔室。例如,含錳前驅物和鈷前驅物可一起流入腔室而與表面反應。採用反應物可專用於前驅物種之一或通用於兩種物種。在一些實施例中,基板或表面接觸第一前驅物、然後為第一反應物,並接觸不同於第一前驅物的第二前驅物、然後為第一反應物或不同於第一反應物的第二反應物。 In some embodiments, more than one precursor gas flows into the processing chamber simultaneously or separately. For example, the manganese-containing precursor and the cobalt precursor can flow together into the chamber to react with the surface. The reactants can be used exclusively for one of the precursor species or for both species. In some embodiments, the substrate or surface contacts the first precursor, then the first reactant, and contacts a second precursor different from the first precursor, then the first reactant or a different one than the first reactant Second reactant.

為沉積摻質金屬,可使用適當的含金屬前驅物。適合的前驅物實例包括含預定摻質的金屬錯合物,例如與有機或甲基配體配位的摻質金屬。適合的摻質前驅物宜具有足夠的蒸汽壓,以於適當製程中沉積,例如ALD、CVD和PVD。視所用摻質前驅物而定,共反應物可用於沉積摻質。例如,諸如氫與氨的還原氣體可用作共反應物來沉積一些摻質。 To deposit the dopant metal, a suitable metal-containing precursor can be used. Examples of suitable precursors include metal complexes containing a predetermined dopant, such as a dopant metal coordinated to an organic or methyl ligand. Suitable dopant precursors preferably have sufficient vapor pressure for deposition in a suitable process, such as ALD, CVD, and PVD. Depending on the dopant precursor used, the co-reactant can be used to deposit dopants. For example, a reducing gas such as hydrogen and ammonia can be used as a co-reactant to deposit some dopants.

本發明的一些實施例提供在沉積導電材料前,用電漿處理摻雜的含錳薄膜。根據一或更多實施例,電漿包含一或更多He、Ar、NH3、H2和N2。可以各種方式沉積導電材料,包括無電沉積製程、電鍍(ECP)製程、CVD製程或PVD製程。在一些實施例中,第一晶種層沉積在阻障層上,大塊導電層接著形成在晶種層上。 Some embodiments of the present invention provide for treating a doped manganese-containing film with a plasma prior to depositing the conductive material. According to one or more embodiments, the plasma contains one or more of He, Ar, NH 3 , H 2 and N 2 . Conductive materials can be deposited in a variety of ways, including electroless deposition processes, electroplating (ECP) processes, CVD processes, or PVD processes. In some embodiments, a first seed layer is deposited on the barrier layer and a bulk conductive layer is then formed on the seed layer.

在一或更多實施例中,阻障層按錳層重量計包含0.1%至10%的摻質。在一些實施例中,阻障層包含0.2重量% 至8重量%的摻質。在特定實施例中,阻障層包含0.5重量%至5重量%的摻質。 In one or more embodiments, the barrier layer comprises from 0.1% to 10% by weight of the manganese layer. In some embodiments, the barrier layer comprises 0.2% by weight Up to 8% by weight of dopant. In a particular embodiment, the barrier layer comprises from 0.5% to 5% by weight of dopant.

本發明的另一態樣係關於以所述一或更多方法製造的半導體裝置。裝置將取決於方法如何使用。例如,當方法包含沉積包含氮化錳的薄膜至介電質上;沉積銅晶種層至薄膜上;及沉積銅填充層至銅晶種層上時,半導體裝置將包含位於銅晶種層上的銅填充層、位於包含氮化錳的薄膜上的銅晶種層和位於介電質上的銅晶種層。 Another aspect of the invention pertains to a semiconductor device fabricated in the one or more methods. The device will depend on how the method is used. For example, when the method includes depositing a film comprising manganese nitride onto a dielectric; depositing a copper seed layer onto the film; and depositing a copper fill layer onto the copper seed layer, the semiconductor device will comprise the copper seed layer A copper fill layer, a copper seed layer on the film comprising manganese nitride, and a copper seed layer on the dielectric.

在一實施例中,半導體裝置包含低k介電質;氮化錳層,位於低k介電質上;晶種層,選自銅晶種層或電化學沉積晶種層,且位於氮化錳層上;銅層,位於銅晶種層上。在方法包含沉積含鈷或釕層的實施例中,半導體裝置將進一步包含含鈷或釕層,含鈷或釕層位於氮化錳層上、但在晶種層下。在方法包含沉積晶種層的實施例中,半導體裝置將進一步包含銅晶種層。在進一步實施例中,晶種層包含電化學沉積晶種層。在一或更多實施例中,半導體裝置進一步包含孔隙封膠,孔隙封膠位於低k介電層上、但在氮化錳層下。 In one embodiment, the semiconductor device comprises a low-k dielectric; a manganese nitride layer on the low-k dielectric; and a seed layer selected from the group consisting of a copper seed layer or an electrochemically deposited seed layer and located in the nitride On the manganese layer; the copper layer is on the copper seed layer. In embodiments where the method comprises depositing a layer comprising cobalt or germanium, the semiconductor device will further comprise a layer comprising cobalt or germanium, the layer comprising cobalt or germanium being on the layer of manganese nitride but below the seed layer. In embodiments where the method includes depositing a seed layer, the semiconductor device will further comprise a copper seed layer. In a further embodiment, the seed layer comprises an electrochemically deposited seed layer. In one or more embodiments, the semiconductor device further comprises a pore encapsulant on the low-k dielectric layer but under the manganese nitride layer.

所用各種製程有許多結合方式。例如,方法可包含氮化錳沉積、然後氨後處理、銅晶種沉積,然後為習知銅電鍍。在一或更多其他實施例中,方法包含氮化錳沉積、鈷或釕沉積或摻雜、然後電化學晶種沉積,然後為電化學電鍍。在一些實施例中,方法包含氮化錳沉積、然後鈷或釕沉積或摻雜,然後為銅晶種及電化學電鍍。在一或更多實施例中,方法包含氮化錳沉積、然後鈷或釕沉積或摻雜、然後銅晶種 及電化學化學沉積晶種,接著為電化學電鍍。上述任一步驟之前可先進行多孔介電質的孔隙密封。方法的某些部分(例如電化學電鍍和電化學沉積)可在破真空後進行。 There are many ways to combine the various processes used. For example, the method can include manganese nitride deposition, then ammonia post treatment, copper seed deposition, and then conventional copper plating. In one or more other embodiments, the method comprises manganese nitride deposition, cobalt or tantalum deposition or doping, followed by electrochemical seed deposition, followed by electrochemical plating. In some embodiments, the method comprises manganese nitride deposition followed by cobalt or hafnium deposition or doping followed by copper seeding and electrochemical plating. In one or more embodiments, the method comprises manganese nitride deposition followed by cobalt or hafnium deposition or doping, followed by copper seeding And electrochemically depositing seed crystals, followed by electrochemical plating. The pore seal of the porous dielectric can be performed prior to any of the above steps. Certain portions of the process, such as electrochemical plating and electrochemical deposition, can be performed after vacuum breaking.

第1A圖圖示微電子裝置100的實施例,微電子裝置包含基板105和介電層110。介電層110沉積在基板105上,介電層110具有溝槽150,溝槽由溝槽底部120、側壁115和開口160所定義。 FIG. 1A illustrates an embodiment of a microelectronic device 100 that includes a substrate 105 and a dielectric layer 110. Dielectric layer 110 is deposited on substrate 105, which has trenches 150 defined by trench bottoms 120, sidewalls 115, and openings 160.

在一或更多實施例中,介電層110係低k介電層。在一些實施例中,介電層包含多孔的碳摻雜SiOx。在一或更多實施例中,介電層係多孔的碳摻雜SiOx層且k值小於3。 In one or more embodiments, the dielectric layer 110 is a low-k dielectric layer. In some embodiments, the dielectric layer comprises a porous carbon-doped SiO x. In one or more embodiments, the dielectric layer is a porous carbon doped SiO x layer and has a k value of less than 3.

第1B圖圖示沉積阻障層130後的同一微電子裝置100,阻障層覆蓋至少一部分的側壁115及/或溝槽底部120。如第1B圖所示,阻障層130覆蓋整個側壁115和溝槽底部120。阻障層130可包含MnNx和一或更多摻質,例如Co、Mn、Ru、Ta、Al、Mg、Cr、Nb、Ti或V。 FIG. 1B illustrates the same microelectronic device 100 after deposition of the barrier layer 130, the barrier layer covering at least a portion of the sidewalls 115 and/or the trench bottoms 120. As shown in FIG. 1B, the barrier layer 130 covers the entire sidewall 115 and the trench bottom 120. The barrier layer 130 may comprise MnN x and one or more dopants such as Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V.

在一或更多實施例中,阻障層按錳層重量計包含0.1%至10%的摻質。在一些實施例中,阻障層包含0.2重量%至8重量%的摻質。在特定實施例中,阻障層包含0.5重量%至5重量%的摻質。 In one or more embodiments, the barrier layer comprises from 0.1% to 10% by weight of the manganese layer. In some embodiments, the barrier layer comprises from 0.2% to 8% by weight of dopant. In a particular embodiment, the barrier layer comprises from 0.5% to 5% by weight of dopant.

根據一或更多實施例,在此所用「阻障層」一詞係指藉由沉積TaN和一或更多摻質而形成的不連續層,並且排除第二元素或摻質只擴散到部分阻障層內的區域。換言之,摻質係遍及TaN層的整個厚度,而非只在TaN層的表面部分。 In accordance with one or more embodiments, the term "barrier layer" as used herein refers to a discontinuous layer formed by depositing TaN and one or more dopants, and excluding the second element or dopant from diffusing only to the portion. The area within the barrier layer. In other words, the dopant system is throughout the thickness of the TaN layer, not just the surface portion of the TaN layer.

導電填充材料140填充至少一部分的溝槽150,溝 槽內加襯阻障層130。根據一或更多實施例,導電填充材料包含銅或銅合金。在其他實施例中,導電填充材料進一步包含鋁(Al)。 The conductive filler material 140 fills at least a portion of the trenches 150, trenches A barrier layer 130 is lined in the trench. According to one or more embodiments, the electrically conductive filler material comprises copper or a copper alloy. In other embodiments, the electrically conductive filler material further comprises aluminum (Al).

雖然第1B圖的導電填充材料140係顯示為直接接觸阻障層130,但導電填充材料140與阻障層130間可有中間層,例如黏著層或晶種層。根據一或更多實施例,微電子裝置進一步包含黏著層,黏著層包含一或更多Ru、Co和Mn。除Ru及/或Co外,黏著層可包含一或更多摻質,例如Ta、Al、Mg、Cr、Nb、Ti或V。在特定實施例中,黏著層包含Ru和Mn。除傳統襯層外,錳與氮化錳可做為襯層。例如,當以CVD Cu取代PVD Cu時,氮化錳係較佳襯層。又,氮化錳可還原成Mn而當作襯層,以促進與Cu的附著性。 Although the conductive fill material 140 of FIG. 1B is shown as directly contacting the barrier layer 130, there may be an intermediate layer, such as an adhesive layer or a seed layer, between the conductive fill material 140 and the barrier layer 130. In accordance with one or more embodiments, the microelectronic device further includes an adhesive layer comprising one or more of Ru, Co, and Mn. In addition to Ru and/or Co, the adhesive layer may comprise one or more dopants such as Ta, Al, Mg, Cr, Nb, Ti or V. In a particular embodiment, the adhesive layer comprises Ru and Mn. In addition to conventional linings, manganese and manganese nitride can be used as a liner. For example, when PVD Cu is replaced by CVD Cu, manganese nitride is preferred as a liner. Further, manganese nitride can be reduced to Mn to serve as a liner to promote adhesion to Cu.

在一些實施例中,晶種層沉積在阻障層的頂部。根據一或更多實施例,晶種層包含銅合金,例如Cu-Mn合金。在一些實施例中,晶種層包含少於約5重量%的Mn、少於約4重量%的Mn、少於約3重量%的Mn或少於約2重量%的Mn。在一或更多實施例中,晶種層包含約1重量%的Mn。含約1重量% Mn的銅合金的線路電阻預期將同於或類似純銅的線路電阻。 In some embodiments, a seed layer is deposited on top of the barrier layer. According to one or more embodiments, the seed layer comprises a copper alloy, such as a Cu-Mn alloy. In some embodiments, the seed layer comprises less than about 5% by weight Mn, less than about 4% by weight Mn, less than about 3% by weight Mn, or less than about 2% by weight Mn. In one or more embodiments, the seed layer comprises about 1% by weight Mn. The line resistance of a copper alloy containing about 1% by weight of Mn is expected to be the same as or similar to the line resistance of pure copper.

儘管不侷限於任何特定理論,據信摻質可選擇性擴散通過阻障層130而至介電層110,並與介電材料形成錯合物,此將能抵抗電遷移。故在一些實施例中,Mn擴散通過阻障層及形成MnSiOx。此自我形成的MnSiOx阻障層則可防止銅從導電材料140電遷移至介電層110。 Although not limited to any particular theory, it is believed that the dopant can selectively diffuse through the barrier layer 130 to the dielectric layer 110 and form a complex with the dielectric material that will resist electromigration. Therefore, in some embodiments, Mn and the diffusion barrier layer is formed by MnSiO x. This self MnSiO x barrier layer is formed of copper migration can be prevented from electrically conductive material 140 to the dielectric layer 110.

除做為銅阻障外,摻雜錳亦可阻礙氧從介電層110擴散到導電材料140。氧從介電層110擴散到導電材料140會導致氧與導電材料及/或晶種層中的組分反應。例如,氧會與阻障層130與導電材料140界面的層反應,致使Mn「釘扎」入阻障層/導電材料界面。同樣地,若存有包含Mn的晶種層,則氧會與晶種層/阻障層界面的晶種層中的Mn反應,並使Mn釘扎入界面。 In addition to being a copper barrier, doping manganese can also prevent oxygen from diffusing from the dielectric layer 110 to the conductive material 140. The diffusion of oxygen from the dielectric layer 110 to the conductive material 140 causes oxygen to react with components in the conductive material and/or seed layer. For example, oxygen will react with the layer at the interface of barrier layer 130 and conductive material 140, causing Mn to "pin" into the barrier/conductive material interface. Similarly, if a seed layer containing Mn is present, oxygen reacts with Mn in the seed layer at the interface of the seed layer/barrier layer, and Mn is pinned into the interface.

第2圖圖示根據本發明一或更多實施例的另一裝置。第2圖圖示低k介電質200,介電質具有數個特徵結構(即鑲嵌圖案化)。如上所述,此類低k介電質可為多孔的。如此,孔隙封膠210可沉積在低k介電質200上。孔隙封膠210上為氮化錳薄膜220。氮化錳薄膜220可為所述任一者。銅晶種層230可沉積在氮化錳薄膜220上。然後,可利用如化學氣相沉積製程來沉積銅填充層240。 Figure 2 illustrates another apparatus in accordance with one or more embodiments of the present invention. Figure 2 illustrates a low-k dielectric 200 having a plurality of features (i.e., damascene patterning). As noted above, such low k dielectrics can be porous. As such, the pore sealant 210 can be deposited on the low-k dielectric 200. On the pore sealant 210 is a manganese nitride film 220. The manganese nitride film 220 may be any of the above. A copper seed layer 230 may be deposited on the manganese nitride film 220. The copper fill layer 240 can then be deposited using, for example, a chemical vapor deposition process.

在一或更多實施例中,可在所述方法後對沉積銅施以化學機械研磨。沉積錳或MnNx薄膜可做為後段銅內連線製程的交替擴散阻障,以取代目前所用的PVD TaN或ALD TaN。沉積方式可和ALD TaN沉積整合,以產生錳摻雜的TaN或摻雜MnNx的鉭。在替代實施例中,可結合TaN和MnN層。 In one or more embodiments, the deposited copper can be subjected to chemical mechanical polishing after the method. The deposited manganese or MnN x film can be used as an alternating diffusion barrier for the subsequent copper interconnect process to replace the PVD TaN or ALD TaN currently used. The deposition mode can be integrated with ALD TaN deposition to produce manganese doped TaN or MnN x doped germanium. In an alternate embodiment, TaN and MnN layers can be combined.

根據本發明不同實施例的薄膜實際上可沉積在任何基板材料上。在此所用「基板表面」一詞係指於製造製程期間進行薄膜處理的任何基板或形成於基板上的材料表面。例如,進行處理的基板表面包括材料,例如矽、氧化矽、應變矽、絕緣層覆矽(SOI)、碳摻雜氧化矽、氮化矽、摻雜矽、 鍺、砷化鎵、玻璃、藍寶石、和任何其他材料,例如金屬、金屬氮化物、金屬合金和其他導電材料,此視應用而定。基板表面的阻障層、金屬或金屬氮化物包括鈦、氮化鈦、氮化鎢、鉭與氮化鉭、鋁、銅或任何其他可用於裝置製造的導體、或導電或非導電阻障層。基板可為各種尺寸,例如直徑200毫米(mm)或300mm的晶圓,且具有矩形或方形窗格。可用於本發明實施例的基板包括半導體晶圓,例如結晶矽(例如Si<100>或Si<111>)、氧化矽、應變矽、矽鍺、摻雜或未摻雜的多晶矽、摻雜或未摻雜的矽晶圓、III-V族材料(例如GaAs、GaN、InP等)和圖案化或未圖案化的晶圓,但不以此為限。基板可經預處理製程處理,藉以研磨、蝕刻、還原、氧化、羥化、退火、及/或烘烤基板表面。 Films in accordance with various embodiments of the present invention may actually be deposited on any substrate material. The term "substrate surface" as used herein refers to any substrate that is subjected to film processing during the manufacturing process or the surface of the material formed on the substrate. For example, the surface of the substrate to be processed includes materials such as tantalum, niobium oxide, strain tantalum, insulating layer coating (SOI), carbon-doped tantalum oxide, tantalum nitride, doped germanium, Niobium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. The barrier layer, metal or metal nitride on the surface of the substrate includes titanium, titanium nitride, tungsten nitride, tantalum and tantalum nitride, aluminum, copper or any other conductor that can be used in device fabrication, or a conductive or non-conductive resistive barrier. . The substrate can be of various sizes, such as a wafer having a diameter of 200 millimeters (mm) or 300 mm, and having a rectangular or square pane. Substrates useful in embodiments of the present invention include semiconductor wafers such as crystalline germanium (eg, Si<100> or Si<111>), hafnium oxide, strained germanium, germanium, doped or undoped polysilicon, doped or Undoped germanium wafers, III-V materials (such as GaAs, GaN, InP, etc.) and patterned or unpatterned wafers, but not limited to them. The substrate can be processed by a pretreatment process to grind, etch, reduce, oxidize, hydroxylate, anneal, and/or bake the substrate surface.

由於本發明的實施例提供沉積或形成摻雜的含錳薄膜的方法,故處理腔室可配置使基板於氣相沉積製程期間接觸一連串氣體及/或電漿。處理腔室可包括分離的反應物供應器和任何的載氣、淨化氣體和鈍氣(例如氬與氮)供應器,載氣、淨化氣體和鈍氣供應器流體連通各反應物與氣體的氣體入口。各入口可由適當的流量控制器控制,例如質量流量控制器或體積流量控制器,流量控制器連接中央處理單元(CPU),以容許各反應物流向基板,從而進行所述沉積製程。中央處理單元可為任一類型的電腦處理器,電腦處理器可用於工業設定來控制各種腔室和子處理器。CPU可耦接至記憶體,且可為一或更多容易取得的記憶體,例如隨機存取記憶體(RAM)、唯讀記憶體(ROM)、快閃記憶體、光碟、軟 碟、硬碟或任何其他類型的本端或遠端數位儲存器。支援電路可耦接至CPU,以藉由習知方式支援CPU。該等電路包括快取記憶體儲存器、電源、時脈電路、輸入/輸出電路和次系統等。 Since embodiments of the present invention provide a method of depositing or forming a doped manganese-containing film, the processing chamber can be configured to contact the substrate with a series of gases and/or plasmas during the vapor deposition process. The processing chamber may include a separate reactant supply and any carrier gas, purge gas, and a blunt gas (eg, argon and nitrogen) supply, the carrier gas, the purge gas, and the blunt gas supply fluidly communicate the gases of each reactant and gas Entrance. Each of the inlets may be controlled by a suitable flow controller, such as a mass flow controller or a volume flow controller, which is coupled to a central processing unit (CPU) to permit each reactant stream to the substrate to perform the deposition process. The central processing unit can be any type of computer processor that can be used in industrial settings to control various chambers and sub-processors. The CPU can be coupled to the memory and can be one or more easily accessible memories, such as random access memory (RAM), read only memory (ROM), flash memory, compact disc, soft. Disc, hard drive or any other type of local or remote digital storage. The support circuit can be coupled to the CPU to support the CPU in a conventional manner. These circuits include cache memory, power supplies, clock circuits, input/output circuits, and subsystems.

在原子層沉積型腔室中,可以空間或時間分離處理方式,使基板接觸第一前驅物和反應物。時間ALD(亦稱作時域ALD)係傳統製程,其中第一前驅物流入腔室而與表面反應(例如化學吸附)。在流入反應物至腔室前,驅淨腔室的第一前驅物。在空間ALD中,第一前驅物和反應物氣體同時流入腔室、但空間上分開,故氣流間會有區域防止前驅物混合。通常,在第一前驅物與反應物間會有氣體簾幕(例如淨化氣體、真空埠口或上述物質組合物),以確保分開。在空間ALD中,基板必須相對氣體分配板移動,反之亦然,使基板各部分得接觸第一前驅物與反應物氣體。 In an atomic layer deposition type chamber, the substrate may be contacted with the first precursor and the reactant by spatial or temporal separation. Time ALD (also known as time domain ALD) is a conventional process in which a first precursor stream enters a chamber to react with a surface (eg, chemisorption). The first precursor of the chamber is purged prior to flowing the reactants into the chamber. In space ALD, the first precursor and reactant gases flow into the chamber simultaneously, but are spatially separated, so there is an area between the gas streams to prevent precursor mixing. Typically, there will be a gas curtain (e.g., purge gas, vacuum rinse or combination of materials) between the first precursor and the reactants to ensure separation. In space ALD, the substrate must move relative to the gas distribution plate, and vice versa, so that portions of the substrate are exposed to the first precursor and reactant gases.

基板可在單一基板沉積腔室中處理,其中在處理另一基板前,裝載、處理及卸載單一基板。亦可以如運送系統般的連續方式處理基板,其中多個基板個別裝載至腔室的第一部分、移動通過腔室及自腔室的第二部分卸載。腔室和相關運送系統的形狀可構成直線路徑或彎曲路徑。此外,處理腔室可為迴轉料架,其中多個基板繞著中心軸移動,並在不同位置接觸沉積氣體。 The substrate can be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded prior to processing another substrate. The substrate can also be processed in a continuous manner as in a transport system wherein a plurality of substrates are individually loaded into the first portion of the chamber, moved through the chamber, and unloaded from the second portion of the chamber. The shape of the chamber and associated transport system may constitute a straight path or a curved path. Additionally, the processing chamber can be a rotating rack in which a plurality of substrates move about a central axis and contact the deposition gases at different locations.

共反應物通常呈蒸汽或氣體形式。反應物可偕同載氣輸送。載氣、淨化氣體、沉積氣體或其他製程氣體可含有氮、氫、氬、氖、氦或上述物質組合物。所述各種電漿(例 如氮電漿或鈍氣電漿)可由電漿共反應物氣體點燃及/或含有電漿共反應物氣體。 The co-reactant is usually in the form of a vapor or a gas. The reactants can be transported in the same carrier gas. The carrier gas, purge gas, deposition gas or other process gas may contain nitrogen, hydrogen, argon, helium, neon or a combination of the above. The various plasmas (examples For example, nitrogen plasma or blunt plasma can be ignited by a plasma co-reactant gas and/or contain a plasma co-reactant gas.

在一或更多實施例中,將各種製程用氣體脈衝供應至入口、通過氣體流道、從不同孔洞或出口而至中央流道。在一或更多實施例中,相繼脈衝供應沉積氣體並通過噴淋頭。或者,如上所述,氣體可同時流過氣體供應噴嘴或頭,基板及/或氣體供應頭可移動使基板相繼接觸氣體。 In one or more embodiments, various process gases are pulsed to the inlet, through the gas flow path, from different orifices or outlets to the central flow passage. In one or more embodiments, the successive pulses are supplied with a deposition gas and passed through a showerhead. Alternatively, as described above, the gas can flow simultaneously through the gas supply nozzle or head, and the substrate and/or gas supply head can be moved to cause the substrate to contact the gas sequentially.

本發明的另一態樣係關於用於沉積薄膜至基板上的設備,用以進行根據上述任一實施例的製程。在一實施例中,設備包含沉積腔室,用以沉積薄膜至基板上。腔室包含處理區域,用以支撐基板。設備包括流體連通錳前驅物供應器的前驅物入口,例如雙[雙(三甲基矽基)醯胺]錳。設備亦包括流體連通含氮前驅物供應器的反應物氣體入口,例如氨。設備亦包括流體連通摻質前驅物供應器的反應物氣體入口,例如含摻質的金屬錯合物。設備進一步包括淨化氣體入口,淨化氣體入口流體連通淨化氣體。設備可進一步包括真空埠口,用以自沉積腔室移除氣體。設備可進一步包括輔助氣體入口,用以供應一或更多輔助氣體至沉積腔室,例如鈍氣。沉積可進一步包括藉由輻射及/或電阻熱以加熱基板的裝置。 Another aspect of the invention relates to an apparatus for depositing a film onto a substrate for performing the process according to any of the above embodiments. In one embodiment, the apparatus includes a deposition chamber for depositing a film onto the substrate. The chamber contains a processing area for supporting the substrate. The apparatus includes a precursor inlet fluidly connected to the manganese precursor supply, such as bis[bis(trimethyldecyl)guanamine] manganese. The apparatus also includes a reactant gas inlet, such as ammonia, in fluid communication with the nitrogen-containing precursor supply. The apparatus also includes a reactant gas inlet fluidly connected to the dopant precursor supply, such as a dopant-containing metal complex. The apparatus further includes a purge gas inlet fluidly connected to the purge gas. The apparatus can further include a vacuum port for removing gas from the deposition chamber. The apparatus may further include an auxiliary gas inlet for supplying one or more auxiliary gases to the deposition chamber, such as an blunt gas. The deposition may further comprise means for heating the substrate by radiation and/or resistive heat.

在一些實施例中,施行所述方法以沉積或形成薄膜時可用的電漿系統和處理腔室或系統可在PRODUCER®、CENTURA®或ENDURA®系統上進行,該等系統皆取自位於美國加州聖克拉拉的應用材料公司。ALD處理腔室的詳細敘述可參見共同讓渡的美國專利案第6,821,563號、第6,878,206 號、第6,916,398號和第7,780,785號。 In some embodiments, the plasma system and processing chamber or system available for performing the method to deposit or form a film can be performed on a PRODUCER ® , CENTURA ® or ENDURA ® system, all of which are taken from California, USA. Santa Clara's Applied Materials. A detailed description of the ALD processing chamber can be found in U.S. Patent Nos. 6,821,563, 6,878,206, 6,916,398 and 7,780,785.

在一些實施例中,可在電漿加強原子層沉積(PEALD)製程期間,形成一或更多層。在一些製程中,電漿提供足夠的能量,以促進物種變成激態,而使表面反應變得有利又可行。可以連續或脈衝方式將電漿引入製程。在一些實施例中,使用相繼脈衝供應的前驅物(或反應氣體)和電漿來處理層。在一些實施例中,可於本地(即處理區域內)或遠端(即處理區域外)離子化試劑。在一些實施例中,可在沉積腔室上游進行遠端離子化,使離子或其他高能或發光物種不直接接觸沉積薄膜。在一些PEALD製程中,電漿係在處理腔室外產生,例如利用遠端電漿產生系統。可利用任何適合的電漿產生製程或熟諳此技術者已知技術來產生電漿。例如,可以一或更多微波(MW)頻率產生器或射頻(RF)產生器產生電漿。可依據所用特定反應物種,調整電漿頻率。適合頻率包括2MHz、13.56MHz、40MHz、60MHz和100MHz,但不以此為限。雖然本文所述沉積製程期間會使用電漿,但應注意也可不需要電漿。事實上,其他實施例係關於在無電漿且非常溫和條件下的沉積製程。 In some embodiments, one or more layers may be formed during a plasma enhanced atomic layer deposition (PEALD) process. In some processes, the plasma provides sufficient energy to promote the species to become excited, making the surface reaction beneficial and feasible. The plasma can be introduced into the process either continuously or in a pulsed manner. In some embodiments, the precursor is supplied with a precursor (or reactive gas) and a plasma supplied by a pulse. In some embodiments, the reagent can be ionized locally (ie, within the treatment zone) or distal (ie, outside of the treatment zone). In some embodiments, distal ionization can be performed upstream of the deposition chamber such that ions or other high energy or luminescent species do not directly contact the deposited film. In some PEALD processes, the plasma is generated outside of the processing chamber, such as with a remote plasma generating system. The plasma can be produced using any suitable plasma generating process or by techniques known to those skilled in the art. For example, plasma can be generated by one or more microwave (MW) frequency generators or radio frequency (RF) generators. The plasma frequency can be adjusted depending on the particular reaction species used. Suitable frequencies include 2MHz, 13.56MHz, 40MHz, 60MHz and 100MHz, but not limited to this. Although plasma is used during the deposition process described herein, care should be taken that plasma is not required. In fact, other embodiments are directed to deposition processes in the absence of plasma and under very mild conditions.

根據一或更多實施例,在形成層之前及/或之後,處理基板。此處理可在同一腔室或在一或更多不同的處理腔室中進行。在一些實施例中,基板從第一腔室移到不同的第二腔室供進一步處理。基板可從第一腔室直接移到不同的處理腔室,或者基板可從第一腔室移到一或更多移送室,然後移到不同的預定處理腔室。因此,處理設備可包含連接移送站 的多個腔室。此類設備稱作「叢集工具」或「叢集系統」等。 According to one or more embodiments, the substrate is processed before and/or after forming the layer. This treatment can be performed in the same chamber or in one or more different processing chambers. In some embodiments, the substrate is moved from the first chamber to a different second chamber for further processing. The substrate can be moved directly from the first chamber to a different processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then moved to a different predetermined processing chamber. Therefore, the processing device can include a connection transfer station Multiple chambers. Such devices are called "cluster tools" or "cluster systems".

通常,叢集工具係包含多個腔室的模組系統,腔室執行各種功能,包括基板中心找尋及定位、除氣、退火、沉積及/或蝕刻。根據一或更多實施例,叢集工具包括至少一第一腔室和中央移送室。中央移送室可容納機器人,用以在處理腔室與負載鎖定室間運送基板。移送室一般維持呈真空條件,且提供中間臺階供基板從某一腔室運送到另一腔室及/或位於叢集工具前端的負載鎖定室。兩種已知適於本發明的叢集工具為Centura®和Endura®,二者均取自美國加州聖克拉拉的應用材料公司。此一分階真空基板處理設備細節描述於西元1993年2月16日授予Tepman等人、名稱為「分階真空晶圓處理設備和方法(Staged-Vacuum Wafer Processing Apparatus and Method)」的美國專利案第5,186,718號。然為進行本文所述製程的特定步驟,可改變腔室的確切配置和組合方式。其他可用處理腔室包括循環層沉積(CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蝕刻、預清洗、化學清洗、諸如RTP的熱處理、電漿氮化、除氣、定位、羥化和其他基板處理,但不以此為限。藉由在叢集工具的腔室中進行處理,可避免基板表面在沉積後續薄膜前還未氧化即遭大氣雜質污染。 Typically, a cluster tool is a modular system that includes multiple chambers that perform various functions, including substrate center finding and positioning, degassing, annealing, deposition, and/or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot for transporting the substrate between the processing chamber and the load lock chamber. The transfer chamber is typically maintained in a vacuum condition and provides an intermediate step for the substrate to be transported from one chamber to another and/or to a load lock chamber at the front end of the cluster tool. Two clustering tools known to be suitable for the present invention are Centura® and Endura®, both of which are taken from Applied Materials, Inc., Santa Clara, California. The details of this stepped vacuum substrate processing apparatus are described in U.S. Patent No. entitled "Staged-Vacuum Wafer Processing Apparatus and Method" by Tepman et al., February 16, 1993. No. 5, 186, 718. The exact configuration and combination of chambers can be varied to perform the specific steps of the processes described herein. Other available processing chambers include cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, heat treatment such as RTP, electricity Slurry nitriding, degassing, positioning, hydroxylation and other substrate treatment, but not limited to this. By processing in the chamber of the cluster tool, it is possible to avoid contamination of the surface of the substrate by atmospheric impurities prior to deposition of the subsequent film.

根據一或更多實施例,基板持續處於真空或「負載鎖定」條件,並且從某一腔室移到下一腔室時,不會接觸周遭空氣。故移送室處於真空且在真空壓力下「泵回」。鈍氣可存於處理腔室或移送室。在一些實施例中,鈍氣用作淨化 氣體,以於基板表面上形成層後,移除部分或所有反應物。根據一或更多實施例,於沉積腔室的出口處,注入淨化氣體,以防止反應物從沉積腔室移到移送室及/或附加處理腔室。故鈍氣流將在腔室出口處形成簾幕。 According to one or more embodiments, the substrate is continuously under vacuum or "load lock" conditions and does not contact ambient air as it moves from one chamber to the next. Therefore, the transfer chamber is under vacuum and "pumped back" under vacuum pressure. Dull gas can be stored in the processing chamber or transfer chamber. In some embodiments, the blunt gas is used for purification The gas, after forming a layer on the surface of the substrate, removes some or all of the reactants. In accordance with one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and/or additional processing chambers. Therefore, the blunt airflow will form a curtain at the exit of the chamber.

基板可在單一基板沉積腔室中處理,其中在處理另一基板前,裝載、處理及卸載單一基板。亦可以如運送系統般的連續方式處理基板,其中多個基板個別裝載至腔室的第一部分、移動通過腔室及自腔室的第二部分卸載。腔室和相關運送系統的形狀可構成直線路徑或彎曲路徑。此外,處理腔室可為迴轉料架,其中多個基板繞著中心軸移動,並在整個迴轉路徑經沉積、蝕刻、退火、清洗等處理。 The substrate can be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded prior to processing another substrate. The substrate can also be processed in a continuous manner as in a transport system wherein a plurality of substrates are individually loaded into the first portion of the chamber, moved through the chamber, and unloaded from the second portion of the chamber. The shape of the chamber and associated transport system may constitute a straight path or a curved path. In addition, the processing chamber can be a rotating rack in which a plurality of substrates are moved about a central axis and are deposited, etched, annealed, cleaned, etc. throughout the rotating path.

處理期間,可加熱或冷卻基板。可以任何適合手段達成加熱或冷卻,包括改變基板支撐件的溫度及使加熱或冷卻氣體流至基板表面,但不以此為限。在一些實施例中,基板支撐件包括加熱器/冷卻器,加熱器/冷卻器經控制以傳導改變基板溫度。在一或更多實施例中,加熱或冷卻所用氣體(反應氣體或鈍氣),以局部改變基板溫度。在一些實施例中,加熱器/冷卻器設在鄰近基板表面的腔室內,以對流改變基板溫度。 The substrate can be heated or cooled during processing. Heating or cooling may be achieved by any suitable means, including changing the temperature of the substrate support and flowing the heating or cooling gas to the surface of the substrate, but not limited thereto. In some embodiments, the substrate support includes a heater/cooler that is controlled to conduct a change in substrate temperature. In one or more embodiments, the gas used (reactive gas or blunt gas) is heated or cooled to locally change the substrate temperature. In some embodiments, the heater/cooler is disposed within a chamber adjacent the surface of the substrate to convect the substrate temperature.

處理期間,基板亦可固定不動或轉動。基板可持續旋轉或按不連續階段轉動。例如,基板可在整個製程過程旋轉,或者基板可在接觸不同反應氣體或淨化氣體之間少量旋轉。處理期間轉動基板(無論持續或分階段)有助於最小化如氣流幾何形狀的局部變異影響,從而得到更均勻的沉積或 蝕刻。 The substrate may also be fixed or rotated during processing. The substrate can be rotated continuously or in a discontinuous phase. For example, the substrate can be rotated throughout the process, or the substrate can be rotated a small amount between contacting different reactive gases or purge gases. Rotating the substrate during processing (whether continuous or in stages) helps to minimize the effects of local variations such as gas flow geometry, resulting in more uniform deposition or Etching.

在原子層沉積型腔室中,可以空間或時間分離處理方式,使基板接觸第一和第二前驅物。時間ALD係傳統製程,其中第一前驅物流入腔室而與表面反應。在流入第二前驅物前,驅淨腔室的第一前驅物。在空間ALD中,第一和第二前驅物同時流入腔室、但空間上分開,故氣流間會有區域防止前驅物混合。在空間ALD中,基板必須相對氣體分配板移動,反之亦然。 In an atomic layer deposition type chamber, the substrate may be contacted with the first and second precursors by spatial or temporal separation. Time ALD is a conventional process in which a first precursor stream enters a chamber and reacts with a surface. The first precursor of the chamber is purged before flowing into the second precursor. In space ALD, the first and second precursors simultaneously flow into the chamber but are spatially separated so that there is an area between the gas streams to prevent precursor mixing. In space ALD, the substrate must move relative to the gas distribution plate and vice versa.

整份說明書提及的「一實施例」、「一些實施例」、「一或更多實施例」或「一個實施例」意指該實施例描述的特定特徵、結構、材料或特性係包含在本發明至少一實施例內。故說明書各處出現的如「在一或更多實施例中」、「在一些實施例中」、「在一實施例中」或「在一個實施例中」等用語不必然指稱本發明的同一實施例。另外,在一或更多實施例中,可以任何適合方式結合特定特徵、結構、材料或特性。 The description of "an embodiment", "an embodiment", "one or more embodiments" or "an embodiment" means that the particular features, structures, materials or characteristics described in the embodiments are included in the specification. At least one embodiment of the invention. Terms such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" are not necessarily referring to the invention. Example. In addition, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

雖然本發明已以特定實施例揭示如上,然應理解該等實施例僅為舉例說明本發明的原理和應用而已。在不脫離本發明的精神和範圍內,熟諳此技術者當可對本發明的方法和設備作各種更動與潤飾。因此本發明擬包括在後附申請專利範圍所界定範圍內的修改例與變化例和其均等物。 While the invention has been described above in terms of the specific embodiments, it is understood that the embodiments are merely illustrative of the principles and applications of the invention. Those skilled in the art can make various modifications and refinements to the methods and apparatus of the present invention without departing from the spirit and scope of the invention. The invention is intended to cover modifications and variations and equivalents thereof within the scope of the appended claims.

100‧‧‧微電子裝置 100‧‧‧Microelectronics

105‧‧‧基板 105‧‧‧Substrate

110‧‧‧介電層 110‧‧‧ dielectric layer

115‧‧‧側壁 115‧‧‧ side wall

120‧‧‧底部 120‧‧‧ bottom

150‧‧‧溝槽 150‧‧‧ trench

160‧‧‧開口 160‧‧‧ openings

Claims (20)

一種形成半導體裝置的方法,該方法包含:a.沉積包含氮化錳的一薄膜至一介電質上;b.沉積一銅晶種層至該薄膜上;及c.沉積一銅填充層至該銅晶種層上。 A method of forming a semiconductor device, the method comprising: a. depositing a film comprising manganese nitride onto a dielectric; b. depositing a copper seed layer onto the film; and c. depositing a copper fill layer to On the copper seed layer. 如請求項1所述之方法,其中該介電質係一低k介電質。 The method of claim 1, wherein the dielectric is a low-k dielectric. 如請求項1所述之方法,進一步包含在沉積包含氮化錳的該薄膜前,沉積一孔隙封膠至該介電質上。 The method of claim 1 further comprising depositing a pore sealant onto the dielectric prior to depositing the film comprising manganese nitride. 如請求項1所述之方法,其中沉積一銅晶種層包含化學氣相沉積、原子層沉積、物理氣相沉積或電化學沉積。 The method of claim 1, wherein depositing a copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition, or electrochemical deposition. 如請求項1所述之方法,其中該氮化錳係由原子層沉積沉積而得。 The method of claim 1, wherein the manganese nitride is deposited by atomic layer deposition. 如請求項1所述之方法,進一步包含用一氨電漿後處理來處理該氮化錳薄膜。 The method of claim 1, further comprising treating the manganese nitride film with an ammonia plasma post treatment. 如請求項1所述之方法,其中該氮化錳和該銅晶種層係在同一腔室中沉積。 The method of claim 1, wherein the manganese nitride and the copper seed layer are deposited in the same chamber. 如請求項1所述之方法,其中該氮化錳具有Mn3N2的一 化學式。 The method of claim 1, wherein the manganese nitride has a chemical formula of Mn 3 N 2 . 一種形成一半導體裝置的方法,該方法包含:a.沉積包含氮化錳的一薄膜至一介電質上;b.沉積包含鈷或釕的一薄膜至包含氮化錳的該薄膜上,或以鈷或釕摻雜該氮化錳層;c.沉積一銅晶種層;及d.沉積一銅填充層至該銅晶種層上。 A method of forming a semiconductor device, the method comprising: a. depositing a film comprising manganese nitride onto a dielectric; b. depositing a film comprising cobalt or germanium onto the film comprising manganese nitride, or Doping the manganese nitride layer with cobalt or antimony; c. depositing a copper seed layer; and d. depositing a copper fill layer onto the copper seed layer. 如請求項9所述之方法,其中該介電質係一低k介電質。 The method of claim 9, wherein the dielectric is a low-k dielectric. 如請求項10所述之方法,進一步包含在沉積包含氮化錳的該薄膜前,沉積一孔隙封膠至該低k介電質上。 The method of claim 10, further comprising depositing a pore sealant onto the low-k dielectric prior to depositing the film comprising manganese nitride. 如請求項10所述之方法,其中沉積一銅晶種層包含化學氣相沉積、原子層沉積、物理氣相沉積或電化學沉積。 The method of claim 10, wherein depositing a copper seed layer comprises chemical vapor deposition, atomic layer deposition, physical vapor deposition, or electrochemical deposition. 如請求項10所述之方法,其中該氮化錳係由原子層沉積沉積而得。 The method of claim 10, wherein the manganese nitride is deposited by atomic layer deposition. 如請求項10所述之方法,進一步包含用一氨電漿後處理來處理該氮化錳薄膜。 The method of claim 10, further comprising treating the manganese nitride film with an ammonia plasma post treatment. 如請求項10所述之方法,其中該氮化錳和該銅晶種層係 在同一腔室中沉積。 The method of claim 10, wherein the manganese nitride and the copper seed layer are Deposited in the same chamber. 如請求項10所述之方法,其中沉積該氮化錳及沉積包含鈷或釕的該薄膜係在不破真空的情況下進行。 The method of claim 10, wherein depositing the manganese nitride and depositing the film comprising cobalt or ruthenium is performed without breaking the vacuum. 如請求項10所述之方法,其中該氮化錳具有Mn3N2的一化學式。 The method of claim 10, wherein the manganese nitride has a chemical formula of Mn 3 N 2 . 一種半導體裝置,包含:a.一低k介電質;b.一氮化錳層,位於該低k介電質上;c.一晶種層,該晶種層選自一銅晶種層或一電化學沉積晶種層,且位於該氮化錳層上;d.一銅層,位於該銅晶種層上。 A semiconductor device comprising: a. a low-k dielectric; b. a manganese nitride layer on the low-k dielectric; c. a seed layer, the seed layer selected from a copper seed layer Or electrochemically depositing a seed layer on the manganese nitride layer; d. a copper layer on the copper seed layer. 如請求項18所述之半導體裝置,進一步包含一含鈷或釕層,該含鈷或釕層位於該氮化錳層上、但在該晶種層下。 The semiconductor device of claim 18, further comprising a cobalt or germanium containing layer on the manganese nitride layer but below the seed layer. 如請求項18所述之半導體裝置,其中該晶種層包含一銅晶種層。 The semiconductor device of claim 18, wherein the seed layer comprises a copper seed layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108315717A (en) * 2018-01-24 2018-07-24 复旦大学 A kind of preparation method of manganese nitride film
CN110804731A (en) * 2019-11-04 2020-02-18 江南大学 Mn grown by atomic layer deposition technologyxN film method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711456B2 (en) 2015-12-19 2017-07-18 International Business Machines Corporation Composite manganese nitride/low-K dielectric cap

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4478038B2 (en) * 2004-02-27 2010-06-09 株式会社半導体理工学研究センター Semiconductor device and manufacturing method thereof
US7253097B2 (en) * 2005-06-30 2007-08-07 Chartered Semiconductor Manufacturing, Ltd. Integrated circuit system using dual damascene process
CN101490811B (en) * 2006-07-14 2011-06-08 株式会社爱发科 Method for manufacturing semiconductor device
AU2008347088A1 (en) * 2007-04-09 2009-07-16 President And Fellows Of Harvard College Cobalt nitride layers for copper interconnects and methods for forming them
US7884475B2 (en) * 2007-10-16 2011-02-08 International Business Machines Corporation Conductor structure including manganese oxide capping layer
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
CN102859662B (en) * 2009-10-23 2015-11-25 哈佛大学校长及研究员协会 For the self-aligned barrier layers that interconnects and capping layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108315717A (en) * 2018-01-24 2018-07-24 复旦大学 A kind of preparation method of manganese nitride film
CN110804731A (en) * 2019-11-04 2020-02-18 江南大学 Mn grown by atomic layer deposition technologyxN film method

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