TW201444046A - Improving metal contacts to group IV semiconductors by inserting interfacial atomic monolayers - Google Patents

Abstract

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Description

Improve metal contact to Group IV semiconductors by inserting a single layer of interface atoms

The present invention relates to the insertion of a Group V or Group III atomic monolayer at the interface between a metal and a semiconductor, or the insertion of a double layer of a Group V atomic monolayer and a Group III atomic monolayer. A layer, or a technique of inserting a plurality of such double layers to reduce the specific contact resistance of a metal-semiconductor (Group IV) junction.

When the size of the transistor is reduced to the nanometer size, for example, it becomes an ultrathin body (UTB) insulating layer overlying cerium (SOI) field effect transistor (FET), fin field effect transistor (FinFET), and nanowire field effect. The form of a nanowire FET, but with the source and drain of the transistor, brings undesired resistance and is becoming more and more important to the performance of these components and the integrated circuit products made using these transistors. The burden. In addition, when the size of the source and drain regions of the transistor is reduced to less than about 10 nanometers (nm), it is theoretically expected and experimentally demonstrated to reduce dopant activation. Dopant activation means that the desired free carrier (electrons or holes) is contributed by intentionally introducing impurity species into the semiconductor host. This nano-level dopant activation is further reduced at the doped source/drain (S/D) region of the nano-scale metal contact. And creating an undesirably high resistance in the body portion of the nano-doped region. If the effective doping in the semiconductor is reduced, the resistance of the metal contact to the semiconductor will increase, which is mainly due to the occurrence of a Schottky barrier at the metal-semiconductor contact.

It is well known that high concentration doping in the shallow regions of the semiconductor close to the metal-semiconductor interface reduces the resistance of the metal-semiconductor contact by reducing the width of the Schottky barrier. Although the energy barrier width is reduced from the viewpoint of electrical reaction (for example, by current-voltage measurement), the Schottky height seems to be lowered. JMShannon was published in the 1976 issue of Solid-State Electronics, Vol. 19, pp. 537-543, entitled "Controlling Schottky barrier height using highly doped surface layers" (Control of Schottky barrier height using highly The early literature of doped surface layers) describes the use of surface doping to achieve this "effective barrier height" reduction. It is also known that a high concentration of dopant atoms can be introduced into a shallow region of a semiconductor close to a metal contact by utilizing a dopant segregation of a metal halide. A. Kikuchi and S. Sugaki reported in the May 1982 issue of J. Appl. Phys, No. 53, Volume 5, that during the formation of PtSi, the implanted phosphorus atoms accumulate near PtSi- At the Si interface, the height of the Schottky barrier of the n-type crucible is lowered. The measured (effective) energy barrier height of the Schottky diode is due to the fact that the phosphorus atoms accumulated in the sputum cause the energy barrier to be steeper. That is, the effect described by Shannon in 1976 caused this result.

Over the past few decades, the microelectronics industry has relied on having a high doping concentration in the bismuth near the metal-germanium contact as a means of achieving acceptable low contact resistance for the source and drain of the transistor. The contact metal is mostly a metal telluride, and most recently it is deuterated nickel or deuterated nickel-platinum. In the future, when the transistor size continues to shrink and the contact resistance becomes a larger part of the total resistance between the source and the drain (and thus becomes an important performance limiting factor), the method of reducing the contact resistance can be expected. Will not be used. The latest International Technology Technology Blueprint (ITRS) report released in 2011 pointed out that in 2014, the transistor gate length specification will reach 18 nm, and the specified specific contact resistance will not exceed 1.0x10 ^-8 ohms. . Square centimeters (Ohm.cm ² ), but there is no known solution to solve the contact resistance problem in bulk MOS transistors. It is increasingly shown that it is necessary to reduce the Schottky barrier at the metal-semiconductor contact to reduce the contact resistance to an acceptable level. Taking the doping source/drain contact of the MOS transistor as an example, the contact resistance is required to be much lower. 1.0x10 ^-8 ohms. Square centimeters. A technique capable of reducing the Schottky barrier and thereby reducing the resistance in contact with the doped semiconductor region can also be applied to a so-called "metal source/dip transistor" which does not have a doped The source and the drain, but the direct contact between the metal and the transistor channel (the transistor channel is a region containing free carriers, which can regulate the free carrier by the voltage on the gate and at the source and the drain Transfer current between).

In the literature published between 1991 and 1992, it was reported that Baroni, Resta, Baldereschi, and other scholars have experimentally demonstrated theoretical predictions. Experiments have shown that a double intralayer formed by two different elements can establish a interface even. Extremely, it not only modifies the heterojunction band discontinuities, but also creates band discontinuities in the homojunction. McKinley et al., J.Vac.Sci.Technol, May/June, issue A9(3), entitled "Borrowing Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers by the ultra-thin Ga-As dipole layer and in the Journal of Applied Surface Science in 1992 56~58 The first report in the article "Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers" on pages 762-765 and titled "Control of Ge homojunction band offsets via ultrathin Ga-As dipole layers" 035 to 0.45 electron volts (eV) can be obtained at the {111}-crystal Ge homojunction.

Arsenic, gallium and germanium deposition were performed on a p-type Ge (111) substrate at room temperature. The valence band offset is measured using in situ core level x-ray photoluminescence. It is confirmed that the deposited Ge region (cover layer) has a valence band offset for the Ge substrate by splitting the 3D core domain of germanium (Ge) into two parts; one part is caused by the Ge substrate, and the other part is caused by the Ge substrate, and the other part is It is caused by the Ge overlay. The Ga-As dipole intralayers can be introduced by the growth order of "Ga (Ga) first" or "Arsenic (As) first" to obtain a positive electricity valence band shift in the Ge homojunction or The negative price can be offset. At lower energies (i.e., more restrained), the band offset was found to be 0.35-0.45 eV, and the edge of the Ge-valent power band was on the arsenic (As) side of the junction. Harrison "Theoretical Chain Gold" as described in WA Harrison et al., 1978 Physics Review Journal (Phys. Rev. B 18, 4402, 1978) entitled "Polar Heterojunction Interfaces" Model to explain the dipole inner layer. Therefore, the use of an inner layer to control the discontinuity of the energy band can be applied to the homojunction to expand the potential area of the band offset engineering beyond the semiconductor heterojunction.

In 1992, following the report of McKinley et al., Marsi The microscopic manipulation of homojunction band lineups was published in the fourth issue of the Journal of Applied Physics (J. Appl. Phys), February 15, 1992, entitled "Microscopic manipulation of homojunction band lineups". The article, "J.Vac.Sci.Technol." Journal of July/August 1992, issue A10 (4), entitled "Using Dipole Inner Layer: Gallium" The article "Homojunction band discontinuities induced by dipolar intralayers: Al-As in Ge" and the "Applied Physics" issue of the 72nd issue of August 15, 1992 In the fourth volume, an article entitled "Local nature of artificial homojunction band discontinuities" is published. In the first article, Marsi et al. reported that when a triple-layer III-V inner layer of atomic thickness is inserted at the interface, a valence-energy band can be generated at the Si-Si and Ge-Ge homojunction junctions. Continuity. The in-situ core orbital X-ray photoluminescence method is also used to measure the discontinuity of the valence band. In the germanium (Ge) sample, it can be confirmed that the deposited Ge region (cover layer) has a valence band offset for the Ge substrate by splitting the 3d core track of germanium (Ge) into two parts; and by 矽 (Si) The splitting of the 2p core rail domain confirms that the deposited Si region has a valence band offset for the Si substrate. The degree of discontinuity observed is in the range of 0.4 to 0.5 eV (for example, the discontinuity of Si-P-Ga-Si is 0.5 eV, and the discontinuity of Si-P-Al-Si is 0.4 eV), And although most theories expect the dipole effect to cause large valence band discontinuities, this result is qualitatively consistent with theoretical predictions. If an anion is deposited first, the III-V inner layer at the homojunction of the group IV will systematically induce the discontinuity of the artificial valence band. It has also been reported that the use of aluminum-phosphorus (Al-P) in Si-Si homojunction Or the gallium-phosphorus (Ga-P) inner layer is taken as an example. As expected, reversing the interface deposition order leads to a reversal of the valence band discontinuity.

In the second article, X-ray photoluminescence was also used, and it was shown that aluminum-arsenic (Al-As) can be induced as a "dipole inner layer" between two {111}-crystal orientation regions. A similar energy band offset effect. In particular, the Ge (substrate)-As-Al-Ge (cover layer) order using "anion-preferred" will result in an offset of 0.4 eV, which is consistent with the results of the "anion-preferred" As-Ga sequence reported by McLinley. And the cover layer portion exhibits lower bonding energy than the substrate portion. The third article examines the multiple stacking of the III-V double layer (inner layer). The valence band offset values measured for a single double layer, two stacked double layers, and three stacked double layers are maintained equal to 0.5 eV. The experiments performed on 2 (Ga-P) and 2 (P-Ga) were identical to the experiments performed on 2 (Al-P) and 2 (P-Al); from a single double layer to two double layers Or even changed to three double layers, no significant increase in the valence band offset value was observed. The conclusion is therefore that stacking multiple III-V bilayers at the interface does not enhance the effect of a single bilayer, as opposed to the basic expectation based on multiple consecutive dipoles.

A metal-semiconductor contact is described by Grupp and Connelly in U.S. Patent Nos. 7,084,423, 7,176,483, 7, 462, 860 and 7, 884, 003, and U.S. Patent Application Serial No. 2011/0169124, the disclosure of which is incorporated herein by reference. The interface of the family semiconductor has an interfacial layer whereby the Schottky barrier at the contact is reduced and thereby reduces the specific resistivity of the contact. A monolayer of arsenic or nitrogen may be included in a possible embodiment or embodiment of the interface layer.

A distinguishing feature of the present invention is the organization of a deliberately introduced Group V or Group III atom (or Group II or Group VI atom) in a single ordered (e.g., epitaxially oriented) interface monolayer. Moreover, the present invention provides a process and structure in which metal contacts can be formed by deposition without the use of silicidation, which is characterized by allowing a wider range of metals to be used to form metal-semiconductor contacts, In particular, it has a metal which is superior to metal telluride in special applications, such as a metal having higher conductivity, light transmittance or ferromagnetism. When the dimensions of such elements are reduced to have a critical dimension of 20 nm or less (e.g., the width and height of the source), it is desirable to have maximum metal conductivity in the metal source/drain field effect transistor. For example, the elements of spin-effect transistors in the field of spintronics applications require efficient spin injection from semiconductors to ferromagnetic metals such as germanium. A spin-metal-oxide-semiconductor field-effect transistor (spin-MOSFET) having a ferromagnetic metal source and a drain and a Group IV semiconductor channel is an example of a spin-effect transistor. In illuminating displays, it is often desirable to have a metal contact that allows the emitted light to penetrate well (high transparency) while at the same time forming a low resistance contact for the active material. Conversely, in optoelectronic components (eg, semiconductor lasers or semiconductor modules), it may be desirable for the metal contact resistance to be opaque to minimize losses due to light absorption. The metal telluride has a somewhat undesirable property of transparency, which causes light energy to enter the telluride region in the light field of the photovoltaic element, which in turn causes light to be absorbed in the telluride.

The present invention does not require doping of a semiconductor in the vicinity of the metal contact, but the invention may also be practiced in conjunction with the semiconductor doping step. The invention also No metal deuteration steps are required. An element constructed in accordance with an embodiment of the present invention contains at least one ordered Group V element monolayer and/or an ordered Group III element monolayer at the interface between the semiconductor and metal contacts. The metal is deposited after forming at least one ordered interfacial atomic monolayer.

Embodiments of the present invention provide electrical contact between a Group IV semiconductor and a metal with one or more single layers, the semiconductor characterized by a crystalline lattice structure and a single atom formed from one or more Group V material atoms a layer or a single layer of monoatomic layers formed of one or more Group III material atoms, each monoatomic layer being epitaxially aligned with each other and epitaxially aligned with the semiconductor crystal lattice; and embodiments of the present invention provide for forming such a layer Method of electrical contact.

A further embodiment of the present invention provides an electrical contact comprising a metal and a Group IV semiconductor, and at the interface between the metal and the semiconductor, by a single layer of a Group V atom and a single layer of an optional Group III atom The metal and the semiconductor are opened. The metal may be made of the same metal element atom as the single layer of the Group III metal atom, or the metal may be made of a metal element atom different from the single layer of the Group III metal atom. In some examples, the Group III atom can be any one or more of: aluminum, gallium, indium, or boron, or a mixture of aluminum, gallium, boron, and/or indium. The Group IV semiconductor may be an alloy of ruthenium, osmium, iridium and ruthenium, an alloy of ruthenium and tin, an alloy or compound of ruthenium and/or ruthenium containing carbon. The Group V atom includes any one or more of the following: nitrogen, phosphorus, arsenic, and antimony. In some instances, a Group III atomic monolayer will be in close proximity to the surface of the Group IV semiconductor. In other examples, a Group V atomic monolayer will be in close proximity to the surface of the Group IV semiconductor. The surface of the Group IV semiconductor may be a {111}-crystal orientation surface or a {100}-crystal orientation surface.

The invention also includes methods of forming electrical contacts, such as those described above. In some examples, the method involves etching a {100}-crystallographic surface of the Group IV semiconductor using a crystallographically selective etch to expose and expose one or more {111}-crystal orientations. a semiconductor crystal plane; forming a Group V atom monolayer on the {111} plane; and subsequently depositing a Group III atomic monolayer on the Group V atom monolayer. The Group V and/or Group III atomic monolayers can be fabricated using individual vapor deposition processes or individual chemical reactions. For example, in a process performed under ultra-high vacuum (UHV) conditions, the {111}-crystal orientation of the semiconductor can be cleaned in situ prior to deposition of the Group V or Group III atoms, as appropriate. And heating the semiconductor to a sufficiently high temperature to obtain a recombination structure, a 7×7 recombination structure can be obtained by taking a {111}矽 surface as an example, or a 5×5 recombination structure can be obtained by taking a {111}矽锗 surface as an example. Alternatively, a 2×8 recombination structure can be obtained by taking the {111}锗 surface as an example, after which the semiconductor can be heated to an elevated temperature during the deposition of the Group V atom and/or the Group III atom. After forming the first group V group monolayer and the first group III metal atom monolayer, a metal atom may be directly deposited on the first bilayer (two monolayers), or a metal atom may be deposited Prior to forming the contact, additional Group V atomic monolayers and/or Group III atomic monolayers may be added to create a stack formed of multiple monolayers over a single bilayer.

The above and further embodiments of the present invention are described in further detail below.

10‧‧‧Process

12, 14, 16, 18‧ ‧ steps

20‧‧‧ surface

22, 24, 26, 28 ‧ ‧ atoms

30‧‧‧ corner hole

32‧‧‧Group V atoms

34‧‧‧矽 Surface atom

36‧‧‧Group IV Semiconductor

38‧‧‧Group V atomic monolayer

40‧‧‧Group III atomic monolayer

42‧‧‧Metal atoms

44‧‧‧Contact

45‧‧‧Process

46, 48, 50, 52, 54 ‧ ‧ steps

70‧‧‧ Curve

72‧‧‧ Curve

80‧‧‧ Curve

82‧‧‧ Curve

The drawings illustrate the invention by way of example and not of limitation,

Figures 1(a) and 1(b) illustrate the potential energy barrier at the metal-semiconductor junction; in particular, Figure 1(a) illustrates the semiconductor (left)-metal (right) interface There is a fixed thick energy barrier that hinders the current; and Figure 1(b) illustrates how the dipole layer interposed between the metal and the semiconductor eliminates the energy barrier except between a pair of atomic planes.

Figure 2 illustrates an example of a process for forming a metal contact having a very low resistance to a semiconductor surface in accordance with an embodiment of the present invention.

Figures 3(a), 3(b) and 3(c) provide a view of the 7 x 7 recombined {111}-crystal orientation surface.

Figure 4 illustrates an example in which a Group V atom is directly bonded to an exposed ruthenium surface atom to form a fully coordinated lattice terminal without a dangling bond.

Fig. 5 is a view showing the fabrication of a contact by inserting a double layer (two single layers) on the (111) surface of the n-type semiconductor by the process shown in Fig. 2 according to an embodiment of the present invention.

Figures 6(a) and 6(b) illustrate two bilayers at the (111) interface, respectively, in an n-type semiconductor having a field region spanning the interplanar spacing or the interplanar spacing.

Figure 7 is a diagram showing two layers of a p-type semiconductor as shown in Figure 6 in accordance with a further embodiment of the present invention, which provides a pole for the conduction of holes throughout the contact. Low resistance.

Figure 8 illustrates a process for establishing the contacts shown in Figure 7 in accordance with an embodiment of the present invention.

Figure 9 illustrates a single double layer (two single layers) for the {100} semiconductor surface as shown in Figure 5 but not for the {111} surface.

Figures 10 and 11 illustrate the Schottky dipole current-voltage characteristics obtained by experimentally contacting aluminum-{111} crystals to p-type germanium and measuring the contact with a single layer of arsenic atoms at the interface. Data and data without contact with the arsenic interface layer are compared.

In view of the above challenges, the inventors of the present invention have realized that there is a need for a metal contact technique capable of reducing the resistance of a metal contact to a doped S/D region, or a metal-semiconductor capable of eliminating a Schottky barrier between a metal and a semiconductor as much as possible. technology. Low resistance metal-semiconductor contact technology will be used in any application requiring low resistance, such as in solar cell applications and in metal S/D field effect transistors (FETs). The present invention relates to the insertion of a Group V or Group III atomic monolayer at the interface between a metal and a semiconductor, or the insertion of a double layer formed by a Group V atomic monolayer and a Group III atomic monolayer. , or a technique of inserting a plurality of such double layers to reduce the specific contact resistance of the metal-(Group IV) semiconductor junction. The present invention includes a method of forming such a metal-semiconductor contact having a very low energy barrier height (near zero) and a very low specific contact resistance by providing at least one single order alignment atomic layer at the interface between the metal and the semiconductor. The formed low specific resistance metal-Group IV semiconductor junction can be applied to semiconductor components (including electronic components such as transistors, diodes, etc.) and optoelectronic components (for example, laser, solar cell, light detection) As a low resistance electrode, and/or as a metal source and/or drain region (or part of the source/drain region). The Group V or Group III atomic monolayer adjacent to the semiconductor surface is primarily an ordered array of atomic layers formed on the surface of the Group IV semiconductor and chemically bonded to the Group IV semiconductor surface atoms.

The present invention differs from the earlier research work of Grupp and Connelly (cited above) in that the present invention focuses on a single layer arranged in an order, and contains a Group V element (for example, phosphorus or lanthanum) and a Group III element ( For example, aluminum, boron, gallium or indium). Furthermore, in the research work by Marsi et al. and McKinley et al. cited above, it is stated that it is intended to establish an energy band shift between two regions of the semiconductor, and there is no mention of modifying the Schottky energy between the metal and the semiconductor. Barriers or even the possibility of doing so.

As described below, if both the Group III atom and the Group V atom are present, the formed bilayer provides an electric dipole between the semiconductor and the host metal. When there is only a single Group V atomic layer, a similar dipole will also occur due to the formation of an image charge in the host metal. Moreover, in some instances, multiple bilayers (eg, two or three such bilayers) can be used between the semiconductor and the host metal. Indeed, the dipole layer can be added until the atoms themselves rearrange as the excess energy produced by the field increases.

Furthermore, although a single layer formed of a Group V or Group III pure material is described herein, certain embodiments of the invention may use atoms containing more than one Group V (eg, containing arsenic in a single layer and a mixture of phosphorus atoms) or a monolayer of one or more Group III atoms. Therefore, when a single layer (whether or not it is part of a double layer or otherwise) is mentioned in the following content and claims, the term shall be taken to cover a single layer formed by a single Group V or Group III atom. And a monolayer formed from more than one Group V or Group III element atom.

In the examples described herein, the semiconductor is a Group IV semiconductor, such as an alloy of ruthenium, osmium, iridium, and iridium, or contains ruthenium, osmium, carbon, and tin. An alloy of two or more elements. Field effect transistors (FETs) or other electronic components made from compound semiconductors can also benefit from the use of low resistance junctions provided in accordance with the present invention. Further in the following examples, the metal forming the junction with the semiconductor (and the interfacial layer formed by the ordered Group V atoms) is a Group III metal. However, this is not an inevitable situation. The metal does not have to be a Group III metal. Other metals, such as low work function metals such as magnesium, ytterbium or gadolinium, can also be used to achieve low potential (low electrical energy) barriers or high hole energy between the metal and the semiconductor. barrier. Alternatively, a high work function metal such as nickel, platinum, iridium or germanium may be used to obtain a low hole energy barrier or a high electron energy barrier between the metal and the semiconductor. However, this does not preclude the use of higher work function metals (eg, platinum or rhodium) to make contacts with low electron energy barriers. Although the metal has a high work function, a large dipole is established by causing an orderly arrangement of the Vth element monolayer at the semiconductor interface, so that the metal Fermi level and the conduction band (conduction band) The energy barrier between them may be low.

In many applications, the same metal is used to make contact with both p-type and n-type doped semiconductor regions, such as source contacts in p-channel field effect transistors and n-channel field effect transistors. Bungee contact may be beneficial. In addition, the above method will be used as a barrier metal (for example, tantalum nitride (TaN) or titanium nitride (TiN) or ruthenium (Ru)) and will be used to fabricate both p-type and n-type doped semiconductor regions. The metal in contact with may also be extremely advantageous. In the case of a low energy barrier contact in which both p-type and n-type doped semiconductor regions are formed using the same metal, the interface monolayer chemically bonded to the semiconductor surface will be in the order of the n-type contacts. V-group atomic interface layer, and will be in the p-type The Group III atomic interface layer in the order of the contacts. Similarly, when the same metal is used to form the metal source and/or drain of both the n-channel and the p-channel metal source/drain MOSFET, the interface monolayer chemically bonded to the semiconductor surface will be in position. The ordered Group V atomic interface layer at the source/drain junction of the n-channel MOSFET, and the ordered Group III atomic interface that will be located at the source/drain junction of the p-channel MOSFET Floor.

Ferromagnetic metals such as ruthenium, iron, nickel or cobalt or alloys of these elements or ferromagnetic alloys of manganese can be used to obtain metal-semiconductor contacts with high spin injection efficiency. In a particular application where high electron spin injection efficiency is desired, the interfacial layer chemically bonded to the surface of the semiconductor is preferably an ordered array of Group V atomic interface layers. The ferromagnetic metal may be deposited directly on the Group V monolayer, or the Group III metal monoatomic layer may be chemically bonded to the Group V atom and a ferromagnetic metal may be deposited on the Group III monolayer.

Other metal materials may also be used, including alloys of pure metals, metal tellurides (for example, nickel or platinum telluride or cobalt telluride having a composition of Ni ₂ Si, NiSi or NiSi ₂ ) or even semimetals, wherein the metal materials are directly Adjacent to the Group V or Group III monolayer. In manufacturing, both n-type and p-type semiconductor contacts use the same metal material, or use the same metal material as the metal source and/or drain of the n-channel and p-channel MOSFETs. Feasible and probably the most convenient.

In order to obtain a desired metal-semiconductor contact having a very low energy barrier height for electrons throughout the contact and a very low electrical resistance for electron conduction, the ordered atomic monolayer may be a sequentially ordered group V atom monolayer. The Group V atom may be a nitrogen atom, a phosphorus atom, an arsenic atom or a ruthenium atom or A mixture of these Group V atoms. In an embodiment of the invention, the Group V atom monolayer is an arsenic atom layer, and the arsenic atom layer is epitaxial (or substantially epitaxial) aligned and aligned with the yttrium or lanthanum or the IV semiconductor alloy crystal lattice. . Such a contact with very low electrical resistance to electron conduction can be used to make electrical contact with an n-type doped semiconductor (eg, an n-type doped source region and a drain region of an n-channel FET), or for fabrication Metal source/drain regions (the metal source/drain regions are in direct contact with the electron channels in the n-channel FET).

In many instances, the metal contact is formed on the surface of the Group IV semiconductor and the surface of the Group IV semiconductor will be a {111}-crystal orientation surface, and in the largest possible range, arranged in the single order. Each of the Group V atoms in the atomic layer forms a chemical bond with an atom in the {111} crystal orientation surface of the semiconductor in a three-way coordination manner. However, in other examples, the contact surface of the Group IV semiconductor will be a {100} or {110} surface. In some instances it may be better to have a {100} surface.

Before discussing the embodiments of the present invention in detail, it is helpful to review some basic theories. At the contact interface between the metal and the semiconductor, it can be observed that the Fermi energy in the metal is "pinned" at a specific energy in the semiconductor energy gap and causes each semiconductor to cause a metal Fermi level. An energy barrier is created between the conduction band or the valence band in the semiconductor. Although the semiconductor can conduct (for example, when a dopant is contained), as shown in the figure (1a), the Fermi energy E _{F is} fixed at a semiconductor band edge E _C close to the bulk crystal (when no voltage is applied, The E _F throughout the system is uniform) and E _{C is} maintained much higher than the E _F at the interface. Therefore, the region of the semiconductor near the interface cannot be a good conductor. Only a weak current can be transmitted between the metal and the strong conductive region of the semiconductor. Conducting electron flow into the conduction band by thermal ion emission (crossing the energy barrier by excitation) or by tunneling the energy barrier, and when the energy barrier may be only a few tens of angstroms (Angstrom) When tunneling, the probability of tunneling tends to be smaller. More broadly, current can be conducted between the metal and the semiconductor by the so-called "thermographic field emission", that is, the thermal ion emission combined with the tunneling of electrons through the energy barrier.

The present invention is directed to eliminating or at least substantially reducing the energy barrier by inserting an electric dipole layer between the metal and the semiconductor to offset the relative position of the energy band edge and the Fermi energy at the interface. The final energy is illustrated in Figure 1(b). The net result is that almost all of the energy barrier regions are removed, leaving only the energy barrier between the dipole layers.

Using the revised edition of Elementary Electronic Structure (2004) by WA Harrison, World Science Press (Singapore, 1999) and WA Harrison et al., 1978 Physics Review (Phys. Rev. B 18, 4402) The "Theoretical Chain Gold" described in the article entitled "Polar Heterojunction Interfaces" can best understand how to complete the bismuth-metal interface. Imagine removing a proton from each nucleus in the plane closest to the metal, converting the nucleus into an aluminum core (one of the elements on the left side of the periodic table) and inserting the proton into the 矽 lattice In the penultaneous nucleus in the penultimate plane, the nucleus becomes a phosphorous nucleus. This method effectively creates a negative charge in the atomic plane closest to the metal and a positive charge in the penultimate plane, and forms a dipole between the two atomic planes with a large electric field. . In fact, this electric field polarizes the bonds in this layer, and the bond in this layer is reduced to the inverse of the dielectric constant (1/12 = 0.083 for 矽), but the result is as in 5(a) The figure still shows a large electric field and a large potential shift. In fact, not only the bonds in the dipole layer are polarized, but also the bonds in the adjacent layers are polarized, changing the effective charge of all atoms in the region and making the electric field become as in 5(b). As shown in the figure. However, it results in a very similar potential shift (in the case of the (100) plane in 矽, which is estimated to be about 1.39 eV, and the bond length d = 2.35 Å), which is sufficient to remove the main energy barrier.

We can repeat the process of the theoretical chain metallurgy, remove another proton from the aluminum core, and turn the aluminum core into a magnesium core, and insert the proton into the phosphorus core to make the phosphorus core become a sulfur core. Apply the same concept, which doubles the charge on each plane and doubles the dipole offset. This is equivalent to inserting the plane of the atom in column II of the periodic table and the plane of the atom inserted in column VI, instead of columns III and V. Even in this method, the NaCl layer can be inserted for the third time, but in the present invention, in most cases, such deposition may make it impossible to maintain the epitaxial structure, and it is possible to form a neutral NaCl rock salt plane. Not a dipole layer. On the other hand, some noble metal halides do form a tetrahedral structure of yttrium, and it is expected that these noble metal halides can be epitaxially grown, equivalent to the single layer of the elements of column VII and the elements of column IB (precious metal). Single layer, and its dipole offset is estimated to be three times the dipole shift of the aluminum-phosphorus (Al-P) double layer. Accordingly, the present invention also includes dipole shifts caused by the epitaxial layers of columns VI, VII, II, and IB and columns V and III.

If instead of theoretically converting the last two planar germanium atoms into phosphorus and aluminum, change the actual atomic layer of phosphorus or any other element of column V between the tantalum and the metal and insert aluminum or other Single of the elements of column III One atomic layer, the result will not change. Any of the appropriately applicable Group V-Group III material bilayers can be used to achieve the elimination (or at least substantially) reduction of Schottky barriers, and can be selected according to convenience or other considerations. And likewise, any of the elements in columns IB, II, VI and VII can achieve the same effect as the elements mentioned in the above paragraphs. More specifically, it is possible to deposit a single layer of the Group VI element ~ sulfur and / or selenium and / or bismuth and combine the order of the group II element ~ zinc and / or cadmium to form a sequence of the second layer -VI double layer.

Returning now to Figure 2, Figure 2 illustrates a process example 10 for forming a metal contact having a very low resistance to a semiconductor surface. In this process, a {100}-crystal orientation surface of a Group IV semiconductor (or a Group IV semiconductor and/or carbon compound or alloy) is used (step 12), and the {100} is etched by crystal selective etching. - Crystallographically oriented surface to expose and expose one or more {111}-semiconductor crystal faces (step 14). Subsequently, a Group V atomic monolayer is formed on the {111}-plane (step 16), followed by deposition of a suitable Group III metal (step 18) to form the contact. It should be noted that the single layer of the group V atom is not necessarily a perfect order to arrange a single layer. That is, the Group V atomic monolayer may have some gap or a slight excess of atoms in terms of coverage. In other words, after depositing the ordered single layer, there may be some unsatisfied dangling bonds of the Group IV semiconductor, or the number of Group V atoms exceeds the number of dangling bonds of the earlier Group IV semiconductor. Or a portion of the semiconductor or Group V atoms on the surface become turbulent and cannot align the semiconductor lattice. However, any of the above cases is still considered to be a Group V atomic monolayer useful for the purposes of the present invention.

In another alternative process of the process described in FIG. 2, in step 18 The metal atom may be a metal atom other than the Group III metal atom. For example, the metal can be an alloy of pure metals, a metal halide or a metal compound.

The Group V atomic monolayer can be fabricated by a vapor deposition process or a chemical reaction. In an example of a vapor deposition process, the process includes exposing the semiconductor to the vapor stream of the Group V atomic vapor or the molecular stream of the Group V element at elevated temperatures. The Group V source/molecular gas stream can be generated by the evaporation of the source of the Group V element. In one embodiment of the invention, the gas stream is an arsenic molecular stream having a composition of As ₄ and can be utilized in a Knudsen cell (k-cell) as is known by molecular beam epitaxy. Heat evaporates the elemental arsenic source to form the As ₄ molecular stream.

Various manufacturing methods that can be used to deposit Group V and/or Group III monolayers include molecular beam epitaxy (MBE), gaseous source molecular beam epitaxy (GSMBE), organometallic molecular beam epitaxy (MOMBE), Organometallic Chemical Vapor Deposition (MOCVD), Organometallic Vapor Deposition (MOVPE), Atomic Layer Deposition (ALD), Atomic Layer Epitaxy (ALE), and Chemical Vapor Deposition (CVD), including electricity Crystal enhanced chemical vapor deposition (PECVD) or photon or laser-induced CVD.

Other vapor deposition processes that can be used in accordance with embodiments of the present invention involve dissociating a gas phase compound of the Group V element (e.g., a hydride of a Group V element) to deposit the Group V element atom on the semiconductor surface. . Suitable Group V hydride gases include ammonia (NH ₃ ) for the deposition of ammonia atoms, phosphine (PH ₃ ) for the deposition of phosphorus, arsine (AsH ₃ ) for the deposition of arsenic, and for deposition Deuterium atomized hydrogen (SbH ₃ ). Alternatively, the gas phase compound of the desired Group V element may be an organometallic compound, and an example of such a compound is an alkyl arsine for depositing an arsenic monolayer, such as tertiary butyl arsine. Or an alkyl hydrogen halide for depositing a tantalum monolayer, such as triethylstibine.

In a process carried out under ultra-high vacuum (UHV) conditions, the ruthenium having a {111}-crystal orientation surface may be cleaned in situ prior to exposing the ruthenium to a vapor stream of the Group V atom or compound. The crucible is heated to a sufficiently high temperature to obtain a 7 x 7 recombination structure of the {111}矽 surface. 3(a) (perspective), 3 (b) (plan view of the original unit cell), and 3 (c) (side view of the original unit cell) provide such a 7×7 surface 20 view. Atom 22 represents an atom in the underlying (1 x 1) host material. Atom 24 represents the so-called rest atom, a layer of atoms below the attached atom. Atom 26 represents a dimer (dimer, a pair of surface germanium atoms). Atom 28 represents an attached atom (a germanium atom placed on the surface of the crystal). Component symbol 30 represents a corner hole in the structure.

Thereafter, the crucible is maintained at a temperature ranging between about 20 ° C and 750 ° C (including the value of both ends) during exposure of the crucible to the vapor of the Group V atom or the vapor of the Group V compound molecule. The surface of the crucible can be exposed to a vapor stream of a Group V atom or compound molecule for a second or a few seconds or even for a few minutes. Keeping the crucible at a suitable temperature to form an ordered array of Group V atomic monolayers, and after formation, the monolayer can inhibit the deposition of additional Group V atoms or deposit other atoms (eg, hydrogen or oxygen or carbon atoms) . Or the semiconductor temperature may be changed during exposure of the semiconductor to the vapor of the group V atom vapor or the group V molecular compound, and the semiconductor temperature is lowered from a high temperature ranging from 600 ° C to 800 ° C to between 500 Lower temperature in the range of °C to 20 °C degree.

As shown in Figure 4, Group V atoms 32 (e.g., As, Sb, or P) are directly bonded to the exposed ruthenium surface atoms 34 to form a fully coordinated lattice termination, and are not suspended to the greatest extent possible. The key, Figure 4 is a side view of the resulting structure. Three of the valence electrons of the five valence electrons of each group V atom form a bond with the argon atom at the surface of the group IV semiconductor, and the remaining two valence electrons form a "single electron" as shown in the figure. Pair (lone-pair) track domain.

A similar process can be applied on the tantalum surface other than the {111} crystal orientation, for example, on the {100} crystal orientation of the tantalum surface to obtain a Group V atomic monolayer. A similar process can be applied to the surface of the Group IV semiconductor other than germanium, for example, on a semiconductor including germanium, antimony, bismuth, antimony, or antimony to obtain a Group V atom monolayer. Alternatively, a similar process can be applied to the surface of the Group IV semiconductor to obtain a Group VI atomic monolayer.

The heated semiconductor surface can be exposed to a Group V atomic stream or a stream of compound molecules in an ultra high vacuum (UHV) chamber, in a vacuum chamber, or in a reduced pressure chamber. If the chamber in which the process is performed is not a UHV chamber, background gas or carrier gas may be present during the exposure. In one embodiment, a gas mainly composed of hydrogen (H ₂₎ or nitrogen (N ₂₎ consisting of a mixture to form a diluted arsine to transport (AsH _3). In the semiconductor manufacturing process, the arsine is generally diluted to a concentration of several percent or even as low as 100 ppm, or the arsine is diluted in ultrapure hydrogen or nitrogen to a concentration of several percent or even as low as 100 ppm. . Whether it is pure arsine or a dilute mixture containing 1% or a few percent of arsine in hydrogen or nitrogen, arsine dissociates at the surface of the heated semiconductor to release free arsenic atoms, free The arsenic atoms are directly bonded to the exposed ruthenium surface to form a fully coordinated lattice termination with little or no dangling bonds.

A preferred process for depositing a single layer of arsenic atoms on a crucible with a hydride precursor gas (AsH ₄ ) begins by heating the surface of the crucible to a temperature in a hydrogen atmosphere sufficient to reduce any surface oxide, which is subsequently The surface is heated to a temperature in the range of 650 ° C to 750 ° C (optimally between 675 ° C and 725 ° C) while simultaneously exposing the surface to AsH ₄ vapor for between 10 seconds and 30 minutes (best Time between 20 seconds and 2 minutes). This process can be carried out in a CVD system or an ALD system and forms a ordered arsenic atomic monolayer. After this formation step, the monolayer resists depositing additional Group V atoms or depositing other atoms (such as hydrogen or oxygen or carbon atoms). Or the semiconductor temperature may be changed during exposure of the semiconductor to AsH ₄ vapor to lower the semiconductor temperature from a high temperature in the range of 650 ° C to 750 ° C to a lower range of 500 ° C to 20 ° C. temperature.

As mentioned above, it is not strictly required that the Group V atoms form a perfect single layer. Metal may be deposited on this Group V monolayer, or more germanium may be deposited and subsequently deposited. Therefore, there may be a charge monolayer at the interface layer (as described above), or if one, two or three germanium atom layers are deposited after the V-th layer single layer and before the metal, respectively, from the semiconductor There may be a charge monolayer at the second, third or fourth plane from the metal interface. The advantage of having one or more layers of germanium atoms between the charged Group V atom (ion) single layer and the metal atom and thereby separating the Group V atom (ion) single layer from the metal atom is that it can be increased The size of the electric dipole established between the layers, and thus the Schottky energy can be greatly reduced for the electrons at the metal-semiconductor junction barrier. On the other hand, the use of one or more germanium atomic layers to separate the charged Group V atom (ion) single layer from the metal atom has the disadvantage that the spatial extent of the dipole region is large and does not facilitate conduction of charge through the energy barrier. . The only advantage that can be thought of between having a layer of germanium atoms between a group V atom and a metal atom is that it can be used in applications where the p-type semiconductor has a large Schottky barrier.

In the embodiment shown in FIG. 5, after forming a coordinated Group V atom monolayer 38 on the surface of the {111}-crystallized Group IV semiconductor 36, a Group III atomic monolayer 40 is deposited, followed by The metal contact (host metal atom 42) is deposited while providing a low energy barrier and low resistance metal contact. In this embodiment of the invention, the metal atomic monolayer 40 is a Group III metal atomic layer which may comprise aluminum, gallium or indium or a mixture of these Group III metal atoms. In other embodiments of the invention, other metals or metal alloys other than the Group III metal, or other metals or metal alloys other than the Group III metal may be used in combination with the Group III metal. The Group III metal atom monolayer is optional, and the Group III metal atom monolayer does not necessarily have to be present in all junctions formed in accordance with the present invention, the image charge formed in the host metal (image charge) It will be a balanced negative charge (more on this below).

If a single layer of a Group III metal atom is present, the metal atom in the single layer of the metal atom preferably forms a coordination with a monolayer of the Group V atom already present in the surface of the semiconductor, thereby forming an ordered array of metal atoms. However, embodiments in which the metal atoms of the first layer are not strongly coordinately bonded to the underlying Group V atomic alignment layer by chemical bonding are also possible. Next, the process continues to deposit additional metal atoms 42 which may be the same metal element as the first layer of metal atoms or different from the first layer of metal atoms. metal element. Figure 5 illustrates the structure obtained if atom 40 and atom 42 are the same element.

A double layer comprising a Group V atom monolayer 38 and a Group III atomic monolayer 40 is disposed between the semiconductor atom 36 and the host metal 42 in FIG. The graphs (a) and (b) in the figure represent the potential energy at different positions across the junction, and the graph (a) shows the first step in the theoretical chaining that does not polarize the adjacent bonds. And the graph (b) is a curve drawn in consideration of relaxation. Curve (b) is somewhat exaggerated to emphasize the potential properties across the junction.

The Group III metal atom monolayer can be fabricated using a vapor deposition process or by chemical reaction. For example, in an example of a vapor deposition process, the metal atom monolayer can be formed on the semiconductor surface by exposing the semiconductor surface to an atomic vapor stream of a Group III metal element or a vapor stream exposed to the metal element compound. . This exposure step can be carried out for less than one second or for up to several seconds or even minutes.

The vapor deposition process may involve exposing a semiconductor having a Group V atomic monolayer to a metal atomic vapor stream or a stream of metal element molecules. The metal source can be vaporized using heat to produce the metal atom/molecular stream. In an embodiment of the invention, the gas stream is heated in a k-cell by means of heat, such as by molecular beam epitaxy, to evaporate the elemental aluminum source or to heat the elemental aluminum using an electron beam. A stream of aluminum atoms produced by the source to evaporate. The semiconductor can be heated during deposition of the metal atom. In an alternative vapor deposition process, a gas phase compound of the metal (eg, an organometallic compound) can be dissociated to deposit the metal atom on the surface of the semiconductor. This type of process is most often classified in chemical vapor deposition. Cheng. Suitable organometallic compounds for aluminum include trimethylaluminum. More specifically, when a metal atom monolayer is deposited by dissociating a chemical vapor source, if the metal atoms are epitaxially aligned and aligned to the semiconductor crystal lattice, the method is called atomic layer epitaxy, or These metal atoms are arranged by epitaxy, and this method is an atomic layer deposition method. In another alternative vapor deposition process, the metal atoms may be deposited by sputtering the metal atoms from a solid source in a known physical vapor phase (PVD) process.

After depositing the single layer of metal atoms, the process can be continued to deposit an additional layer of metal atoms (the metal atoms can be the same metal or different metals as the Group III atomic monolayer). The elemental composition and thickness of the additional metal atomic layer may depend on the particular application of the resulting metal-semiconductor contact. For example, as a contact of a nanoscale FET, the additional metal atomic layer may be a barrier metal layer such as tantalum nitride, titanium nitride or tantalum. In the terminology used herein and in the microelectronics industry, barrier metals are typically deposited using conformal deposition techniques such as atomic layer deposition (ALD), plasma enhanced ALD, or chemical vapor deposition (CVD). A thin metal layer that provides a barrier that prevents the copper metal layer from diffusing into the semiconductor. Alternatively, the barrier metal can be deposited using an electrochemical deposition process or by reactive physical vapor deposition (PVD), which is sputtered from a solid source or target. In an alternative embodiment, the additional metal atomic layer may be composed of a metal ruthenium, such as nickel hydride, platinum telluride, nickel ruthenium platinum or cobalt telluride having a composition of Ni ₂ Si, NiSi or NiSi ₂ , wherein the metal The telluride is directly adjacent to the Group V single layer or the Group V to Group III double layer.

In addition to depositing Group V materials on the surface of the crucible as previously described (eg In addition to a single layer of arsenic, phosphorus, etc., it is advantageous to deposit a portion of the Group V material at a sufficiently high temperature that some Group V atoms will enter the ruthenium itself at a sufficiently high temperature. Alternatively, the surface of the crucible can be prepared in other known ways such that the Group V is present near the surface of the crucible. After this step, the Group V material is deposited in a suitable manner to form a single layer on the surface of the crucible. The purpose of this practice is to facilitate the formation of additional dipoles by the additional Group V atoms in the crucible and to have an image charge in the metal deposited on the monolayer of the Group V material, which is beneficial to increase the overall dipole effect.

Figures 6(a) and 6(b) are further examples of metal-semiconductor contacts constructed in accordance with embodiments of the present invention. In the 6(a) diagram, the contact 44 is similar to the contact shown in Fig. 5, but the contact 44 contains an additional double layer formed of a Group V element and a Group III metal. An electric dipole is created across the long interlayer spacing (i.e., a relatively long distance between the single layer 38 and the single layer 40 that make up the bilayer). In Figure 6(b), contact 44' has an electric dipole across the short interlayer spacing (i.e., a relatively short distance between the single layer 38 and the monolayer 40 that make up the bilayer).

As shown in Fig. 7, in order to obtain a metal-semiconductor contact having a very low energy barrier height for the hole and a very low resistance for the conduction hole through the contact, the ordered atomic monolayer is an ordered metal. The atomic monolayer 40 and comprises a monoatomic layer 38 formed by a Group V atom that is chemically bonded to the metal atom monolayer and is separated from the surface atoms of the semiconductor 36 by the metal atom monolayer 40. In some embodiments, the monoatomic layer formed by the metal atom is a single layer of a Group III metal atom, and the Group III atom may be an aluminum atom, a gallium atom, or an indium atom or a mixture of these Group III metal atoms. Things. In some examples, the Group III metal atom monolayer is an indium atom layer, and the indium atom layer is epitaxial (or substantially epitaxial) aligned and aligned with the germanium or germanium or the IV semiconductor alloy crystal lattice, and the phase The adjacent Group V atomic monolayer is chemically bonded to the metal atom monolayer. The Group V atom may be a nitrogen atom, a phosphorus atom, an arsenic atom or a ruthenium atom or a mixture of these Group V atoms. In some examples, the single layer of the Group V metal atom is an arsenic atomic layer, and the arsenic atomic layer is arranged in an order and aligned with the Group III metal atom to form a chemical bond, and the Group III metal atom forms a single The atomic layer forms crystal alignment and chemical bonding with the surface atoms of the ruthenium or iridium or the crystal lattice of the IV semiconductor alloy. Two bilayers interposed between the semiconductor and the bulk metal are shown, but embodiments comprising a single bilayer are also contemplated within the scope of the present invention.

In some embodiments, it is desirable to form a contact having a very low resistance to a p-type semiconductor or to provide a source and/or a drain having a very high conductivity for use in a p-channel field effect transistor. The surface is a {111}-crystallographic semiconductor surface. In other embodiments, the contact surface of the semiconductor is a {100} crystal orientation surface.

Figure 8 illustrates a process 45 for establishing the contacts shown in Figure 7. Starting with a {100}-crystallized semiconductor surface (step 46), the {100} surface is etched using a crystal selective etch to expose and expose one or more {111}-crystallographic semiconductor faces ( Step 48). A Group III metal atom monolayer is formed on the {111} plane (step 50), followed by deposition of a Group V atomic monolayer (step 52). Obviously, based on different component geometries or other considerations, the existing {111} surface can be used directly as the beginning of the process.

After depositing a single layer of the Group V atom, the process continues to sink An additional plurality of metal layers are accumulated (step 54). The elemental composition and thickness of the additional metal atomic layer may be tailored to the particular application of the resulting metal-semiconductor contact, and may be formed as described above for the contact of an n-type semiconductor having very low electrical resistance to electron conduction. .

The Group III atomic monolayer can be fabricated using a vapor deposition process or a chemical reaction. In an example of a vapor deposition process, the semiconductor is exposed to a molecular stream of the Group III metal atomic vapor or the Group III metal element. The Group III atom/molecular gas stream can be produced by the evaporation of the source of the Group III element using heat. In one embodiment of the invention, the gas stream is an indium atomic stream formed by evaporation of an elemental indium source by heat in a k-cell as is known by molecular beam epitaxy. In an alternative vapor deposition process, a gas phase compound of a Group III element (eg, an organometallic compound of a Group III element) can be dissociated to deposit a Group III element atom on the surface of the semiconductor. Dissociation of the gas phase precursor compound of the Group III metal can be achieved by heating the surface of the semiconductor. If it is not appropriate to heat the surface of the semiconductor to too high a temperature, the disintegration can be achieved by means of a plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD) type of tool and process. Alternatively, a photon induced process can be utilized to dissociate the metal precursor.

The semiconductor having a {111}-crystal orientation surface may be cleaned in situ prior to exposing the semiconductor having the {111}-crystal orientation surface to a vapor stream of the Group III atom or the Group III molecular compound, for example, For example, the semiconductor can be heated to a sufficiently high temperature under ultra-high vacuum conditions to obtain a 7x7 recombination structure of the {111}矽 surface. Subsequently, the semiconductor is maintained during exposure of the semiconductor to the Group III atomic vapor or the Group III molecular compound vapor Temperatures in the range of from about 20 ° C to 750 ° C inclusive. Alternatively, the semiconductor temperature may be changed during exposure of the semiconductor to the Group III atomic vapor or the Group III molecular compound vapor, and the semiconductor temperature is lowered from a high temperature ranging from 600 ° C to 800 ° C to Lower temperatures in the range of 500 ° C to 20 ° C.

The semiconductor can be exposed to a Group III atom or compound vapor stream for a period of less than one second or for a few seconds or even minutes. The Group III atom is directly bonded to the exposed Group IV semiconductor surface to form a third atomic monolayer, the crystal of which is aligned to the semiconductor lattice to the greatest extent possible.

The surface of the semiconductor can be exposed to a Group III atomic stream or a molecular compound vapor stream in a UHV chamber, in a vacuum chamber, or in a reduced pressure chamber. If the chamber in which the process is performed is not a UHV chamber, background gas or carrier gas may be present during the exposure. In one embodiment, the organometallic compound precursor (eg, trimethylindium) is delivered in a dilute formation with a gas mixture consisting essentially of a carrier gas (eg, hydrogen or nitrogen), and the organometallic compound precursor is The heated semiconductor surface dissociates to release free indium atoms, and the free indium atoms are directly bonded to the exposed germanium. In another embodiment, the organometallic compound is trimethylaluminum or trimethylgallium, and trimethylaluminum or trimethylgallium is reacted at the surface of the heated semiconductor to form a single layer of aluminum atoms or gallium atoms, respectively. Single layer.

After forming a coordinated Group III metal atom monolayer on the surface of the {111}-crystallized Group IV semiconductor, a Group III atomic monolayer 40 is deposited, followed by deposition of a Group V atom to form a low energy barrier, low Metal contact of the resistor. Preferably, the Group V atom of the Group V atomic layer is already on the surface of the semiconductor. The Group III metal atom monolayer is coordinated to form an ordered Group V atomic layer. Subsequently, the process continues to deposit additional metal atoms which may be the same metal element as the first layer of metal atoms or a different metal element than the first layer of metal atoms.

In another embodiment of the present invention, after forming a coordinated Group III metal atom monolayer on the surface of the {100} or {111}-crystallographic Group IV semiconductor, it may then be deposited on the monolayer The metal is in contact with a metal that forms a low energy barrier and low resistance. The metal is not necessarily a Group V metal. The metal may be a metal having desirable properties, such as structural or chemical stability to ensure the reliability of the electrical contacts or electronic components formed. Examples of the stabilizer metal used to form the contact include platinum (Pt), tungsten (W), and the aforementioned "barrier metal": TaN, TiN, and Ru. The metal may be deposited directly on the Group III monolayer such that the Group III monolayer is located just at the interface between the metal and the semiconductor, or may be separated by one or two Group IV semiconductor monolayers Group III monolayer and the metal. Therefore, if one or two Group IV semiconductor atomic layers are respectively interposed between the Group III single layer and the metal, there may be a presence at the interface layer or at a third plane from the semiconductor-metal interface. There is a single layer charge brought by the III single layer. The advantage of having one or several layers of germanium atoms between the charged third atom (ion) single layer and the metal atom and thereby separating the charged third atom (ion) single layer from the metal atom is that it can be increased The size of the electric dipoles established between the layers, and thus the Schottky barrier at the p-type semiconductor junction or the metal of the MOSFET and the p-type channel source/drain junction.

Another embodiment of the invention forms a metal semiconductor contact having a Group V or III at the metal-semiconductor interface a family of atomic monolayers, and at the metal-semiconductor interface, the Group V (eg, arsenic) monolayer is formed by segregating a Group V or Group III atom from a layer of material in contact with the surface of the semiconductor. Or a Group III (eg, boron) monolayer. The layer of material can be deposited on the surface of the semiconductor, for example using CVD or PVD. The Group V group atoms are introduced into the material layer by incorporating a Group V atom into the CVD or PVD deposition process as a dopant or by ion implantation. Alternatively, the material layer may be formed by reacting another element or elements with a semiconductor surface, in which case the group V or group III may be implanted before or after the material is formed by a chemical reaction. atom. For example, the layer may be a layer of yttrium oxide or tantalum nitride formed by subjecting the surface of the tantalum to thermal oxidation, and ion implantation may be used to introduce a Group V or Group III atom into the tantalum oxide or tantalum nitride layer. Inside. In another embodiment, the layer may be a deposited film formed of yttrium oxide doped with a high concentration of a Group V element (eg, phosphorus) or a Group III element (eg, boron). The former is generally considered to be "phosphorus bismuth glass (PSG)" and the latter is usually "boron bismuth glass (BSG)", and methods for depositing such doped tellurite glasses (for example, CVD) are widely known and widely used. Used in the microelectronics industry. Alternatively, the layer of material may be a metal halide formed by reacting a metal with a surface of the crucible, and a Group V or Group III atom may be introduced into the metal halide layer by ion implantation.

After introducing a concentration of Group V or Group III atoms into the material layer in contact with the surface of the semiconductor, the entire layer structure is annealed at a sufficiently high temperature to cause segregation of the Group V or Group III atoms. Segregate to the interface, at which an ordered Group V or Group III monolayer is formed, and the Group V or Group III atoms are epitaxially coordinated to the top layer of the semiconductor atom. The material layer is doped cerium oxide (eg, PSG or BSG) Or in the case of tantalum nitride and the semiconductor is germanium, after the annealing cycle causes a part of the group V or group III element to segregate to the interface of the germanium-yttria (or tantalum nitride), then the selection may be utilized. Moisture chemical etching removes the hafnium oxide (niobium nitride) leaving a coordinated Group V or Group III atomic monolayer at the surface of the semiconductor and depositing a metal to form a metal contact of the semiconductor . In the example where the material layer is a metal telluride and the semiconductor is germanium, the metal germanide can be removed after the annealing cycle causes interfacial segregation of the group V or group III elements to form an ordered interfacial monolayer. Or leaving the metal telluride in place, with the metal telluride itself being in contact with the metal.

Still other embodiments of the invention relate to the use of {100}-crystal oriented semiconductor surfaces. Figure 9 illustrates a contact comprising such a surface comprising a Group V atomic monolayer, and the Group V atomic deposit can be deposited on the IV semiconductor {100} surface using any of the techniques described above. Floor. A single layer of a Group III metal atom is then deposited on the Group V atom, followed by deposition of an additional metal layer. These additional metal atoms may be the same metal element as the first layer of metal atoms, or these additional metal atoms may be different metal elements than the first layer of metal atoms. The metal-semiconductor contact shown in Figure 9 provides an extremely low energy barrier height for electrons and provides extremely low resistance for electron conduction through the electrical conduction of the contact. If the contact is to provide an extremely low energy barrier height for the electron and provide a very low resistance for the electrical conduction of the hole through the contact, the position of the Group V atom and the Group III atom in the double layer can be made to each other. Reversed.

The Schottky dipole for the experiment was fabricated to illustrate the effect of the arsenic interface monolayer on the exemplary aluminum-germanium-based energy barrier. These demonstration experiments are not representative of typical process conditions and do not necessarily represent optimal process conditions. These exemplary experiments were performed on a {111}-crystallized p-type doped germanium wafer having a boron concentration of about 1 x 10 ¹⁷ atoms/cm 3 . A first set of Schottky dipoles for the experiments were fabricated under ultra-high vacuum conditions, and a second set of Schottky dipoles for the experiments were fabricated under low pressure chemical vapor deposition conditions in a hydrogen atmosphere.

The first set of dipoles are treated in the following manner: after heating the crucible at 800 ° C in an ultra-high vacuum to clean the {111} Si surface and recombining the {111} Si surface into a 7×7 recombination structure, the temperature is varied from The temperature was lowered to 700 ° C at 800 ° C and the surface of the crucible was subsequently exposed to the As ₂ arsenic molecular stream for 10 minutes before the As ₂ gas stream was terminated. Using the Rutherford back scattering analysis, it was confirmed that the surface density of the arsenic atoms obtained by this exposure step was equal to 7.30 x ^{10 14} atoms/cm 2 , which is close to the known surface of the 1 × 1 recombination {111} The surface density of the surface atoms on the surface is 7.83x10 ¹⁴ atoms/cm 2 . Thus, it can be reasonably concluded that a single layer of arsenic atoms has been deposited. After cooling to room temperature, a layer of pure aluminum is deposited in the same ultra-high vacuum system and the layer of pure aluminum is subsequently patterned to provide a simple dipole structure for electrical measurements. For comparison, a similar wafer can be processed in a similar sequence, except that the surface of the crucible is not intentionally exposed to any arsenic atoms. Figure 10 illustrates the measured current-voltage characteristics of these experimental dipoles after measurements of the same size dipoles on each wafer (containing arsenic and no arsenic). As shown by measurement curve 72 of Figure 10, the dipoles that do not contain arsenic at the interface on the wafer consistently exhibit a relatively small Schottky barrier height for p-type germanium. From curve 72, the height of the energy barrier can be obtained by fitting the measurement data using a standard dipole equation (thermionic emission model). The height of the dipole of the dipole obtained without exposure to arsenic is 0.40 eV (experimental error is about 0.03 eV), and the height of the barrier is the same as the height of the barrier of the closed aluminum on the disclosed p-type crucible. . As shown by the data curve 70 in FIG. 10, the dipole forming the arsenic monolayer on the wafer after exposing the tantalum interface to arsenic consistently exhibits a large Schottky barrier height for the p-type germanium. . According to the sum of the heights of the n-type and p-type barriers, the general rule of the band gap is very close. The larger barrier height of the p-type 就 means that the n-type 矽 has a smaller energy barrier height. . Therefore, experiments have shown that the introduction of a single layer of arsenic atoms at the interface between aluminum and the {111}-crystal orientation surface, for p-type germanium, does provide a large Schottky barrier, which is in aluminum The reduced energy barrier results between the Fermi level and the 矽 conduction band are consistent (i.e., the results for the reduced Schottky barrier height for n-type 一致 are consistent).

The second set of dipoles are treated in the following manner: after heating the crucible at 900 ° C in flowing hydrogen to clean the {111} Si surface, the temperature is lowered from 900 ° C to 700 ° C and then the crucible surface is exposed to arsenic The hydrogen (AsH ₃ ) molecular stream was continued for 10 minutes and the temperature was maintained at 700 ° C before the end of the AsH ₃ gas flow. The arsine was diluted to a concentration of about 2 ppm with a large amount of hydrogen (H ₂ ) and the total gas flow rate was 20.4 liters per minute. Using the Rutherford backscattering analysis, it was confirmed that the surface density of the arsenic atom obtained by this exposure step was equal to 7.8 x ^{10 14} atoms/cm 2 , which is close to the surface of the surface atom known on the surface of the 1 × 1 recombination {111}矽. Density 7.83x10 ¹⁴ atoms / square centimeter. Thus, it can be reasonably concluded that a single layer of arsenic atoms has been deposited. After cooling to room temperature, a layer of pure aluminum is deposited by electron beam evaporation in a separate ultra-high vacuum system, and then the layer of pure aluminum is patterned to provide a simple dipole structure. Conduct electrical measurements. For comparison, a similar wafer can be processed in a similar sequence, except that the surface of the crucible is not intentionally exposed to any arsenic atoms. Figure 11 illustrates the measured current-voltage characteristics of these experimental dipoles (arsenic and arsenic free). As shown by measurement curve 82 of Figure 11, the dipoles that do not contain arsenic at the interface on the wafer consistently exhibit a relatively small Schottky barrier height for p-type germanium. From curve 82, the height of the energy barrier can be obtained by fitting the measurement data using a standard dipole equation (thermionic emission model). The height of the dipole of the dipole obtained without exposure to arsenic was 0.42 eV (experimental error was about 0.03 eV), and the height of the barrier was consistent with the height of the barrier of the disclosed close aluminum contact on the p-type crucible. As shown by the data curve 80 in Fig. 11, the dipole forming the arsenic monolayer on the wafer after exposing the germanium interface to arsenic consistently exhibits a large Schottky energy for the p-type germanium. Barrier height. According to the general sum of the n-type and p-type barrier heights, the general rule of the band gap is very close, and the p-type enthalpy has a larger energy barrier height, which means that the n-type enthalpy has a smaller energy barrier height. Therefore, experiments have shown that the introduction of a single layer of arsenic atoms at the interface between aluminum and the surface of the {111}-crystal to the crucible, for the p-type crucible, does provide a large Schottky barrier, which is in aluminum The reduced energy barrier results between the Fermi level and the 矽 conduction band are consistent (i.e., the results for the reduced Schottky barrier height for n-type 一致 are consistent).

Thus, several methods have been described for reducing metal-semiconductor junctions by inserting a Group V or Group III atomic monolayer or a plurality of Group V and Group III atomic monolayers at the interface between the metal and the semiconductor. The technique of contact resistance.

Claims (30)

An electrical contact comprising a metal and a Group IV semiconductor, and separating the metal from the Group IV by one of the following layers at an interface between the metal and the Group IV semiconductor a semiconductor: (i) a Group V atomic monolayer, (ii) a Group III atomic monolayer, or (iii) one or more bilayers, and each bilayer is composed of a Group V atomic monolayer and a III a single atom of a group of atoms, the single layer of the group V atom or the single layer of the group III atom or the atomic system of each double layer composed of the group V and group III atoms is epitaxially aligned with a crystal of the semiconductor Grid structure. The contact as claimed in claim 1, wherein the atom contained in the metal is the same metal element as the atom of the single layer of the group III metal atom. The contact according to claim 1, wherein the atom contained in the metal is a different metal element from the atom of the single layer of the group III metal atom. The contact of claim 3, wherein the metal comprises tantalum, tantalum nitride or titanium nitride. The contact according to claim 1, wherein the Group IV semiconductor comprises any one of: an alloy of ruthenium, osmium, iridium and ruthenium, an alloy of ruthenium and tin, a ruthenium alloy containing carbon, a compound of ruthenium and carbon , a carbon-containing niobium alloy, a compound of tantalum and carbon. The contact as claimed in claim 1, wherein the group V atom comprises the following One: nitrogen, phosphorus, arsenic, and antimony; or a mixture of any two or more of nitrogen, phosphorus, arsenic, and antimony atoms. The contact of claim 1, wherein the Group III atom comprises any one or more of the following: aluminum, gallium, indium, or an alloy of aluminum, gallium, and/or indium. The contact of claim 1, wherein a single layer III atomic single layer is adjacent to the surface of the Group IV semiconductor. The contact of claim 1 wherein a single layer V atomic single layer is adjacent to the surface of the Group IV semiconductor. The contact of claim 1, wherein a surface of the Group IV semiconductor site at the interface is a {111}-crystal orientation surface or a {100}-crystal orientation surface. A method of forming a contact according to any one of claims 1 to 10, wherein the method comprises introducing at least the V-group atomic monolayer at the interface between the metal and the Group IV semiconductor Or the Group III atomic monolayer or the bilayer formed by the Group V atom and the Group III atom forms the contact. The method of claim 11, wherein a {100}-crystal orientation surface of the Group IV semiconductor is etched by a crystalline selective etch to expose and expose a plurality of {111}-crystal direction semiconductor crystal faces; Forming the at least one V-group atomic monolayer on the {111} crystal face; and subsequently depositing the III on the V-th atom monolayer A single atom of a family atom. The method of claim 11, wherein the Group V atomic monolayer is formed by a vapor deposition process, and the vapor deposition process comprises: using heat to evaporate a source of the Group V element or Generating a vapor stream of the Group V atom or a stream of homonuclear molecules of the Group V element by a chemical reaction, and exposing the Group IV semiconductor to the vapor stream of the Group V atom or the same Group V element Nuclear molecular flow. The method of claim 13, wherein the Group V atom/molecular stream is an arsenic molecular stream having a composition of either As ₄ or As ₂ and is in a Knudsen cell The source of arsenic is evaporated by heat to generate the molecular stream. The method of claim 11, wherein the Group V element atoms are deposited on the surface of the semiconductor by dissociating a gas phase compound of the Group V element. The method of claim 15, wherein the compound of the Group V element is a hydride of a Group V element, and the Group V hydride gas comprises one of: ammonia, phosphine (phosphine) ), arsine or stilbine. The method of claim 16, wherein the Group V hydride comprises arsine (AsH ₄ ), and the surface of the semiconductor is heated to a temperature ranging between 675 ° C and 725 ° C. The method of claim 17, wherein the semiconductor is germanium, and the surface of the crucible is heated to a sufficiently high temperature in hydrogen to remove any antimony oxide or other contaminants prior to depositing the arsenic atom. The method of claim 15, wherein the compound of the Group V element is an organometallic compound of the Group V element. The method of claim 19, wherein the organometallic compound of the Group V element comprises tert-butyl arsenic (TBA), and heating the surface of the semiconductor to a temperature ranging from 500 ° C to 610 ° C. . The method of claim 12, wherein the semiconductor is germanium, and the {111}-crystal orientation surface is cleaned in situ prior to depositing the group V atom, and the crucible is heated to a sufficiently high temperature Obtaining a 7×7 recombination structure of the {111}矽 surface, after obtaining the recombination structure, during exposing the crucible to a vapor stream of the group V atom or a molecular vapor of the compound of the group V element, The crucible is maintained at a temperature ranging between about 20 ° C and 750 ° C inclusive. The method of claim 11, wherein after forming the Group V atomic monolayer and the Group III atomic monolayer, depositing additional gold on the Group III atom Is an atom, the additional metal atom is the same metal element atom as the single layer III atom, or the additional metal atom is a different metal element atom from the group III atom. The electrical contact of any one of claims 1 to 10, wherein the metal is one of: a metal halide, a nickel telluride, a nickel-niobium (NiSi) composition, a platinum telluride, or a tantalum nitride or a barrier metal composed of titanium nitride or tantalum or a ferromagnetic metal containing one or more of nickel, cobalt, iron and/or niobium. The electrical contact according to any one of claims 1 to 10, wherein one or more double layers consisting of a single layer of a group V atom and a single layer of a group III atom are located at the interface, and each Each atomic layer of the bilayer is epitaxially aligned with each other and epitaxially aligned with the semiconductor crystal lattice. An electrical contact comprising a metal and a Group IV semiconductor, and an epitaxially aligned Group VI atomic monolayer and an epitaxially aligned Group II at an interface between the metal and the semiconductor One or both of the atomic monolayers separate the metal from the Group IV semiconductor. The contact of claim 25, wherein the Group VI atom comprises any one or more of the following: sulfur, selenium or tellurium, and/or the Group II atom comprises: zinc or cadmium or a zinc and An alloy of cadmium. An electrical contact comprising a ferromagnetic metal and a Group IV semiconductor, and At a interface between the ferromagnetic metal and the semiconductor, a single layer of a group V atom with an epitaxial alignment or a single layer of a group V atom aligned by the epitaxy and a group III atom A double layer of layers separates the metal from the Group IV semiconductor. A method of forming an electrical contact comprising: a surface of a Group IV semiconductor being prepared to contain an atom of a first Group V material adjacent to the surface and deposited on the surface of the Group IV semiconductor a second V-group material monolayer, the atomic epitaxy of the second V-group material is aligned with the crystal lattice structure of the semiconductor, and a metal is deposited on the second V-group material monolayer, the mirror image in the metal The charge will form a dipole between the atoms of the first group V material. The method of claim 28, wherein the first group V material is the same Group V material as the second group V. The method of claim 28, wherein the first group V material is deposited into the semiconductor by depositing the first group V material on the semiconductor at a sufficiently high temperature to prepare the IV. Family semiconductor.