TW201442310A - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device comprising at least a laminate structure is provided. The laminate structure consists of a structure of a top electrode/an upper resistive switching layer/an oxygen-plasma-treated lower resistive switching layer/a bottom electrode.

Description

Memory component and its process

This invention relates to a semiconductor structure, and more particularly to a non-volatile memory component and process thereof.

In recent years, flash memory has faced problems such as miniaturized physical limit and excessive operating voltage. Therefore, resistive memory components with simple structure, small area, fast operation speed and low power consumption (Resistive Random Access) Memory; RRAM) is very likely to replace the traditional flash memory, forming the mainstream of the next generation of non-volatile memory. Resistive memory has excellent memory operation characteristics such as low voltage operation, low power consumption, and high density stacked structure. However, resistive memory has poor endurance or repeated write/erase (Program) /Erase) The number of times cannot be effectively improved. After several consecutive operations, the high-resistance resistance of the resistive memory cannot maintain the high-resistance state, and the high-low-resistance ratio (on/off ratio) of the subsequent resistance transition is reduced, resulting in a memory state. Interpretation errors become obstacles to mass production of resistive memory.

In addition, the resistive state of the resistive memory is the use of oxygen vacancies or oxygen ions to form a conductive filament (conductive Filament), using the external application of voltage polarity and current value, causing the phenomenon of breakage and re-generation of the conductive filament, resulting in a difference in resistance value. After performing multiple resistance transitions, the available oxygen ions are exhausted, resulting in an inability to effectively improve the resistance.

The invention provides a memory device structure, comprising at least a laminated structure, the laminated structure comprising at least a lower conductive layer, a resistive transition layer on the lower conductive layer, and a resistor on the lower resistive transition layer The transition layer is on the conductive layer above the upper resistive transition layer. The upper resistive transition layer includes a first oxide material layer formed by atomic layer deposition, and the lower resistive transition layer includes a second oxide material layer formed by atomic layer deposition and treated via oxygen plasma.

According to an embodiment of the invention, the material of the first oxide material layer included in the upper resistance change layer is ceria, alumina, titania, zirconia, tin oxide or zinc oxide. The upper resistance transition layer has a thickness of 1 nm to 100 nm. The material of the second oxide material layer included in the lower resistance transition layer is ceria, alumina, titania, zirconia, tin oxide or zinc oxide. The lower resistance transition layer has a thickness of 1 nm to 100 nm.

According to an embodiment of the invention, the upper conductive layer material is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium or indium. Tin oxide. The upper conductive layer has a thickness of from 1 nm to 1000 nm. The foregoing conductive layer material is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or heavy Doped germanium semiconductor. The thickness of the lower conductive layer is from 1 nm to 500 nm.

The present invention provides a method of fabricating a memory device structure. The method includes first forming a conductive layer and forming a lower resistance transition layer over the lower conductive layer by atomic layer deposition. After the oxygen plasma treatment is performed on the lower resistance transition layer, an upper resistance transition layer on the lower resistance transition layer is formed by atomic layer deposition. Next, an upper conductive layer is formed over the upper resistive transition layer.

According to an embodiment of the invention, the upper conductive layer is formed by atomic layer deposition, electron beam evaporation or sputtering, and the upper conductive layer material is selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, Cerium oxide, cerium, lanthanum, cerium nitride, nickel, molybdenum, zirconium or indium tin oxide. The upper conductive layer has a thickness of from 1 nm to 1000 nm.

According to an embodiment of the invention, the lower conductive layer is formed by an atomic layer deposition method, an electron beam evaporation method, a sputtering method or a high temperature furnace tube, and the lower conductive layer material is selected from the group consisting of titanium, titanium nitride, platinum, aluminum, Tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or heavily doped germanium semiconductor. The thickness of the lower conductive layer is from 1 nm to 500 nm.

According to an embodiment of the present invention, the lower conductive layer is formed by atomic layer deposition, and the lower conductive layer and the upper resistive transition layer and the lower resistive transition layer are not broken in the cavity through the same atomic layer deposition system. Continuous deposition.

According to an embodiment of the present invention, the lower resistance transformation layer is subjected to the same atomic layer deposition system, and the lower resistance transformation layer is subjected to 200 in a cavity temperature of 250 ° C and a working pressure of 0.2 Torr. W lasts 10 minutes of oxygen plasma treatment.

According to an embodiment of the invention, the material of the upper resistive transition layer or the lower resistive transition layer is ceria, alumina, titania, zirconia, tin oxide or zinc oxide.

Based on the above, the present invention adopts the structure described in the foregoing embodiments, and can suppress the decrease of the resistance value of the high resistance state, so that the ratio of the high and low resistance states does not decrease with the increase of the number of transition states, thereby improving the resistance of the memory.

The invention enhances the oxygen ion content in the resistance transition layer by oxygen plasma treatment, and the increased number of oxygen ions can effectively increase the number of resistance transitions. In addition, the oxygen plasma treatment and the deposition of the resistive layer film are all achieved by the same atomic layer deposition system, which reduces the deterioration of the film quality or the resistance transition property which may be caused by the vacuum of the process cavity. Such problems, so the process method can improve the quality of the film and facilitate mass production. The process method of the present invention is quite suitable for mass production of high performance resistive non-volatile memory components.

The above described features and advantages of the present invention will be more apparent from the following description.

10, 11, 12‧‧‧ memory component structure

100‧‧‧矽 substrate

200‧‧‧ cerium oxide film

300‧‧‧Titanium film

400‧‧‧Platinum film

500‧‧‧Titanium nitride film

600‧‧‧Purified cerium oxide film after plasma treatment

700‧‧‧ cerium oxide film

800‧‧‧Titanium film

900‧‧‧2O2 film

1000‧‧‧2O2 film

FIG. 1A is a partial schematic structural view of a memory device according to an embodiment of the present invention.

Fig. 1B is a schematic view showing the structure of a ruthenium oxide element control group of the embodiment.

1C is a schematic view showing the structure of a control group of a cerium oxide element treated by an oxygen plasma according to an embodiment.

2 is a diagram showing the relationship between the formation process of the memory device and the voltage and current of the first transition state in the embodiment of the present invention shown in FIG. 1A.

FIG. 3 is a diagram showing the relationship between voltage and current in which the memory element of the embodiment of the present invention shown in FIG. 1A actually performs a continuous cycle of applying a bias voltage for 100 times.

4 shows the resistance test of the memory element of the embodiment of the present invention shown in FIG. 1A actually applying DC write and erase voltages.

Fig. 5A is a graph showing the relationship between the formation process of the ceria element control group and the voltage and current of the first transition state in the embodiment shown in Fig. 1B.

FIG. 5B is a graph showing the relationship between the formation process of the control group of the ceria element through the oxygen plasma and the voltage and current of the first transition state in the embodiment shown in FIG. 1C.

Fig. 6A is a graph showing the relationship between voltage and current in which the ceria element control group of the embodiment shown in Fig. 1B actually performs a continuous cycle of applying a bias voltage for 100 times.

Fig. 6B is a graph showing the relationship between the voltage and current of the continuous oxidation cycle of applying the bias voltage for 10 times in the control group of the cerium oxide element treated by the oxygen plasma treatment of the embodiment shown in Fig. 1C.

Fig. 7A shows the resistance test of the ruthenium oxide element control group of the embodiment shown in Fig. 1B in the application of the DC write and erase voltages.

Figure 7B shows the endurance test of the DC write and erase voltages applied to the control group of the ceria element via the oxygen plasma treatment of the embodiment of Figure 1B.

FIG. 8 shows the endurance test of the memory element applied to the dynamic pulse of the embodiment of the present invention shown in FIG. 1A.

In order to improve the number of times of resistance of the resistive memory, the present invention utilizes plasma treatment, such as oxygen plasma, to effectively increase the oxygen ion content available in the resistive transition layer while the device is being fabricated. . Moreover, in order to avoid active upper electrodes (such as titanium electrodes) in the resistive memory, the number of additional oxygen ions added by the oxygen plasma treatment is directly captured, and the present invention is additionally on the resistive transition layer after the plasma treatment. A thin dielectric film is introduced to prevent direct contact between the active upper electrode and the plasma-transformed layer after the plasma treatment, thereby preventing additional oxygen ions from being adsorbed by the active upper electrode, resulting in an inability to improve and improve the resistance.

The following embodiment takes a resistive memory structure as an example. The resistive memory structure of the embodiment of the present invention includes: a stack of upper electrode/upper resistance transition layer/oxygen plasma treated lower resistance transition layer/lower electrode structure.

Using a metal or a conductive compound as a lower electrode, a thin film of hafnium oxide (HfO ₂ ) is formed as an underlying resistive layer by an atomic layer deposition (ALD) system, and after depositing the lower resistance layer, The atomic layer deposition system is used to perform the action of oxygen plasma treatment on the lower resistance layer under the environment in which the deposition chamber is not broken, thereby increasing the oxygen ion content in the lower resistance layer, and then using the atomic layer. Deposition system, deposit another layer of resistive transition layer over the lower resistance transition layer after treatment by oxygen plasma, and finally deposit the upper electrode to complete the lower resistance switch after the upper electrode/upper resistance transition layer/oxygen plasma treatment Resistive memory structure of the layer/lower electrode.

Example

FIG. 1A is a partial schematic structural view of a memory device according to an embodiment of the present invention. The formation process of the memory device 10 of the embodiment of the present invention shown in Fig. 1A is briefly described below. The ruthenium substrate 100 after the RCA cleaning step is cleaned, and a 200 nm thick ruthenium dioxide film 200 is formed on the ruthenium substrate 100 as an isolation oxide layer by using a high temperature furnace tube, and then formed by a beam evaporation method to form a 20 nm thick layer. The titanium film 300 and the 50 nm thick platinum film 400 serve as a lower conductive layer. Then we use the Atomic Layer Deposition system to use tetramethylammonium titanium (Ti[N(CH ₃ ) ₂ ] ₄ ; TDMAT for short) as the precursor, using nitrogen plasma and TDMAT. The reaction, at a deposition temperature of 250 ° C and a working pressure of 0.3 Torr, formed a 10 nm titanium nitride film 500 as a lower electrode. Thereafter, using the same atomic layer deposition system, tetramethylethylammonium hydride (Hf[N(C ₂ H ₅ )(CH ₃ )] ₄ ; TEMAH) and water are used as precursors at the deposition temperature. A 9 nm thick ruthenium dioxide film was deposited as a lower resistance transition layer at 250 ° C and a working pressure of 0.2 Torr. Then, using an atomic layer deposition system, the lower resistance layer is subjected to 200 W for 10 minutes of oxygen plasma treatment in a cavity temperature of 250 ° C and a working pressure of 0.2 Torr to obtain a plasma-treated cerium oxide. Film 600. Thereafter, using an atomic layer deposition system, a 1 nm thick ruthenium dioxide film 700 is deposited as an upper resistance over the lower resistance transition layer (plasma treated ruthenium oxide film 600) after the oxygen plasma treatment. Transition layer. Thereafter, an electron beam evaporation method is used to define an upper electrode area (for example, 4.9×10 ⁻⁴ cm ² ) by a metal mask, and a 50 nm thick titanium metal film 800 is formed as an upper electrode, and finally the memory of the present invention is used. The body element is placed in a vacuum annealing furnace tube at a temperature of 400 ° C and a high vacuum environment (for example, about 10 ^-7 Torr) for a long time deposition metal post-annealing (PMA) for 30 minutes to obtain a partial structural diagram of the element 10 as shown in the figure. Figure 1A shows. The structure of the memory element 10 has a substrate 100, a ceria film 200 (insulation oxide layer), a titanium film 300/platinum film 400 (lower conductive layer), a titanium nitride film 500 (lower electrode), and a via titanium nitride film sequentially from bottom to top. Oxygen plasma treated ruthenium dioxide film 600 (lower resistance transition layer), ruthenium dioxide film 700 (upper resistance transition layer) and titanium metal film (upper electrode).

The invention provides a memory device comprising at least a laminated structure, the laminated structure comprising at least a lower conductive layer, a resistive transition layer on the lower conductive layer, and a resistance transition state on the lower resistance transition layer The layer and the conductive layer on the upper resistive transition layer. The resistive transition layer and the lower resistive transition layer on the component are grown by atomic layer deposition, and the lower resistive transition layer is processed via oxygen plasma. Through this structural design, the laminated structure is applied to a resistive non-volatile memory, which can effectively improve the resistance of the resistive memory.

The material of the upper resistive transition layer and the material of the lower resistive transition layer in the device laminated structure of the present invention may comprise any oxide material which can be deposited by atomic layer deposition, for example: ceria, alumina, titania , zirconium dioxide, tin oxide or zinc oxide. The upper resistive transition layer and the lower resistive transition layer deposited by the atomic layer deposition method have a deposition temperature ranging, for example, from 100 ° C to 500 ° C. The lower resistance transition layer has a thickness of, for example, 1 nm to 100 nm. The upper resistive transition layer has a thickness of, for example, 1 nm to 100 nm. Alternatively, the upper resistive transition layer may also be omitted depending on the design of the component.

For the lower resistance transformation layer after the oxygen plasma treatment, the same atomic layer deposition system is used for plasma treatment, and the plasma may include deposition by atomic layer The system provides any type of plasma of oxygen ions, such as oxygen plasma.

In the layer stack structure of the present invention, the upper conductive layer serves as the upper electrode and the lower conductive layer serves as the lower electrode. The upper conductive layer has a thickness of, for example, 1 nm to 1000 nm. The lower conductive layer has a thickness of, for example, 1 nm to 500 nm. The material of the upper conductive layer is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium or indium tin oxide. The material of the lower conductive layer is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or heavy Doped germanium semiconductor. The upper conductive layer may be formed by an atomic layer deposition method, an electron beam evaporation method, or a sputtering method. The lower conductive layer may be formed by an atomic layer deposition method, an electron beam evaporation method, a sputtering method, or a high temperature furnace tube. According to the embodiment of the present invention, the lower conductive layer and the upper resistive transition layer and the lower resistive transition layer can pass different formulas through the same atomic layer deposition system without changing the vacuum in the process machine and the cavity. Continuous deposition with process conditions.

Further, with respect to the memory element of the above-described embodiment, a simple ceria element and a ceria element treated with an oxygen plasma were used as a control group of the memory element of the present invention. Fig. 1B is a schematic view showing the structure of a cerium oxide element control group of the embodiment, and the formation process of the simple cerium oxide element control group shown in Fig. 1B is briefly described below. The tantalum substrate 100, the hafnium oxide film 200, the titanium thin film 300, the platinum thin film 400, and the titanium nitride thin film 500, which are included in the structure, are formed in accordance with the method steps similar to those described above with reference to FIG. 1A, and then, by atomic layer deposition ( ALD) system, depositing a 10 nm thick ruthenium dioxide film 900 over a 10 nm thick titanium nitride film 500, Then, a 50 nm thick titanium metal film 800 is formed on the ceria film 900, and the titanium metal film 800 is used as an upper electrode. The method and parameters are the same as the above-mentioned process method, and a partial structure diagram of the element 11 is obtained. 1B is shown.

1C is a schematic view showing the structure of a control group of a cerium oxide element treated by an oxygen plasma according to an embodiment. The formation process of the cerium oxide element-treated control group via the oxygen plasma in the embodiment shown in Fig. 1C is briefly described below. The tantalum substrate 100, the hafnium oxide film 200, the titanium thin film 300, the platinum thin film 400, and the titanium nitride thin film 500, which are included in the structure, are formed in accordance with the method steps similar to those described above with reference to FIG. 1A, and then, by atomic layer deposition ( ALD) system, depositing a 10 nm thick ruthenium oxide film 1000 over a 10 nm thick titanium nitride film 500, and then performing a 200 W continuous on a 10 nm thick ruthenium oxide film 1000 using an atomic layer deposition system. After 10 minutes of oxygen plasma treatment, a 50 nm thick titanium metal film 800 is formed on the cerium oxide film 1000 treated by oxygen plasma, and the titanium metal film 800 is used as an upper electrode, and the method and parameters are fabricated. Similar to the foregoing process method, a schematic structural view of the component 12 is shown in FIG. 1C.

2 is a diagram showing the relationship between the forming process of the memory device and the voltage and current of the first transition state of the embodiment of the present invention shown in FIG. 1A, which shows the operation mode of the component using the present invention. During the formation process, when a positive DC bias is applied to the titanium film 800 (upper electrode) and the titanium nitride film 500 (lower electrode) is grounded, the current increases as the voltage increases, and when the current rises to the current limit value ( At 500μA, the bias voltage is a forming voltage, which usually requires a large bias voltage. At this time, the resistance value of the device is switched from the initial state of the high resistance to the low resistance state. (Low Resistance State; LRS), the forming voltage of the device of the present invention is about 3 V. Next, a negative bias operation is applied to the device of the present invention. When a bias voltage is applied from 0 V to -0.7 V, the current value begins to decrease when the voltage reaches -0.7 V, which indicates that the resistance value of the device increases with the negative bias voltage. Rising, after continuously applying a negative bias to -2 V, the component has a higher resistance value, and then the applied bias voltage is swept from -2 V to 0 V, and it can be found that when the bias voltage is applied from 0 V to - The voltage-current curve (IV curve) at 2 V is different from -2 V to 0 V, showing the low current of the component from a high current state of low resistance state to a high resistance state (HRS). After applying a positive bias voltage of 0 V to 2 V to the device, the current increases with increasing voltage. When a positive bias voltage is applied to reach a write voltage of about 0.6 V, the current value reaches the current limit value ( 500 μA, at this time, the component changes from a high resistance state to a low resistance state. Then, when the reset voltage of the component is applied with a negative bias voltage of about -0.6 V, the current is again decreased, and the low resistance state is at this time. The current is transferred to the high resistance state to complete the first resistance transition (1st switch), and the resistance conversion characteristic can be repeatedly operated. FIG. 3 is the memory component of the embodiment of the present invention shown in FIG. 1A, and the actual application is performed. The continuous cycle of the bias voltage is 0 V~1.5 V~0 V~-1.5 V~0V cycle 100 times, showing high current value (1 mA) and low current value (100μA) when the read voltage is 0.3 V. 2 kinds of different resistance states, that is, we can control the bias voltage of the component to make the resistance conversion of the component to achieve the memory purpose, and the high and low resistance states can maintain the stable memory state without the external power supply. Can be used in non-volatile memory applications.

4 is an endurance test for applying a DC write and erase voltage to the memory device of the embodiment of the present invention shown in FIG. 1A, and the measurement conditions are all in the element. The upper electrode of the device is biased and the lower electrode of the component is grounded, wherein both the high resistance state and the low resistance state read the high and low resistance current values at a bias voltage of 0.3 V, and the component of the present invention exceeds 11,000 times. Under the above continuous transition operation, the resistance ratio of the high resistance state and the low resistance state still maintains a value greater than 10 times, showing excellent excellent resistance characteristics.

Fig. 5A is a graph showing the relationship between the formation process of the ceria element control group and the voltage and current of the first transition state in the embodiment shown in Fig. 1B. FIG. 5B is a graph showing the relationship between the formation process of the control group of the ceria element through the oxygen plasma and the voltage and current of the first transition state in the embodiment shown in FIG. 1C. FIG. 6A is a result of actually performing the cycle of applying a bias voltage of 0 V~1.5 V~0 V~-1.5 V~0 V for 100 times in the structure of the embodiment shown in FIG. 1B. FIG. 6B is a result of the embodiment of the embodiment shown in FIG. 1C actually performing a cycle of applying a bias voltage of 0 V~1.5 V~0 V~-1.5 V~0 V for 10 times. Fig. 7A shows the structure of the embodiment shown in Fig. 1B subjected to a DC write and erase voltage tolerance test, the measurement conditions are that the electrode is biased on the upper electrode of the component and the lower electrode of the component is grounded, wherein the high resistance state Both the high and low resistance current values were read at a bias voltage of 0.3 V with the low resistance state. The results showed that the resistance test of the cerium oxide component control group was performed under more than 6,000 consecutive transition operations. The current value in the high resistance state tends to rise continuously, resulting in a resistance ratio of the high and low resistance states of the ceria element control group after several consecutive transition operations being less than 10 times. In addition, FIG. 7B shows the structure of the embodiment shown in FIG. 1C in which the DC write and erase voltages are subjected to the endurance test. The measurement conditions are all on the upper electrode of the component and the lower electrode of the component is grounded, wherein the high resistance Both the state and the low resistance state read their high and low resistance states under a bias voltage of 0.3 V. The flow value, the results show that the control group of the cerium oxide component treated by the oxygen plasma can increase the number of transitions of the resistance test from 6,000 times to 10,000 times, showing that the cerium oxide component has been treated via oxygen plasma. The group can improve the number of transitions of the endurance test, which represents the positive impact of the plasma treatment on the resistance test. However, in the continuous resistance operation of more than 10,000 cycles, the current value of the high resistance state continues to rise, resulting in the control of the ceria component via oxygen plasma after several consecutive transition operations. The resistance ratio of the high and low resistance states is less than 10 times.

The voltage-current relationship diagram of FIG. 2 obtained by the memory device of the embodiment of the present invention is compared with the voltage-current relationship diagram of FIG. 5A obtained by the embodiment of the ruthenium dioxide element, and FIG. 5B obtained by treating the ruthenium dioxide element with oxygen plasma. Comparing the voltage-current relationship diagrams, it can be observed that the formation voltages of the elements of the present invention and the respective control groups all fall at a position of 3 V. In addition, the voltage-current relationship diagram of FIG. 3 obtained by the memory device of the embodiment of the present invention, the voltage-current relationship diagram of FIG. 6A obtained by the embodiment of the ruthenium dioxide element, and the diagram obtained by treating the ruthenium dioxide element via the oxygen plasma. Comparing the voltage and current relationship diagrams of 6B, it can be observed that the same current limit value (2 mA and the same applied bias period is 0 V~1.5 V~0 V~-1.5 V~0 V, the implementation of the present invention The memory components have the same write and erase voltages as the respective control groups, 0.7 V and -0.6 V. This result shows that the components are below the total thickness of the same resistance transition layer (the total thickness is 10). Nano), whether or not treated by oxygen plasma, has no direct effect on the operation of the resistive memory, but the results of the resistance shown in Fig. 4 obtained from the memory device of the embodiment of the present invention, and cerium oxide Figure 7A of the component and the results of the endurance shown in Figure 7B of the oxygen dioxide treated ceria element, the present invention In the memory element structure of the embodiment, it is possible to suppress the problem that the current value of the high-resistance state is increased due to the writing and erasing voltages under the durability test, and the resistance of the resistive memory can be effectively improved.

8 is a view showing the results of the test of the performance of the memory element structure of the embodiment of the present invention shown in FIG. 1A for performing dynamic measurement, which is performed by applying a pulse voltage to the upper electrode of the memory element of the embodiment of the present invention. And the lower electrode of the component is grounded, wherein the applied pulse write voltage is 2.1 V, the pulse width is 30 nanoseconds, the applied pulse erase voltage is -3.3 V, the pulse width is 30 nanoseconds, and the read voltage is 0.3. Under V, read the current value of its high and low configuration. It can be seen from the experimental results that the memory component structure of the embodiment of the present invention can effectively improve the number of times of resistance operation of the resistive memory. Under the ultra-fast pulse voltage operation of 30 nanoseconds, the ratio of the high and low resistance resistance can be maintained more than 10 times. value of up to one million times (10 ⁸ cycles) operation, a display example of the memory device of the embodiment of the present invention have excellent characteristics Naicao degrees.

The structure described in the foregoing embodiment is compared to a simple resistive memory that has not been treated with oxygen plasma and a resistively-transformed layer resistive memory that has not been additionally deposited with a resistive transition layer (Figure 1A). ), for the resistance of the memory, it is possible to suppress the decrease in the resistance value of the high resistance state, so that the ratio of the high and low resistance states does not decrease as the number of transitions increases. The invention enhances the oxygen ion content in the resistance transition layer by oxygen plasma treatment, and the increased number of oxygen ions can effectively increase the number of resistance transitions.

In addition, the oxygen plasma treatment and the deposition of the resistance transition layer film are all achieved by the same instrument atomic layer deposition system, which reduces the deterioration of the film quality or the resistance transition caused by the vacuum of the process cavity. Characteristics, etc. This process method is more suitable for mass production of high-performance resistive non-volatile memory components. Moreover, the resistive memory manufacturing process method provided by the present invention is compatible with the current complementary metal oxide semiconductor process, and is convenient for mass production.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Memory component structure

100‧‧‧矽 substrate

200‧‧‧ cerium oxide film

300‧‧‧Titanium film

400‧‧‧Platinum film

500‧‧‧Titanium nitride film

600‧‧‧Purified cerium oxide film after plasma treatment

700‧‧‧ cerium oxide film

800‧‧‧Titanium film

Claims (18)

A memory device structure comprising at least one laminated structure, wherein the laminated structure comprises at least: a lower conductive layer; a lower resistance transition layer located above the lower conductive layer; and an upper resistance transition layer located at the lower resistance layer Above the layer; and an upper conductive layer over the upper resistive transition layer, wherein the upper resistive transition layer comprises a first oxide material layer formed by atomic layer deposition, the lower resistive transition layer comprising A layer of a second oxide material formed by atomic layer deposition and treated via an oxygen plasma. The memory device structure of claim 1, wherein the material of the first oxide material layer included in the upper resistance transition layer is ceria, alumina, titania, zirconia, tin oxide. Or zinc oxide. The memory device structure of claim 1, wherein the material of the second oxide material layer included in the lower resistance transformation layer is ceria, alumina, titania, zirconia, tin oxide. Or zinc oxide. The memory device structure of claim 1, wherein the upper resistance layer has a thickness of from 1 nm to 100 nm. The memory device structure of claim 1, wherein the lower resistance layer has a thickness of from 1 nm to 100 nm. The memory device structure of claim 1, wherein the lower conductive layer has a thickness of from 1 nm to 500 nm. The memory device structure of claim 1, wherein the upper conductive layer has a thickness of from 1 nm to 1000 nm. The memory device structure of claim 1, wherein the upper conductive layer material is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride. , nickel, molybdenum, zirconium or indium tin oxide. The memory device structure of claim 1, wherein the lower conductive layer material is a conductor material selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride. , nickel, molybdenum, zirconium, indium tin oxide or heavily doped germanium semiconductor. A method for fabricating a memory device structure, comprising at least: forming a conductive layer; forming a resistive transition layer by atomic layer deposition on the lower conductive layer; performing an oxygen plasma treatment on the lower resistance transition layer; The atomic layer deposition method forms an upper resistive transition layer over the lower resistive transition layer; and an upper conductive layer is formed over the upper resistive transition layer. The method for fabricating a memory device structure according to claim 10, wherein the upper conductive layer is formed by atomic layer deposition, electron beam evaporation or sputtering, and the upper conductive layer material is selected from the group consisting of titanium, Titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium or indium tin oxide. The method for fabricating a memory device structure according to claim 10, wherein the lower conductive layer is deposited by atomic layer deposition, electron beam evaporation, sputtering, or Formed by a high temperature furnace tube, the material of the lower conductive layer is selected from the group consisting of titanium, titanium nitride, platinum, aluminum, tungsten, tantalum, niobium oxide, tantalum, niobium, tantalum nitride, nickel, molybdenum, zirconium, indium tin oxide or heavy Doped germanium semiconductor. The method of manufacturing a memory device structure according to claim 10, wherein the upper conductive layer has a thickness of from 1 nm to 1000 nm. The method for manufacturing a memory device structure according to claim 10, wherein the lower conductive layer has a thickness of from 1 nm to 500 nm. The method of fabricating a memory device structure according to claim 10, wherein the lower conductive layer is formed by atomic layer deposition, and the lower conductive layer and the upper resistive transition layer and the lower resistive transition layer are via The same atomic layer deposition system continuously deposits in the cavity without breaking the vacuum. The method for fabricating a memory device structure according to claim 15, wherein the oxygen plasma treatment is performed through the same atomic layer deposition system at a cavity temperature of 250 ° C and a working pressure of 0.2 Torr. Under the environment, the lower resistance transformation layer was subjected to an oxygen plasma treatment of 200 W for 10 minutes. The method for fabricating a memory device structure according to claim 10, wherein the material of the upper resistance transition layer is ceria, alumina, titania, zirconia, tin oxide or zinc oxide. The method for manufacturing a memory device structure according to claim 10, wherein the material of the lower resistance transition layer is ceria, alumina, titania, zirconia, tin oxide or zinc oxide.