TW201437817A - A FLASH memory apparatus and data transmission method - Google Patents
A FLASH memory apparatus and data transmission method Download PDFInfo
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本發明係有關於快閃記憶體，特別是有關於一種適用於具有複數個快閃記憶體晶片之快閃記憶裝置與資料傳輸方法。 The present invention relates to flash memory, and more particularly to a flash memory device and data transmission method suitable for use with a plurality of flash memory chips.
由於快閃記憶體可於未供電之情況下保留已儲存之資料，且具有編程時間短、低功率消耗等優點，因此，廣泛地作為手機、數位相機、筆記型電腦等各種電子產品之儲存媒體，例如：記憶卡、隨身碟等。為了因應日益增加的儲存資料量，而發展出多晶片(Multi-Die)堆疊結構的快閃記憶體裝置。然而，相較於動態隨機存取記憶體，快閃記憶體具有較長的寫入時間，使得多晶片堆疊結構的快閃記憶體裝置需要耗費大量時間進行資料的寫入，使得快閃記憶體裝置傳輸資料的效率低落。 Because the flash memory can retain the stored data without power supply, and has the advantages of short programming time, low power consumption, etc., it is widely used as a storage medium for various electronic products such as mobile phones, digital cameras, and notebook computers. For example: memory card, flash drive, etc. In order to cope with the increasing amount of stored data, a flash memory device of a multi-Die stack structure has been developed. However, compared with the dynamic random access memory, the flash memory has a long writing time, so that the flash memory device of the multi-wafer stack structure requires a large amount of time for writing data, so that the flash memory is The efficiency of the device to transmit data is low.
有鑑於此，需要一種新的方案，以提昇快閃記憶體裝置之資料傳輸的效率。 In view of this, a new solution is needed to improve the efficiency of data transmission in a flash memory device.
本發明之目的在於解決因為快閃記憶體較長的寫入時間而造成之低資料傳輸效率。本發明所提供的快閃記憶體 裝置包括複數記憶體晶片，每一記憶體晶片在接收到指令後會先判斷該指令之辨識資訊是否與自身的辨識碼相同。當該指令之辨識資訊與自已的辨識碼相同，才執行該指令進行對應的資料傳輸。符合該指令之辨識資訊的記憶體晶片在進行寫入操作時，另一記憶體晶片可進行一寫入操作或讀取操作。本發明所揭露之複數個記憶體晶片可各自進行存取操作，因而提升快閃記憶體裝置之資料傳輸效率。 The object of the present invention is to solve the problem of low data transmission efficiency due to the long write time of the flash memory. Flash memory provided by the present invention The device includes a plurality of memory chips, and each memory chip first determines whether the identification information of the instruction is the same as its own identification code after receiving the instruction. When the identification information of the instruction is the same as the identification code of the instruction, the instruction is executed to perform corresponding data transmission. The memory chip conforming to the identification information of the instruction may perform a write operation or a read operation on another memory chip while performing a write operation. The plurality of memory chips disclosed in the present invention can each perform an access operation, thereby improving data transmission efficiency of the flash memory device.
本發明提供一種快閃記憶體裝置，包括一第一記憶體晶片以及一第二記憶體晶片，其中第一記憶體晶片包括一第一辨識碼、一第一控制器以及一第一快閃記憶體，當第一控制器所接收的一第一指令中之一第一辨識部分相同於第一辨識碼時，執行第一指令中之一第一資料傳輸部分，用以在一第一操作週期內對第一快閃記憶體進行一第一存取操作；第二記憶體晶片具有不同於第一辨識碼之一第二辨識碼，並且第二記憶體晶片包括一第二控制器以及一第二快閃記憶體，第二控制器係於第一操作週期中時接收一第二指令，並且當第二指令中之一第二辨識資訊相同於第二辨識碼時，第二控制器係執行第二指令中之一第二資料傳輸指令，用以對第二快閃記憶體進行一第二存取操作。 The present invention provides a flash memory device including a first memory chip and a second memory chip, wherein the first memory chip includes a first identification code, a first controller, and a first flash memory. And when one of the first instructions received by the first controller is identical to the first identification code, executing one of the first data transmission portions of the first instruction for a first operation cycle Performing a first access operation on the first flash memory; the second memory chip has a second identification code different from the first identification code, and the second memory chip includes a second controller and a first a second flash memory, the second controller receives a second instruction when in the first operation cycle, and when the second identification information of the second instruction is the same as the second identification code, the second controller executes And a second data transmission instruction of the second instruction for performing a second access operation on the second flash memory.
本發明提供一種一種資料傳輸方法，應用於一快閃記憶體裝置，快閃記憶體裝置包括一第一記體體晶片以及一第二記憶體晶片，其中第一記體體晶片包括一第一辨識碼、一第一控制器以及一第一快閃記憶體，第二記體體晶片包括一第二辨識碼、一第二控制器以及一第二快閃記憶體，資料傳輸方 法包括：接收一第一指令，其中第一指令包括一第一辨識部分以及一第一資料傳輸部分；當第一控制器所接收的第一辨識部分相同於第一辨識碼時，執行第一資料傳輸部分，用以在一第一操作週期內對第一快閃記憶體進行一第一存取操作；以及第二控制器係於第一操作週期中時接收一第二指令，並且當第二指令中之一第二辨識資訊相同於第二辨識碼時，第二控制器係執行第二指令中之一第二資料傳輸指令，用以對第二快閃記憶體進行一第二存取操作。 The present invention provides a data transmission method for a flash memory device. The flash memory device includes a first body wafer and a second memory chip, wherein the first body wafer includes a first The identification code, a first controller and a first flash memory, the second body wafer includes a second identification code, a second controller and a second flash memory, and the data transmission side The method includes: receiving a first instruction, where the first instruction includes a first identification part and a first data transmission part; and when the first identification part received by the first controller is the same as the first identification code, performing the first a data transmission portion for performing a first access operation on the first flash memory in a first operation cycle; and a second controller receiving a second instruction in the first operation cycle, and When the second identification information of the second instruction is the same as the second identification code, the second controller executes one of the second data transmission instructions of the second instruction for performing a second access to the second flash memory. operating.
100‧‧‧快閃記憶體裝置 100‧‧‧Flash memory device
110‧‧‧第一記憶體晶片 110‧‧‧First memory chip
112‧‧‧第一控制器 112‧‧‧First controller
114‧‧‧第一快閃記憶體 114‧‧‧First flash memory
120‧‧‧第二記憶體晶片 120‧‧‧Second memory chip
122‧‧‧第二控制器 122‧‧‧Second controller
124‧‧‧第二快閃記憶體 124‧‧‧Second flash memory
130‧‧‧輸入緩衝器 130‧‧‧Input buffer
140‧‧‧輸出緩衝器 140‧‧‧Output buffer
160‧‧‧主機 160‧‧‧Host
C10‧‧‧第一指令 C10‧‧‧ first order
C11‧‧‧第一辨識部分 C11‧‧‧ first identification part
C12‧‧‧第一資料傳輸部分 C12‧‧‧First data transmission part
C20‧‧‧第二指令 C20‧‧‧Second Directive
C21‧‧‧第二辨識部分 C21‧‧‧Second identification part
C22‧‧‧第二資料傳輸部分 C22‧‧‧Second data transmission part
VDD‧‧‧電源供應端 V DD ‧‧‧Power supply
第1圖為本發明所提供之快閃記憶體裝置之示意圖。 Figure 1 is a schematic diagram of a flash memory device provided by the present invention.
第2圖為本發明所提供之應用於快閃記憶體裝置之資料傳輸方法的流程圖。 FIG. 2 is a flow chart of a data transmission method applied to a flash memory device according to the present invention.
以下將詳細討論本發明各種實施例之裝置及使用方法。然而值得注意的是，本發明所提供之許多可行的發明概念可實施在各種特定範圍中。這些特定實施例僅用於舉例說明本揭露之裝置及使用方法，但非用於限定本發明之範圍。 The apparatus and method of use of various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are only intended to illustrate the apparatus and methods of use of the present disclosure, but are not intended to limit the scope of the invention.
第1圖為本發明所提供之快閃記憶體裝置之示意圖。快閃記憶體裝置100接受來自主機160的指令，並依據該指令將來自主機160或其他電子裝置(未顯示)之資料寫入快閃記憶體裝置100中，或是依據該指令將讀取自快閃記憶體裝置100之資料傳送至主機160或其他電子裝置。於一實施例中，主機160可為可攜式裝置或電腦產品，而耦接於主機160之快閃記憶 裝置100可為記憶卡。快閃記憶體裝置100包括複數記憶體晶片，每一記憶體晶片在接收到來自主機160的指令後會先判斷該指令之辨識資訊是否與自身的辨識碼相同。當該指令之辨識資訊與自已的辨識碼相同，才執行該指令進行對應的資料傳輸。符合該指令之辨識資訊的記憶體晶片在進行寫入操作時，另一記憶體晶片可進行一寫入操作或讀取操作。為了方便說明之故，在本實施例中快閃記憶體裝置100僅具有兩個記憶體晶片。在一實施例中，快閃記憶體裝置100包括兩個以上之記憶體晶片。在另一實施例中，快閃記憶體裝置100為一多晶片堆疊結構。 Figure 1 is a schematic diagram of a flash memory device provided by the present invention. The flash memory device 100 accepts an instruction from the host 160 and writes data from the host 160 or other electronic device (not shown) to the flash memory device 100 according to the instruction, or reads the data according to the instruction. The data of the flash memory device 100 is transferred to the host 160 or other electronic device. In an embodiment, the host 160 can be a portable device or a computer product, and is coupled to the flash memory of the host 160. Device 100 can be a memory card. The flash memory device 100 includes a plurality of memory chips. Each memory chip, after receiving an instruction from the host 160, first determines whether the identification information of the command is the same as its own identification code. When the identification information of the instruction is the same as the identification code of the instruction, the instruction is executed to perform corresponding data transmission. The memory chip conforming to the identification information of the instruction may perform a write operation or a read operation on another memory chip while performing a write operation. For convenience of explanation, the flash memory device 100 has only two memory chips in this embodiment. In one embodiment, flash memory device 100 includes more than two memory chips. In another embodiment, the flash memory device 100 is a multi-wafer stack structure.
如第1圖所示，快閃記憶體裝置100包括一第一記憶體晶片110、第二記憶體晶片120、輸入緩衝器130以及輸出緩衝器140。如第1圖所示，輸入緩衝器130耦接至第一記憶體晶片110與第二記憶體晶片120，用以將來自主機160之指令或資料傳送至第一記憶體晶片110及/或第二記憶體晶片120。輸出緩衝器140耦接至第一記憶體晶片110與第二記憶體晶片120，用以將第一記憶體晶片110及/或第二記憶體晶片120之資料傳送至主機160或其他電子裝置。在一實施例中，輸入緩衝器130與輸出緩衝器140之功能可合併為一輸出入緩衝器。第一記憶體晶片110具有一第一辨識碼(未顯示)、一第一控制器112、以及一第一快閃記憶體114，而第二記憶體晶片120具有一第二辨識碼(未顯示)、一第二控制器122、以及一第二快閃記憶體124，其中第一控制器112與第二控制器122係為邏輯電路所組成之一硬體控制器。此外，快閃記憶體裝置100可連接至 一電源供應端VDD以及一接地端，以獲取資料存取所需之電源。 As shown in FIG. 1, the flash memory device 100 includes a first memory chip 110, a second memory chip 120, an input buffer 130, and an output buffer 140. As shown in FIG. 1 , the input buffer 130 is coupled to the first memory chip 110 and the second memory chip 120 for transferring instructions or data from the host 160 to the first memory chip 110 and/or the first Two memory wafers 120. The output buffer 140 is coupled to the first memory chip 110 and the second memory chip 120 for transferring the data of the first memory chip 110 and/or the second memory chip 120 to the host 160 or other electronic devices. In an embodiment, the functions of input buffer 130 and output buffer 140 may be combined into an output buffer. The first memory chip 110 has a first identification code (not shown), a first controller 112, and a first flash memory 114, and the second memory chip 120 has a second identification code (not shown). a second controller 122, and a second flash memory 124, wherein the first controller 112 and the second controller 122 are one of the hardware controllers. In addition, the flash memory device 100 can be connected to a power supply terminal V DD and a ground terminal for obtaining power required for data access.
值得注意的是，由於快閃記憶體裝置100連接至電源供應端VDD與接地端，因此可藉由不同的電壓值來定義第一辨識碼與第二辨識碼。在一實施例中，電源供應端VDD所提供之高電壓被標示為數位信號1，接地端所提供之低電壓被標示為數位信號0。在一實施例中，第一記憶體晶片110與第二記憶體晶片120之接腳連接到上述之電源供應端VDD與接地端，使得第一辨識碼與第二辨識碼被標示為1和0。在另一實施例中，快閃記憶體裝置100具有四個記憶體晶片，則電源供應端VDD與接地端之間可區分為複數個電壓準位，並且四個記憶體晶片之接腳分別連接至複數個電壓準位，使得其對應之第一辨識碼至第四辨識碼分別被標示為00、01、10與11。在另一實施例中，複數個辨識碼亦可藉由快閃記憶體裝置100內部之軟體或程式加以編碼或標示。舉例而言，快閃記憶體裝置100內部之軟體或程式輸入特定信號至複數個記憶體晶片並加以儲存，做為該等記憶體晶片之辨識碼。 It should be noted that since the flash memory device 100 is connected to the power supply terminal V DD and the ground terminal, the first identification code and the second identification code can be defined by different voltage values. In one embodiment, the high voltage provided by the power supply terminal V DD is labeled as digital signal 1 and the low voltage provided by the ground terminal is labeled as digital signal 0. In one embodiment, the pins of the first memory chip 110 and the second memory chip 120 are connected to the power supply terminal V DD and the ground end, so that the first identification code and the second identification code are marked as 1 and 0. In another embodiment, the flash memory device 100 has four memory chips, and the power supply terminal V DD and the ground terminal can be divided into a plurality of voltage levels, and the pins of the four memory chips are respectively Connected to a plurality of voltage levels such that their corresponding first to fourth identification codes are labeled 00, 01, 10, and 11, respectively. In another embodiment, the plurality of identification codes may also be encoded or labeled by a software or program internal to the flash memory device 100. For example, a software or program inside the flash memory device 100 inputs a specific signal to a plurality of memory chips and stores them as identification codes of the memory chips.
首先，快閃記憶體裝置100被開啟(power-up)後，會重新設定第一記憶體晶片110之第一辨識碼與第二記憶體晶片120之第二辨識碼，其中第一辨識碼不同於第二辨識碼。詳細而言，為了有效區別每一個辨識碼，快閃記憶體裝置100中的複數個記憶體晶片之辨識碼都是彼此相異的。然後，快閃記憶體裝置100會接收來自一主機160之一第一指令C10，第一指令C10包括一第一辨識部分C11以及一第一資料傳輸部分(亦可稱為第一主指令部分)C12。第一指令C10係透過輸入緩衝器130 而傳送到第一記憶體晶片110與第二記憶體晶片120。值得注意的是，此時第一記憶體晶片110與第二記憶體晶片120皆同時收到第一指令C10，並且第一控制器112會比對第一辨識碼與第一辨識部分C11，第二控制器122會比對第二辨識碼與第一辨識部分C11。由於各個辨識碼之間彼此相異，因此只有一個辨識碼會相同於該第一辨識部分C11。 First, after the flash memory device 100 is powered-up, the first identification code of the first memory chip 110 and the second identification code of the second memory chip 120 are reset, wherein the first identification code is different. In the second identification code. In detail, in order to effectively distinguish each identification code, the identification codes of the plurality of memory chips in the flash memory device 100 are different from each other. Then, the flash memory device 100 receives a first command C10 from a host 160, the first command C10 includes a first identification portion C11 and a first data transmission portion (also referred to as a first main command portion). C12. The first command C10 is transmitted through the input buffer 130 And transferred to the first memory chip 110 and the second memory chip 120. It should be noted that, at this time, the first memory chip 110 and the second memory chip 120 both receive the first command C10, and the first controller 112 compares the first identification code with the first identification part C11, The second controller 122 compares the second identification code with the first identification portion C11. Since the identification codes are different from each other, only one identification code will be identical to the first identification portion C11.
在一實施例中，當第一辨識部分C11相同於第一辨識碼時，亦即第一辨識部分C11不同於第二辨識碼，第一快閃記憶體114會執行該第一指令C10之第一資料傳輸部分C12，用以在第一操作週期內對第一快閃記憶體114進行第一存取操作。舉例而言，第一存取操作可為資料讀取或寫入之操作。當第一存取操作為資料寫入時，則資料會透過輸入緩衝器130而寫入第一快閃記憶體114之中。由於快閃記憶體需要較長的資料寫入時間，因此資料在通過輸入緩衝器130之後，可暫時儲存於快閃記憶體裝置100內部之一暫存器(未顯示)中。詳細而言，該暫存器可設置於記憶體晶片之控制器之中，或是設置於輸入緩衝器130之中。在第一操作週期內，被寫入第一快閃記憶體114已被儲到暫存器中的資料中，此時輸入緩衝器130可用以傳輸一第二指令C20至第一記憶體晶片110與第二記憶體晶片120。當第一存取操作為資料讀取時，自第一快閃記憶體114讀取的資料會通過輸出緩衝器140而輸出至主機160。在另一實施例中，當第一辨識部分C11不同於第一辨識碼時，則第一控制器112係忽略該第一指令C10，不對第一快閃記憶體114進行任何存取操作。 In an embodiment, when the first identification portion C11 is the same as the first identification code, that is, the first identification portion C11 is different from the second identification code, the first flash memory 114 executes the first instruction C10. A data transmission portion C12 is configured to perform a first access operation on the first flash memory 114 during the first operation cycle. For example, the first access operation can be an operation of reading or writing data. When the first access operation is data writing, the data is written into the first flash memory 114 through the input buffer 130. Since the flash memory requires a long data write time, the data can be temporarily stored in a register (not shown) inside the flash memory device 100 after passing through the input buffer 130. In detail, the register can be disposed in the controller of the memory chip or in the input buffer 130. During the first operation cycle, the first flash memory 114 is written into the data stored in the temporary memory. At this time, the input buffer 130 can be used to transmit a second command C20 to the first memory chip 110. And the second memory wafer 120. When the first access operation is data reading, the data read from the first flash memory 114 is output to the host 160 through the output buffer 140. In another embodiment, when the first identification portion C11 is different from the first identification code, the first controller 112 ignores the first instruction C10 and does not perform any access operation on the first flash memory 114.
值得注意的是，在第一快閃記憶體114執行第一存取操作之第一操作週期內，快閃記憶體裝置100可接收來自一主機或電腦裝置之一第二指令C20，第二指令C20包括一第二辨識部分C21以及一第二資料傳輸部分(亦可稱為第二主指令部分)C22。在一實施例中，快閃記憶體裝置100中的第一控制器112與第二控制器122都會接收該第二指令C20。當第二辨識部分C21相同於第二辨識碼時，第二快閃記憶體124會執行第二指令C20之第二資料傳輸部分C22，在第二操作週期內對第二快閃記憶體124進行第二存取操作。第二存取操作可為資料讀取或寫入之操作，其資料傳輸之詳細操作類似於第一存取操作，故此處不在贅述。 It should be noted that during the first operation cycle in which the first flash memory 114 performs the first access operation, the flash memory device 100 can receive the second instruction C20 from a host or a computer device, the second instruction The C20 includes a second identification portion C21 and a second data transmission portion (also referred to as a second main instruction portion) C22. In an embodiment, the first controller 112 and the second controller 122 in the flash memory device 100 both receive the second command C20. When the second identification portion C21 is identical to the second identification code, the second flash memory 124 executes the second data transmission portion C22 of the second instruction C20, and performs the second flash memory 124 in the second operation cycle. Second access operation. The second access operation may be an operation of reading or writing data, and the detailed operation of the data transmission is similar to the first access operation, so it will not be described here.
詳細而言，在一實施例中，當第一存取操作為資料寫入之操作時，在資料寫入第一快閃記憶體114之第一操作週期，第二快閃記憶體120可接收第二指令C20。此時，如果第二辨識碼相同於第二辨識部分C21，則第二快閃記憶體124可執行資料讀取或寫入之第二存取操作。由於第一快閃記憶體114所寫入的資料可儲存於暫存器中，因此當第一快閃記憶體114進行資料寫入的同時，第二快閃記憶體124可透過輸入緩衝器130而寫入另一筆資料，或是透過輸出緩衝器140輸出被讀取的資料。因此，當第一快閃記憶體114依據第一指令C10寫入資料時，第二快閃記憶體124可依據第二指令C20執行另一筆資料的讀取或寫入。 In detail, in an embodiment, when the first access operation is an operation of data writing, the second flash memory 120 can receive the data in the first operation cycle of the first flash memory 114. The second instruction C20. At this time, if the second identification code is identical to the second identification portion C21, the second flash memory 124 may perform a second access operation of data reading or writing. Since the data written by the first flash memory 114 can be stored in the temporary memory, the second flash memory 124 can pass through the input buffer 130 while the first flash memory 114 performs data writing. The other data is written, or the read data is output through the output buffer 140. Therefore, when the first flash memory 114 writes data according to the first command C10, the second flash memory 124 can perform reading or writing of another data according to the second command C20.
要注意的是，由於輸出緩衝器140一次只能通過一筆資料，並且快閃記憶體的讀取時間短於寫入時間，故快閃記 憶體的讀取資料不需要暫時存入一暫存器中。因此，當第一快閃記憶體114所讀取的資料通過輸出緩衝器140時，第二快閃記憶體124所讀取的資料便無法通過輸出緩衝器140。此外，在另一實施例中，當第二辨識部分C21不同於第二辨識碼，則第二控制器122係忽略該第二指令C20，不對第二快閃記憶體124進行任何存取操作。 It should be noted that since the output buffer 140 can only pass one data at a time, and the flash memory read time is shorter than the write time, the flash memory The reading data of the memory does not need to be temporarily stored in a temporary memory. Therefore, when the data read by the first flash memory 114 passes through the output buffer 140, the data read by the second flash memory 124 cannot pass through the output buffer 140. In addition, in another embodiment, when the second identification portion C21 is different from the second identification code, the second controller 122 ignores the second instruction C20 and does not perform any access operation on the second flash memory 124.
第2圖為本發明所提供之應用於快閃記憶體裝置之資料傳輸方法的流程圖。首先，在步驟S202中，開啟快閃記憶體裝置100之電源，在步驟S204中，重新設定每一記憶體晶片之辨識碼。於步驟S206中，每一記憶體晶片接收第一指令C10，其中第一指令C10包括第一辨識部分C11以及第一資料傳輸部分C12。於步驟S208中，判斷是否有一記憶體晶片之辨識碼相同於所接收的第一辨識部分C11。如果是，則進入步驟S210；如果否，則回到步驟S206。在步驟S210中，辨識碼與第一辨識部分C11相同之記憶體晶片(假設是第一記憶體晶片110)執行第一資料傳輸部分C12，用以在第一操作週期中執行第一存取操作，並且每一記憶體晶片於第一操作週期中接收第二指令C20，其中第二指令C20包括第二辨識部分C21以及第二資料傳輸部分C22。然後，進入步驟S212，判斷是否有一記憶體晶片之辨識碼相同於所接收的第二辨識部分C21。如果是，則進入步驟S214；如果否，則回到步驟S210。在步驟S214中，辨識碼與第二辨識部分C21相同之記憶體晶片(假設是第二記憶體晶片120)執行第二資料傳輸部分C22以進行一第二存取操作。接著，進入步驟S216，結束快閃記憶體裝置100傳輸資料之流 程。 FIG. 2 is a flow chart of a data transmission method applied to a flash memory device according to the present invention. First, in step S202, the power of the flash memory device 100 is turned on, and in step S204, the identification code of each memory chip is reset. In step S206, each memory chip receives a first instruction C10, wherein the first instruction C10 includes a first identification portion C11 and a first data transmission portion C12. In step S208, it is determined whether a memory chip has an identification code identical to the received first identification portion C11. If yes, go to step S210; if no, go back to step S206. In step S210, the memory chip (which is assumed to be the first memory chip 110) whose identification code is identical to the first identification portion C11 executes the first data transfer portion C12 for performing the first access operation in the first operation cycle. And each memory chip receives the second instruction C20 in the first operation cycle, wherein the second instruction C20 includes the second identification portion C21 and the second data transmission portion C22. Then, proceeding to step S212, it is determined whether a memory chip identification code is identical to the received second identification portion C21. If yes, go to step S214; if no, go back to step S210. In step S214, the memory chip (assuming the second memory chip 120) having the same identification code as the second identification portion C21 executes the second data transfer portion C22 to perform a second access operation. Next, proceeding to step S216, ending the flow of data transmitted by the flash memory device 100 Cheng.
惟以上所述者，僅為本揭露之較佳實施例而已，當不能以此限定本揭露實施之範圍，即大凡依本揭露申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本揭露專利涵蓋之範圍內。另外，本揭露的任一實施例或申請專利範圍不須達成本揭露所揭露之全部目的或優點或特點。此外，摘要部分和標題僅是用來輔助專利文件搜尋之用，並非用來限制本揭露之權利範圍。 The above is only the preferred embodiment of the present disclosure, and the scope of the disclosure is not limited thereto, that is, the simple equivalent changes and modifications made by the disclosure of the patent application scope and the description of the invention, All remain within the scope of this disclosure. In addition, any of the embodiments or advantages of the present disclosure are not required to achieve all of the objects or advantages or features disclosed in the present disclosure. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the disclosure.
100‧‧‧快閃記憶體裝置 100‧‧‧Flash memory device
110‧‧‧第一記憶體晶片 110‧‧‧First memory chip
112‧‧‧第一控制器 112‧‧‧First controller
114‧‧‧第一快閃記憶體 114‧‧‧First flash memory
120‧‧‧第二記憶體晶片 120‧‧‧Second memory chip
122‧‧‧第二控制器 122‧‧‧Second controller
124‧‧‧第二快閃記憶體 124‧‧‧Second flash memory
130‧‧‧輸入緩衝器 130‧‧‧Input buffer
140‧‧‧輸出緩衝器 140‧‧‧Output buffer
160‧‧‧主機 160‧‧‧Host
C10‧‧‧第一指令 C10‧‧‧ first order
C11‧‧‧第一辨識部分 C11‧‧‧ first identification part
C12‧‧‧第一資料傳輸部分 C12‧‧‧First data transmission part
C20‧‧‧第二指令 C20‧‧‧Second Directive
C21‧‧‧第二辨識部分 C21‧‧‧Second identification part
C22‧‧‧第二資料傳輸部分 C22‧‧‧Second data transmission part
VDD‧‧‧電源供應端 V DD ‧‧‧Power supply
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| US10394456B2 (en) | 2017-08-23 | 2019-08-27 | Micron Technology, Inc. | On demand memory page size |
| TWI679536B (en) * | 2017-08-23 | 2019-12-11 | 美商美光科技公司 | Memory with virtual page size |
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| TW200519585A (en) * | 2003-12-11 | 2005-06-16 | Genesys Logic Inc | Method and related devices for enhancing accessing performance of flash memory |
| US7870351B2 (en) * | 2007-11-15 | 2011-01-11 | Micron Technology, Inc. | System, apparatus, and method for modifying the order of memory accesses |
| TWI425512B (en) * | 2009-06-16 | 2014-02-01 | Phison Electronics Corp | Flash memory controller circuit and storage system and data transfer method thereof |
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| US10394456B2 (en) | 2017-08-23 | 2019-08-27 | Micron Technology, Inc. | On demand memory page size |
| TWI679536B (en) * | 2017-08-23 | 2019-12-11 | 美商美光科技公司 | Memory with virtual page size |
| US11157176B2 (en) | 2017-08-23 | 2021-10-26 | Micron Technology, Inc. | On demand memory page size |
| US11210019B2 (en) | 2017-08-23 | 2021-12-28 | Micron Technology, Inc. | Memory with virtual page size |
| US11747982B2 (en) | 2017-08-23 | 2023-09-05 | Micron Technology, Inc. | On-demand memory page size |
| US12001715B2 (en) | 2017-08-23 | 2024-06-04 | Micron Technology, Inc. | Memory with virtual page size |
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