TW201436028A - Wafer edge protector - Google Patents

Wafer edge protector Download PDF

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Publication number
TW201436028A
TW201436028A TW102108541A TW102108541A TW201436028A TW 201436028 A TW201436028 A TW 201436028A TW 102108541 A TW102108541 A TW 102108541A TW 102108541 A TW102108541 A TW 102108541A TW 201436028 A TW201436028 A TW 201436028A
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Taiwan
Prior art keywords
wafer
protection device
edge protection
inner diameter
wafer edge
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TW102108541A
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Chinese (zh)
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Chia-Hao Chen
Yi-Feng Wei
Yao-Chung Hsieh
I-Te Cho
Walter Tony Wohlmuth
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Win Semiconductors Corp
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Priority to TW102108541A priority Critical patent/TW201436028A/en
Publication of TW201436028A publication Critical patent/TW201436028A/en

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A wafer edge protector used in an inductively coupled plasma reactive ion etching instrument for the manufacturing of GaN semiconductor devices and circuits. The wafer edge protector comprises a ring clamp, which has a first inner diameter and a second inner diameter, and the ring clamp covers the edges of a wafer and a wafer carrier to clamp the wafer and the wafer carrier and to prevent damage on the edges of the wafer and the wafer carrier during the etching process.

Description

晶圓邊緣保護裝置 Wafer edge protector

本發明係有關一種晶圓邊緣保護裝置,尤指一種應用於一用於氮化鎵半導體元件及電路製程之感應耦合電漿離子蝕刻機台內之晶圓邊緣保護裝置。 The present invention relates to a wafer edge protection device, and more particularly to a wafer edge protection device for use in an inductively coupled plasma ion etching machine for a gallium nitride semiconductor device and a circuit process.

感應耦合電漿離子蝕刻(inductively coupled plasma reactive ion etch)方法常應用於化合物半導體晶片之製程中,蝕刻時須先將化合物半導體晶圓固定於一作為晶圓載具之晶座上,再將晶圓連同晶座固定於蝕刻機台內進行蝕刻。習知技術中用於固定晶圓及晶座之夾具通常為一爪型晶圓夾具,此爪型晶圓夾具一般具有六個或八個指型物,以環繞方式排列,用於固定半導體晶圓及晶座;由於進行化合物半導體晶片背面導孔蝕刻時須使用較高偏壓功率,因此常在蝕刻過程中造成晶片邊緣損壞,使產品良率無法提高,承載半導體晶圓之晶座也會因其邊緣曝露於電漿中而受到損壞而須時常更換而增加生產成本。 The inductively coupled plasma reactive ion etch method is commonly used in the fabrication of compound semiconductor wafers. The etched semiconductor semiconductor wafer must be fixed on a wafer holder as a wafer carrier. The etching is performed together with the crystal holder fixed in the etching machine. The fixture for fixing the wafer and the crystal holder in the prior art is usually a claw type wafer fixture. The claw type wafer fixture generally has six or eight fingers arranged in a surrounding manner for fixing the semiconductor crystal. Circles and crystal holders; due to the use of higher bias power during the etching of the back side of the compound semiconductor wafer, the edge of the wafer is often damaged during the etching process, so that the yield of the product cannot be improved, and the crystal holder carrying the semiconductor wafer is also Increased production costs due to damage to the edges due to exposure to the plasma and frequent replacement.

本發明之主要目的在於提供一種晶圓邊緣保護裝置,用於半導體晶圓電漿離子蝕刻製程中,使半導體晶圓之邊緣不易受損,晶座在蝕刻過程中能免受蝕刻物質的破壞,因此能提高產品的良率,並能延長晶座之使用壽命以節省製程成本。 The main object of the present invention is to provide a wafer edge protection device for use in a semiconductor wafer plasma ion etching process, so that the edge of the semiconductor wafer is not easily damaged, and the crystal holder can be protected from etching substances during the etching process. Therefore, the yield of the product can be improved, and the service life of the crystal seat can be prolonged to save the process cost.

為達上述目的,本發明提供一種晶圓邊緣保護裝置,其係供 安裝於一感應耦合電漿離子蝕刻機台內,前述晶圓邊緣保護裝置具有一環形夾持部,其中前述環形夾持部具有一第一內直徑以及一第二內直徑,覆蓋一半導體晶圓及一晶座之邊緣,用以夾持前述半導體晶圓及晶座,並保護前述半導體晶圓及晶座之邊緣在蝕刻過程中不受損壞。 To achieve the above object, the present invention provides a wafer edge protection device for Mounted in an inductively coupled plasma ion etching machine, the wafer edge protection device has an annular clamping portion, wherein the annular clamping portion has a first inner diameter and a second inner diameter, covering a semiconductor wafer And an edge of a crystal holder for holding the semiconductor wafer and the crystal holder, and protecting the edges of the semiconductor wafer and the crystal holder from being damaged during the etching process.

於實施時,前述第一內直徑為介於40 mm至200 mm之間。 In implementation, the aforementioned first inner diameter is between 40 mm and 200 mm.

於實施時,前述第二內直徑為介於50 mm至1000 mm之間。 In implementation, the aforementioned second inner diameter is between 50 mm and 1000 mm.

於實施時,前述環形夾持部係以陶瓷材料製成。 In implementation, the aforementioned annular clamping portion is made of a ceramic material.

於實施時,前述晶圓係為一化合物半導體氮化鎵(GaN)晶圓,其尺寸為介於50 mm至200 mm之間 In implementation, the wafer is a compound semiconductor gallium nitride (GaN) wafer with a size between 50 mm and 200 mm.

於實施時,前述化合物半導體氮化鎵晶圓係固定於一尺寸介於50 mm至200 mm間之晶座。 In implementation, the compound semiconductor gallium nitride wafer is fixed to a crystal holder having a size between 50 mm and 200 mm.

於實施時,前述供固定氮化鎵晶圓之晶座係以藍寶石(sapphire)材料基板、玻璃材料基板或碳化矽材料基板製作。 In the implementation, the crystal holder for fixing the gallium nitride wafer is made of a sapphire material substrate, a glass material substrate or a tantalum carbide material substrate.

為對於本發明之特點與作用能有更深入之瞭解,茲藉實施例配合圖式詳述於後。 For a better understanding of the features and functions of the present invention, the embodiments are described in detail below with reference to the drawings.

10‧‧‧感應耦合電漿離子蝕刻機台 10‧‧‧Inductively coupled plasma ion etching machine

100‧‧‧晶圓邊緣保護裝置 100‧‧‧ Wafer edge protection device

101‧‧‧環形夾持部 101‧‧‧Ring clamping

102‧‧‧第一內直徑 102‧‧‧First inner diameter

103‧‧‧第二內直徑 103‧‧‧Second inner diameter

104‧‧‧晶圓邊緣覆蓋寬度 104‧‧‧ Wafer edge coverage width

110‧‧‧半導體晶圓 110‧‧‧Semiconductor wafer

120‧‧‧晶座 120‧‧‧crystal seat

第1A至1C圖係為本發明所提供的晶圓邊緣保護裝置之一實施例之示意圖與局部截面放大圖。 1A to 1C are schematic and partial cross-sectional enlarged views of an embodiment of a wafer edge protection device provided by the present invention.

請參閱第1A至1C圖,其為本發明所提供的晶圓邊緣保護裝置之一種實施例之示意圖,其中第1C圖為第1B圖中由虛線C所圈出部分之放大圖,此晶圓邊緣保護裝置100係安裝於一感應耦合電漿離子蝕刻機 台10內,具有一環形夾持部101,其中前述環形夾持部101具有一第一內直徑102以及一第二內直徑103,前述邊緣保護裝置100於使用時覆蓋一半導體晶圓110及一晶座120之邊緣,用以夾持前述半導體晶圓110及晶座120,並保護前述半導體晶圓110及晶座120之邊緣在蝕刻過程中不受損壞。 Please refer to FIGS. 1A to 1C , which are schematic diagrams of an embodiment of a wafer edge protection device according to the present invention, wherein FIG. 1C is an enlarged view of a portion circled by a broken line C in FIG. 1B. The edge protection device 100 is mounted on an inductively coupled plasma ion etching machine The ring 10 has a first inner diameter 102 and a second inner diameter 103. The edge protection device 100 covers a semiconductor wafer 110 and a The edge of the crystal holder 120 is used to sandwich the semiconductor wafer 110 and the crystal holder 120, and protect the edges of the semiconductor wafer 110 and the crystal holder 120 from being damaged during the etching process.

在本發明所提供的實施例中,由前述第一內直徑102所形成之開口係作為半導體晶圓之蝕刻區域,而第二內直徑103所形成之空間需能完全包含整個晶圓及晶座,此發明可應用在化合物半導體氮化鎵晶圓,尺寸大小涵蓋2吋(50 mm)到8吋(200 mm),氮化鎵(GaN)晶圓包含成長於一半絕緣性4H碳化矽(4H-SiC)或6H碳化矽(6H-SiC)基板之以氮化鎵為主之磊晶層,而用以承載晶圓的晶座其尺寸須大於等於晶圓尺寸,因此第一內直徑102可為介於40 mm至200 mm之間,而第二內直徑103可為介於50 mm至1000 mm之間;以目前氮化鎵晶圓生產線之主流尺寸4吋(100 mm)晶圓為例,氮化鎵晶圓常用晶座為以具導電性材料構成之藍寶石(sapphire)晶座、玻璃晶座或碳化矽晶座,尺寸可為4吋(100 mm)至8吋(200 mm),因此對4吋晶圓而言,本發明所提供的晶圓邊緣保護裝置之最佳實施例中,第一內直徑102之範圍為介於90 mm至100 mm之間,而第二內直徑103之範圍可介於100 mm至200 mm之間,此設計所覆蓋之4吋晶圓邊緣覆蓋寬度104約為1.5至5.0 mm;前述第一內直徑及第二內直徑之範圍可隨晶圓及晶座尺寸大小而進行調整;為了達到保護晶圓及晶座邊緣的功能,前述環形夾持部101以具有高硬度、高抗蝕刻性及高抗腐蝕性之材料製成為較佳,其中以陶瓷材料為最佳選擇。 In the embodiment provided by the present invention, the opening formed by the first inner diameter 102 is used as an etched area of the semiconductor wafer, and the space formed by the second inner diameter 103 needs to completely cover the entire wafer and the crystal seat. The invention can be applied to compound semiconductor gallium nitride wafers ranging in size from 2 吋 (50 mm) to 8 吋 (200 mm), and gallium nitride (GaN) wafers containing half of insulating 4H tantalum carbide (4H) a gallium nitride-based epitaxial layer of a -SiC) or 6H tantalum carbide (6H-SiC) substrate, and the size of the crystal holder used to carry the wafer must be greater than or equal to the wafer size, so the first inner diameter 102 can be Between 40 mm and 200 mm, and the second inner diameter 103 can be between 50 mm and 1000 mm; for example, the current mainstream size of a gallium nitride wafer production line is 4 吋 (100 mm) wafer. The commonly used crystal holder for a gallium nitride wafer is a sapphire crystal holder made of a conductive material, a glass crystal holder or a silicon carbide crystal holder, and the size can be 4 吋 (100 mm) to 8 吋 (200 mm). Therefore, in the preferred embodiment of the wafer edge protection device provided by the present invention, the range of the first inner diameter 102 is between Between 90 mm and 100 mm, and the second inner diameter 103 can range from 100 mm to 200 mm. The 4 吋 wafer edge coverage width 104 covered by this design is about 1.5 to 5.0 mm; The range of the inner diameter and the second inner diameter can be adjusted according to the size of the wafer and the crystal seat; in order to protect the function of the wafer and the edge of the crystal seat, the annular clamping portion 101 has high hardness and high etching resistance. High corrosion resistance materials are preferred, with ceramic materials being the best choice.

因此,本發明所提供的晶圓邊緣保護裝置藉由覆蓋晶圓及晶座之邊緣,使半導體晶圓之邊緣不易受損,且因晶圓及晶座之邊緣皆受到覆蓋保護,用於接合晶圓與晶座之膠質或蠟在蝕刻過程中不會曝露於蝕刻 材料中,因此能避免膠質及蠟受蝕刻而漏出汙染晶圓,同時亦能避免晶座在蝕刻過程中受蝕刻物質的破壞。 Therefore, the wafer edge protection device provided by the present invention covers the edge of the wafer and the crystal seat, so that the edge of the semiconductor wafer is not easily damaged, and the edges of the wafer and the crystal holder are covered and protected for bonding. The paste or wafer of the wafer or wafer is not exposed to etching during the etching process. In the material, it is possible to prevent the glue and the wax from being etched and leaking the contaminated wafer, and at the same time, the crystal seat can be prevented from being damaged by the etching material during the etching process.

綜上所述,本發明提供之晶圓邊緣保護裝置確實可達到預期之目的,於電漿離子蝕刻製程中保護晶圓及晶座邊緣,因此能提高產品的良率,並能延長晶座之使用壽命,進而節省製程成本。其確具產業利用之價值,爰依法提出發明專利申請。 In summary, the wafer edge protection device provided by the present invention can achieve the intended purpose, and protect the wafer and the edge of the crystal holder in the plasma ion etching process, thereby improving the yield of the product and extending the crystal seat. Service life, which in turn saves process costs. It does have the value of industrial use, and it submits invention patent applications according to law.

又上述說明與圖示僅是用以說明本發明之實施例,凡熟於此業技藝之人士,仍可做等效的局部變化與修飾,其並未脫離本發明之技術與精神。 The above description and the drawings are merely illustrative of the embodiments of the present invention, and those skilled in the art can still make equivalent local variations and modifications without departing from the spirit and scope of the invention.

10‧‧‧感應耦合電漿離子蝕刻機台 10‧‧‧Inductively coupled plasma ion etching machine

100‧‧‧晶圓邊緣保護裝置 100‧‧‧ Wafer edge protection device

101‧‧‧環形夾持部 101‧‧‧Ring clamping

102‧‧‧第一內直徑 102‧‧‧First inner diameter

103‧‧‧第二內直徑 103‧‧‧Second inner diameter

110‧‧‧半導體晶圓 110‧‧‧Semiconductor wafer

120‧‧‧晶座 120‧‧‧crystal seat

Claims (8)

一種晶圓邊緣保護裝置,供安裝於一感應耦合電漿離子蝕刻機台內,該晶圓邊緣保護裝置具有一環形夾持部,其中該環形夾持部具有一第一內直徑以及一第二內直徑,覆蓋一半導體晶圓及一晶座之邊緣,用以夾持該半導體晶圓及該晶座,並保護該半導體晶圓及該晶座之邊緣在蝕刻過程中不受損壞。 A wafer edge protection device for mounting in an inductively coupled plasma ion etching machine, the wafer edge protection device having an annular clamping portion, wherein the annular clamping portion has a first inner diameter and a second The inner diameter covers an edge of a semiconductor wafer and a crystal holder for holding the semiconductor wafer and the crystal holder, and protects the semiconductor wafer and the edge of the crystal holder from being damaged during the etching process. 如申請專利範圍第1項所述之晶圓邊緣保護裝置,其中該第一內直徑為介於40 mm至200 mm之間。 The wafer edge protection device of claim 1, wherein the first inner diameter is between 40 mm and 200 mm. 如申請專利範圍第1項所述之晶圓邊緣保護裝置,其中該第二內直徑為介於50 mm至1000 mm之間。 The wafer edge protection device of claim 1, wherein the second inner diameter is between 50 mm and 1000 mm. 如申請專利範圍第1項所述之晶圓邊緣保護裝置,其中該環形夾持部係以陶瓷材料製成。 The wafer edge protection device of claim 1, wherein the annular clamping portion is made of a ceramic material. 如申請專利範圍第1項所述之晶圓邊緣保護裝置,其中該晶圓係為一化合物半導體氮化鎵(GaN)晶圓,其尺寸為介於50 mm至200 mm之間。 The wafer edge protection device of claim 1, wherein the wafer is a compound semiconductor gallium nitride (GaN) wafer having a size between 50 mm and 200 mm. 如申請專利範圍第5項所述之晶圓邊緣保護裝置,其中該化合物半導體氮化鎵(GaN)晶圓包含成長於一半絕緣性4H碳化矽(4H-SiC)或6H碳化矽(6H-SiC)基板之以氮化鎵為主之磊晶層。 The wafer edge protection device according to claim 5, wherein the compound semiconductor gallium nitride (GaN) wafer comprises a semi-insulating 4H tantalum carbide (4H-SiC) or 6H tantalum carbide (6H-SiC). The substrate is a gallium nitride-based epitaxial layer. 如申請專利範圍第6項所述之晶圓邊緣保護裝置,其中該化合物半導體氮化鎵晶圓係固定於一尺寸介於50 mm至200 mm間之晶座。 The wafer edge protection device of claim 6, wherein the compound semiconductor gallium nitride wafer is fixed to a crystal holder having a size between 50 mm and 200 mm. 如申請專利範圍第7項所述之晶圓邊緣保護裝置,其中該晶座係以藍寶石(sapphire)材料基板、玻璃材料基板或碳化矽材料基板製作。 The wafer edge protection device of claim 7, wherein the crystal holder is made of a sapphire material substrate, a glass material substrate or a tantalum carbide material substrate.
TW102108541A 2013-03-11 2013-03-11 Wafer edge protector TW201436028A (en)

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