TW201435888A - Data storage device and flash memory control method - Google Patents

Abstract

A data storage device and a control method for a FLASH memory thereof are disclosed. The control method includes the following steps: dividing a plurality of blocks of the FLASH memory into different groups to be accessed via different channels; allocating cache space in a Random Access Memory, wherein, each cache space is allocated to provide every channel with temporary storage space for write data; separating write data from a host to correspond to the different channels; and, when a latest updated temporary data in the cache space corresponds to a logical address of the write data from the host, the latest updated temporary data in the cache space is overwritten by the write data.

Description

Data storage device and flash memory control method

The present invention relates to a data storage device implemented in a flash memory and a control method for a flash memory.

Today's data storage devices often use FLASH memory as the storage medium. For example, NAND FLASH, which is not a gate type, is often used as a memory card, a USB flash device, a solid state drive (SSD), etc. . Another application is to package a NAND FLASH wafer and a control wafer into a single chip package called an embedded flash memory module (eMMC).

Flash memory is not only widely used, but its capacity has also increased significantly with the development of process technology. However, the ever-increasing memory capacity makes the control mode of the flash memory more significantly affect the operational performance of the flash memory.

The invention discloses a data storage device implemented by flash memory, and discloses a control method of a flash memory.

A data storage device implemented according to an embodiment includes: a flash memory and a controller coupled to the flash memory. The flash memory has a plurality of blocks, and each block has a plurality of pages. The partitions are divided by a plurality of access channels. The controller includes an arithmetic unit and a unique Read memory, and a random access memory. The program contained in the read-only memory is executed by the arithmetic unit as the firmware of the data storage device. The random access memory system supplies a set of cache space under the computing unit plan for executing the firmware. The set of cache space provides a temporary storage space for writing data for each of the plurality of access channels. In addition, the computing unit further distributes the write data issued by one host to the plurality of access channels. When the logical address mapped by the write data is the same as the logical address mapped by the latest temporary data in the set of cache space, the operation unit is updated in the set of cache space by the write data. The latest temporary data.

According to another embodiment of the present invention, a method for controlling a flash memory includes: dividing a plurality of blocks of a flash memory by a plurality of access channels, each block having a plurality of pages; At least one set of cache space is planned in the memory, and the set of cache space provides a temporary storage space for writing data for each of the plurality of access channels; and the write data distributed by one host is corresponding to the plurality of accesses. a channel; and, when the logical address mapped by the write data is the same as the logical address of the latest temporary data in the set of cache space, the write data is used in the set of cache space Update the latest temporary data.

The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

102‧‧‧ data storage device

104‧‧‧Host

106‧‧‧Flash memory

108‧‧‧ Controller

110‧‧‧ arithmetic unit

112‧‧‧Read-only processor

114‧‧‧ Random access memory

Cache_CE1, Cache_CE2...Cache_CEi, Cache_CEi+1, Cache_CEi+2, Caceh_CEN‧‧‧ a set of cache space

CE1, CE2...CEN‧‧‧ wafer/access channel

HPage1, HPE2...HPageN‧‧‧ logical address

HPage1_Old, HPN_Old‧‧‧ Logical addresses HPage1 and HPageN do not need to be updated

HPageA, HPPB, HPP, HPageF, HPageG‧‧‧ logical address

PAGE11...PAGE1K, PAGE21...PAGE2K, PAGEN1...PAGENK‧‧‧

S502...S510, S602...S612‧‧‧ steps

T1, T2, T3, T4, T5‧‧‧ timing

1 illustrates a data storage device 102 implemented in accordance with an embodiment of the present invention that communicates with a host 104; FIG. 2 illustrates an embodiment of the present invention in which a write by host 104 is performed. The input operation involves a plurality of logical addresses HPage1, HPage2...HPageN (not limited to consecutive logical addresses), and logical addresses HPage1, HPage2...HPageN are not repeated; FIG. 3 illustrates another embodiment of the present invention, The write operation issued by the host 104 sequentially involves logical addresses HPageF, HPageG, and HPageF, and the logical address HPageF is repeatedly discontinuous; FIG. 4 illustrates another embodiment of the present invention, wherein the write by the host 104 is performed. The operation sequentially involves the logical address HPageA, HPageB and the continuously repeated logical address HPageC; the fifth figure describes the data sorting operation of the "logical address check" by a flowchart; and the sixth figure depicts the logical position by a flowchart Another embodiment of the data sorting operation of the address check.

The following description sets forth various embodiments of the invention. The following description sets forth the basic concepts of the invention and is not intended to limit the invention. The scope of the actual invention shall be defined in accordance with the scope of the patent application.

1 illustrates a data storage device 102 implemented in communication with a host 104 in accordance with an embodiment of the present invention. The data storage device 102 includes a flash memory 106 and a controller 108.

This paragraph discusses the design of the flash memory 106. In order to process more than one operation command at the same time, the flash memory 106 adopts a multi-access channel technology, wherein a plurality of blocks of the flash memory 106 are divided by a plurality of access channels for access. As shown in the embodiment shown, the flash memory 106 is Multiple access channels are implemented with multiple wafers CE1, CE2...CEN (involving chip enabled technology). A single wafer corresponds to a single access channel, and the access channels are labeled with the same reference numerals CE1, CE2, ... CEN. Each wafer is provided with a plurality of blocks. Each block has a plurality of pages (pages, PAGE11~PAGENK, that is, "pages"). Although a single wafer simultaneous segment allows only a single access operation, the multiple access channel design formed by the multi-chip allows the flash memory 106 to cope with multiple access operations simultaneously.

The design of the controller 108 is discussed below.

The controller 108 is coupled to the flash memory 106 and includes an operation unit 110, a read-only memory 112, and a random access memory 114. The program contained in the read-only memory 112 is executed by the arithmetic unit 110 as the firmware of the data storage device 102. The random access memory 114 supplies a set of cache space (Cache Space), including a space Cache_CE1, Cache_CE2, ... Cache_CEN, corresponding to the plurality of access channels CE1, CE2, respectively, under the planning of the computing unit 110 executing the firmware. ...CEN for data collation. The computing unit 110 executing the firmware causes the write data distributed by the host 104 to be distributed corresponding to the plurality of access channels CE1, CE2, . . . CEN to be temporarily stored in the cache space Cache_CE1, Cache_CE2... The Cache_CEN is merged with the data read from the flash memory 106. The completed data will be written to the flash memory 106 according to the access channel corresponding to its space. In one embodiment, the space Cache_CE1, Cache_CE2, ... Cache_CEN each occupy a "super page" size, the size is K "pages", and K is a quantity value. The content of the space Cache_CE1 can be written to the page PAGE11...page PAGE1K dispersed on the K block via the access channel CE1, and the content of the space Cache_CE2 can be accessed. The channel CE2 writes the page PAGE21...page PAGE2K dispersed on the K block, and so on, the content of the space Cache_CEN can be written to the page PAGEN1 ... PAGENK scattered on the K block via the access channel CEN. The "super page" design allows the writing of K pages to be implemented by a single write command, effectively reducing the number of instructions.

The present invention includes considering the logical address of the host 104 in the utilization of the cache space Cache_CE1, Cache_CE2, ... Cache_CEN. The implementation in the figure is to design a logical address checking mechanism in the firmware. Figure 2, Figure 3, and Figure 4 illustrate the use of cache space for different logical addresses.

Referring to FIG. 2, the write operation issued by the host 104 involves a plurality of logical addresses HPage1, HPage2...HPageN (not limited to consecutive logical addresses), and the logical addresses HPage1, HPage2...HPageN are not repeated. . The operation unit 110 is configured to distribute the logical addresses HPage1, HPage2, ...HPageN corresponding to different access channels CE1, CE2, ..., CEN, and according to the host 104, about the logical addresses HPage1, HPage2 The write data of HPageN is temporarily stored in the cache space Cache_CE1, Cache_CE2, ... Cache_CEN. As shown in the figure, the write data of the logical address HPage1 is temporarily stored by the space Cache_CE1, and the write data of the logical address HPage2 is temporarily stored by the space Cache_CE2... The write data of the logical address HPageN is temporarily stored by the space Cache_CEN. As for the logical address that only needs to be locally written - for example, the start logical address HPage1 and the end logical address HPageN of a write operation - the data that does not need to be updated, HPage1_Old, and HPen_Old are copied from the flash memory 106 to the random memory. The corresponding spaces Cache_CE1 and Cache_CEN on the memory 114 are combined with the write data issued by the host 104. In this way, the logical addresses HPage1, HPage2...HPageN are each The complete data is organized in the cache space Cache_CE1, Cache_CE2, ... Cache_CEN, which can be exposed according to the access channels CE1, CE2 of the cache space Cache_CE1, Cache_CE2, Cache_CEN... CEN is written to the flash memory 106.

Referring to FIG. 3, the write operation issued by the host 104 sequentially involves logical addresses HPageF, HPageG, and HPageF, and the logical address HPageF is repeatedly discontinuously. The actions of the arithmetic unit 110 are discussed below in chronological order. At time T1, the data of the logical address HPageF is organized in the space Cache_CEi. At time T2, the data of the logical address HPageG is organized in the space Cache_CEi+1. At time sequence T3, the host 104 again issues a write command of the logical address HPageF, and the arithmetic unit 110 executing the firmware will check that the logical address HPageF is already in the latest use of the set of cache space (the latest use is Cache_CEi+) 1, non-latest use includes Cache_CE1...Cache_CEi) There is a corresponding configuration data space Caceh_CEi, then, under the timing T4, the set of cache space has temporary storage content (ie space Cache-CE1...Cache- The content of CEi+1 is written to the flash memory 106 in accordance with the associated access channel CE1...CEi+1. As for the logical address HPageF write operation of the host 104 at the timing T3, the data is sorted by a contiguous space Cache_CEi+2 in the set of flash space at the timing T5. Regarding the unexpected power down event, the design is such that the content of the flash memory 106 is updated in accordance with the timing of the write operation issued by the host 104, and the update timing of each logical address is correct. As for Cache_CEi+2 and the following space (to Cache_CEN), it can be written according to the access channel CEi+2...CEN after the end space of the set of cache space (ie Cache_CEN) is filled. The flash memory 106.

Referring to FIG. 4, the write operation issued by the host 104 sequentially involves the logical address HPageA, the HPageB, and the HPageC repeated twice. The logical address HPageC is repeated continuously. The actions of the arithmetic unit 110 are discussed below in chronological order. Timing T1, the data of the logical address HPageA is organized in the space Cache_CEi. At time T2, the data of the logical address HPageB is organized in the space Cache_CEi+1. At time T3, the data of the logical address HPageC is organized in the space Cache_CEi+2. At time sequence T4, the host 104 again issues a write instruction to the logical address HPageC, and the operation unit 110 executing the firmware will check that the logical address HPageC has been configured correspondingly to the latest use location Cache_CEi+2 of the set of cache space, thus, At time sequence T5, the computing unit 110 executing the firmware repeatedly uses the latest usage location Cache_CEi+2 to organize the logical address HPageC. This design can effectively improve the performance of the cache space Cache_CE1, Cache_CE2...Cache_CEN.

Figure 5 is a flow chart describing the data sorting operation of the "logical address check". Regarding the write operation issued by the host 104, a logical address to be collated is HPagej. Step S502 is to compare whether the logical address HPagej is the same as the logical address HPagej-1 corresponding to the configuration of the latest use location (Cache_CEj-1) in the set of cache spaces. If the logical address HPagej is the same as the logical address HPagej-1, then step S504 is performed to repeatedly use the space Cache_CEj-1 as the data of the logical address HPagej. If the logical address HPagej is different from the logical address HPagej-1, proceed to step S506, and further configure the logical address HPagej to be collated and the non-latest use location (Cache_CE1...Cache_CEj-2) in the set of cache space. Corresponding logical addresses HPage1...HPagej-2 are compared. If there is no duplication between the logical address HPagej and the logical addresses HPage1...HPagej-2, proceed to step S508 to cache the set The splicing space Cache_CEj in the space is used as the data of the logical address HPagej. If the logical address HPagej is repeated with any of the logical addresses HPage1...HPagej-2, then step S510 is performed, and the portion Cache_CE1...Cache_CEj-1 in which the set of cache space has been temporarily stored has the access according to the access. The channel CE1...CEj-1 is written into the flash memory 106, and then proceeds to step S508 to organize the data of the logical address HPagej with the connection space Cache_CEj in the set of cache space.

Fig. 6 is a flow chart showing another embodiment of the data sorting operation of "logical address check". Step S602 is used to determine whether the logical address of the data to be mapped is the same as the logical address of the latest temporary data in the set of cache data; if the same, the flow proceeds to step S604, where the cache is set. In the space, the latest temporary data is updated with the written data. If the result of the determination in step S602 is not the same, the flow proceeds to step S606, and it is determined whether the logical address mapped by the written data is the same as the logical address mapped by the non-latest temporary data in the set of cached space. If the result of the determination in step S606 is different, the process proceeds to step S608, and the write data is stored in the set of cache space. Otherwise, the process proceeds to step S610, and the same logic is mapped to the write data in the set of cache space. The non-latest temporary data of the address is written to the flash memory. Then, the process proceeds to step S612, where the written data is stored in the set of cache space.

The data storage device disclosed in the above embodiments can be implemented as a memory card, a universal flash memory device (USB flash device), a solid state hard disk (SSD), and the like. In another embodiment, a multi-chip package is used to package a NAND FLASH wafer and a control chip into a single chip - called an embedded flash memory module (eMMC).

The above disclosed content can be implemented in firmware in a stylized manner. The associated code can be carried in the read-only memory 112 and executed by the arithmetic unit 110. In addition, in addition to the structure of the controller 108 disclosed above, other techniques for controlling the flash memory using the same concept are within the scope of the present invention. The present invention further relates to a method of controlling a flash memory, and is not limited to the configuration of the controller 108 shown in FIG.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102‧‧‧ data storage device

104‧‧‧Host

106‧‧‧Flash memory

10‧‧‧ Controller

110‧‧‧ arithmetic unit

112‧‧‧Read-only processor

114‧‧‧ Random access memory

Cache_CE1, Cache_CE2...Caceh_CEN‧‧‧ a set of cache space

CE1, CE2...CEN‧‧‧ wafer/access channel

PAGE11...PAGE1K, PAGE21...PAGE2K, PAGEN1...PAGENK‧‧‧Page

Claims (12)

A data storage device comprising: a flash memory having a plurality of blocks, each block having a plurality of pages, the blocks being divided by a plurality of access channels; and coupled to the flash memory a controller of the body, comprising: an arithmetic unit; a read-only memory, the program is executed by the computing unit as a firmware of the data storage device; and a random access memory is executed in the firmware The operating unit is configured to supply a set of cache space, and the set of cache space provides a temporary storage space for writing data for each of the plurality of access channels; wherein: the computing unit that executes the firmware is issued by a host The write data is distributed corresponding to the plurality of access channels; and when the logical address mapped by the write data is the same as the logical address mapped by the latest temporary data in the set of cache space, the operation unit is In the set of cache space, the latest temporary data is updated by the written data. The data storage device of claim 1, wherein when the logical address of the written data is the same as the logical address of the non-latest temporary data in the set of cache spaces, The operation unit writes the temporary storage data in the set of cache space and the same logical address as the write data into the flash memory. The data storage device of claim 2, wherein the computing unit maps the same logical bit in the cache space to the write data. After the temporary storage data of the address is written into the flash memory, the written data is stored in the set of cache space. The data storage device of claim 1, wherein: the computing unit that executes the firmware further stores the cached space after the end space of the set of cache space is filled. The flash memory is written according to the access channel to which it belongs. The data storage device of claim 1, wherein: when the logical address has a corresponding data collation space at the latest use of the cache space, the computing unit that executes the firmware reuses The latest use is for the logical address of the data. The data storage device of claim 1, wherein the computing unit is configured to distribute the written data corresponding to the plurality of access channels, and corresponding to a set of data temporarily stored in the cache space. . A flash memory control method includes: dividing a plurality of blocks of a flash memory by a plurality of access channels, each block having a plurality of pages; planning at least one in a random access memory a set of cache space, the set of cache space for each of the plurality of access channels provides a temporary storage space for writing data; the write data released by a host is distributed corresponding to the plurality of access channels; and when the write When the logical address of the data mapping is the same as the logical address of the latest temporary data in the set of cache space, the latest temporary data is updated by the written data in the set of cache space. The flash memory control method as described in claim 7 further includes: a logical bit mapped to the non-latest temporary data in the set of cache spaces when the logical address of the write data is mapped When the address is the same, the temporary data in the set of cache space and the same logical address as the write data is written into the flash memory. The flash memory control method of claim 8, further comprising: writing, to the flash memory, the temporary data in the cache space that is the same logical address as the write data; The write data is stored in the set of cache space. The method for controlling the flash memory according to the seventh aspect of the patent application further includes: after the space at the end of the set of the cache space is filled, the content temporarily stored in the cache space is stored according to the access The channel is written to the flash memory. The flash memory control method of claim 7, further comprising: reusing the latest use location when the logical address has a correspondingly configured data sorting space at the latest use of the set of cache space Make data for this logical address. The flash memory control method of claim 7, wherein the written data is distributed corresponding to the plurality of access channels, and is integrated with a set of data temporarily stored in the cache space.