TW201435372A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device in which the occurrence of timing mismatch in a laminated semiconductor device is suppressed without screening the operation speed of semiconductor chips before lamination. This semiconductor device comprises a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes: a first internal circuit and a first measurement circuit that generates a first signal indicating the operation speed of the first internal circuit. The second semiconductor chip is laminated on the first semiconductor chip, and includes: a second internal circuit and a second measurement circuit that generates a second signal indicating the operation speed of the second internal circuit. The semiconductor device also comprises: a comparison circuit that is formed on the first semiconductor chip, compares the first signal and the second signal, and generates a comparison result signal and an operation speed adjustment circuit that is formed on either the first or second semiconductor chip and adjusts the first or second operation speed on the basis of the comparison result signal.

Description

Semiconductor device (about the relevant application record)

The present invention claims priority based on Japanese Patent Application No. 2012-274877 (filed on Dec. 17, 2012), the entire disclosure of which is hereby incorporated by reference.

The present invention relates to a semiconductor device. In particular, there is an adjustment of the operation timing between wafers in a stacked semiconductor device in which a plurality of semiconductor wafers are stacked.

In recent years, the miniaturization and high functionality of electronic devices such as mobile phones and smart phones have become remarkable. Therefore, in the semiconductor devices used in such electronic devices, the development of a technology in which a plurality of semiconductor wafers are stacked and mounted in one package has progressed.

Here, in Patent Document 1, a laminated semiconductor device including a plurality of core wafers and an interface wafer for controlling the same is disclosed.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Laid-Open Patent Publication No. 2011-145257

In addition, the disclosure of the above prior art documents is repeatedly referred to in the present specification. The following analysis is performed by the inventors.

As disclosed in Patent Document 1, in a laminate semiconductor device including an interface wafer and a plurality of core wafers, it is necessary to operate the semiconductor devices in such a manner that the laminated semiconductor devices can operate normally. The operating speed of each circuit included in the wafer is designed.

However, in each circuit of the semiconductor wafer after the manufacture, there is a case where the operation speed deviates from the predetermined value at the time of design due to the influence of the manufacturing variation. When the semiconductor wafers whose operating speeds of the mounted circuits are deviated from the design values are mutually stratified, there is a problem that synchronization of the operation timings between the wafers cannot be obtained (sequence defective), and the layers are caused. The integrated semiconductor device cannot operate normally.

Patent Document 1 discloses the measurement of the difference in time constant between a plurality of through electrodes. However, in Patent Document 1, there is no mention of the operation speed of each circuit mounted in each semiconductor wafer.

Therefore, the inventors of the present invention reviewed a semiconductor device capable of solving the above problems. More specifically, a circuit for measuring the operation speed is placed at each of a plurality of semiconductor wafers, and the operating speed of each semiconductor wafer is measured at the wafer stage before the lamination. Thereafter, a semiconductor wafer in which the operation speed is fast or a semiconductor wafer having a slow operation speed is laminated with each other to form a stacked semiconductor device. However, in such a method of selecting the operating speed of the semiconductor wafer before the lamination, there is a problem that the cost of the semiconductor device increases due to an increase in the number of test projects.

According to a first aspect of the invention, there is provided a semiconductor device comprising: a first semiconductor chip including a first internal circuit; and a first signal generating an operation speed representative of the first internal circuit The first measurement circuit; and the second semiconductor wafer are laminated with the first semiconductor wafer, and include a second internal circuit and a second measurement circuit that generates a second signal representing the second operation speed; and a comparison circuit is formed on the first semiconductor wafer, and compares the first signal with the second signal to generate a comparison result signal; and an operation speed adjustment circuit is formed in the first or second One of the semiconductor wafers is adjusted for the first or second operating speed based on the comparison result signal.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor wafer; a first oscillating circuit that generates a first oscillating signal, and a first counting circuit that changes a first count value in response to the first oscillating signal; and a second semiconductor wafer that includes an internal power generating circuit that generates an internal power supply voltage, And a second oscillating circuit that operates by the internal power supply voltage and generates a second oscillating signal, and a second counting circuit that changes the second count value in response to the second oscillating signal, wherein the first semiconductor wafer is further And a comparison circuit for comparing the first count value and the second count value to generate a comparison result signal, wherein the internal power generation circuit adjusts the internal power supply voltage according to the comparison result signal.

According to the respective viewpoints of the present invention, it is possible to provide a semiconductor device capable of suppressing occurrence of timing defects in a stacked semiconductor device without performing screening by the operating speed of the semiconductor wafer before lamination.

1‧‧‧Semiconductor device

10‧‧‧Interface Wafer

11‧‧‧IF control circuit

12‧‧‧ Data input and output control circuit

13, 25‧‧‧ROSC circuit

14‧‧‧ROSC comparison circuit

20, 20-1~20-4‧‧‧ core chip

21‧‧‧ core control circuit

22‧‧‧Reading and writing control circuit

23‧‧‧SID selection circuit

24‧‧‧ switch

26‧‧‧ Memory Cell Array

27‧‧‧Power circuit

101‧‧‧Circular oscillator

102, 401‧‧‧ counter

201‧‧‧ROSC register

202‧‧‧ROSC comparator

301~305‧‧‧Adder

402‧‧‧Latch

403‧‧‧Decoder

404‧‧‧reference voltage generation circuit

405‧‧‧Internal power generation circuit

501‧‧‧Operational Amplifier

AND01~AND06‧‧‧Logical product circuit

FF01~FF05‧‧‧Factor

INV01~INV06, INV101~INV164‧‧‧Inverter circuit

NAND01~NAND06‧‧‧negative logic product circuit

NM01‧‧‧N-channel MOS transistor

OR01, OR02‧‧‧ logic and circuit

R01~R64‧‧‧resistance

TG01~TG64‧‧‧Transmission gate

XOR01, XOR02‧‧‧Exclusive logic and circuits

Fig. 1 is a view showing an example of the internal configuration of the semiconductor device 1 of the first embodiment.

FIG. 2 is a diagram showing an example of the internal configuration of the ROSC circuit 13.

FIG. 3 is an example of a time chart showing an example of the operation of the ring oscillator 101.

FIG. 4 is a diagram showing an example of the circuit configuration of the ring oscillator 101.

FIG. 5 is a diagram showing an example of the internal configuration of the ROSC comparison circuit 14.

FIG. 6 is a diagram showing an example of the circuit configuration of the ROSC register 201.

FIG. 7 is a diagram showing an example of the circuit configuration of the ROSC comparator 202.

Fig. 8 is a view showing an example of the circuit configuration of the adder shown in Fig. 7.

FIG. 9 is a diagram showing an example of the internal configuration of the power supply circuit 27.

FIG. 10 is a diagram showing an example of the circuit configuration of the reference voltage generating circuit 404.

FIG. 11 is a diagram showing an example of the circuit configuration of the internal power source generating circuit 405.

FIG. 12 is a diagram showing an example of the operation of the semiconductor device 1.

FIG. 13 is a diagram showing an example of a time chart when the ROSC circuit 13 included in the interface wafer 10 is operated and the count value of the ring oscillator 101 is held in the ROSC register 201.

FIG. 14 is a view showing an example of a time chart when the ROSC circuit 25 and the ROSC comparison circuit 14 included in the core wafer 20 are operated.

FIG. 15 is a view showing an example of a time chart when the power supply circuit 27 included in the core wafer 20 is operated.

First, the outline of one embodiment of the present embodiment will be described using FIG. In addition, the symbols of the drawing elements attached to the outlines are attached to each element as an example to help understanding, and the summary is not intended to be any limitation.

As shown in FIG. 1, a semiconductor device generally includes a first semiconductor wafer (for example, an interface wafer 10) and a second semiconductor wafer (for example, a core wafer 20). The first semiconductor wafer includes a first internal circuit and a first measurement circuit (for example, the ROSC circuit 13) that generates a first signal representing the operating speed of the first internal circuit. The second semiconductor wafer is laminated with the first semiconductor wafer, and includes a second internal circuit and a second measurement circuit (for example, the ROSC circuit 25) that generates a second signal representing the operating speed of the second internal circuit. Further, the semiconductor device includes a comparison circuit (for example, the ROSC comparison circuit 14) formed on the first semiconductor wafer and comparing the first signal and the second signal to generate a comparison result signal, and is formed in the first or An operation speed adjustment circuit (for example, the power supply circuit 27) that adjusts the first or second operation speed based on the comparison result signal in one of the second semiconductor wafers.

The semiconductor device shown in FIG. 1 has a structure in which a first semiconductor wafer and a second semiconductor wafer are laminated. Therefore, in the half In the conductor device, it is necessary to adjust the operation timing of the internal circuit of the first semiconductor wafer and the internal circuit of the second semiconductor wafer. However, in this case, the operating speed of the first internal circuit representing the first semiconductor wafer is required. The signal is compared with a signal representing the operating speed of the second internal circuit of the second semiconductor wafer, and the operating speed of the first or second internal circuit is adjusted in a direction to suppress timing failure between the semiconductor wafers. Here, the adjustment of the operating speed of the first or second internal circuit can be performed after the semiconductor wafer is laminated. As a result, it is possible to suppress the occurrence of the timing failure in the laminated semiconductor device without performing the selection by the operation speed of the semiconductor wafer before the lamination.

[First Embodiment]

The first embodiment will be described in more detail with reference to the drawings.

Fig. 1 is a view showing an example of the internal configuration of the semiconductor device 1 of the present embodiment. The semiconductor device 1 includes an interface wafer 10 for realizing an interface with an external semiconductor device (for example, a memory controller or the like), and core chips 20-1 to 20-4 including memory cells. The semiconductor device 1 is composed of an interface wafer 10 having one interface and four core chips 20-1 to 20-4 laminated. Further, in the following description, when it is not necessary to distinguish the core chips 20-1 to 20-4 in particular, it is referred to as "core wafer 20".

The interface wafer 10 is electrically connected to each core wafer via a through electrode (TSV; Trough-substrate Via) that penetrates the substrate of the core wafers 20-1 to 20-4. Interface wafer 10, from the outside half The conductor device receives the clock signal CK, the command signal CMD, and the address signal ADD. Further, the data written in the memory cell included in the core wafer 20 or the data read from the memory cell is transmitted and received as a data signal DATA between the semiconductor device and the external semiconductor device.

The interface wafer 10 includes an IF (Interface) control circuit 11, a data input/output control circuit 12, a ROCS (Ring Oscillator) circuit 13, and a ROSC comparison circuit 14. Here, at least one of the IF control circuit 11, the data input/output control circuit 12, the ROSC circuit 13, and the ROSC comparison circuit 14 constitutes the first internal circuit of the present invention.

The IF control circuit 11 outputs a control signal CTL to the core wafer 20 to be accessed in accordance with the address signal ADD supplied from the outside during normal operation. Further, the IF control circuit 11 adjusts the operating speed of the core wafer 20 when the power is turned on, for example, when the power is turned on in the semiconductor device 1 during the speed adjustment operation. More specifically, the IF control circuit 11 controls various signals of the START signal, the END signal, the RESET signal, the SID signal, the TEST_END signal, and the P_IN signal in order to adjust the operating speed of the core chip 20. The details of the signals about these are described in order.

The data input/output control circuit 12 controls data transfer between the read/write control circuit 22 included in the core wafer 20 and an external semiconductor device. Specifically, the data input/output control circuit 12 is from the core wafer 20 during the read operation of the semiconductor device 1. The read/write control circuit 22 receives the internal data signal i_DATA and supplies it to the external semiconductor device as the data signal DATA. Further, the data input/output control circuit 12 receives the data signal DATA from the external semiconductor device when the semiconductor device 1 is in the address operation, and supplies it to the read/write control circuit 22 of the core wafer 20 as the internal data signal i_DATA. .

The ROSC circuit 13 (first measurement circuit) is an oscillation circuit including an annular oscillator as an oscillation circuit. The ROSC circuit 13 receives the START signal, the END signal, the RESET signal, and the SID signal SID_IF output by the IF control circuit 11. The ROSC circuit 13 outputs an RO_IF signal (first signal) representing the number of times the output of the ring oscillator included in the inside is double-converted. Further, since the RO_IF signal in the present embodiment is a 5-bit wide signal, it is marked as RO_IF<4:0> as needed. Further, the ROSC circuit 25 (second measurement circuit) of the core wafer 20 is also provided with substantially the same configuration as the ROSC circuit 13. Specifically, the ROSC circuit 25 of the core chip 20 receives the SID signal SID_CORE instead of the SID signal SID_IF, and outputs the RO_CORE signal (the second signal) instead of the RO_IF signal. In addition, the RO_CORE signal is a signal of the same type as the RO_IF signal, and is a 5-bit wide signal. The RO_CORE signal is a signal representing the number of times that the ring oscillator included in the ROSC circuit 25 of the core chip 20 is double-state interconverted for a predetermined period of time. For the RO_CORE signal, the same is marked as RO_CORE<4:0> as needed. Below, reference Details of the configuration and operation of the ROSC circuit 13 will be described with reference to Figs. This detail is also substantially in accordance with the ROSC circuit 25.

FIG. 2 is a diagram showing an example of the internal configuration of the ROSC circuit 13. The ROSC circuit 13 includes a ring oscillator 101 (first oscillating circuit, second oscillating circuit) and a counter 102.

The ring oscillator 101 receives the START signal, the END signal, and the SID signal SID_IF output by the IF control circuit 11. The output of the ring oscillator 101 is used as the RO signal (the first oscillating signal and the second oscillating signal).

FIG. 3 is an example of a time chart showing an example of the operation of the ring oscillator 101. The ring oscillator 101 starts to oscillate in response to the START signal (time T01). The ring oscillator 101 ends the oscillation in response to the END signal (time T02).

In this case, the time from the rise of the START signal until the END signal rises (the period of the oscillation; the time T01~T02) is divided by the RO signal during the oscillating period (the first period, the second period). The value obtained after the number of times (the first number of times and the second number of times) corresponds to the period of the RO signal. Therefore, if the number of double-state interconversions of the RO signal during the oscillating period is larger, the period of the RO signal is shorter (the frequency of the RO signal is higher), and the operating speed of the ring oscillator 101 is fast. That is to say, it can be said that the internal circuit is moving at a fast speed. Wafer. In other words, by matching the frequency of the RO signal output from the ring oscillator 101 of the ROSC circuit 13 with the frequency of the RO signal output from the ring oscillator 101 of the ROSC circuit 25, it can be as will be described later. The operating speed of the internal circuit of the core wafer 20 is adjusted in such a manner as to suppress the timing failure. In the following description of the present embodiment, the RO signal output from the ring oscillator 101 of the ROSC circuit 13 is simply referred to as the RO signal of the interface wafer 10. Similarly, the RO signal output from the ring oscillator 101 of the ROSC circuit 25 is simply described as the RO signal of the core chip 20.

The ring oscillator 101 can be realized, for example, by the circuit configuration shown in FIG. More specifically, the ring oscillator 101 includes the logical product circuits AND01 and AND02, and the negative logical product circuits NAND01 to NAND06 and the inverting circuit INV01. The signal output by the inverting circuit INV01 is an RO signal.

The counter 102 shown in FIG. 2 is a counting circuit for counting the number of double-state interconversions of the RO signal output from the ring oscillator 101. The result counted by the counter 102 is output as a 5-bit wide RO_IF signal. For example, if the number of two-state interconversions of the RO signal is six times as shown in FIG. 3, it becomes RO_IF<4:0>=(L, L, H, H, L). The frequency of the RO signal can be determined based on the RO_IF signal. Moreover, the number of double-state interconversions of the RO signals counted by the counter 102 is activated by the RESET signal outputted by the IF control circuit 11, and is like RO_IF<4:0>=(L, L, L, L, L) are generally initialized.

The ROSC comparison circuit 14 shown in FIG. 1 compares the RO_IF signal outputted by the ROSC circuit 13 with the RO_CORE signal outputted by the ROSC circuit 25 included in the core chip 20, and outputs a P_OUT signal in response to the comparison result. .

The ROSC comparison circuit 14 is a binary state of the ring oscillator included in the core wafer 20 by the number of double-state interconversions of the ring oscillator included in the interface wafer 10 in a predetermined period. The number of mutual changes is compared to produce a circuit for the P_OUT signal. In addition, since the number of double-state interconversions of the ring oscillator included in the interface wafer 10 represents the operating speed of the internal circuit of the interface wafer 10, the two-state mutual impedance of the ring oscillator included in the core wafer 20 The number of times of change represents the operating speed of the internal circuit of the core wafer 20. Therefore, the ROSC comparison circuit 14 can be regarded as a comparison of the operating speeds of the internal circuits of the two chips.

Fig. 5 is a view showing an example of the internal configuration of the ROSC comparison circuit 14. The ROSC comparison circuit 14 receives the SID_IF signal and the TEST_END signal and the P_IN signal in addition to the RO_IF signal and the RO_CORE signal.

As described above, in order to adjust the operation speed of the internal circuit of the core wafer 20, it is necessary to select and operate the ROSC circuit included in the interface wafer 10 and the core wafers 20-1 to 20-4. The signal used to select the ROSC circuit to operate is the SID signal. Specifically, the signal selected by the ROSC circuit 13 included in the interface chip 10 is the SID signal SID_IF, and is selected. The signal of the ROSC circuit 25 included in the core chip 20 is the SID signal SID_CORE. Further, the IF control circuit 11 determines the selected core wafer 20 based on the address signal ADD supplied from the external semiconductor device.

When the IF control circuit 11 ends the operation of the ROSC circuit 13 (stopping the oscillation of the ring oscillator 101), the signal activated from the L level to the H level is the TEST_END signal. Moreover, the click pulse signal generated when the IF control circuit 11 activates the END signal from the L level to the H level is a P_IN signal.

The ROSC comparison circuit 14 outputs a P_OUT signal. The P_OUT signal is a comparison result of the RO_CORE signal outputted by the ROSC circuit 25 included in the core chip 20 selected by the SID_CORE signal and the RO_IF signal outputted by the ROSC circuit 13 included in the interface chip 10. And the output signal. The P_OUT signal is output to the power supply circuit 27 via the switch 24 of the core chip 20. Moreover, as shown in FIG. 1, the data input/output control circuit 12 can also receive the P_OUT signal and output the P_OUT signal to the outside. By outputting the P_OUT signal to the outside, it is possible to observe the P_OUT signal during the test. In addition, the details of the P_OUT signal will be described later.

The ROSC comparison circuit 14 is provided with a ROSC register 201 and a ROSC comparator 202 (refer to FIG. 5).

The ROSC register 201 is a circuit for holding the RO_IF signal output from the ROSC circuit 13 of the interface chip 10. ROSC register The value held by 201 is a value that becomes a reference when the comparison operation at the ROSC comparator 202 is performed. The value output by the ROSC register 201 is set to the RO_REG signal. This signal, because it is a 5-digit wide signal, is marked as RO_REG<4:0> as needed.

FIG. 6 is a diagram showing an example of the circuit configuration of the ROSC register 201. For example, the ROSC register 201 includes a logical product circuit AND03 and a flip-flop FF01 to FF05.

The ROSC register 201 is generally controlled as follows.

The IF control circuit 11 activates the SID_IF signal from the L level to the H level. Thereafter, the IF control circuit 11 activates the START signal from the L level to the H level and oscillates the ring oscillator 101. The IF control circuit 11 activates the END signal from the L level to the H level after oscillating the ring oscillator 101 for a predetermined period of time. In this way, the RO_IF signal representing the number of times the ring oscillator 101 is subjected to the two-state interconversion is output from the ROSC circuit 13. In this state, the IF control circuit 11 activates the TEST_END signal from the L level to the H level.

At this time, at the logical product circuit AND03, since the SID_IF signal and the TEST_END signal of the H level are supplied, the RO_IF signal is introduced to the flip-flops FF01 to FF05 of the ROSC register 201. In the stage where the RO_IF signal is held in the ROSC register 201, the SID_IF signal and the TEST_END signal are taken together. The H level is not activated as the L level.

The ROSC comparator 202 shown in FIG. 5 is a circuit for comparing the number of times of double-state interconversion between the ring oscillators included in each of the interface wafer 10 and the core wafer 20. The ROSC comparator 202 compares the RO_CORE signal supplied from the core chip 20 selected by the IF control circuit 11 with the RO_REG signal supplied from the ROSC register 201, and displays the RO_REG signal when the RO_CORE signal is displayed. In the case of a larger value, a P_OUT signal is generated. That is, the ROSC comparator 202 generates a P_OUT signal when the operating speed of the core wafer 20 is faster than the operating speed of the interface wafer 10.

FIG. 7 is a diagram showing an example of the circuit configuration of the ROSC comparator 202. The ROSC comparator 202 includes an adder 301 to 305, and inverter circuits INV02 to INV06, a logical sum circuit OR01, and a logical product circuit AND04.

The adders 301 to 305 are circuits for adding the RO_CORE signal supplied from the selected core chip 20 and the RO_REG signal supplied from the ROSC register 201 in units of bits. However, since the RO_REG signal is inverted by the inverter circuits INV02 to INV06, the adders 301 to 305 function as a circuit for subtracting the RO_REG signal in units of bits from the RO_CORE signal.

The OUT0 signals output by each of the adders 301 to 305 are obtained by the subtraction calculation of each of the adders 301 to 305. The absolute value of the result. Here, the OUT0 signals output by the adders 301 to 305 are respectively labeled as absolute values S<0>...<S4>. Or, the signal is co-ordinated to the absolute value S<4:0> as needed.

The adder 305 outputs a C0 signal representing positive and negative in the result of the above-mentioned subtraction calculation. In addition, when the C0 signal is the H level, the result of the subtraction calculation is positive, and when it is the L level, the result of the subtraction calculation is negative. For example, when RO_CORE<4:0>=5 (L, L, H, L, H), RO_REG<4:0>=7 (L, L, H, H, H), due to the subtraction calculation The result is -2, so S<4:0>=(L, L, L, H, L) and C0=L.

The logic AND circuit OR01 is the logic and calculation of the absolute value S<4:0>. The signal output by the logic AND circuit OR01 is set to C1. The logic AND circuit OR01 detects whether there is a difference between the RO_CORE signal and the RO_REG signal (whether the two are consistent) by performing the logic and calculation of the absolute value S<4:0>.

The logical product circuit AND04 is a logical product calculation of the C0 signal, the C1 signal, and the P_IN signal. The signal output by the logic product circuit AND04 is the P_OUT signal.

Here, the relationship between the frequency of the RO signal of the interface chip 10 and the frequency of the RO signal of the core chip 20 can be classified into the following three types.

First, the frequency of the RO signal of the core chip 20 is The frequency of the RO signal of the interface chip 10 is higher. In this case, since the C0 signal and the C1 signal system both become the H level, the P_OUT signal is consistent with the P_IN signal.

Second, the frequency of the RO signal of the core chip 20 and the frequency of the RO signal of the interface chip 10 are equal. In this case, since the absolute value S<4:0> received by the logic AND circuit OR01 is 0, the C1 signal becomes the L level. Therefore, regardless of the P_IN signal, the P_OUT signal is fixed to the L level.

Thirdly, the frequency of the RO signal of the core wafer 20 is lower than the frequency of the RO signal of the interface wafer 10. In this case, since the result of the subtraction calculation in the adders 301 to 305 is negative, the C0 signal becomes the L level. Therefore, regardless of the P_IN signal, the P_OUT signal is fixed to the L level.

According to the above, it can be seen that when the frequency of the RO signal of the core chip 20 is higher than the frequency of the RO signal of the interface chip 10 (the first case), the click pulse signal is output as the P_OUT signal. On the other hand, in the second and third cases, the P_OUT signal is fixed to the L level.

Further, for example, the adders 301 to 305 can be realized by the circuit configuration shown in FIG. The adder 301 shown in Fig. 8 is constituted by the exclusive logical sum circuits XOR01 and XOR02, and the logical product circuits AND05 and AND06, and the logical sum circuit OR02. The adders 301 to 305 are realized by the same circuit configuration, respectively, and therefore the description about the adders 302 to 305 is omitted. slightly. However, this does not mean that the configuration of the adders 301 to 305 is limited to the configuration shown in FIG.

Next, the operation of the core wafer 20 will be described.

The core wafer 20 shown in FIG. 1 includes a core control circuit 21, and a read/write control circuit 22, and an SID selection circuit 23, and a switch 24, and a ROSC circuit 25, and a memory cell array 26, and a power supply circuit. 27, and constitute it. Here, at least one of the core control circuit 21, the read/write control circuit 22, the SID selection circuit 23, the switch 24, and the ROSC circuit 25 constitutes the second internal circuit of the present invention.

The core control circuit 21 supplies the control signal CCTL to the read/write control circuit 22 of the core wafer 20 on which it is mounted in response to the control signal CTL supplied from the IF control circuit 11.

The read/write control circuit 22 controls the read and write operations of the core chip 20 in response to the control signal CCTL.

The SID selection circuit 23 activates the SID_CORE signal when the SID signal output from the IF control circuit 11 is a selection of the core chip mounted on itself. For example, when the IF control circuit 11 selects the core chip 20-1 by the SID signal, the SID selection circuit 23 included in the core chip 20-1 activates the SID_CORE signal. However, the SID selection circuit 23 included in the other core chips 20-2 to 20-4 does not activate the SID_CORE signal.

The switch 24, when the SID_CORE signal is activated, outputs the output of the ROSC comparison circuit 14 of the interface wafer 10. The P_OUT signal is supplied to the power supply circuit 27.

The ROSC circuit 25 of the core wafer 20 has substantially the same configuration as the ROSC circuit 13 included in the interface wafer 10 as described above.

The memory cell array 26 is provided with a plurality of memory cells, each of which holds data.

The power supply circuit 27 is a circuit that generates an internal power supply voltage VPERI. Fig. 9 is a view showing an example of the internal configuration of the power supply circuit 27.

The power supply circuit 27 includes a counter 401, a latch 402, a decoder 403, a reference voltage generating circuit 404, and an internal power generating circuit 405.

The counter 401 is a circuit for counting the click pulse signals output by the ROSC comparison circuit 14 as the P_OUT signal. In the present embodiment, the counter 401 is a counter using a 6-bit counter.

The latch 402 latches the count value output by the counter 401.

The decoder 403 generates a voltage selection signal VSEL based on the signal output by the latch 402. More specifically, the decoder 403 is a circuit that converts the count value of the 6-bit held by the latch 402 into a 64-bit voltage selection signal VSEL. The voltage selection signal VSEL is labeled as VSEL<63:0> as needed.

The reference voltage generating circuit 404 is for generating the supply to the inside A circuit of the reference voltage VPERI_REF at the power generation circuit 405. The reference voltage generating circuit 404 generates a reference voltage VPERI_REF in response to the voltage selection signal VSEL output from the decoder 403.

FIG. 10 is a diagram showing an example of the circuit configuration of the reference voltage generating circuit 404. The reference voltage generating circuit 404 includes a resistor ladder type circuit formed by connecting a plurality of resistors R01 to R64 in series, and a transmission gate selected for connecting the resistors of the resistor ladder type circuit to each other. The poles TG01 to TG64 and the inverter circuits INV101 to INV164.

The reference voltage generating circuit 404 turns on one of the transmission gates TG01 to TG64 in response to the voltage selection signal VSEL, thereby thereby connecting the nodes of the resistor ladder circuit (node N01 shown in FIG. 10). The voltage at ~N64) is output as the reference voltage VPERI_REF. The resistor ladder circuit is connected to the power supply VREF_MAX and the power supply VREF_MIN. For example, if the power supply VREF_MAX is set to 1.32V and the power supply VREF_MIN is set to 0.68V, the 64-stage reference voltage VPERI_REF can be generated on a scale of 0.01V. That is, by passing one resistor included in the resistor ladder type circuit, the voltage system at which the resistors are connected is reduced by 0.01 V each. Further, the reason why the power supply VREF_MAX is set to 1.32 V and the power supply VREF_MIN is set to 0.68 V is that if the internal power supply voltage of the interface wafer 10 is 1.00 V, the internal power supply voltage of the interface wafer 10 is centered at 0.01 V. The scale is changed for the reference voltage VPERI_REF.

Here, in the initial state of the core wafer 20, the counter 401 included in the power supply circuit 27 is also in an initial state. In this case, the voltage selection signal VSEL<0> of the H level is output from the decoder 403, and the other voltage selection signals VSEL<63:1> are set to the L level. As a result, in the initial state, the transfer gate TG01 is turned on, and the voltage of the reference voltage VERF_REF is equal to the voltage of the power supply VREF_MAX (for example, 1.32 V). In this state, when the frequency of the ring oscillator of the core wafer 20 is higher than the frequency of the ring oscillator of the interface wafer 10, the counter 401 increments the count value. In this way, since the voltage selection signal VSEL<1> is at the H level, and the other voltage selection signals VSEL are at the L level, the voltage of the reference voltage VPERI_REF is reduced in one stage (for example, from 1.32V). And reduce 0.01V and become 1.31V).

The internal power generation circuit 405 is a circuit that generates an internal power supply voltage VPERI supplied to circuits (for example, the core control circuit 21, the read/write control circuit 22, and the ROSC circuit 25, etc.) included in the core wafer 20. Fig. 11 is a view showing an example of the circuit configuration of the internal power source generating circuit 405. The internal power generation circuit 405 includes an operational amplifier 501 and an N-channel MOS transistor NM01. The operational amplifier 501 controls the gate voltage of the N-channel MOS transistor NM01 such that the reference voltage VPERI_REF and the internal power supply voltage VPERI coincide with each other.

Next, the operation of the semiconductor device 1 will be described.

Figure 12 is a view of the operation of the semiconductor device 1 An example of a picture for display. With reference to FIG. 12, an example of an operation when the IF control circuit 11 adjusts the operating speed of the core wafer 20 when the power is turned on during the POWER ON in the semiconductor device 1 will be described.

In step S01, the IF control circuit 11 selects and operates the ROSC circuit 13 of the interface wafer 10. More specifically, the IF control circuit 11 activates the SID signal SID_IF to the H level. Further, the IF control circuit 11 activates the START signal from the L level to the H level. In response to the transition of the START signal to the H level, the ring oscillator 101 of the ROSC circuit 13 begins to oscillate.

In step S02, the IF control circuit 11 causes the ROSC register 201 to hold the RO_IF signal. More specifically, the IF control circuit 11 activates the END signal from the L level to the H level, and then activates the TEST_END signal from the L level to the H level. As a result, the ROSC register 201 holds the RO_IF signal.

In step S03, the IF control circuit 11 selects and operates the ROSC circuit 25 included in the core wafer 20. More specifically, the IF control circuit 11 outputs an SID signal for selecting one of the core chips 20-1 to 20-4. In this way, the SID selection circuit 23 of the selected core chip 20 activates the SID signal SID_CORE to the H level. Further, the IF control circuit 11 activates the START signal from the L level to the H level. In response to the START signal moving to the H level, the ring oscillator 101 began to oscillate. The counter 102 of the ROSC circuit 25 included in the core chip 20 is a two-state interchanging of the RO signal outputted by the ring oscillator 101 of the ROSC circuit 25. Count the number.

In step S04, the ROSC comparison circuit 14 performs a comparison of the RO_IF signal and the RO_CORE signal. More specifically, the ROSC comparator 202 performs a comparison of the RO_REG signal held by the ROSC register 201 and the RO_CORE signal supplied from the core chip 20 (comparison of count values). At this time, if the RO_CORE signal is larger than the RO_REG signal (the count value is larger), the click pulse signal is output as the P_OUT signal. On the other hand, when the RO_CORE signal is consistent with the RO_REG signal, or when the RO_REG signal is a large value, the click pulse signal is not output as the P_OUT signal.

When comparing the two signals, the RO_CORE signal is a larger value than the RO_REG signal, and when the pulse signal of the click is output as the P_OUT signal (step S05, Yes divergence), the reference voltage is generated. The circuit 404 lowers the voltage of the reference voltage VPERI_REF in one step (step S06). More specifically, when the click pulse signal is output as the P_OUT signal, the count value of the counter 401 is incremented, and the value of the voltage selection signal VSEL output from the decoder 403 rises. As a result, the reference voltage VPERI_REF is lowered by 0.01V.

On the other hand, when the click pulse signal is not output as the P_OUT signal (step S05, No. divergence), the reference voltage generating circuit 404 does not change the reference voltage VPERI_REF (step S06 is not performed).

In step S07, the IF control circuit 11 determines whether or not the comparison in step S05 has been performed for a predetermined number of times. More specifically, the IF control circuit 11 determines whether or not the comparison of the maximum count (for example, 64 times) of the counter 401 included in the power supply circuit 27 of the core wafer 20 is performed.

If the comparison is not performed for a predetermined number of times (step S07, No divergence), the processing after step S03 is repeatedly performed. If the comparison of the predetermined number of times is performed (step S07, Yes divergence), the processing of step S08 is performed. Further, the IF control circuit 11 causes the SID signal SID_CORE to be activated from the H level instead of the L level when the comparison of the step S05 is performed for a predetermined number of times.

In step S08, the IF control circuit 11 determines whether or not the adjustment of the operation speed is performed for all of the core chips 20. If the adjustment of the operation speed is completed for all the core chips 20 (step S08, Yes divergence), the processing shown in Fig. 12 is ended.

The decrease in the reference voltage VPERI_REF is equivalent to the decrease in the internal power supply voltage VPERI of the core chip 20. If the internal power supply voltage VPERI of the core wafer 20 is lowered, the operating speed of the internal circuit of the core wafer 20 is also lowered. As a result, the RO_CORE signal outputted by the ROSC circuit 25 included in the core wafer 20 is approached toward the RO_IF signal outputted by the ROSC circuit 13 included in the interface wafer 10.

In this way, if the internal power supply voltage VPERI of the core wafer 20 is gradually lowered, the interface wafer 10 and the core crystal are gradually removed. The count values of the frequencies representing the RO signals at the slice 20 are compared, and at a certain timing, the frequencies of the RO signals at the interface wafer 10 and the core wafer 20 are identical. Alternatively, the frequency of the RO signal at the interface wafer 10 and the core wafer 20 is reversed. In this way, the pulse signal of the click is not output as the P_OUT signal, and is fixed at the L level, and the increment at the counter 401 is stopped. As a result, the value of the voltage selection signal VSEL outputted from the decoder 403 is also fixed, and the internal power supply voltage VPERI at the core wafer 20 is also fixed. That is, the reference voltage generating circuit 404 adjusts the reference voltage VPERI_REF until the magnitude of the number of double-state interconversions of the ring oscillator included in the interface wafer 10 and the core wafer 20 coincides with each other or Reversed so far.

The timing adjustment of the interface wafer 10 and the core wafer 20 is terminated by performing a series of operations as shown in FIG. By lowering the internal power supply voltage VPERI of the core wafer 20, the operating speeds of the various circuits of the internal circuit of the core wafer 20 are lowered, and the operating speeds of the interface wafer 10 and the core wafer 20 are substantially identical. Also. The actions shown in the flowchart of Fig. 12 are merely examples, and do not necessarily limit the order of processing. For example, the process of operating the ROSC circuit 13 of the interface wafer 10 and maintaining the RO_IF signal (steps S01 and S02) and the process of operating the ROSC circuit 25 of the core wafer 20 (step S03) can be performed in parallel.

Next, the operation of the semiconductor device 1 will be described using a timing chart. Figure 13 is for inclusion in the interface wafer 10 One example of the timing chart when the ROSC circuit 13 operates and holds the count value of the ring oscillator 101 in the ROSC register 201 is shown.

At time T11, the IF control circuit 11 activates the SID_IF signal of the selected ROSC circuit 13 to the H level.

At time T12, the IF control circuit 11 activates the START signal from the L level to the H level.

At time T13, the IF control circuit 11 activates the END signal from the L level to the H level. Between time T12 and T13, the ring oscillator 101 is subjected to five-stage inter-state transition. Therefore, after time T13, the RO_IF signal output by the counter 102 becomes RO_IF<4:0>=5 (L, L, H, L, H). In addition, in FIG. 13, RO_IF<4> and RO_IF<3> are not illustrated because the system does not change from the L level.

At time T14, the IF control circuit 11 activates the TEST_END signal from the L level to the H level. By activating the TEST_END signal to the H level, the flip-flops FF01 to FF05 included in the ROSC register 201 import the RO_IF signal at time T14. Since the data held by the flip-flops FF01 to FF05 is the RO_REG signal, the RO_REG signal after the time T14 maintains the "5" of the number of double-state mutual transitions of the ring oscillator 101.

At time T15, the IF control circuit 11 deactivates the SID_IF signal, the START signal, the END signal, and the TEST_END signal to the L level.

FIG. 14 is a view showing an example of a timing chart when the ROSC circuit 25 and the ROSC comparison circuit 14 included in the core wafer 20 are operated. Further, before time T21, it is assumed that the ROSC register 201 holds the RO_IF signal. Further, the value held by the ROSC register 201 is set to "5".

At time T21, the IF control circuit 11 activates the SID signal for selecting the core chip 20 for operating the ROSC circuit 25 from the L level to the H level (encoding the SID_CORE signal).

At time T22, the IF control circuit 11 activates the START signal from the L level to the H level.

At time T23, the IF control circuit 11 activates the END signal from the L level to the H level. Between time T22 and T23, the ring oscillator 101 is subjected to seven-state inter-state transition. Therefore, at time T23, the RO_CORE signal output by the counter 102 becomes RO_CORE<4:0>=7 (L, L, H, H, H). Moreover, the comparison result of the ROSC comparator 202 at the time T23 is an absolute value S<4:0>=2 (L, L, L, H, L), C0 signal = H level, C1 signal = H Level.

At time T24, the IF control circuit 11 generates a P_IN signal which is a click pulse signal in response to activation of the END signal. At this time, the logical product circuit AND04 included in the ROSC comparator 202 calculates the logical product of the C0 signal, the C1 signal, and the P_IN signal. As a result, the click pulse signal occurs in the P_OUT signal.

At time T25, the IF control circuit 11 will SID_CORE signal, START signal and END signal are not activated. The IF control circuit 11 repeats the operation of the time T22 to T25 64 times, and then ends the adjustment of the operation speed at the selected core wafer 20 (the comparison operation using the ROSC comparison circuit 14 is completed).

Fig. 15 is a view showing an example of a time chart when the power supply circuit 27 included in the core wafer 20 is operated. At time T31, a click pulse signal is generated in the P_OUT signal. In this way, the counter 401 increments the count value. In response to the increase in counter 401, the voltage selection signal VSEL is also incremented. In response to the increase in the voltage selection signal VSEL, the node of the resistor ladder circuit that generates the reference voltage VPERI_REF supplied to the internal power supply generating circuit 405 is reduced in one stage. As a result, the voltage of the reference voltage VPERI_REF is also lowered.

In the example shown in Fig. 15, a 0.01V reduction is made each time a click pulse signal is generated in the P_OUT signal. The pulse signal clicked in the P_OUT signal, when the output values of the ring oscillator at the interface wafer 10 and the core wafer 20 coincide with each other or the ring oscillator at the interface wafer 10 and the core wafer 20 After the timing of the output values reversing each other, the system does not occur. Therefore, after the comparison operation at the ROSC comparison circuit 14 is repeated 64 times (after time T32), the output of the counter 401, the voltage selection signal VSEL, and the reference voltage VPERI_REF are not changed. That is, the core wafer 20 operates using the internal power supply voltage VPERI generated by the reference voltage VPERI_REF after time T32.

In the present embodiment, the power supply of the memory cell array 26 is set to Varray, and the internal power supply voltage VPERI supplied to the peripheral circuit of the semiconductor device 1 is changed to adjust the operating speed. The description is not intended to limit the invention to such a configuration.

In the present embodiment, the case where the operation speed of the core wafer 20 is adjusted when the power of the POWERON or the like of the semiconductor device 1 is turned on is described. However, the adjustment of the operation speed is not representative. Limited to this form. For example, in the power supply circuit 27, a memory means for mounting an anti-fuse or the like that holds the count value output from the latch 402 non-volatilely can be considered. In this case, the adjustment value of the operating speed of the core wafer 20 is obtained during the test (for example, the count value of the counter 401 after the time T32 in FIG. 15), and the obtained adjustment value is stored in the non-volatile state. Means of memory. As a result, it is not necessary to adjust the operation speed every time the actual use of the semiconductor device 1 is performed, and the operation speed of the core wafer 20 can be made by reading the value stored in the memory means. Adjustment.

Alternatively, in the present embodiment, the internal power supply voltage VPERI of the core wafer 20 is changed with respect to the number of double-state interconversions of the ring oscillator 101 included in the ROSC circuit 13 of the interface wafer 10. The way to illustrate it. However, the reference of the operating speed of the core wafer 20 may be based on the interface wafer 10, but may be set as a reference in each of the core wafers 20. In this case, in the interface wafer 10 and the core wafer 20, the matching is performed. The ROSC comparison circuit and the power supply circuit are placed, and the count value which becomes the reference is input to the ROSC register (refer to FIG. 5), and the two-state inter-variation times of the ring oscillators of the interface wafer 10 and the core wafer 20 are input. To the ROSC comparator 202. In this manner, the speed of operation can also be adjusted for each of the layers including the interface wafer 10.

Further, the value to be the reference may be a value that does not match the count value of the core wafer 20, not the value generated in the interface wafer 10. For example, it may be configured to coincide with the operating speed of the core wafer in which the speed of movement of each core wafer 20 is the fastest or slowest. In this case, the number of double-state interconversions of the ring oscillator in the fastest (or slowest) core wafer 20 is input to the ROSC of the ROSC comparison circuit included in each core wafer 20. In the memory.

Furthermore, in the present embodiment, the description has been made on the premise that the operating speed of the core wafer 20 is made faster than that of the interface wafer 10. However, this does not mean that the relationship between the operating speeds of the interface wafer 10 and the core wafer 20 is limited to the above relationship. Even when the operating speed of the core wafer 20 is slower than the operating speed of the interface wafer 10, the adjustment of the operating speed of the core wafer 20 (adjustment of the operation timing of the semiconductor device 1) can be performed. In this case, the configuration of the power supply circuit 27 of the core wafer 20 is changed, for example, so that the counter 401 can increase the reference voltage VPERO_REF every time the count value is incremented.

As described above, the semiconductor device 1 of the present embodiment, The speed of movement of the core wafer 20 can be adjusted. In the semiconductor device 1, the operating speed of the interface wafer 10 (the frequency of the ring oscillator) and the operating speed of the core chip 20 (the frequency of the ring oscillator) are repeatedly compared, and the internal power supply voltage of the core chip 20 is made. cut back. At this time, when the frequencies of the ring oscillators at the interface wafer 10 and the core wafer 20 are coincident with each other, or when the frequency of the ring oscillator at the interface wafer 10 becomes high, the system stops. The internal supply voltage at the core wafer 20 is reduced. In other words, the internal power supply voltage of the core wafer 20 is determined in such a manner that the frequency of the ring oscillator in the interface wafer 10 and the core wafer 20 is slightly uniform.

Further, as a parameter for adjusting the timing of the stacked semiconductor device, the internal power supply voltage of the core chip is used to adjust the timing of the entire wafer. Therefore, it is possible to suppress an increase in the area of the semiconductor device 1, and it is possible to suppress the influence on the entire wafer. In the semiconductor device 1, it is possible to adjust the operating speed of the core wafer 20 after the assembly process. Therefore, it is possible to reduce the cost and the number of projects by eliminating the need for timing confirmation work in the pre-engineering.

Further, in the above-described embodiment, the semiconductor device in which the interface wafer and the core wafer are laminated is shown. However, the semiconductor device to which the present invention is applicable is not limited thereto. For example, a semiconductor device in which a so-called system chip (SOC) chip or a memory chip including a memory controller or the like is stacked or a semiconductor device in which a plurality of logic chips are stacked with each other may be used. Applicable. Further, in the above embodiment, the use of the through electrode is The TSV is shown as a semiconductor wafer in which a plurality of wafers are connected, but the present invention is not limited thereto. For example, the present invention can also be applied to a semiconductor device in which a plurality of stacked wafers are electrically connected via wire bonding or interposer or the like.

In addition, the disclosures of the above-mentioned prior art documents and the like cited are referred to in the present specification. Modifications and adjustments of the embodiments and the embodiments may be made based on the basic technical idea of the invention in the scope of the disclosure. Further, various disclosure elements (including each element of each request item, each embodiment, each element of the embodiment, each element of each drawing, etc.) within the scope of the patent application scope of the present invention may be various. Combination of sex and even choice. In other words, the present invention includes various modifications and corrections that can be made by the practitioner based on all the disclosures and technical ideas including the scope of the patent application. In particular, the numerical ranges recited in the present specification are to be construed as any of the numerical values included in the range and even any minor ranges, even if they are not specifically described in the specification. .

1‧‧‧Semiconductor device

10‧‧‧Interface Wafer

11‧‧‧IF control circuit

12‧‧‧ Data input and output control circuit

13, 25‧‧‧ROSC circuit

14‧‧‧ROSC comparison circuit

20-1~20-4‧‧‧ core chip

21‧‧‧ core control circuit

22‧‧‧Reading and writing control circuit

23‧‧‧SID selection circuit

24‧‧‧ switch

26‧‧‧ Memory Cell Array

27‧‧‧Power circuit

Claims (9)

A semiconductor device comprising: a first internal circuit including a first internal circuit; and a first measurement circuit for generating a first signal representing an operation speed of the first internal circuit; and a second semiconductor wafer; And a second operation measuring circuit including a second internal circuit and a second signal generating an operating speed of the second internal circuit, and a comparison circuit formed on the first semiconductor wafer. The first semiconductor wafer is compared with the first signal and the second signal to generate a comparison result signal; and the operation speed adjustment circuit is formed on one of the first or second semiconductor wafers. Based on the comparison result signal, the first or second operation speed is adjusted. The semiconductor device according to claim 1, wherein the first measuring circuit includes a first oscillating circuit that generates a first oscillating signal, and the first signal represents that the first oscillating signal is at the first During the period, the first number of toggles is toggled. The second measurement circuit includes a second oscillation circuit that generates a second oscillation signal. The second signal represents that the second oscillation signal is The substantial length is the second number of double-state transitions in the second period equal to the first period. The semiconductor device according to claim 1 or 2, wherein the operation speed adjustment circuit is replaced by the second signal When the second number of times in the table is larger than the first number of times represented by the first signal, the direction is decreased toward the direction in which the operating speed of the second internal circuit is lowered, and the second signal is represented by the second signal. When the second number of times is smaller than the first number of times represented by the first signal, the direction is increased in a direction in which the operating speed of the second internal circuit is increased. The semiconductor device according to the first or second aspect of the invention, wherein the operation speed adjustment circuit adjusts an operation speed of the first or second internal circuit until the first number of times and the second time The magnitude of the number of times is consistent or reversed. The semiconductor device according to any one of claims 1 to 4, wherein the operation speed adjustment circuit adjusts the first power source by changing an internal power supply voltage of a semiconductor wafer formed by itself Or the operating speed of the second internal circuit. A semiconductor device comprising: a first semiconductor chip including a first oscillating circuit for generating a first oscillating signal; and a first counting circuit for changing a first count value in response to the first oscillating signal; And the second semiconductor wafer includes an internal power generating circuit that generates an internal power supply voltage, a second oscillating circuit that operates by the internal power supply voltage and generates a second oscillating signal, and a second oscillating signal that is responsive to the second oscillating signal In the second counting circuit in which the count value is changed, the first semiconductor wafer further includes a comparison between the first count value and the second count value to generate a comparison result signal. The circuit, the internal power generating circuit, adjusts the internal power supply voltage according to the comparison result signal. The semiconductor device according to claim 6, wherein the comparison circuit generates a click pulse signal based on a result of comparing the first count value and the second count value, wherein the internal portion The power generation circuit adjusts the aforementioned internal power supply voltage in response to the count value of the click pulse signal. The semiconductor device according to claim 7, wherein the internal power source generating circuit lowers the internal power source voltage when the first count value is larger than the second count value. When the first count value is smaller than the second count value, the internal power supply voltage is increased. The semiconductor device according to any one of claims 6 to 8, wherein the reference voltage generating circuit receives the comparison result signal and supplies the internal power generating circuit to generate the internal portion. The reference voltage at the time of the power supply voltage, the reference voltage generating circuit changes the reference voltage in response to the comparison result signal.