TW201432861A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure including a substrate, a plurality of conductive rods and a plurality of heat dissipation trenches is provided. The substrate has a first surface and a second surface opposite to each other. The conductive rods are disposed in the substrate. Each of the conductive rods extends from the first surface to the second surface. The heat dissipation trenches are located on the first surface and the second surface, and each of the heat dissipation trenches is located between two adjacent conductive rods.

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a conductive pillar.

In today's information society, electronic products are designed to be light, thin, short, and small, so that packaging technologies such as stacked semiconductor component packages that facilitate miniaturization have been developed.

The stacked semiconductor device package uses a vertical stacking method to package a plurality of semiconductor components in the same package structure, thereby increasing the package density to miniaturize the package body, and shortening the signal transmission between the semiconductor components by means of stereoscopic stacking. The path length is used to increase the speed of signal transmission between semiconductor components, and semiconductor components of different functions can be combined in the same package.

The current stacked semiconductor component package mainly focuses on the development of the Through Silicon Via (TSV) process technology of the Three Dimension Integrated Circuit (3D IC), and hopes to use various digital logic, memory or analog wafers. The circuit stack is packaged in a single package to greatly increase the speed and function of the integrated circuit. The main appeal of the three-dimensional integrated circuit is to thin the wafer to be stacked, and to use the through-via via structure to penetrate the wafer, and to transmit the circuit signal to the Re-Distributing Layer (RDL) and the contact. The next layer of wafer. The more stacked layers, the more powerful the integrated circuit.

However, since the three-dimensional integrated circuit mainly stacks different wafers (or wafers), the result of the stacking will increase the heat resistance of the overall structure of the three-dimensional integrated circuit. As a result, when the three-dimensional integrated circuit operates, a high heat generation phenomenon occurs, resulting in an increase in the operating temperature of the entire three-dimensional integrated circuit and a decrease in reliability.

The present invention provides a semiconductor structure which can improve the phenomenon of high heat generation generated during operation of a three-dimensional integrated circuit.

The present invention provides a semiconductor structure including a substrate, a plurality of conductive pillars, and a plurality of heat dissipation trenches. The substrate has opposing first and second surfaces. The conductive pillars are disposed in the substrate. Each of the conductive posts extends from the first surface to the second surface. The heat dissipation trench is located on the first surface and the second surface, and each heat dissipation trench is located between the adjacent two conductive pillars.

In an embodiment of the invention, the heat dissipation trench has a depth less than half the thickness of the substrate.

In an embodiment of the invention, the aforementioned heat dissipation grooves are in communication with each other.

In an embodiment of the invention, the semiconductor structure further includes a first redistribution pattern and a second redistribution pattern. The first redistribution pattern is disposed on the first surface of the substrate and electrically connected to the conductive pillar. The second redistribution pattern is disposed on the second surface of the substrate and electrically connected to the conductive pillar.

In an embodiment of the invention, the heat dissipation trenches on the first surface are located in a region other than the first redistribution pattern, on the second surface The heat dissipation trenches are located in regions other than the second redistribution pattern, and the heat dissipation trenches are spaced apart from the first redistribution pattern or the second redistribution pattern by a distance.

In an embodiment of the invention, the area of the heat dissipation trenches on the first surface occupies 50% or less of the area of the region other than the first redistribution pattern, and the area of the heat dissipation trenches on the second surface occupies The area of the region other than the second redistribution pattern is 50% or less.

In an embodiment of the invention, the foregoing semiconductor structure further includes a plurality of first contacts and a plurality of second contacts. The first contact is located on the first redistribution pattern, and the first redistribution pattern is located between the first contact and the conductive pillar. The second contact is located on the second redistribution pattern, and the second redistribution pattern is located between the second contact and the conductive pillar.

Based on the above, the present invention can utilize the provision of heat sinking trenches to increase the flow of air within the semiconductor structure. In this way, the phenomenon of high heat generation generated during operation of the three-dimensional integrated circuit can be improved, and the overall reliability of the three-dimensional integrated circuit using the semiconductor structure can be improved.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention. FIG. 1B is a top view of FIG. 1A. Referring to FIGS. 1A and 1B, the semiconductor structure 100 of the present embodiment is, for example, an interposer in a three-dimensional integrated circuit, but the present invention is not limited thereto. Further, the semiconductor structure 100 of the embodiment includes a substrate 110 and a plurality of conductive pillars 120. And a plurality of heat dissipation grooves 130A.

The substrate 110 has opposing first and second surfaces S1 and S2. Further, the material of the substrate 110 is, for example, tantalum or glass. The conductive pillars 120 are disposed in the substrate 110, wherein each of the conductive pillars 120 extends from the first surface S1 of the substrate 110 to the second surface S2. Further, the material of the conductive pillar 120 is, for example, copper (Cu) or nickel (Ni) or the like. The heat dissipation trenches 130A are located on the first surface S1 and the second surface S2, and the heat dissipation trenches 130A are located between the adjacent two conductive pillars 120. In the present embodiment, the method of forming the heat dissipation trench 130A is, for example, etching, but the present invention is not limited thereto. In other embodiments, the method of forming the heat dissipation trench 130A may be other suitable processing methods such as laser etching or mechanical etching.

Further, the heat dissipation trench 130A formed in this embodiment is, for example, a structure formed by the hollow substrate 110, wherein the heat dissipation trench 130A located on the first surface S1 and/or the second surface S2 is, for example, as shown in FIG. 1B. Continuous groove. That is, the heat dissipation grooves 130A surround at least two sides of the respective conductive pillars 120, and the heat dissipation grooves 130A communicate with each other. Of course, in other embodiments, the heat dissipation trench 130A may also be a plurality of trenches that are discontinuously distributed.

On the other hand, in the present embodiment, the heat dissipation grooves 130A located at the first surface S1 and the second surface S2 are not electrically connected to each other. In detail, the depth H of the heat dissipation groove 130A of the present embodiment is, for example, less than half the thickness T of the substrate 110. That is, the ratio of the depth H of the heat dissipation trench 130A to the thickness T of the substrate 110 is greater than 0 and less than 0.5, wherein the depth H of the heat dissipation trench 130A is, for example, between several micrometers and several tens of micrometers, but the present invention does not need to Defining the depth H of the heat dissipation trench 130A, the depth H may vary with the thickness of the substrate 110 T changes.

In addition, the heat dissipation groove 130A of the present embodiment may have a plurality of different sectional shapes. In the present embodiment, the heat dissipation groove 130A is exemplified by a U-shaped groove having a U-shaped cross section. However, in other embodiments, the heat dissipation trench 130A may also be a V-shaped groove having a V-shaped cross section or other suitable structure. In other words, the type of the heat dissipation groove 130A of the present invention is not limited thereto.

Further, the shape, depth H, width, length of the heat dissipation trench 130A and the distance D1 between the heat dissipation trench 130A and the conductive pillar 120 may be different depending on process conditions or design requirements. Those skilled in the art can form different types of heat dissipation grooves according to actual needs, and will not be described here.

The above embodiments are merely illustrative of the basic embodiments of the semiconductor structure and are not intended to limit the invention. In other embodiments, the semiconductor structure may further include other film layers, and another embodiment of the semiconductor structure will be described below with reference to FIGS. 2A and 2B.

2A is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention. 2B is a top plan view of FIG. 2A. Referring to FIGS. 2A and 2B, the semiconductor structure 200 of the present embodiment has a similar structure to the semiconductor structure 100 of FIGS. 1A and 1B. The main difference between the two is that the semiconductor structure 200 of the embodiment further includes a first red wiring pattern 140A, a second red wiring pattern 140B, a plurality of first contacts 150A, and a plurality of second contacts 150B.

The first redistribution pattern 140A (or the second redistribution pattern 140B) is a method of changing a semiconductor junction by using a redistribution technique. The position of the first contact 150A (or the second contact 150B) of the structure 200 is such that it conforms to the wiring layout of the semiconductor elements stacked vertically with the semiconductor structure 200. It should be noted that the first redistribution pattern 140A and the second redistribution pattern 140B, the first contact 150A and the second contact 150B may have the same or different layout, and the semiconductor structure 200 may also include only one side of the weight. a wiring pattern and a contact (that is, the first surface S1 or the second surface S2 of the substrate 110 does not have a redistribution pattern and a contact). Specifically, the rewiring pattern of the semiconductor structure and the arrangement or layout of the contacts are The present invention is not intended to limit the layout of the first redistribution pattern 140A and the second redistribution pattern 140B or the arrangement or layout of the first and second contacts 150A and 150B, depending on the layout of the electrically connected semiconductor components. .

The first redistribution pattern 140A and the second redistribution pattern 140B of the present embodiment are located on opposite sides of the substrate 110. Further, the first redistribution pattern 140 is disposed on the first surface S1 of the substrate 110 and electrically connected to the conductive pillars 120 . The second redistribution pattern 140B is disposed on the second surface S2 of the substrate 110 and electrically connected to the conductive pillars 120 . In other words, the first redistribution pattern 140 is electrically connected to the second redistribution pattern 140B through the conductive pillars 120. The materials of the first redistribution pattern 140A and the second redistribution pattern 140B are, for example, aluminum (Al), copper, or both. Alloy.

The first contact 150A and the plurality of second contacts 150B are located on opposite sides of the substrate 110. Further, the first contact 150A is located on the first redistribution pattern 140A, and the first redistribution pattern 140A is located between the first contact 150A and the conductive pillars 120. The second contact 150B is located on the second redistribution pattern 140B, and the second redistribution pattern 140B is located at the second contact 150B. Between the conductive pillars 120. In addition, the first contact 150A is electrically connected to the first redistribution pattern 140A, and the second contact 150B is electrically connected to the second redistribution pattern 140B, wherein the materials of the first contact 150A and the second contact 150B are, for example, It is copper, nickel, nickel/gold (Ni/Au), nickel/palladium/gold (Ni/Pd/Au) or gold.

In addition, the heat dissipation trench 130B of the present embodiment is located in a region other than the first redistribution pattern 140A and the second redistribution pattern 140B except for being located between the adjacent two conductive pillars 120. Further, the heat dissipation trench 130B of the present embodiment has, for example, a heat dissipation trench 130B1, a heat dissipation trench 130B2, a heat dissipation trench 130B3, and a heat dissipation trench 130B4, wherein each of the heat dissipation trenches 130B1, 130B2, 130B3, and 130B4 is along the first The redistribution pattern 140A (or the second redistribution pattern 140B) extends and is spaced apart from the first redistribution pattern 140A (or the second redistribution pattern 140B) by a distance D2.

It should be noted that the present invention does not need to limit the number, shape, width, and length of the heat dissipation trenches 130B and the distance D2 between the heat dissipation trenches 130B1, 130B2, 130B3, and 130B4 and the conductive pillars 120. The above parameters may be different due to factors such as process conditions or design requirements, and those skilled in the art may form different types of heat dissipation grooves according to actual needs, and will not be described herein.

On the other hand, since the heat dissipation trench 130B of the present embodiment is a structure formed by the hollow substrate 110, the heat dissipation trench 130B located in a region other than the first redistribution pattern 140A and the second redistribution pattern 140B is The area needs to have a certain area ratio to maintain the structural strength of the semiconductor structure 200 as a whole. In this embodiment, the heat dissipation trench 130B on the first surface S1 For example, the area of the area other than the first redistribution pattern 140A is 50% or less, and preferably about 30% to 40% of the area of the area. Further, the heat dissipation groove 130B on the second surface S2 is, for example, 50% or less of the area of the region other than the second redistribution pattern 140B, and preferably accounts for about 30% to 40% of the area of the area.

By the arrangement of the heat dissipation trench 130B, the present embodiment can increase the flow of air in the semiconductor structure 200 (refer to the first surface S1 and/or the second surface S2 of the substrate 110). In this way, the phenomenon of high heat generation generated during operation of the three-dimensional integrated circuit in which the active component or the passive component and the semiconductor structure 200 are stacked and packaged can be improved, thereby improving the overall reliability of the three-dimensional integrated circuit.

3 is a cross-sectional view showing a three-dimensional integrated circuit of the semiconductor structure 200 of the embodiment of FIG. 2B, wherein the cross section of the semiconductor structure 200 of FIG. 3 is, for example, a cross section taken along line A-A' of FIG. 2B. Referring to FIG. 2B and FIG. 3, the present embodiment can increase the flow of air in the semiconductor structure 200 (refer to the first surface S1 and/or the second surface S2 of the substrate 110) by the arrangement of the heat dissipation trenches 130B. In this way, the three-dimensional integrated circuit 1 stacked and packaged by the memory circuit 10, the digital logic circuit 20, the analog wafer circuit 30, the other wafer 40, and the semiconductor structure 100 interposed between the wafers or circuits can be improved. The phenomenon of high heat generation during operation enhances the reliability of the entire three-dimensional integrated circuit 1. Of course, the semiconductor structure 200 of the foregoing embodiment is not limited to being applied to the three-dimensional integrated circuit 1 shown in FIG.

In summary, the present invention increases the space inside the semiconductor structure by providing heat dissipation trenches on opposite surfaces (and the first surface and the second surface) of the substrate. The flow of gas. In this way, the phenomenon of high heat generation generated during operation of the three-dimensional integrated circuit can be improved, and the overall reliability of the three-dimensional integrated circuit using the semiconductor structure can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ semiconductor structure

110‧‧‧Substrate

120‧‧‧conductive column

130A, 130B, 130B1, 130B2, 130B3, 130B4‧‧‧ heat dissipation trench

140A‧‧‧First redistribution pattern

140B‧‧‧Second red wiring pattern

150A‧‧‧ first joint

150B‧‧‧second junction

10‧‧‧Digital logic circuit

20‧‧‧ memory circuit

30‧‧‧ analog wafer circuit

1‧‧‧Three-dimensional integrated circuit

S1‧‧‧ first surface

S2‧‧‧ second surface

H‧‧‧ Depth

T‧‧‧ thickness

D1, D2‧‧‧ distance

1A is a cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention.

FIG. 1B is a top view of FIG. 1A.

2A is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention.

2B is a top plan view of FIG. 2A.

3 is a schematic cross-sectional view showing a three-dimensional integrated circuit of the semiconductor structure of the embodiment of FIG. 2B.

100‧‧‧Semiconductor structure

110‧‧‧Substrate

120‧‧‧conductive column

130A‧‧‧heating trench

S1‧‧‧ first surface

S2‧‧‧ second surface

H‧‧‧ Depth

T‧‧‧ thickness

D1‧‧‧ distance

Claims (6)

A semiconductor structure comprising: a substrate having an opposite first surface and a second surface; a plurality of conductive pillars disposed in the substrate, each of the conductive pillars extending from the first surface to the second surface And a plurality of heat dissipation trenches on the first surface and the second surface, and each of the heat dissipation trenches is located between two adjacent conductive pillars. The semiconductor structure of claim 1, wherein the heat dissipation trenches have a depth less than half the thickness of the substrate. The semiconductor structure of claim 1, further comprising: a first redistribution pattern disposed on the first surface of the substrate and electrically connected to the conductive pillar; and a second redistribution The pattern is disposed on the second surface of the substrate and electrically connected to the conductive pillar. The semiconductor structure of claim 3, wherein the heat dissipation trenches on the first surface are located in a region other than the first redistribution pattern, and the heat dissipation trenches on the second surface are located a region other than the second redistribution pattern, and the heat dissipation trenches are spaced apart from the first redistribution pattern or the second redistribution pattern by a distance. The semiconductor structure of claim 4, wherein the heat dissipation trenches on the first surface occupy an area of 50% or less of an area other than the first redistribution pattern, and the second surface The area of the heat dissipation grooves accounts for 50% or less of the area of the region other than the second redistribution pattern. The semiconductor structure of claim 3, further comprising: a plurality of first contacts located on the first redistribution pattern, and the first redistribution pattern is located at the first contacts and the conductive pillars And a plurality of second contacts located on the second redistribution pattern, and the second redistribution pattern is located between the second contacts and the conductive pillars.