TW201432691A - Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency - Google Patents

Abstract

A non-volatile multi-level cell (''MLC'') memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.

Description

Non-electrical multi-level cell memory with decoupled bits for higher performance and energy efficiency

The present invention relates to non-electrical multi-level meta-cell memory with decoupled bits for higher performance and energy efficiency.

Background of the invention

Non-electrical memory such as memristors and phase change memory (PCM) have emerged as promising and scalable alternatives to current memory technologies such as dynamic random access memory (DRAM) and cache memory. Program. In addition to comparing fundamentally different ways in which DRAM and cache memory can lead to higher memory densities, lower cost per bit, and larger capacity storage data, these evolving non-electrical memories The body supports multi-bit cell (MLC) technology, which allows each memory cell to store two or more bits (instead, DRAM can store only one bit per cell). The potential to operate at lower power further adds to the competitiveness of memristors and PCM as a scalable DRAM alternative.

More specifically, PCM is a budding memory technology that stores resources by changing the resistance of a material called chalcogenide. material. By applying heat and then permitting cooling at different rates, the chalcogenide can be manipulated to stay in a non-crystalline (rapid quenching) high resistance state (eg, logic low or zero) and crystalline (slow cooling) low resistance state (eg Logic high or 壹). PCM is non-electrical because the state of chalcogenide remains in the absence of electricity. The large electrical resistance difference between the amorphous and crystalline states of the PCM cell (up to a power of 3) is permitted in the MLC technology of the PCM cell. This is achieved by dividing the large resistance difference into four separate areas, each representing the 2-bit value of "11", "10", "01", and "00". By precisely controlling the resistance within one of these resistance regions, more than one bit can be stored in one cell.

However, the PCM support MLC suffers from higher access latency and energy. MLC requires that the cell resistance be accurately controlled over a narrow range, which requires iterative write and read techniques with multiple sensing iterations, resulting in higher read latency and energy, as well as higher write latency and energy.

According to an embodiment of the present invention, a non-electrical multi-level cell (MLC) memory comprises an array of non-electric memory cells, and each non-electrical memory cell is stored. a plurality of sets of bits; and a column of buffers having a plurality of buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write delays and energy.

100, 610, 810‧‧‧ memory, non-electrical multi-level cell (MLC) memory

105, 120, 125, 130, 135, 400, 620‧‧‧ memory cells

110, 625, 825‧‧ ‧ character lines

115, 630, 830 ‧ ‧ bit line

Columns 140, 415, 425‧‧

145‧‧‧

150a-c‧‧‧Sense Amplifier

155, 635, 835 ‧ ‧ column buffer

160, 615, 815‧‧‧ memory controller

170‧‧‧ Memory Banking, Most Significant Bit (MSB)

175‧‧‧Least Significant Bit (LSB)

200, 420A-B‧‧‧ cells

205‧‧‧Sense Amplifier

210, 235‧‧‧ line chart

215, 240, 305, 310, 320, 325‧‧ Thick line

220‧‧‧ analog to digital converter

225, 230‧‧ ‧ latch

300, 315‧‧‧ thumbnail

430a, 700‧‧‧MSB half-column

430b, 705‧‧‧LSB half-column

500‧‧‧data block address mapping

505‧‧‧Study data block address mapping

600, 800‧‧‧ computer system

605, 805 ‧ ‧ processing resources

640‧‧‧MSB buffer section

645‧‧‧LSB buffer section

710, 715‧‧‧ half-column

840-850‧‧‧Buffer section

900-910, 1000-1025‧‧‧ squares

The detailed description of the accompanying drawings may be more apparent in the accompanying drawings. 1 is a schematic diagram of a non-electrical MLC memory according to various embodiments; FIG. 2A-B is a schematic diagram illustrating a read delay of a memory cell according to various embodiments; FIG. 3A-B is a schematic diagram illustrating the basis Multiple embodiments - write latency of memory cells; Figure 4 is a schematic diagram illustrating how MSB and LSB can be decoupled from non-electrical multi-level memory cells to exploit read and write delays and energy asymmetry FIG. 5 is a schematic diagram comparing the data block address mapping and the conventional scheme suggested herein; FIG. 6 is for the higher performance and energy efficiency having decoupling bits in a non-electrical MLC memory. A schematic diagram of a computer system; Figure 7 illustrates the interleaving of MSB and LSB in a column of buffers for writing to the memory; Figure 8 is for a higher performance and energy efficiency in a non-electrical MLC memory. Another schematic diagram of a computer system with decoupled bits; Figure 9 is a flow chart for decoupling bits in a non-electrical MLC memory for higher performance and energy efficiency; and Figure 10 is for High performance and efficiency combine writing with first-class non-electrical MLC memory Fig.

Detailed description of the preferred embodiment

Reveal decoupled bits for higher performance and energy efficiency Non-electrical multi-level cell (MLC) memory. As described generally herein, the non-electrical MLC memory is a non-electrical memory having a plurality of memory cells, each memory cell storing more than one bit. In various embodiments, the non-electrical MLC memory may store a plurality of sets of non-electrical memory (eg, PCM, memristor, etc.) for each cell, where each group may have one Or multiple bits. For example, a memory cell can store two sets of bits, each group having a single bit (each cell storing a total of two bits). One group can store one most significant bit (MSB) and the other can store a least significant bit (LSB). In another embodiment, a memory cell can store four sets of bits, each set having a single bit (each cell storing a total of 4 bits). In yet another embodiment, a memory cell can store two sets of bits, each set having 2 bits (each cell also storing a total of 4 bits). It is also contemplated that various other embodiments are contemplated and described in further detail.

The non-electrical MLC memory divides each memory cell into multiple groups. A column of buffers having a plurality of buffer portions is used to store the bits from the memory cells, each buffer portion having a different read and write delay and energy. For ease of explanation, the following description may be referred to as the first embodiment, where a memory cell has two sets of bits, each group having a single bit. In this embodiment, the MLC memory has an MSB half storing an MSB bit and an LSB half storing an LSB bit. The MSB half has reduced read latency and energy, while the LSB half has reduced write latency and energy. The MSB bits from the MSB half of the memory are stored in an MSB buffer portion of a column of buffers, and the LSB bits from the LSB half of the memory are stored in the column buffer. An LSB buffer section. The data block in the MSB buffer portion can be interleaved with the data block in the LSB buffer portion to increase the chance of incorporating writes into the memory and improve its durability.

It is to be understood that in the following description, numerous specific details are set forth It is to be understood that the embodiments are not limited to such specific details. In other instances, well-known methods and structures may not be described in detail to avoid obscuring the description of the embodiments. Again, the embodiments can be used in combination with one another.

Referring now to Figure 1, a schematic diagram of a non-electrical MLC memory in accordance with various embodiments is depicted. The non-electrical MLC memory 100 includes a memory cell array and peripheral circuits. In an array, the memory cell lines are organized into columns and rows, and all of the cell lines in each column are connected to a common word line, and all cell lines in each row are connected to a common bit. Line (each cell is connected to one word line and one bit line). For example, memory cell 105 is coupled to word line 110 and bit line 115. Memory cell 105 is on the same column 140 as memory cells 120 and 125, and on the same row 145 as memory cells 130 and 135. Those skilled in the art will appreciate that the Memory 100 series shows nine memory cells for illustrative purposes only. A typical memory 100 can have additional cells.

When accessing data in memory 100, the same column of cells (e.g., column 140) is simultaneously accessed. In doing so, a column decoder (not shown) declares a word line to select all of the cells in the target column, and the bit line transmits data between the cells and the peripheral circuits. In the peripheral circuits, the data signals from the bit lines are borrowed from a sense amplifier of a column of buffers 155. 150a-c detects and latches in column buffer 155, and a row of decoders (not shown) selects a subset of column buffers 155 to communicate with I/O pads (not shown).

It should be understood that the memory 100 can be logically divided into blocks, commonly known as memory banks. A memory bank is the smallest zone of memory 100 that can be independently addressed. For example, memory 100 is illustrated by a memory bank 170. Each column in memory bank 170 delivers a large number of bits to sense amplifiers 150a-c. The number of bits delivered is a multiple of the processor word (eg, 32 bits or 64 bits). The memory bank 170 is controlled by the memory controller 165, which provides an interface between the memory bank in the memory 100 and a processor (not shown). The memory controller 165 reads, writes, and re-creates the memory 100 through a combination of a multiplexer and a demultiplexer that selects the correct column, row, and memory locations for the data.

Once a column of data is placed in the column buffer 155, subsequent data requests for the same column can be accessed by the data service in the buffer. Such access is referred to as a list of buffer hits, and the access latency of the column buffer 155 can be quickly serviced without having to interact with the slower cell array. However, in order to service a data request to another column, the data must be accessed from the array (replace the contents of the column buffer 155). This type of access is referred to as a column of buffer errors, resulting in higher latency and power consumption due to the actuation of a column of cells in the array.

Applications with high data locality can benefit from large column buffers and suffer from reduced memory access time. But with multi-core processors, memory requests from multiple threads (processing) access the same memory The time-varying transaction is inserted, resulting in an increase in column buffer collisions and thus a high column buffer miss rate. This also increases competition in the memory controller 165 because the memory request tends to wait longer in the memory controller 165 for a longer time before signing. One possible solution to this problem is to support multiple column buffers for each bank to improve the parallelism of the memory. As such, the column buffer contents of the active state are less likely to be defeated by conflicting accesses from another thread (processing). However, this approach significantly increases the area's extra burden and memory costs.

As will be described in detail later, the MLC characteristics of the memory 100 can be explored to effectively achieve multiple column buffers with an extra burden on very low areas. Each memory cell within memory 100 has an MSB 170 and an LSB 175. The MSBs from all cells in the memory bank 170 can be stored in an MSB buffer portion of the column buffer 155, and the LSBs from all cells in the memory bank 170 can be stored in the An LSB buffer portion of column buffer 155. Significant improvements in memory latency and column buffer hits can be achieved by having the column buffer 155 effectively partitioned into two column buffer portions. As will be described later in detail, the memory delay of the memory 100 actually depends on the bit type in a memory cell. The MSB has a lower read latency and energy than the LSB, which in turn has a lower write latency and energy than the MSB bit.

Referring now to Figures 2A-B, a schematic diagram illustrating the read latency of a memory cell is illustrated in accordance with various embodiments. In FIG. 2A, an integrated analog to digital converter (ADC) quantifies the resistance of a cell 200 to a 2-bit value by sensing the time it takes for a column of charge (ie, current) to pass through cell 200. The line graph 210 shows a sense of the sensed time sensed by the sense amplifier 205. The number changes. The higher the resistance, the longer the sensing time. As a result, the read latency is limited by the time it takes to sense the highest cell resistance.

As can be seen from the line graph 210, it is possible to distinguish some information about the cell data before the read operation is completed. Each sensing time provides information to the bits stored in cell 200. For example, the thick line 215 in the line graph 210 is displayed at the sensing time of t3, and the bit stored in the cell 200 is "01", or "0" MSB and "1" LSB. The sense amplifier 205 outputs a "01" bit through a analog-to-digital converter 220 when sensing the sensing time of t3. The "0" MSB is stored in the latch 225 and the "1" LSB is stored in the latch 230.

As illustrated in Figure 2B, the MSB can be determined halfway through the read operation. In this embodiment, if the cell resistance is determined halfway through the read operation, the MSB is "1", otherwise the MSB is "0" regardless of the LSB. This point can be seen in thick line 240 of line graph 235, which represents half of the read operation shown by thick line 215 in line graph 210. At time t2 earlier than time t3, it has been determined that the bit stored in cell 200 is "01". In other words, the MSB can be read before the read operation is completed.

This observation indicates that the MSB has a lower read latency (and energy) than the LSB. However, in the conventional non-electrical MLC memory, the nature of the read asymmetry is not explored, and a block of data is developed across the MSB and the LSB. This delays the memory read request service until the slower LSB is ready. On the other hand, if the MSB and the LSB are mapped to logically separated memory addresses, the data block stored in the MSB can be read with a lower delay (and the data block stored in the LSB can be read as the same delay as before). take).

Similar write asymmetry can be observed in an MLC PCM, The LSB has a lower write latency and energy than the MSB. Turning now to Figures 3A-B, a schematic diagram illustrating the write latency of a memory cell in accordance with various embodiments is described. The write delay of a multi-bit quasi-PCM cell depends on two terms: the initial state of the cell, and the target state of the cell. This point is illustrated in FIG. 3A by diagram 300, which shows the delay experienced by a memory cell transitioning from either state to another state in a 4-bit PCM write operation. For any transition, the target cell resistance is achieved with a lower delay by using a planning method (either to partially crystallize the amorphous chalcogenide or partially amorphize the crystalline chalcogenide).

When writing any data to the cell block, the write delay is limited by the maximum time to complete any transition (in bold emphasis on Figure 3A, with a thick line between the memory cell state "01" and the state "10" 305, and a thick line 310 between the cell state "00" and the state "10". However, if both LSB and MSB are not changed in a single write operation (and thus the diagonal transition of Figure 3A is not used), the delay caused by the varying LSB is lower than the variation MSB. For example, changing the LSB from "0" to "1" results in a 0.8x or 0.84x write latency, and changing the LSB from "1" to "0" results in a 0.3x or 0.2x write latency.

Figure 3B emphasizes that only changing the MSB (thick line 320 in thumbnail 315) is limited by the 1.0x delay (from "00" to "10"), while only changing the LSB is limited by the lower 0.84x delay of 3 (from "00" to "01", thick line 325). The memory cell is planned to be "10" only when the transition from the "11" that has been in the crystalline state is delayed by 0.2x, where partial amorphization requires the application of a reset pulse. This observation indicates that the LSB has a lower write latency (and energy) than the MSB. But similar to the reading asymmetry discussed above in Figure 2A-B, when a block of data is exhibited When the LSB and MSB are crossed, this property is not leveraged in the conventional MCL PCM. If the LSB and the MSB are mapped to logically separated memory addresses, the data blocks stored in the LSB can be written with lower latency when detailed later (and the data blocks stored in the MSB can be written with the same delay as before). In).

Attention is now directed to Figure 4, which shows how the MSB and LSB are decoupled in the MLC PCM cell to take advantage of such read and write asymmetry. Each of the memory cells 400 of the MLC PCM (e.g., the memory 100 shown in FIG. 1) has an MSB and an LSB. In a conventional MLC PCM, the bits are coupled to form a single contiguous memory address along a column, as shown by column 415. Column 415 illustrates the change from cell to cell, with the memory address changing in a sequential or sequential manner. The first cell 420a in column 415 is addressed before the second cell 420b, and the MSB is addressed prior to the LSB. For illustration purposes, a 4-bit size data block is highlighted with different shading. The 4-bit block formed by the cell 420a-b is first associated with the MSB (labeled "0") in cell 420a, followed by the LSB (labeled "1") in cell 420a, cell 420b. The MSB (labeled "2") and the LSB (labeled "3") in cell 420b are addressed. Column 415 is traversed in this style.

Conversely, the non-electrical MLC memory presented here (eg, memory 100 in FIG. 1) will group along the MSB of one column to form a contiguous address, and group the LSBs along the same column to form another contiguous address. Address. In this way, a data block (eg, a 64-bit cache block) resident at a logical address is physically occupied only by the MSB or only by the LSB. If the data block is at the MSB, the read asymmetry (discussed above with reference to Figures 2A-B) is discussed and the block is read with reduced delay and energy. Similarly, if the information The block is at the LSB, and the write asymmetry is discussed (previously discussed above with reference to Figures 3A-B) and written to the block with reduced delay and energy.

The decoupling bit effectively divides all columns in the memory into two logical addresses; one uses the MSB and the other uses the LSB. For example, column 425 is effectively divided into an MSB half column 430a and an LSB half column 430b. In contrast to column 415 of a conventional MLC PCM, where the bits traversing the column are addressed in a contiguous manner, the memory presented here (e.g., memory 100 in Figure 1), all bits of MSB half column 430a It is addressed before all bits of the LSB half column 430b. The MSB of the first cell 430a is addressed before the MSB of the second cell 430b, and so on until the MSB half column 430a ends. The LSB in the LSB half column 430b is considered only after all MSBs in a memory bank are addressed.

Figure 5 compares the data block address mapping and the proposed scheme presented here. Assuming that an application's virtual page address is randomly and randomly translated to a physical box address in memory, the application's working setpoint is roughly half of the MSB and the other half is at the LSB. Therefore, using the data block address map 500 presented here, the average 50% memory read is served with reduced latency (up to 48%) and energy (up to 48%), and 50% memory writes are reduced. Delay (up to 16%) and energy (up to 26%) service.

The disadvantage of the data block address map 500 is that it increases the number of cells that are planned during the write operation, adding an additional burden of durability. The reason is that from each 2-bit cell, only one bit is obtained from a data block, and when writing to the block, the number of cells is equal to the number of bits in a block. But this does not double the extra burden of durability than the conventional solution. The reason is that the probability that the planning cell becomes redundant (because the cell is already in the target state to be planned) is lower than the conventional scheme, where both the MSB and the LSB must match the written data.

On the other hand, a block that writes data to 500 has only MSB or only LSB, such a block-write has more redundant bits-writes. The simulation shows an average 21% durability extra burden. This is small enough to achieve the 5-year lifespan of a typical server design, and it has been shown that previous work has shown that the PCM main memory has an average life of 8.8 years. By using the data block address mapping 500, the two separate logical address spaces share the column buffer space, and each address space occupies half of the column buffer. This minimizes the longest contiguous address space that can be held in the column buffer, potentially reducing the locality of the column buffer. However, the reduced memory address delay exposed by the data block address mapping 500 not only compensates for this effect, but also significantly improves system performance (and energy efficiency) over conventional data block address mapping. Figure 505, without significant modifications to the memory circuitry and architecture.

Attention is now directed to Figure 6, which shows a computer system with decoupled bits in a non-electrical MLC memory for higher performance and energy efficiency. Computer system 600 has a processing resource 605 that communicates with a non-electrical MLC memory 610 via memory controller 615. Processing resource 605 can include one or more processors and one or more other memory resources (eg, cache memory). The non-electrical MLC memory 610 has an array of non-electrical memory cells (eg, memory cells 620), and each multi-level memory cell stores an MSB and an LSB. The array of memory cells can be organized into an array of word lines (columns) x bit lines (rows), such as word line 625 and bit lines. 630.

The memory controller 615 provides an interface between the non-electrical memory cell array and the processing resource 605 in the memory 610. The memory controller 615 reads, writes, and re-news the memory 610 by selecting the correct column, row, and memory location of the data through the combination of the multiplexer and the demultiplexer. In various embodiments, the memory controller 615 reads and writes data to the memory 610 via a column of buffers 635. The column buffer 635 has an MSB buffer portion 640 and an LSB buffer portion 645 for storing MSBs and LSBs from the non-electrical memory cell arrays in the memory 610, respectively. As previously described with reference to Figures 4 and 5, the MSBs in memory 610 are decoupled from the LSBs and mapped to separate logical addresses. The MSB and LSB of the memory cells in the decoupled memory 610 effectively divide a column into two halves, each having its own contiguous logical address. As shown, the permissible column buffer 635 is manipulated as two half column buffers having an MSB buffer portion 640 for storing the MSB and an LSB buffer portion 645 for storing the LSB.

The MSB is decoupled from the LSBs in column buffer sections 640-645 and accessed as separate logical addresses, achieving significant improvements in read latency and energy and write latency and energy. When reading data from memory 610, memory controller 615 can read the data block from MSB buffer portion 640 with reduced read latency and energy (read data from LSB buffer portion 645 with conventional read latency and energy). Block). Similarly, when writing data to the memory 610, the memory controller 615 can reduce the write latency and energy write data blocks to the LSB buffer portion 645 (using conventional write latency and energy write data blocks to the MSB buffer). Part 640).

A disadvantage of such MSB/LSB decoupling is that the memory 610 has poor durability compared to conventional memory in which the bit system is decoupled. The reason is that in a conventional bit scheme, in order to plan M bits, since there are two logically connected bit elements mapped to the same cell, the M/2 cell performs a physical planning cycle of heating and cooling. However, in order to plan the M bits in the memory 610, since only one of the two bits in each cell changes, the M cell performs physical programming. Thus, in the absence of data buffering effects, the MSB and LSB decoupling in memory 610 consumes a durable cycle at twice the rate of conventional memory, thus halving the lifetime of the memory. For example, taking the memory 610 as the PCM, the memory 610 can simply plan the existing data existing anywhere in the memory, and each cell to be planned performs a durable cycle. Therefore, the number of cells involved in the plan directly affects the lifetime of the memory 610.

The poor memory durability effect due to the decoupling of the MSB and the LSB can be mitigated by combining the writes to the MSB and the LSB as a single write. The write to memory 610 is combined such that a memory cell in the memory 610 can be scheduled only once instead of twice. Interleaving the data block in the MSB buffer with the data block in the LSB buffer further increases the combined write probability. An example of an interleaving system is illustrated in Figure 7. By interleaving a cache block between two pages of a column (where the smallest unit of memory 610 is accessed), the spatial locality in the write back is explored to increase the chance of the cached block being written back to the same cell. In order to combine writeback, the two bits of the cell can be changed during planning.

As shown in FIG. 7, the MSB half column 700 has eight data blocks from 0 to 7, and the LSB half column 705 has eight data blocks from 8 to 15. The MSB half column 700 is stored in the MSB buffer portion of a column of buffers (eg MSB) Buffer portion 640), and LSB half column 705 are stored in the LSB buffer portion of a column of buffers (e.g., LSB buffer portion 645). The data stored in column buffer 635 can be sent to a processing resource 605 for processing before being sent back to column buffer 635. In this way, some of the data can be shaded "stained", indicating that the bits must be written to the memory before other blocks can be read from the memory to the buffer.

The dirty cache block evicted from the last level of cache memory is typically issued as a write back to the memory and a write buffer initially inserted into the memory controller. Most systems prioritize sequence buffer hit requests (to varying degrees), so these dirty cache blocks wait in the memory controller's write buffer until they reach their destination column, at that point. Its data is sent to the column buffer 635. The dirty cache block data is then resident in the column buffer 635 until the contents of the column buffers need to be evicted (ie, eviction to a different column of buffers), which is actually the dirty cache data is planned into The memory cell array.

In this embodiment, bits 1, 2, and 4-7 are dirty. If all of these blocks are written, then a total of 6 writes are written to the column corresponding to the MSB half column 700 and the LSB half column 705. However, if before writing back to the memory, as in the half column 710-715, the bit is interleaved in the column buffer 635, in other words, if the write is combined and the data locality is discussed, then the bits 4-5 and 6 -7 can be written together. It does not need to write to the memory separately 6 times, only 4 times to write separately. Note that the number of interleaved cache blocks can range from 1 up to the number of cache blocks that fit a single page (which is one and a half of a column).

It is important to understand that although the first column first come first (FR-FCFS) The scheduling strategy is of course written in conjunction with the column buffer 635, which can be improved by carefully waiting for the write queue to be queued to the memory controller 615. The mechanism for servicing this project is known as DRAM aware of the last level of cacheback (DLW). Each time the dirty last-most cache block is evicted, the DLW searches for the last-level cache of the last-level cache to the other dirty cache block in the same column, and sends this as a write-back to the test. Memory. The data block interleaving system in column buffer 635 works in conjunction with the DLW to issue a number of writebacks to the same column, thus increasing the possibility of write binding. It is also important to understand that interleaving only changes how the data is interpreted in the column buffer 635; it does not require any changes to the memory 610. However, when calculating the location of the cache line within a page, the memory controller 615 must consider the degree of interleaving and decode the address accordingly.

Attention is now directed to Figure 8, which shows another embodiment of a computer system having decoupled bits in a non-electrical MLC memory for higher performance and energy efficiency. As previously mentioned, for ease of illustration, Figures 1-7 depict an embodiment of a memory cell having two sets of bits, each group having a single bit (MSB or LSB). The computer system 800 of Figure 8 has memory cells that can store a plurality of other group bits (rather than just MSBs and LSBs). Similar to the computer system 600 of FIG. 6, the computer system 800 has a processing resource 805 that communicates with the non-electrical MLC memory 810 via the memory controller 815. Processing resource 805 can include one or more processors and one or more other memory resources (eg, cache memory). The non-electrical MLC memory 810 has an array of non-electrical memory cells (eg, memory cell 820), and each multi-level memory cell stores a plurality of sets of bits, labeled as GB1, GB2, and GB3. Wait until GBN, where N can be any integer equal to or higher than 3 and subject to the physical limit of memory 810 Limited by system. The memory cells of the array can be organized into an array of word line (columns) x bit lines (rows), such as word line 825 and bit line 830.

The memory controller 815 provides an interface between the array of non-electrical memory cells in the memory 810 and the processing resource 805. The memory controller 815 reads, writes, and re-news the memory 810 by selecting the correct column, row, and memory location of the data through the combination of the multiplexer and the demultiplexer. In various embodiments, the memory controller 815 reads and writes data to the memory 810 via a column of buffers 835. The column buffer 835 has a plurality of buffer portions 840-850 labeled "first buffer portion" (840), "second buffer portion" (845), etc. until "nth buffer portion" (850). Each of the buffer portions 840-850 can store a set of bits from the memory cell 820. For example, buffer portion 840 can store GB1, buffer portion 845 can store GB2, and buffer portion 850 can store GBN. Each of the buffer portions 840-850 has a different read delay and energy and a different write delay and energy.

Turning now to Figure 9, there is shown a flow chart for decoupling bits in a non-electrical MLC memory for higher performance and energy efficiency. First, the physical address space of the non-electrical MLC memory is decoupled into a plurality of groups of bits, each group having a different read and write delay (900). For example, one set of bits can be an MSB with reduced read latency, and another set of bits can be an LSB with reduced write latency. Different read and write delays for multiple sets of bits are exposed to the memory cells (905). The control services a memory request (e.g., a read and write request) based on a plurality of sets of read and write delays (910).

Figure 10 is a flow chart for writing to a non-electrical MLC The memory is used for higher performance and energy efficiency. First, when mapping a page to a physical memory, the bit blocks across the plurality of column buffer portions are interleaved, such as the bit block from the MSB buffer portion and the bit from the LSB buffer portion. The metablock is interleaved as previously described with reference to Figure 7 (1000). Second, the memory cell issues a write request to the first address (1005). If a write request placed for a second address is mapped to the same column and the same set of cells (1010) in the memory, the first and second write requests are combined into a single combined write to The memory column is a single write update (1015). Otherwise, the first and second addresses are written separately (1025). When the memory controller schedules a write request, if there is a possibility of combining, the memory block can be forwardly sent from the last level memory to the memory (1020).

Excellently, in the decoupling of bits in non-electrical MLC memory, the read and write delays and energy-enhanced read and write asymmetry are discussed. The MSB is read with reduced delay and energy, while the LSB is written with reduced delay and energy. The MSB and LSB interleaved in the column buffer before writing to the memory, combined with the durability effect of writing and mitigating bit decoupling.

It is to be understood that the foregoing description of the disclosed embodiments is provided by the skilled artisan. The various modifications of the embodiments are apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit and scope of the disclosure. As such, the disclosures are not intended to be limited to the embodiments shown herein, but rather the broad scope of the principles and novel features disclosed herein.

800‧‧‧ computer system

805‧‧ ‧ Processing resources

810‧‧‧ Non-electrical multi-level cell (MLC) memory

815‧‧‧ memory controller

820‧‧‧ memory cells

825‧‧‧ character line

830‧‧‧ bit line

835‧‧‧ column buffer

840‧‧‧ first buffer section

845‧‧‧Second buffer section

850‧‧‧Nth buffer section

Claims (14)

A non-electrical multi-level cell (MLC) memory cell comprising: an array of non-electrical memory cells, each non-electric memory cell storing multiple sets of bits; And a column of buffers having a plurality of buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write delays and energy. The non-electrical MLC memory of claim 1, which comprises a memory controller to issue a write request to different bits in a set of memory cells, and to instruct the memory to combine the writes Request a single write to the memory cells of the set. The non-electrical MLC memory of claim 1, wherein the first group of bits is stored in a first buffer portion, and the second group of bits is stored in a second buffer portion, and The bit block of the first buffer portion is interleaved with the bit block from the second buffer portion to be coupled to the write of the column buffer. The non-electrical MLC memory of claim 2, wherein the column buffer comprises a plurality of sense amplifiers and an analog to digital converter, each sense amplifier being coupled to a bit line. The non-electrical MLC memory of claim 4, wherein each analog to digital converter is coupled to a plurality of latches to hold the plurality of sets of bits. The non-electrical MLC memory of claim 4, wherein the read latency is taken This is due to the time consumed by the plurality of sense amplifiers to sense the resistance of one of the non-electrical memory cells. The non-electrical MLC memory of claim 1, wherein the write delay is dependent on an initial state of the non-electrical memory cells and a target state of the non-electrical memory cells. A method for decoupling higher performance and energy efficiency bits in a non-electrical multi-level cell (MLC) memory, the method comprising: decoupling a physical address space into a plurality of groups Bits, each group having a different read and write delay; exposing read and write delays of the plurality of groups of bits to a memory controller; and servicing a memory based on the plurality of sets of read and write delays Request. The method of claim 8, wherein decoupling a physical address space into a plurality of sets of bit systems comprises storing a plurality of buffer portions of the plurality of sets of bits to a column of buffers. The method of claim 9, comprising the data block interleaved in a first buffer portion and the data block in a second buffer portion to increase a write binding opportunity. The method of claim 8, further comprising: searching for the mapping of a last-level cache memory to a memory column each time the dirty data of the last level is evicted. The dirty cache block and the dirty cache block are issued as write back to the non-electrical MLC memory. A computer system comprising: a non-electrical multi-level cell (MLC) memory having an array of non-electrical memory cells, each memory cell storing a most significant bit ( MSB) and a least significant bit (LSB); a column of buffers having an MSB buffer to store MSBs and LSB buffers from the memory cells to store LSBs from the memory cells, wherein a bit block from the MSB buffer is interleaved with a bit block from the LSB buffer; and a memory controller to write a bit of a block to the non-electrical MLC memory A set of cells in a column, identifying other write requests for the same set of cells in the column, and instructing the memory to bind the writes to the memory. The computer system of claim 12, wherein the column buffer comprises a plurality of sense amplifiers, and the memory controller controls the plurality of sense amplifiers to select the MSB buffer or the LSB buffer to store the block Information. The computer system of claim 12, wherein the non-electrical MLC memory system comprises a phase change memory.