TW201430798A - Source driver and display device - Google Patents

Abstract

A source driver including a controller, a plurality of flip-flops, a plurality of shift registers and a plurality of driving channels is provided. The controller extracts control information from an image data stream. Each of the flip-flops respectively receives a corresponding control bit of the control information, and output the corresponding control bit. The shift registers correspond to the flip-flops one by one, and sequentially transmit an enable pulse. Each of the shift registers determines whether to output the enable pulse according to the control bit outputted by the corresponding flip-flop. The driving channels correspond to the shift registers one by one. Each of the driving channels switches an operation state into an enable mode or a disable mode according to the enable pulse outputted by the corresponding shift register.

Description

Source driver and display device

The present invention relates to a source driver and display device, and more particularly to a source driver and display device that can utilize the control information from the image stream to adjust the operational state of each drive channel.

Due to advances in display technology, the size of display panels has also become more diverse. In order to meet a variety of different display panel specifications, in the general display driver circuit design, the two sets of pin drivers of the source driver are usually used as the set pin of the set channel number, and the preset array is preset. Different channel number specifications to match different sizes of display panels.

However, the compatibility of the source driver designed in this way is still limited to a certain extent. Moreover, since the respective source drivers must be set one by one by additionally setting the traces connected to the set pins of the source driver, the influence of the traces must be further considered when designing the source driver. In addition, if the driver circuit design is to be miniaturized, the extra traces are bound to increase the difficulty in circuit design.

The invention provides a source driver, which can extract control information from the received image data stream and determine whether to allow the corresponding driving channel to access the display data according to the control information.

The invention provides a display device which can be used without using a set foot In this case, adjust the number of drive channels that can be used in each source driver.

The invention provides a source driver comprising a controller, a plurality of flip-flops, a plurality of shift registers and a plurality of drive channels. The controller extracts control information from the image data stream. The plurality of flip-flops are electrically connected in series with each other and receive control information. Each of the flip-flops receives a control bit in the control information and outputs the control bit. The plurality of shift registers are electrically connected in series with each other and are in one-to-one correspondence with the plurality of flip-flops, wherein the plurality of shift registers transfer the enable pulses one by one, and are transmitted During the process of enabling the pulse, each shift register determines whether to output an enable pulse according to the control bit output of the corresponding flip-flop. The plurality of driving channels are in one-to-one correspondence with the plurality of shift registers, wherein each driving channel switches the operating state to enable according to the enabled pulse of the corresponding shift register output Mode or disable mode.

In an embodiment of the invention, the source driver further includes a plurality of level shifters. The plurality of level shifters are in one-to-one correspondence with the plurality of flip-flops, wherein each level shifter determines whether to generate a disable voltage according to a control bit output by the corresponding flip-flop. To turn off an output buffer of one of the plurality of drive channels.

In an embodiment of the invention, when the enable pulse of the corresponding shift register output is received, the operational state is switched to the enable mode, and when the corresponding shift register output is not received When the pulse is enabled, the operating state is switched to the disable mode.

In an embodiment of the invention, the controller further extracts a plurality of display materials from the image data stream, and each of the driving channels accesses the enabled mode in the enabling mode. A plurality of display materials are displayed, and access to the plurality of display materials is prohibited in the disable mode.

In an embodiment of the invention, the controller samples the start pulse signal by using the polarity inversion signal, and generates a sampling signal according to the image, wherein when the sampling signal is at the first level, the controller according to the picture start signal and the start pulse signal The plurality of display materials are extracted from the image data stream, and when the sampling signal is the second level, the controller successively extracts the control information from the image data stream according to the initial pulse signal.

In an embodiment of the invention, when the sampling signal is at the second level, the controller extracts the control information from a blank interval of the image data stream according to the initial pulse signal.

The invention provides a display device comprising a display panel and a plurality of source drivers. The plurality of source drivers are used to drive the display panel, and each of the source drivers includes a controller, a plurality of flip-flops, a plurality of shift registers, and a plurality of drive channels. The controller extracts control information from the image data stream. The plurality of flip-flops are electrically connected in series with each other and receive control information. Each of the flip-flops receives a control bit in the control information and outputs the control bit. The plurality of shift registers are electrically connected in series with each other and are in one-to-one correspondence with the plurality of flip-flops, wherein the plurality of shift registers transfer the enable pulses one by one, and are transmitted During the process of enabling the pulse, each shift register determines whether to output an enable pulse according to the control bit output of the corresponding flip-flop. The plurality of driving channels are in one-to-one correspondence with the plurality of shift registers, wherein each driving channel switches the operating state to enable according to the enabled pulse of the corresponding shift register output mode Or disable mode.

Based on the above, the source driver of the embodiment of the present invention uses the control information captured from the image data stream to cause each drive channel in the source driver to determine whether to allow access to the display data according to the corresponding control bit. The display device of the embodiment of the present invention does not need to use the setting pin of the source driver to set the number of available driving channels, thereby reducing the influence of the routing of the setting pin on the source driver, and increasing Compatibility between the panel drive circuit and the display panel.

The above described features and advantages of the present invention will be more apparent from the following description.

The source driver proposed by the embodiment of the present invention uses the control information from the image stream to adjust the operation state of each driving channel, so that the display device applying the source driver has higher compatibility and facilitates display. Modular integrated design of the device. In addition, wherever possible, the elements and/

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention. Referring to FIG. 1 , the display device 100 includes a timing controller 110 , a plurality of source drivers 120_1 120 120 — n , a plurality of gate drivers 130_1 130 130 — m , and a display panel 10 . The timing controller 110 generates a plurality of control signals to respectively control the operation timings of the source drivers 120_1~120_n and the gate drivers 130_1~130_m, and output the image data stream DS to the source driver. 120_1~120_n.

The source drivers 120_1~120_n are electrically connected to the timing controller 110 and the display panel 10. In addition, the source drivers 120_1~120_n convert the display data in the image data stream DS into a pixel voltage, and output the pixel voltage to a data line in the display panel 10, so that the display panel 10 displays corresponding data. Image screen. The gate drivers 130_1~130_m are electrically connected to the timing controller 110 and the display panel 10. In addition, the gate drivers 130_1~130_m sequentially output the scan signals to the scan lines in the display panel 10 according to the corresponding control signals, thereby driving the pixels on the scan lines.

In practical applications, the control signals generated by the timing controller 110 include a picture start signal STV, a start pulse signal TP, and a polarity inversion signal POL. The start signal STV is the start signal of each image frame, the start pulse signal TP is the latch signal of the display data, and the polarity inversion signal POL is the control signal for controlling the polarity of the display panel. .

In detail, the source drivers 120_1~120_n will latch the display data in the image data stream according to the start pulse signal TP. For example, the source drivers 120_1~120_n sequentially latch the display data of the series according to the rising edge of the start pulse signal TP, and generate parallel display data according to the falling edge of the start pulse signal TP, and further A display data is converted to a pixel voltage. In addition, in the process of converting the display data into the pixel voltage, the source drivers 120_1~120_n further adjust the voltage polarity of the pixel voltage according to the polarity inversion signal POL.

In order to further illustrate the present embodiment, FIG. 2 is a schematic diagram of a display device in accordance with another embodiment of the present invention. 2, taking the source driver 220_1 as an example, the source driver 220_1 includes a controller 222, a plurality of flip-flops 224_1~224_i, a plurality of shift registers 226_1~226_i, a plurality of drive channels 228_1~228_i, and Multiple level shifters LS_1~LS_i. In a preferred embodiment, the source driver 220_1 can include, for example, 171 drive channels, and each drive channel includes six output pins. That is, in a preferred embodiment, the output pin of the source driver 220_1 can be, for example, 1026.

The controller 222 extracts the control information CI and the plurality of display materials D_1~D_j from the image data stream DS. The flip-flops 224_1~224_i are electrically connected in series with each other, wherein the flip-flops 224_1~224_i pass the plurality of control bits CB_1~CB_i in the control information CI one by one, and output the control bits CB_1~CB_i in parallel. For example, if the source driver 220_1 includes 171 drive channels, the control information CI will include 171 control bits, and the source driver 220_1 at this time will correspondingly include 171 flip-flops and 171 shift registers. For control of 171 drive channels.

The shift registers 226_1~226_i are electrically connected in series with each other and are in one-to-one correspondence with the flip-flops 224_1~224_i. In addition, the shift registers 226_1~226_i pass the enable pulses EP one by one, and in the process of transmitting the enable pulses EP, each shift register determines whether or not according to the control bits output by the corresponding flip-flops. The output enable pulse EP. The drive channels 228_1~228_i are in one-to-one correspondence with the shift registers 226_1~226_i. Wherein, each of the drive channels 228_1~228_i will be temporarily stored according to the corresponding shift The enable pulse EP of the output of the device switches the operating state to the enable mode or the disable mode. In detail, each of the drive channels 228_1~228_i detects whether the corresponding enable pulse EP of the shift register output is received, and switches the operation state to the enable mode or disables according to the detection result. Mode to determine whether to allow access to display data D_1~D_j.

For example, taking the driving channel 228_1 as an example, when the control bit CB_1 output by the flip-flop 224_1 is logic 1, the shift register 226_1 will receive the enable pulse EP from the controller 222, and then The control bit CB_1 of the logic 1 outputs the enable pulse EP to the drive channel 228_1, and passes the enable pulse EP to the next stage shift register 226_2. At this time, the drive channel 228_1 will receive the enable pulse EP and accordingly switch the operational state to the enable mode. Therefore, the drive channel 228_1 will allow access to the display material D_1~D_j to convert the corresponding display material into a pixel voltage and output the pixel voltage to the display panel 10.

On the other hand, taking the drive channel 228_2 as an example, the shift register 226_2 will receive the enable pulse EP from the shift register 226_1 and transfer the enable pulse EP to the next stage shift register. In addition, when the control bit CB_2 outputted by the flip-flop 224_2 is logic 0, the shift register 226_2 will not output the enable pulse EP to the drive channel 228_2 according to the control bit CB_2 having the logic 0. In other words, when control bit CB_2 is logic 0, shift register 226_2 simply bypasses enable pulse EP to the next stage shift register. At this time, the drive channel 228_2 will not be able to receive the enable pulse EP output by the corresponding shift register 226_2, and accordingly switch the operation state to the disable mode. Therefore, the drive channel 228_2 will prohibit the display of access to data D_1~D_j.

In other words, in practical applications, if the source driver 220_1 includes 171 driving channels, the source driver 220_1 can control the operating state of each driving channel one by one according to the 171 control bits, thereby causing the source driver 220_1 to be used. The number of output pins corresponds to the size of the display panel 20. For example, if the driving channel 228_2 in the source driver 120_1 is not required to be used according to the size of the display panel 20, that is, the driving channel 228_2 does not need to be electrically connected to the data line in the display panel 20, the source driver 120_1 will be available at this time. Control bit CB_2 sets drive channel 228_2 to the disable mode.

In addition, in the embodiment, the source driver 220_1 also includes the level shifters LS_1 LS LS_i. The level shifters LS_1 to LS_i are in one-to-one correspondence with the flip-flops 224_1 to 224_i. In addition, each of the quasi-shifters determines whether to generate the disable voltage V_d according to the control bit outputted by the corresponding flip-flop to turn off the output buffer in the corresponding drive channel.

For example, taking the driving channel 228_1 and the driving channel 228_2 as an example, when the control bit CB_1 output by the flip-flop 224_1 is logic 1, the level shifter LS_1 does not generate the disable voltage V_d to drive the channel. The output buffer in 228_1 works fine. Conversely, when the control bit CB_2 output by the flip-flop 224_2 is logic 0, the level shifter LS_1 will generate the disable voltage V_d to cause the output buffer in the drive channel 228_2 to be further turned off.

In detail, when the drive channel 228_2 is operated in the disable mode, the drive The latch in the active channel 228_2 will be disabled from receiving the enable pulse EP from the shift register 226_2, thereby rendering the drive channel 228_2 unable to access the display data D_1~D_j. In addition, in order to ensure that the driving channel 228_2 can be maintained in the disable mode, the embodiment further utilizes the disable voltage V_d output by the level shifter LS_2 to turn off the output buffer in the driving channel 228_2.

As described above, in the present embodiment, the source driver 220_1 uses the controller 222 to extract the control information CI and the display data D_1~D_j from the image data stream DS. In detail, the controller 222 samples the start pulse signal TP by using the polarity inversion signal POL, and generates a sampling signal accordingly. Thereby, the controller 222 will determine according to the sampling signal, and the received image data stream DS at this time includes the display data D_1~D_j or the corresponding blank interval. Therefore, the controller 222 can transfer the display materials D_1 to D_j to the drive channels 228_1 to 228_i, and extract the control information CI from the blank section.

Furthermore, FIG. 3 is a timing diagram of signals for explaining a display device according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3 simultaneously, the controller 222 samples the start pulse signal TP according to the rising edge of the pulse PU31 in the polarity inversion signal POL. At this time, the start pulse signal TP corresponding to the rising edge of the pulse PU31 is at a low level, that is, the obtained sampling signal is at the first level, so the controller 222 will determine that the currently transmitted image data stream DS31 is It consists of display data D_1~D_j. In other words, when the sampling signal is at the first level (for example, a low level), the controller 222 can extract a plurality of display data D_1 from the image data stream DS31 according to the picture start signal STV and the start pulse signal TP. D_j.

For example, FIG. 4A is a timing diagram for explaining display data according to an embodiment of the invention. Referring to FIG. 4A, in the present embodiment, each drive channel includes six output pins. Therefore, the timing controller 210 generates a video data stream DS composed of six data strings LV0 LV LV5 according to the clock signal CLK. Furthermore, in this embodiment, each display material includes 8 bits. For example, the display data D_1 can be composed, for example, by data bits R1[0]~R1[7], and the display data D_2 can be, for example, The data bits are composed of G1[0]~G1[7], and so on. In other words, as shown in FIG. 4A, in a data period T41, the controller 222 will extract six display materials from the image data stream DS31. Moreover, if the display device 200 includes six source drivers, and the number of driving channels set in the enable mode in each source driver is 161, between the start pulse TP31 and the start pulse TP32. The timing controller 210 will sequentially transmit 6 ^* 6 ^* 161 display data through 6 ^* 161 data periods.

On the other hand, the controller 222 also samples the start pulse signal TP according to the rising edge of the pulse PU32 in the polarity inversion signal POL. At this time, the start pulse signal TP corresponding to the rising edge of the pulse PU32 is at a high level, that is, the obtained sampling signal is at the second level, so the controller 222 will know that the current image data stream DS32 is corresponding blank. Interval. Moreover, when the sampling signal is at the second level, the controller 222 will retrieve the control information CI from the blank interval. In other words, when the sampling signal is at the second level, the controller 222 extracts the control information CI from the blank interval according to the start pulse signal TP before the next pulse of the polarity inversion signal POL is generated.

For example, FIG. 4B is a timing diagram for explaining a blank interval according to an embodiment of the present invention. Similar to the display material shown in FIG. 4A, in a data period T42, the blank interval of the image data stream corresponds to six pieces of data, and each piece of data consists of eight data bits. In addition, during each data period, the controller 222 extracts a data bit from the blank interval as a control bit in the control information CI. For example, in the data period T42, the controller 222 extracts a data bit CI[0] from the blank interval as a control bit in the control information CI. In other words, as shown in FIG. 3, if the display device 200 includes six source drivers, and each source driver includes 171 drive channels, between the start pulse TP33 and the start pulse TP34, the timing controller 210 will Six control information CIs are sequentially transmitted through 6 ^* 171 data periods, and each control information CI includes 171 control bits. Wherein, as shown in FIG. 4B, in each data period, only one data bit has a message for controlling the information CI.

The foregoing embodiments use the control information in the image data stream to respectively control the operation states of the respective driving channels of the source drivers 220_1~220_n, thereby causing the number of driving channels that can be used in the source drivers 220_1~220_n to be consistent. The size of the display panel 20 is shown. Thereby, compared with the conventional display device, the embodiment not only reduces the influence of the trace of the set foot, but also improves the compatibility between the source drivers 220_1 220 220_n and the display panel 20.

In summary, the source driver of the embodiment of the present invention uses the control information extracted from the image data stream to cause each drive channel in the source driver to determine whether to allow access to the display data according to the corresponding control bit. In addition, the display device of the embodiment of the invention can also be driven without a source. In the case of the device, the timing controller is used to adjust the timing controller to output the idle data to the corresponding drive channel. The display device of the embodiment of the present invention does not need to use the setting pin of the source driver to set the number of available driving channels, thereby reducing the influence of the routing of the setting pin on the source driver, and further Increased compatibility between the source driver and the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧ display panel

100, 200‧‧‧ display devices

110, 210‧‧‧ timing controller

120_1~120_n, 220_1~220_n‧‧‧ source drive

130_1~130_m‧‧‧gate driver

STV‧‧‧ screen start signal

TP‧‧‧start pulse signal

POL‧‧‧ polarity reversal signal

222‧‧‧ Controller

224_1~224_i‧‧‧Factor

226_1~226_i‧‧‧Shift register

228_1~228_i‧‧‧ drive channel

LS_1~LS_i‧‧‧ position shifter

CB_1~CB_i‧‧‧ control bit

CI‧‧‧Control Information

DS, DS31, DS32‧‧‧ image data stream

D_1~D_j‧‧‧Display data

EP‧‧‧Enable Pulse

V_d‧‧‧ disable voltage

PU31, PU32‧‧‧ pulse

TP31~TP34‧‧‧start pulse

CLK‧‧‧ clock signal

LV0~LV5‧‧‧ data string

T41, T42‧‧‧ data period

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a display device in accordance with another embodiment of the present invention.

FIG. 3 is a timing diagram of signals for explaining a display device according to an embodiment of the invention.

4A is a timing diagram for explaining display data according to an embodiment of the invention.

4B is a timing diagram for explaining a blank interval in accordance with an embodiment of the present invention.

20‧‧‧ display panel

200‧‧‧ display device

210‧‧‧ Timing Controller

220_1~220_n‧‧‧Source drive

222‧‧‧ Controller

224_1~224_i‧‧‧Factor

226_1~226_i‧‧‧Shift register

228_1~228_i‧‧‧ drive channel

LS_1~LS_i‧‧‧ position shifter

CB_1~CB_i‧‧‧ control bit

CI‧‧‧Control Information

D_1~D_j‧‧‧Display data

DS‧‧‧ image data stream

EP‧‧‧Enable Pulse

V_d‧‧‧ disable voltage

STV‧‧‧ screen start signal

TP‧‧‧start pulse signal

POL‧‧‧ polarity reversal signal

Claims (14)

A source driver includes: a controller that extracts a control information from an image data stream; a plurality of flip-flops electrically connected to each other and receives the control information, wherein each of the positive and negative Receiving a control bit in the control information and outputting the control bit respectively; the plurality of shift registers are electrically connected in series with each other and corresponding to the flip-flops one-to-one, wherein the The shift register transfers the consistent energy pulses one by one, and in the process of transmitting the enable pulse, each of the shift registers determines whether to output the control bit according to the control bit outputted by the corresponding flip-flop And a plurality of driving channels, one-to-one correspondence with the shift registers, wherein each of the driving channels is based on the corresponding enabled pulse of the shift register output The operating state is switched to the consistent mode or a disabled mode. The source driver of claim 1, further comprising: a plurality of level shifters, one-to-one correspondence with the flip-flops, wherein each of the level shifters is corresponding to The control bit outputted by the flip-flop determines whether an disable voltage is generated to turn off an output buffer of one of the drive channels. The source driver of claim 1, wherein the operational state is switched to the enable mode when the corresponding enable pulse output of the shift register is received, when not received Corresponding shift When the enable pulse is output from the bit register, the operational state is switched to the disable mode. The source driver of claim 1, wherein the controller further extracts a plurality of display materials from the image data stream, and each of the driving channels accesses the displays in the enabling mode. Data, and access to the display materials is prohibited in the disable mode. The source driver of claim 1, wherein the controller samples a start pulse signal by using a polarity inversion signal, and generates a sample signal, wherein when the sample signal is at a first level, The controller extracts a plurality of display materials from the image data stream according to a picture start signal and the start pulse signal. When the sample signal is at a second level, the controller is based on the start pulse signal. The control information is successively extracted from the image data stream. The source driver of claim 5, wherein when the sampling signal is the second level, the controller extracts the control information from a blank interval of the image data stream according to the starting pulse signal. The source driver of claim 5, wherein the picture start signal, the start pulse signal and the polarity inversion signal are generated by a timing controller. A display device includes: a display panel; and a plurality of source drivers for driving the display panel, and each of the source drivers includes: a controller for extracting a control resource from an image data stream The plurality of flip-flops are electrically connected to each other and receive the control information, wherein each of the flip-flops respectively receives a control bit in the control information and outputs the control bit; The shift register is electrically connected in series with each other and has a one-to-one correspondence with the flip-flops, wherein the shift register transfers the uniform energy pulse one by one, and in the process of transmitting the enable pulse Each of the shift registers determines whether to output the enable pulse according to the corresponding control bit output by the flip-flop; and a plurality of drive channels, one-to-one with the shift registers Correspondingly, each of the driving channels switches an operating state to a consistent energy mode or a disabled mode according to the enabled pulse outputted by the corresponding shift register. The display device of claim 8, wherein each of the source drivers further comprises: a plurality of level shifters, one-to-one correspondence with the flip-flops, wherein each of the levels The shifter determines whether to generate a disable voltage according to the corresponding control bit outputted by the flip-flop to close an output buffer of one of the drive channels. The display device of claim 8, wherein the operating state is switched to the enabling mode when the corresponding enabling pulse of the shift register is received, when the receiving mode is not received When the enable pulse output by the shift register is corresponding, the operation state is switched to the disable mode. The display device of claim 8, wherein the controller further extracts a plurality of display materials from the image data stream, and each of the driving channels accesses the display materials in the enabling mode. And in the disable mode prohibits access to the display materials. The display device of claim 8, wherein the controller samples a start pulse signal by using a polarity inversion signal, and generates a sample signal, wherein when the sample signal is at a first level, the The controller extracts a plurality of display materials from the image data stream according to a picture start signal and the start pulse signal. When the sample signal is at a second level, the controller continues according to the start pulse signal. The control information is extracted from the image data stream. The display device of claim 12, wherein when the sampling signal is the second level, the controller extracts the control information from a blank interval of the image data stream according to the starting pulse signal. The display device of claim 12, further comprising: a timing controller, generating the picture start signal, the start pulse signal and the polarity inversion signal.