TW201428762A - Memory structure with reduced number of reflected signals - Google Patents
Memory structure with reduced number of reflected signals Download PDFInfo
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- TW201428762A TW201428762A TW102100168A TW102100168A TW201428762A TW 201428762 A TW201428762 A TW 201428762A TW 102100168 A TW102100168 A TW 102100168A TW 102100168 A TW102100168 A TW 102100168A TW 201428762 A TW201428762 A TW 201428762A
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Abstract
Description
本發明是有關於一種降低反射訊號的記憶體結構，尤指一種可於處理單元配合各記憶體作訊號傳輸時，利用反射訊號吸收單元吸收相關之反射訊號，以降低訊號傳輸時之反射訊號，而達到使各記憶體可穩定運作之功效者。
The present invention relates to a memory structure for reducing a reflected signal, and more particularly to a method for absorbing a correlated reflected signal by a reflected signal absorbing unit when the processing unit cooperates with each memory for signal transmission, so as to reduce the reflected signal during signal transmission. And to achieve the effect of making each memory stable operation.
按，一般習用之記憶體結構，通常係由一處理器、多數與處理器連接之記憶體、以及一設於各記憶體並接端前端之訊號反射器。
然，以上述之結構而言，仍無法有效降低訊號傳輸時之反射訊號，進而嚴重影響系統之整體運作；且以習用欲進行多記憶體之整合時（例如：將32位元之記憶體整合為64位元），係將至少兩個晶片加以共接，而共接時係將多個記憶體之位址區與控制區加以連接，如此，不但會導致線路佈局之複雜度增加，更會大幅提高線路之佈局層數。
有鑑於此，本案之發明人特針對前述習用發明問題深入探討，並藉由多年從事相關產業之研發與製造經驗，積極尋求解決之道，經過長期努力之研究與發展，終於成功之開發出本發明「降低反射訊號的記憶體結構」，藉以改善習用之種種問題。
Generally, the conventional memory structure is usually a processor, a plurality of memories connected to the processor, and a signal reflector disposed at the front end of each memory.
However, with the above structure, it is still unable to effectively reduce the reflected signal during signal transmission, thereby seriously affecting the overall operation of the system; and when it is used for integration of multiple memories (for example, integrating 32-bit memory) For 64-bit units, at least two chips are connected in common, and the address areas of the plurality of memories are connected to the control area when connected in common, which not only leads to an increase in the complexity of the line layout, but also increases Significantly increase the number of layout layers of the line.
In view of this, the inventors of this case have intensively discussed the above-mentioned problems of conventional inventions, and actively pursued solutions through years of experience in R&D and manufacturing of related industries. After long-term efforts in research and development, they have finally succeeded in developing this book. Invented "reducing the memory structure of the reflected signal" to improve the problems of the application.
本發明之主要目之係在於，可於處理單元配合各記憶體作訊號傳輸時，利用反射訊號吸收單元吸收相關之反射訊號，以降低訊號傳輸時之反射訊號，而達到使各記憶體可穩定運作之功效。
為達上述之目之，本發明係一種降低反射訊號的記憶體結構，其包含有：一處理單元；一與處理單元連接之總線路單元；多數與總線路單元連接之記憶體；以及一設於總線路單元末端處之反射訊號吸收單元。
於本發明之一實施例中，各記憶體係分別包含有與總線路單元連接之位址線路、命令線路及控制線路。
於本發明之一實施例中，各記憶體係分別單獨與總線路單元並接。
於本發明之一實施例中，各記憶體係設置於一晶片上而形成一記憶體晶片，而該記憶體晶片係與總線路單元連接。
於本發明之一實施例中，該總線路單元之前端處係可設置有另一反射訊號吸收單元。
於本發明之一實施例中，該反射訊號吸收單元係可為電阻。
於本發明之一實施例中，該處理單元、總線路單元、各記憶體及反射訊號吸收單元於進行電路佈局時，係於處理單元與總線路單元之間設有至少二位址/控制/命令區，而各記憶體則可分別設於各位址/控制區兩側，且該總線路單元與各記憶體之間係設有接地區，並於該處理單元與各記憶體之間設有多數電源線。
The main purpose of the present invention is to use the reflected signal absorbing unit to absorb the relevant reflected signal when the processing unit cooperates with each memory for signal transmission, so as to reduce the reflected signal during signal transmission, so as to stabilize each memory. The effectiveness of the operation.
In order to achieve the above, the present invention is a memory structure for reducing reflected signals, comprising: a processing unit; a total line unit connected to the processing unit; a plurality of memory connected to the total line unit; and a setting A reflected signal absorption unit at the end of the main line unit.
In an embodiment of the invention, each memory system includes an address line, a command line, and a control line connected to the total line unit.
In an embodiment of the invention, each memory system is separately connected to the total line unit.
In an embodiment of the invention, each memory system is disposed on a wafer to form a memory chip, and the memory chip is connected to the total line unit.
In an embodiment of the invention, another reflective signal absorbing unit may be disposed at the front end of the main line unit.
In an embodiment of the invention, the reflected signal absorbing unit can be a resistor.
In an embodiment of the present invention, the processing unit, the total line unit, each of the memory and the reflected signal absorbing unit are provided with at least two addresses/controls between the processing unit and the total line unit when performing circuit layout. a command area, and each memory can be respectively disposed on each side of the address/control area, and a connection area is provided between the total line unit and each memory, and is disposed between the processing unit and each memory. Most power cords.
1．．．處理單元1. . . Processing unit
2．．．總線路單元2. . . Total line unit
3．．．記憶體3. . . Memory
30．．．記憶體晶片30. . . Memory chip
31．．．位址線路31. . . Address line
32．．．命令線路32. . . Command line
33．．．控制線路33. . . Control line
4、4a．．．反射訊號吸收單元4, 4a. . . Reflected signal absorption unit
5．．．位址/控制區5. . . Address/control area
6．．．接地區6. . . Connected area
7．．．電源線7. . . power cable
第１圖，係本發明第一實施例之示意圖。
第２圖，係本發明第二實施例之示意圖。
第３圖，係本發明之電路佈局示意圖。
Fig. 1 is a schematic view showing a first embodiment of the present invention.
Fig. 2 is a schematic view showing a second embodiment of the present invention.
Figure 3 is a schematic diagram of the circuit layout of the present invention.
請參閱『第１圖』所示，係本發明第一實施例之示意圖。如圖所示：本發明係一種降低反射訊號的記憶體結構，其至少包含有一處理單元１、一總線路單元２、多數記憶體３以及一反射訊號吸收單元４所構成。
上述所提之處理單元１係作為各記憶體３之控制中心。
該總線路單元２係與處理單元１連接。
各記憶體３係與總線路單元２連接，而各記憶體３係分別包含有與總線路單元２連接之位址線路３１、命令線路３２及控制線路３３，且各記憶體３係分別單獨與總線路單元２並接。
該反射訊號吸收單元４係設於總線路單元２之末端處，而該反射訊號吸收單元４係可為電阻。
當本發明於運用時，係可應用於DRAM、NAND、MRAM、NOR或SRAM等相關領域中，而於處理單元１配合各記憶體３之位址線路３１、命令線路３２及控制線路３３作訊號傳輸時，係可利用反射訊號吸收單元４吸收相關之反射訊號，以降低訊號傳輸時之反射訊號，而達到使各記憶體３可穩定運作之功效。
請參閱『第２圖』所示，係本發明第二實施例之示意圖。如圖所示：本發明除上述第一實施例所提型態之外，更可為本第二實施例之型態，而其所不同之處係在於，各記憶體３係設置於一晶片上而形成一記憶體晶片３０，而該記憶體晶片３０係與總線路單元２連接，且該總線路單元之前端與末端處係可分別設置有一反射訊號吸收單元４、４ａ；藉此，可於處理單元１配合記憶體晶片３０之各記憶體３作訊號傳輸時，係可利用反射訊號吸收單元４、４ａ分別吸收相關之反射訊號，以降低訊號傳輸時之反射訊號，而達到使各記憶體３可穩定運作之功效。
請參閱『第３圖』所示，係本發明之電路佈局示意圖。如圖所示：當本發明之處理單元１、總線路單元２、各記憶體３及反射訊號吸收單元４於進行電路佈局時，係於處理單元１與總線路單元２之間設有至少二位址/控制/命令區５，而各記憶體３則可分別設於各位址/控制/命令區５兩側，且該總線路單元２與各記憶體３之間係設有接地區６，並於該處理單元１與各記憶體３之間設有多數電源線７；如此，當本發明作多記憶體３之整合時（例如：將32位元之記憶體整合為64位元），可達到易於進行線路佈局以及減少佈局層數之效果。
綜上所述，本發明降低反射訊號的記憶體結構可有效改善習用之種種缺點，可於處理單元配合各記憶體作訊號傳輸時，利用反射訊號吸收單元吸收相關之反射訊號，以降低訊號傳輸時之反射訊號，而達到使各記憶體可穩定運作之功效；進而使本發明之産生能更進步、更實用、更符合消費者使用之所須，確已符合發明專利申請之要件，爰依法提出專利申請。
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍；故，凡依本發明申請專利範圍及發明說明書內容所作之簡單之等效變化與修飾，皆應仍屬本發明專利涵蓋之範圍內。
Please refer to FIG. 1 for a schematic view of a first embodiment of the present invention. As shown in the figure, the present invention is a memory structure for reducing reflection signals, which comprises at least one processing unit 1, a total line unit 2, a majority of memory 3, and a reflected signal absorbing unit 4.
The processing unit 1 mentioned above is used as the control center of each memory 3.
The total line unit 2 is connected to the processing unit 1.
Each memory 3 is connected to the main line unit 2, and each memory 3 includes an address line 31, a command line 32, and a control line 33 connected to the main line unit 2, and each memory 3 is separately and separately The total line unit 2 is connected in parallel.
The reflected signal absorption unit 4 is disposed at the end of the total line unit 2, and the reflected signal absorption unit 4 is a resistor.
When the present invention is applied, it can be applied to related fields such as DRAM, NAND, MRAM, NOR or SRAM, and the processing unit 1 cooperates with the address line 31, the command line 32 and the control line 33 of each memory 3 as a signal. When transmitting, the reflected signal absorbing unit 4 can absorb the relevant reflected signal to reduce the reflected signal during signal transmission, so as to achieve stable operation of each memory 3.
Please refer to FIG. 2, which is a schematic view of a second embodiment of the present invention. As shown in the figure, the present invention can be in the form of the second embodiment in addition to the above-mentioned first embodiment, and the difference is that each memory 3 is disposed on a wafer. Forming a memory chip 30, and the memory chip 30 is connected to the main line unit 2, and a reflective signal absorbing unit 4, 4a is respectively disposed at the front end and the end of the main line unit; When the processing unit 1 cooperates with the memory 3 of the memory chip 30 for signal transmission, the reflected signal absorbing unit 4, 4a can respectively absorb the relevant reflected signals to reduce the reflected signal during the signal transmission, thereby achieving the memory. Body 3 can work stably.
Please refer to FIG. 3, which is a schematic diagram of the circuit layout of the present invention. As shown in the figure, when the processing unit 1, the total line unit 2, the memory 3 and the reflected signal absorbing unit 4 of the present invention perform circuit layout, at least two are disposed between the processing unit 1 and the total line unit 2. Address/control/command area 5, and each memory 3 can be respectively disposed on both sides of the address/control/command area 5, and the connection area 6 is provided between the total line unit 2 and each memory 3. And a plurality of power lines 7 are disposed between the processing unit 1 and each of the memories 3; thus, when the present invention is integrated into the multi-memory 3 (for example, integrating 32-bit memory into 64-bit elements), It is easy to layout and reduce the number of layout layers.
In summary, the memory structure of the present invention for reducing the reflected signal can effectively improve various shortcomings of the conventional use. When the processing unit cooperates with each memory for signal transmission, the reflected signal absorption unit absorbs the relevant reflected signal to reduce the signal transmission. Reflecting the signal at the time, and achieving the effect of making the memory stable operation; thereby making the invention more progressive, more practical, and more in line with the needs of the consumer, indeed meeting the requirements of the invention patent application, File a patent application.
However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the invention are modified. All should remain within the scope of the invention patent.
1．．．處理單元1. . . Processing unit
2．．．總線路單元2. . . Total line unit
3．．．記憶體3. . . Memory
31．．．位址線路31. . . Address line
32．．．命令線路32. . . Command line
33．．．控制線路33. . . Control line
4．．．反射訊號吸收單元4. . . Reflected signal absorption unit
Claims (7)
一處理單元；
一總線路單元，係與處理單元連接；
多數記憶體，係與總線路單元連接；以及
一反射訊號吸收單元，係設於總線路單元之末端處。A memory structure for reducing reflected signals, comprising:
a processing unit;
a total line unit connected to the processing unit;
Most of the memory is connected to the main line unit; and a reflected signal absorbing unit is provided at the end of the main line unit.
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| TW102100168A TWI509626B (en) | 2013-01-03 | 2013-01-03 | Memory structure with reduced number of relfected signals |
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| Application Number | Priority Date | Filing Date | Title |
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| TW102100168A TWI509626B (en) | 2013-01-03 | 2013-01-03 | Memory structure with reduced number of relfected signals |
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| TW201428762A true TW201428762A (en) | 2014-07-16 |
| TWI509626B TWI509626B (en) | 2015-11-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI791657B (en) * | 2018-11-02 | 2023-02-11 | 森富科技股份有限公司 | configuration memory structure |
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| US20100327902A1 (en) * | 2009-06-25 | 2010-12-30 | Uniram Technology, Inc. | Power saving termination circuits for dram modules |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI791657B (en) * | 2018-11-02 | 2023-02-11 | 森富科技股份有限公司 | configuration memory structure |
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