TW201428474A - Power management methods and systems using the same - Google Patents

Abstract

Power management methods for use in a system operated in a working state are provided. The system includes a central processing unit (CPU), a chipset and a basic input output system (BIOS). First, a specific processor state configuration for the CPU is provided. When detecting a command that configures the CPU to the configured specific processor state, the chipset triggers a system management interrupt to the CPU such that the CPU enters a system management mode, and then the system enters a dedicated system power saving state for power saving.

Description

Power management method and related system

The present invention relates to a power management method and system thereof, and more particularly to a power management method that can efficiently enter a power saving state.

For power saving purposes, general systems, especially portable devices such as notebook computers, use the Advanced Configuration and Power Interface (ACPI) standard to manage their power supplies. ACPI defines various states, including device state D (Device), system state S (Sleeping), and processing unit state C (CPU). The system state defines the overall power state of the computer system. The device state defines the power state of each device in the computer system, and the state of the processing unit is defined as the power state of the central processing unit. The processing unit status may have four different levels, for example, C0, C1, C2, and C3. When the system is in operation, the operating system drives the central processing unit to an appropriate state according to the current usage state of the central processing unit. For example, the system is generally in a working state (S0 state), and when the system is idle for a period of time, the operating system drives the central processing unit to an appropriate power saving state according to the current state of use of the central processing unit, even in terms of the system. It can also enter the power-saving state of the more power-saving system S1 to S5, where S3 saves power compared to S1, S4 saves power compared to S3, and so on. Although the S3 state is more power efficient than the S1 state, the time it takes to return to the normal operating state is relatively long.

Conventionally, when the system is idle for a period of time, the system automatically enters a preset power state to save power. In recent years, handheld devices, such as mobile phones, smart phones, personal digital assistants, etc., have become more sophisticated and more functional. Due to the convenience of these devices, these devices have also become one of the necessities of life. With the change of usage habits, users are increasingly hoping that devices, such as computer systems and handheld devices, can always be connected forever. (Always On Always Connected) capabilities are therefore more important for system power management.

However, although ACPI provides a power management mechanism for various power saving states of the operating system, such as a C state, a P state, etc., the overall power saving of a system such as a portable computer is still insufficient, and power saving is still not effective.

In view of the above, it is an object of the present invention to provide a power management method and system therefor.

The embodiment of the invention provides a power management method suitable for a system in a working state, the system comprising a central processing unit, a chip set and a basic input output system. The method includes the following steps. First, a specific processing unit state setting is provided for one of the central processing units. When the chipset detects an instruction to set the central processing unit to a specific processing unit state, triggering a system management interrupt signal to the central processing unit, causing the central processing unit to enter a system management mode, and causing the system to enter a designated system Power saving status.

Another embodiment of the present invention provides a system in which the system is in an active state, including at least a central processing unit, a basic input/output system, and a chip set. The chipset is coupled to the central processing unit and the basic input/output system for detecting when the central processing unit is set to one of the specific processing unit states, triggering a system management interrupt signal to the central processing unit, causing the central processing unit to enter A system management mode that allows the system to enter a specified system power saving state.

The above method of the present invention can be recorded in physical media through code. When the code is loaded and executed by the machine, the machine becomes the means for practicing the invention.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

100‧‧‧ system

110‧‧‧Central Processing Unit

120‧‧‧chipset

122‧‧‧Power Management Unit

124‧‧‧Scratch

SMI#‧‧‧System Management Interrupt Signal

130‧‧‧Basic input and output system

132‧‧‧System Management Interrupt Handler

S202, S204, S206, S208‧‧‧ execution steps

S302, S304, ..., S312‧‧‧ steps

Figure 1 is a schematic diagram showing the system architecture in accordance with an embodiment of the present invention.

2 is a flow chart showing a power management method according to an embodiment of the present invention.

Figure 3 is a flow chart showing a power management method in accordance with another embodiment of the present invention.

The embodiment of the present invention provides a power management method and a device thereof, which can detect that a processing unit state of a central processing unit (CPU) is set to a specific processing unit state (for example, a most power-saving C3 state). When a system management interrupt (SMI) signal is triggered, the central processing unit is driven into a system management mode (SMM), which in turn causes the central processing unit to perform a specific portion of the basic input/output system (BIOS). The system management interrupt handler (SMI handler routine) is used to set the system to the specified system power saving state to save power.

Figure 1 shows a system 100 in accordance with an embodiment of the present invention. For example, the system 100 can be a computer system or a portable device, such as a notebook computer, an ultrabook, such as a mobile phone, a smart phone, a personal digital assistant (PDA), etc., but is not limited thereto. this. The system 100 can operate in a working state (such as the S0 state of the ACPI standard) and multiple system power saving states (such as the S1~S5 state of the ACPI standard). In the present embodiment, when operating in an active state, the system 100 is in a state of normal operation. As shown in FIG. 1, computer system 100 includes at least a central processing unit (CPU) 110, a chipset 120, and a basic input/output system (BIOS) 130. The central processing unit 110 can be set to different processing unit states according to the current usage status when the computer system 100 is in an operating state (ie, the S0 state), for example, a C0-Cx state, where the Cx state is the central processing unit. The most power-saving state of 110 is to save power consumption of the central processing unit 110. In other words, depending on the design of the different central processing units, the most power-saving Cx state will vary.

The chipset 120 is coupled to the central processing unit 110 and the BIOS 130 for performing the power management method in accordance with the present invention. The chipset 120 can be further provided with a power management unit 122 and a register 124. The power management unit 122 of the chipset 120 can send control signals to the central processing unit 110, so that the central processing unit 110 can enter different processes according to the current usage state. The cell state (C state), and the register 124 is used to store a particular processing unit state setting. In this embodiment, the power management unit 122 can send a control signal to the central processing unit 110 to set the power state of the central processing unit 110 to a specified processing unit state. In addition, when the power management unit 122 detects that the power state of the central processing unit 110 is set to a specific processing unit state in the scratchpad, the chipset 120 triggers a system management interrupt signal SMI# to the center. The unit 110 drives the central processing unit 110 into a system management mode (SMM). For example, when the operating system detects that the current operating state of the central processing unit 110 is in compliance with a particular processing unit state (eg, C3 state), the operating system issues an instruction to set the central processing unit 110 to a particular processing unit state. To the chipset 120, the chipset 120 can send control messages/signals to the central processing unit 110 in response to the command, causing the central processing unit 110 to enter the designated processing unit state.

The basic input/output system 130 includes a system management interrupt handler (SMI handler routine) 132 of the corresponding system management mode, which can be executed by the central processing unit 110 entering the management mode 130 through a system management interrupt handler (SMI handler).

Fig. 2 is a flow chart showing a power management method according to an embodiment of the present invention. Please refer to both Figure 1 and Figure 2. The power management method according to an embodiment of the present invention can be applied to the system 100 of Fig. 1.

First, as step S202, a specific processing unit state setting of one of the central processing units 110 is provided. For example, if the processing unit status of the central processing unit 110 can be set to the C0-C3 state, the specific processing unit status setting can be a more power-saving C2 state or a C3 state that is the most power-saving, wherein the specific processing unit The state settings can be pre-stored in the register 124 of the chipset 120. It is worth mentioning that in different embodiments, the central processing unit can be set to the C0-Cx state according to different designs, and the Cx state is the most power-saving state of the central processing unit. In some embodiments, the register 124 storing the particular processing unit state settings may also need not be disposed within the wafer set 120, and may be additionally disposed in any system unit or storage space accessible to the wafer set 120. In other words, wafer set 120 can be derived from scratchpad 124 for a set value for a particular processing unit state. This setting can be predefined by the user or preset. In an embodiment, the specific processing unit status is the most power saving processing unit status of the central processing unit 110. For example, when the processing unit status of the central processing unit 110 is in the C0-C3 state, the state of the most power saving processing unit is C3 status.

When the system 100 (eg, a portable computer) is in an active state (S0 state) and is idle for a period of time, the operating system sends a request to the central processing unit 110 to enter a specified processing unit state (eg, C1-C3 state, etc.) An instruction of the power saving state) causes the central processing unit 110 to enter the specified processing unit state. In an embodiment, the operating system can know which processing unit states are supported by the system 100 through the _CST object defined in the ACPI. (For example: support C1, C2, and C3 states or only C1 and C2 states) and which scratchpads are used to trigger the processing unit state.

Next, in step S204, the chipset 120 detects an instruction to set the central processing unit 110 to a specific processing unit state, triggering a system management interrupt signal SMI# to the central processing unit 110. In some embodiments, the chipset 120 detects that an instruction to set the central processing unit 110 to a specific processing unit state is through an input/output interrupt capture (IO trap) mode, wherein the input/output interrupt capture (IO trap) The manner of detecting a particular output of the definition and trapping to a particular output indicates that the operating system requires the central processing unit 110 to enter a particular processing unit state.

After the central processing unit 110 receives the system management interrupt signal SMI#, in step S206, the central processing unit 110 enters into a system management mode (SMM) according to the system management interrupt signal SMI# from the current mode, and after entering the system management mode. A system management interrupt handler 132 that sends a control message to the basic input output system 130 to execute the corresponding system management mode in the basic input output system 130. The central processing unit 110 executes the system management interrupt processing program 132 of the corresponding system management mode in the basic input/output system 130 through a system management interrupt processing program.

Thus, in step S208, system management interrupt handler 132 can drive system 100 into a specified system power saving state (eg, S3 state). In this embodiment, when the central processing unit 110 executes the system management interrupt processing program 132 of the present case, the central processing unit 110 executes a certain piece of code in the basic input/output system 130, so that the central processing unit 110 can The system power state is set to a specific power saving state (for example, S3 state). Specifically, the system management interrupt processing program is a program code of a corresponding system management mode preset in the basic input/output system 130. The program code mainly stores the necessary context and performs a series of defined operations. To store some status of the current system and the register settings, and finally forward an instruction to enter the specified system power saving state to the chipset 120 to drive the system 100 into a specified system power saving state (eg, S3 state), Turn off some unnecessary power to save power.

After the system 100 enters the specified system power saving state, if a peripheral device sends an interrupt event or a bus master request event, a response signal may be generated corresponding to the response indication, thereby causing the system to 100 is saved by the specified system power saving state The new reply is the working status (S0). The basic input output system 130 can re-restore the content and process the interrupt event or bus master request event by the operating system.

It is worth mentioning that the power management mode of the conventional system is that when the central processing unit is the power saving state of the processing unit (usually the most power-saving state of the processing unit), and the system is idle for a period of time, the central processing unit needs to After the power saving state of the processing unit is restored to the working state of the processing unit C0, the system can enter the system power saving state (for example, the S3 state) from the system working state S0. However, in the case where the central processing unit is the power saving state of the processing unit (usually the most power-saving state of the processing unit), and the system is idle for a period of time, the central processing unit is driven to enter by triggering a system management interrupt (SMI) signal. System Management Mode (SMM), which in turn allows the system to enter the system power-saving state directly (for example, the S3 state).

Some embodiments are listed below to assist in explaining the details of the system management method according to the present invention, but the present invention is not limited thereto. Figure 3 is a flow chart showing a power management method in accordance with another embodiment of the present invention. Please refer to both Figure 1 and Figure 3. The system management method according to the present embodiment can be applied to the system 100. In this embodiment, it is assumed that the system 100 is a portable device, the working state of the system 100 is the S0 state, and the system power saving state specified by the system 100 is the S3 state, and the processing unit state of the central processing unit 110 can be The C0-C3 state is set, and the set value of the specific processing unit state of the register 124 is set to the state of the most power-saving processing unit of the central processing unit 110, that is, the C3 state.

Assuming that system 100 is in the S0 state and the processing unit state of central processing unit 110 is in the C0 state, after a period of inactivity, the operating system will send an instruction to request central processing unit 110 to enter a specified processing unit state C1-C3 state.

In step S302, the chipset 120 detects the processing unit state setting command of the central processing unit 110 and determines whether the command is an instruction to set the central processing unit 110 to the most power-saving C3 state, as in step S304.

In this embodiment, the chipset 120 can continuously detect the read cycle of each input/output port (IO port) or input/output port through the input/output interrupt capture mode and capture a specific input/output port or input/output port. The operation of the read cycle indicates that a command to set the central processing unit 110 to the most power-saving state of the power supply has been received.

If the processing unit state setting command of the central processing unit 110 is not an instruction to set the central processing unit 110 to the most power-saving C3 state (NO in step S304), the chipset 120, the central processing unit 110 is set to the processing unit state of the corresponding instruction (step S306), and returns to step S302 to continue detecting the processing unit status setting instruction of the central processing unit 110. For example, when it is detected that the processing unit state setting command of the central processing unit 110 is an instruction to set the central processing unit 110 to the C1 or C2 state, the chipset 120 can correspondingly set the central processing unit to the C1 or C2 state. .

If the processing unit state setting command of the central processing unit 110 is to be central When the processing unit 110 is set to the instruction of the most power-saving C3 state (YES in step S304), the chipset 120 triggers a system management interrupt signal SMI# to the central processing unit 110 (step S308), so that the central processing unit 110 is managed according to the system. The interrupt signal SMI# enters the system management mode, and executes the system management interrupt processing program 132 of the corresponding system management mode in the basic input/output system 130 (step S310). The system management interrupt handler 132 will store the necessary contexts, perform a series of defined operations to store some of the current system status and register settings, and finally forward an instruction to enter the specified system power saving state - S3 state. To the chipset 120, the system 100 is driven into the S3 state, turning off some unnecessary power (step S312).

After the system enters the S3 state, if a peripheral device sends an interrupt event or When a bus master requests an event, the basic input output system 130 can re-restore the content and transfer control back to the operating system, causing the system 100 to return from the S3 state to the S0 state, which is handled by the operating system. The row master requests an event.

In summary, the power management method and system of the system according to the present invention are When the central processing unit is ready to enter a specific processing unit state such as the C2 state or the most power-saving processing unit state, the chip group can be returned to the C0 state, and the chip group can receive the central processing unit through the input/output interrupt capture mode. The instruction of the specific processing unit state is transferred from the operating system to the basic input/output system through the system management interrupt signal, so that the basic input/output system can forward the system to set the system to the specified system power saving state, for example, the S3 state. The state of the system is set to the specified system power saving state, which can further achieve the purpose of power saving.

The method of the present invention, or a specific type or part thereof, may be in the form of a code Included in physical media, such as floppy disks, CDs, hard drives, or any other machine readable (such as computer readable) storage media, where the code is loaded and executed by a machine, such as a computer, The machine becomes a device for participating in the present invention. The method and apparatus of the present invention can also be transmitted in a coded form through some transmission medium such as a wire or cable, an optical fiber, or any transmission type. Wherein, when the code is received, loaded and executed by a machine, such as a computer, the machine becomes a device for participating in the present invention. When implemented in a general purpose processor, the code in conjunction with the processor provides a unique means of operation similar to application specific logic.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

S202, S204, S206, S208‧‧‧ execution steps

Claims (16)

A power management method for a system in a working state, the system comprising a central processing unit, a chip set and a basic input/output system, comprising the steps of: providing a specific processing unit state setting of one of the central processing units, The specific processing unit state is a power saving state of the central processing unit; and when the chipset detects that the central processing unit is set to one of the specific processing unit states, triggering a system management interrupt signal to The central processing unit causes the central processing unit to enter a system management mode to bring the system into a designated system power saving state. The power management method of claim 1, wherein the specific processing unit state setting is pre-stored in a register of the chipset. The power management method of claim 1, wherein the specific processing unit status is a state of the most power saving processing unit of the central processing unit. The power management method of claim 1, wherein the specific processing unit state is a C3 state of the ACPI standard. The power management method according to claim 1, wherein the working state is an S0 state, and the specified system power saving state is an S3 state. The power management method according to claim 1, wherein the central processing unit is configured to execute a system management interrupt processing program corresponding to the system management mode in the basic input/output system when entering the system management mode, thereby causing the The system enters the specified system power saving state. The power management method according to claim 6, wherein the central processing unit executes the system management interrupt processing program corresponding to the system management mode in the basic input/output system through a system management interrupt processing program. The power management method of claim 1, wherein the chipset detects that the central processing unit is set to the state of the specific processing unit, and the command is transmitted through an input/output interrupt (IO trap) mode. One action that detects one of the specific outputs and traps to that particular output indicates the state of that particular processing unit. The power management method of claim 1, wherein the chipset enters the specified system power saving state after the power state of the system, and receives an interrupt event or a bus master request At the time of the event, a control message is sent to the central processing unit, causing the central processing unit to revert the system back to the operational state from the designated system power saving state. A system, the system being in an active state, comprising: a central processing unit; a basic input/output system; and a chip set coupled to the central processing unit and the basic input/output system for detecting the central processing When the unit is set to one of the specific processing unit states, a system management interrupt signal is triggered to the central processing unit, causing the central processing unit to enter a system management mode, and the system enters a specified system power saving state. The specific processing unit state is a power saving state of the central processing unit. The system of claim 10, wherein the central processing unit is configured to execute a system management interrupt processing program corresponding to the system management mode in the basic input/output system when entering the system management mode, so that the system enters The specified system saves power. The system of claim 10, wherein the chip set is further provided with a register for storing the specific processing unit state setting. The system of claim 10, wherein the specific processing unit state is the most power saving processing unit state of the central processing unit. The system of claim 10, wherein the working state is an S0 state, and the designated system power saving state is an S3 state. The system of claim 10, wherein the specific processing unit state is a C3 state. The system of claim 10, further comprising a specific input port, wherein the chipset detects that the central processing unit is set to the state of the specific processing unit, and the command is interrupted by an input/output interrupt ( The IO trap method is to detect the specific output of the defined input and to trap to the specific output, indicating the state of the particular processing unit.