TW201419538A - Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors - Google Patents

Abstract

An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.

Description

Vertically oriented transistor arrays, and memory arrays including vertically oriented transistors

Embodiments disclosed herein relate to vertically oriented transistor arrays and to memory arrays including vertically oriented transistors.

Memory system A type of integrated circuit that is used to store data in a computer system. The memory can be fabricated into one or more arrays of individual memory cells. The memory unit can be written or read using a digit line (which can also be referred to as a bit line, a data line, a sense line, or a data/sensing line) and an access line (which can also be referred to as a word line). The digit lines can electrically interconnect the memory cells along a row of the array, and the access lines can electrically interconnect the memory cells along the array of arrays. Each memory cell can be uniquely addressed by a combination of a bit line and an access line.

The memory unit can be volatile or non-volatile. Non-volatile memory cells can store data for extended periods of time in a number of cases, including when the computer is turned off. Volatile memory is dissipated and therefore needs to be renewed/rewritten multiple times per second in many cases. Regardless, the memory unit is configured to hold or store the memory in at least two different selectable states. In a binary system, these states are treated as a "0" or a "1". In other systems, at least some of the individual memory cells can be configured to store more than two information levels or information states.

An effect electron crystal system can be a type of electronic component used in a memory cell. The transistors include a pair of conductive source/drain regions in between one of the half conductive channel regions. A conductive gate is adjacent to the channel region and is separated therefrom by a thin dielectric. Applying a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, for example, a reversibly programmable charge storage region that is part of the gate structure. Alternatively or in addition, a transistor other than a field effect transistor may be used in the memory cell, for example, a bipolar transistor.

One type of volatile memory system dynamic random access memory (DRAM). Some DRAM memory cells can include a field effect transistor coupled to a charge storage device such as a capacitor. Other example memory cells may lack capacitors, and alternatively electrically floating transistor bodies may be used. Use electrically floating body transistor to the data storage memory may be referred to as a zero-electric crystal capacitor (0C1T) memory, or a memory capacitor-called called ZRAM ^TM (zero capacitor DRAM), and may be formed as a DRAM than A much higher level of integration.

Regardless, the gates of the transistors can be interconnected along the columns of memory cells and form access lines. The digits or data/sensing lines can be interconnected with one of the source/drain of each transistor along a row of memory cells. The data/sensing lines can be connected to individual sense amplifiers on the outside of the memory array. The access lines and data/sensing lines can be used in a memory array in which individual memory cells include transistors other than or in addition to field effect transistors. Regardless, the desired data/sensing line is highly conductive. In addition, it is desirable to minimize parasitic capacitance and crosstalk between adjacent data/sensing lines.

The transistor can be used in memory other than DRAM and in memory other than volatile memory. In addition, the transistor can also be formed as an array other than the memory.

2-2‧‧‧ line

3-3‧‧‧ line

4-4‧‧‧ line

5-5‧‧‧ line

10‧‧‧Substrate fragments

10c‧‧‧Substrate fragment

10d‧‧‧Substrate fragment

10e‧‧‧Alternative embodiment substrate segment

10f‧‧‧Alternative embodiment substrate segment

10g‧‧‧Alternative embodiment substrate segment

10h‧‧‧Alternative embodiment substrate segment

10j‧‧‧Alternative embodiment substrate segment

12‧‧‧Array or subarray area/array

14‧‧‧Circuit area/area

14-14‧‧‧ line

15‧‧‧Charge storage device

Line 15-15‧‧

16‧‧‧Vertically oriented transistor/transistor

18‧‧‧ memory unit / vertical orientation transistor

22‧‧‧Substrate material/underlying semiconductor material/material

24‧‧‧Semiconductor/semiconductor base with semiconductor

26‧‧‧Channel area

28‧‧‧Vertical internal source area/vertical internal drain area/internal source area/internal drain area/area/source area/bungee area

30‧‧‧Vertical external source area/vertical external drain area/external source area/external drain area/area/source area/bungee area

32‧‧‧ lateral external side/side

34‧‧‧ lateral external side

36‧‧‧ Column/Array Column

38‧‧‧

38‧‧‧

40a‧‧‧Access line/access line pair/gate line pair/access gate line

40b‧‧‧Access Line/Access Line Pair/Gate Pair/Access Gate Line

41‧‧‧Interconnection lines

42‧‧‧gate dielectric

44‧‧‧data/sensing line

44a‧‧‧Flexible wire/pair/line

44b‧‧‧Flexible wire/pair/line

45‧‧‧Interconnection lines

50‧‧‧ dielectric materials

60‧‧‧Conductive wire/wire/conductive material

60f‧‧‧Flexible wire

60g‧‧‧Flexible wire

60h‧‧‧Flexible wire

61‧‧‧ capacitor

64‧‧‧Composed dielectric materials/materials/dielectric/dielectric materials

66‧‧‧Composition dielectric materials/materials/dielectric/dielectric materials

68‧‧‧through hole

68j‧‧‧ conductive through hole

70‧‧‧Overlying conductive wire/wire/conductive wire

70j‧‧‧Flexible wire

72‧‧‧Base

73‧‧‧Top/Line Top

77‧‧‧Example conductive contacts

80‧‧‧ position

81‧‧‧Regional/highly doped areas

T ₁ ‧‧‧Facade thickness / thickness

T ₂ ‧‧‧Facade thickness / thickness

V‧‧‧ Suitable for potential

1 is a schematic, segmented, mixed top plan view and schematic view of one of a plurality of substrate segments including an array of vertically oriented transistors in accordance with an embodiment of the present invention.

Figure 2 is a cross-sectional view and a cross-sectional view taken through line 2-2 of Figure 1.

Figure 3 is a cross-sectional view and a cross-sectional view taken through line 3-3 of Figure 1.

Figure 4 is a cross-sectional view of a structure taken through line 4-4 of Figure 1.

Figure 5 is a cross-sectional view of a structure taken through line 5-5 of Figure 1.

Figure 6 shows two schematics.

Figure 7 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 4 in place.

Figure 8 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 4 in place.

Figure 9 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 4 in place.

Figure 10 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 5 in place.

Figure 11 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 4 in place.

Figure 12 is a cross-sectional view showing a structure of a substrate segment of an array according to an alternative embodiment of the present invention, and corresponding to the substrate segment of Figure 4 in place.

13 is a diagrammatic, fragmented top plan view of one of a substrate segment comprising an array in accordance with an embodiment of the present invention, and the substrate segment comprising a vertically oriented transistor.

Figure 14 is a cross-sectional view of a structure taken through line 14-14 of Figure 13.

Figure 15 is a cross-sectional view showing a structure taken through line 15-15 of Figure 13.

Embodiments of the invention include a vertically oriented transistor array, a memory array including vertically oriented transistors, and a memory cell including a vertically oriented transistor. First Exemplary embodiments are set forth in Figures 1 through 5. These figures show a substrate segment 10 (for example, a semiconductor substrate) comprising an array or sub-array region 12 and a circuit region 14 at the periphery of the array/sub-array region 12. Array 12 includes an array of vertically oriented transistors 16. In this document, the vertical system is generally orthogonal to one of the major surfaces, the substrate being processed relative to the major surface during fabrication and the major surface being considered to define a generally horizontal direction. Moreover, "vertical" and "horizontal" as used herein are independent of the orientation of the substrate in three-dimensional space and generally perpendicular to each other. In addition, in this document, such as "under", "below", "lower", "outward", "below", "above" and "vertical" The wording corresponds to a relative term relative to the vertical direction of the structure being illustrated. Circuitry can be fabricated on the outside of the array 12 (e.g., in region 14) for operating the vertically oriented transistor 16. The control circuitry and/or other peripheral circuitry for operating the vertically oriented transistor 16 may or may not be fully or partially received within the array 12, wherein as an example of a minimum amount, an exemplary array includes all of a given array/subarray A vertically oriented transistor (eg, it can include a memory cell). In addition, multiple sub-arrays may be fabricated and operated relative to one another, independently, in conjunction, or otherwise. As used in this document, a "subarray" can also be considered an array.

In some embodiments, the array comprises a memory, for example, comprising a plurality of individual memory cells comprising a substantially vertically oriented transistor. One example is DRAM, but other volatile and non-volatile memories that are currently available or yet to be developed are also contemplated. 1 through 5 illustrate, by way of example, array 12 as comprising a plurality of memory cells 18, each of which includes a transistor 16 and a charge storage device 15 (shown schematically in FIG. 2 and Figure 3). The charge storage device 15 is shown as a capacitor, although other storage devices or techniques may be used and may be formed in and/or on the substrate segment 10.

The substrate segment 10 comprises a substrate material 22 that may be homogenous or non-homogenous and may comprise a plurality of different composition materials, regions and/or layers. Exemplary materials include semiconductor materials, for example, a light background doped with a p-type conductivity modifying impurity, SiGe, InGaAs, and/or Or a bulk single crystal crucible of a composite of such materials. Other semiconductor materials (including semiconductor-on-insulator substrates) can also be used. In certain embodiments and as shown, the vertically oriented transistor 16 is a field effect transistor. 1 through 3 illustrate an individual transistor 16 including a semiconductor-containing pedestal 24 having a vertical external source/drain region 30, a vertical internal source/drain region 28, and a vertical Directly within one of the channel regions 26 between the internal source/drain regions 28 and the external source/drain regions 30. Each may be homogenous or non-homogeneous, with a suitable doped semiconductor material (eg, single crystal germanium) being exemplified. In particular, internal source/drain regions 28 and external source/drain regions 30, respectively, may comprise a highly doped concentration portion that is suitably conductively doped with one type of electrically conductive modified impurity, wherein channel region 26 It may be doped with a lower concentration of one of the opposite types of impurities. Each of regions 28 and/or 30 may include one or more of the same type of lightly doped regions (eg, LDD) and opposite types of doped annular regions (none of which are not specifically designated or displayed) . Regardless, individual charge storage devices 15 can be electrically coupled to respective external source/drain regions 30. In the context of this document, current flows continuously from one to the other by moving a subatomic positive and/or negative charge (when such charge is sufficiently generated), primarily in contrast to the movement of ions primarily. The devices or components are then electrically coupled relative to each other. The inner source/drain region 28 can be considered to have a relatively lateral outer side 32 (Fig. 3). Moreover, the channel region 26 can be considered to have a relatively lateral outer side 34 (Fig. 2), and in one embodiment, the outer sides are laterally oriented relative to the side 32 of the inner source/drain region 28.

Array 12 includes a plurality of columns 36 of access lines and a plurality of rows 38 of data/sensing lines (Fig. 1). The use of "columns" and "rows" in this document is to facilitate the division of a series of access lines and a series of data/sensing lines. Therefore, "columns" and "rows" are intended to be synonymous with a series of access lines and a series of data/sensing lines. The columns may be straight and/or curved and/or parallel and/or non-parallel with respect to each other, as may rows. Moreover, the rows and columns may intersect at 90[deg.] or at one or more other angles relative to each other. In the illustrated example, each of the columns and rows are shown as being individually straight and at an angle of 90° relative to each other.

Individual columns contain one of the access lines in the interconnected transistors. One or more of the access lines of the transistors in the interconnect can be used. Where multiple access lines are used, then the lines can be electrically coupled with respect to each other. 1 through 4 show individual columns 36 as including a pair of access lines 40a, 40b. In one embodiment and as shown, the access lines also form the gates of individual field effect transistors, and thus include access gate lines in some embodiments. One of the pair of access wires 40a, 40b is operatively transverse to one of the laterally outer sides 34 of the channel region 26, wherein the other of the pair of gate wires 40a, 40b is operatively transverse to the channel region Above the other of the lateral outer sides 34 of 26. A gate dielectric 42 is provided laterally between the individual access gate lines 40a, 40b and the respective channel regions 26. The access lines 40a, 40b may be homogenous or non-homogenous, may be the same composition or different compositions with respect to each other and will comprise any suitable electrically conductive material, for example elemental metal, an elemental metal alloy, one Any one or more of a conductive metal compound and a conductively doped semiconductor material. The access lines 40a, 40b are shown as being rectangular in cross section, but any shape can be used. Moreover, each does not need to be the same shape relative to the other. Access lines 40a, 40b and gate dielectric 42 are shown as laterally outermost lateral recesses relative to source/drain regions 28,30. Alternatively, as another example, the access lines 40a, 40b and the gate dielectric 42 may be laterally received outside the sides of the source/drain regions 28, 30, which may, for example, simplify fabrication and / or to affect the operation of the transistor 16.

Access lines 40a, 40b within individual columns 36 can be electrically coupled with respect to one another, for example, as shown schematically via respective interconnects 41 (FIG. 1). As an alternative example, the gate dielectric can be received circumferentially around the channel region (not shown), wherein the access lines in a single column wrap around the gate dielectric and serve as individual columns (not shown) A single access line continues continually.

The individual rows contain an internal data/sensing line that is vertically inward from the access line and interconnects one of the transistors in the row. A data/sensing line or a plurality of data/sensing lines for interconnecting the transistors in the row can be used vertically from the access line. 1 through 5 show individual rows 38 as data/sensing lines 44 containing vertically inward from the access lines 40a, 40b. In one embodiment and as shown, the vertical internal source/drain regions 28 are continuously connected in individual rows 38 to include at least a portion of the data/sensing lines in the other row (Fig. 2). Alternatively, as an example, the internal source/drain regions 28 may not be connected as such. Regardless, in one embodiment and as shown, a pair of conductive lines 44a, 44b form part of the data/sensing line 44 (Figs. 1, 3, and 5). One of the pair 44a, 44b is shown as being electrically coupled to and against one of the lateral outer sides 32 of the inner source/drain region 28, and the other of the pair 44a, 44b is electrically coupled to And against the other of the lateral outer sides 32 of the inner source/drain regions 28. Lines 44a and 44b may be electrically coupled to each other via respective interconnects 45 (FIG. 1), except for example only through internal source/drain regions 28, for example. The wires 44a, 44b can be homogenous or non-homogenous and can be the same composition or different compositions relative to each other. Exemplary materials include those materials set forth above for access lines 40a, 40b. The sections of lines 44a, 44b are shown as arcuate and concave, but any shape can be used. Moreover, each does not need to be the same shape relative to the other. One or more of the lines 44a/44b may be formed of a material having a higher electrical conductivity than the conductively doped internal source/drain regions 28. The data/sensing line 44 can be made to exclude one or both of the lines 44a/44b. An exemplary total n-type doping concentration of the highest conductive portion of the inner source/drain region 28 and the semiconductor material portion of the data/sensing line 44 is at least 5 x 10 ¹⁹ atoms/cm ³ . Examples of the channel region 26 of p-type dopant concentration of about 1 × 10 ¹⁸ based atoms / cm ^3.

The individual rows may include one or more external data/sensing lines (not shown) from the access line vertically outward and the one or more external data/sensing lines are electrically coupled to the internal data/sensing line in the row, For example, the inventors who submitted the application on March 6, 2012 are Lars P. Heineck and Jonathan T. Doebler and the serial number is "Arrays Of Vertically-Oriented Transistors, Memory Arrays Including Vertically-Oriented Transistors, And Memory Cells". It is disclosed in U.S. Patent Application Serial No. 13/413,402. These configurations reduce the overall resistance of the data/sense line to sensing outside the array Amplifier. In addition, these configurations can reduce the ratio of data/sense line to data/sense line capacitance to data/sensing line to word capacitance, thus potentially improving the final signal delivered to individual sense amplifiers.

The dielectric material 50 is received around the transistor 16, including access lines 40a, 40b, data/sensing lines 44, and a semiconductor-containing pedestal 24. Dielectric material 50 may be homogenous or non-homogeneous, with cerium nitride and boron and/or phosphorus cerium oxide being exemplified. The access gate lines 40a, 40b are shown in FIG. 1 by diagonal hatching for clarity purposes, but such access gate lines are received within the dielectric material 50 as shown in FIGS. 2 through 4. The semiconductor-containing pedestal 24 is shown diagrammatically as having vertical, straight, and aligned sidewalls. However, such pedestals may not be provided as such and may, for example, include arcuate and/or angled portions regardless of any alignment.

Array 12 includes a plurality of electrically conductive lines 60 that extend individually in a manner that is longitudinally parallel and laterally interposed between adjacent data/sensing lines 44 (Figs. 1, 3, and 5). Exemplary materials include those materials set forth above with respect to access lines 40a, 40b. Individual conductive lines 60 can be electrically coupled to a suitable potential to at least reduce parasitic capacitance and/or crosstalk between adjacent data/sense lines. For example, Figure 6 diagrammatically shows two schematic views of a pair of immediately adjacent data/sensing lines 44. The top view does not show the conductive lines therebetween or may show a conductive line (not shown) therebetween, the voltage of which allows for floating rather than providing a suitable potential. The parasitic capacitance between adjacent data/sensing lines 44 is shown by a capacitor 61. In the bottom view, a conductive line 60 is shown between the adjacent data/sensing lines 44. When provided at a suitable potential V, line 60 will at least reduce one or both of parasitic capacitance and/or crosstalk between adjacent data/sensing lines 44 and may eliminate this capacitance and/or crosstalk. The skilled person will be able to select a suitable positive voltage, negative voltage and/or ground voltage which may be constant or varied during operation to achieve this (equal) effect.

In one embodiment, the individual conductive lines are electrically coupled to each other, but in other embodiments such conductive lines may not be so coupled. Regardless, Figure 3 through Figure 5 show individual conductive lines An embodiment of 60 is surrounded by at least a dielectric material within the array 12. The dielectric material may be homogenous or non-homogenous, wherein two different composition dielectric materials 64, 66 are shown. In one embodiment, one of material 64 and material 66 comprises hafnium oxide and the other comprises tantalum nitride. The individual conductive lines 60 of the embodiment of Figures 1 through 5 are shown as being proximate to at least one of their respective ends by extending through the dielectrics 64, 66 and 50 to a via 68 of the overlying conductive line 70. They are electrically coupled to each other. Alternatively or additionally, vias 68 and lines 70 may be provided at other ends of line 60 (not shown). In one embodiment, the individual access lines are oriented parallel to one another, with the individual conductive lines being electrically coupled to one another by one of the conductive lines (eg, as shown by line 70) oriented parallel to the access line. For example, other modes of electrical coupling may be used as set forth below. Alternatively, a configuration (not shown) in which individual conductive lines are not electrically coupled and can be individually controlled can be provided.

Individual conductive lines 60 can be considered to have respective substrates 72. In FIGS. 3 through 5, substrate 72 is separated from the underlying semiconductor material 22 by dielectric material 64/66. Alternatively, the individual conductive lines 60 can have their respective substrates 72 that are directly abutted and electrically coupled to the underlying semiconductor material 22, as shown, for example, with respect to one of the substrate segments 10c of FIG. Where appropriate, similar numbers from the embodiments set forth above have been used. Figure 7 is an alternate embodiment of the embodiment illustrated by Figure 4 of the embodiment of Figures 1 through 5. In FIG. 7, dielectric 64/66 is not received over respective substrate 72 whereby substrate 72 is directly abutted and electrically coupled to semiconductor material 22 continuously along longitudinally along individual conductive lines 60 (ie, at The array 12 has at least a majority of its respective lengths). In this document, a material or structure "directly abuts" the other when there is at least some of the physical contact contacts of the stated materials or structures relative to each other. In contrast, "directly above", "above" and "resistance" without "directly" include "direct abutment" and the intervening material or structure causes the material or structure to be relatively The construction of the contacts without physical contact with each other. Through holes 68 and 70 (not shown) may not be used in the embodiment of FIG.

As an alternative example, the substrate can be directly abutted and electrically coupled to each other along an individual conductive The underlying semiconductor material at a plurality of spaced apart locations in which the lines are longitudinally parallel. One of the substrate segments 10d of Figure 8 shows one such exemplary embodiment. Where appropriate, the same numbering from the embodiments set forth above has been used, with the suffix "d" or a different number indicating certain structural differences. In FIG. 8, conductive substrate 72 of conductive line 60 directly abuts underlying semiconductor material 22 at spaced apart locations 80. In one embodiment and as shown, the spaced apart locations 80 are parallel between the vertically oriented transistors 16, and in one embodiment, are oriented longitudinally along the vertical of the individual conductive lines in the transistor 18. Each is parallel. The spaced apart locations 80 are alternately positionable.

In the exemplary FIGS. 7 and 8 embodiments, individual conductive lines can be effectively electrically coupled to one another by providing underlying substrate material 22 at a suitable potential to, for example, at least reduce the proximity of the data/feel Parasitic capacitance and/or crosstalk between lines.

In one embodiment, the semiconductor material of the underlying substrate can be provided to have a higher doped region vertically above a lower doped region (eg, a background doping of a semiconductor material), wherein the substrate is directly Abut the higher doped area. This may, for example, facilitate electrical coupling of the conductive lines to the underlying semiconductor material. For example, Figure 9 shows this alternative embodiment substrate segment 10e. Where appropriate, the same numbering from the embodiment of Figure 7 has been used, with the suffix "e" or a different number indicating certain structural differences. In FIG. 9, semiconductor material 22 includes a highly doped region 81 vertically above the remainder of semiconductor material 22 (ie, region 81 is vertically above one of the lower doped regions of material 22), wherein the substrate 72 directly abuts the higher doped region 81. It is also possible to use a higher doped region with respect to the embodiment of Figure 8, regardless of whether a higher doped region is continuous or only directly at position 80 of the dielectric 64/ across the respective lines of the array. The lower part of the opening is shown in 66.

Conductive lines 60 may be considered to comprise vertical face thickness T _1, and data may be considered to comprise sense line 44 facade thickness T ₂ (FIG. 3 and FIG. 5). The thickness T ₁ may be the same for individual conductive lines 60 or may be different for different line systems. Additionally or alternatively lines, T ₁ lines can be constant or within a single system of individual conductive lines 60 may be changed. If variable, T ₁ refers to the average façade thickness of one of the other conductive lines 60. Likewise, the thickness T _{2 of the} individual data/sensing lines 44 may be the same or different. Additionally or alternatively based, T ₂ may be constant, or based on a single data / sense lines 44 can be changed based. If variable, T ₂ refers to the average façade thickness of one of the other data/sensing lines 44. Regardless, in one embodiment, and as the information on the implementation of 3 to 5 shown in FIG embodiment, the conductive wire 60 relative to its respective proximate the embodiments / sense line 44 vertically extending inwardly (i.e., T ₁ below T ₂ extension).

3 through 5 also show an exemplary embodiment in which the conductive line 60 does not extend vertically outward relative to the immediately adjacent data/sensing line 44. 10 shows an alternative embodiment substrate segment 10f in which individual conductive lines 60f extend vertically outward relative to the immediately adjacent data/sensing line 44. The same numbers from the embodiments set forth above have been used where appropriate, with the suffix "f" indicating certain structural differences. FIG. 10 also shows an exemplary embodiment in which individual conductive lines 60 do not extend vertically inward relative to the immediately adjacent data/sensing line 44.

Figure 11 shows an alternative embodiment substrate segment 10g in which the conductive line 60g has one of the individual face thicknesses across all of the façade thicknesses of the data/sensing line immediately adjacent thereto. FIG 11 also shows where the respective conductive lines 60 have one exemplary embodiment of _a facade of the thickness of immediately adjacent data / sense lines 44 of the respective vertical T ₂ coincides with the facade thickness T. The same numbers from the embodiments set forth above have been used where appropriate, with the suffix "g" indicating certain structural differences.

12 shows an alternative embodiment substrate segment 10h in which individual conductive lines 60h extend vertically inwardly and outwardly relative to their immediately adjacent data/sensing lines 44. The same numbers from the embodiments set forth above have been used where appropriate, with the suffix "h" indicating certain structural differences.

Any of the embodiments of Figures 10-12 may include any of the features shown and described with respect to Figures 1-9.

The structure according to an embodiment of the present invention can be made using any existing or yet to be developed technology. For example, at least in part as illustrated in any one or more of the following applications It can be dealt with: the inventors who submitted the application on November 1, 2010 are Lars P. Heineck and Jaydip Guha and the title of "Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells" is 12/917,346. U.S. Patent Application; the inventors filed on February 22, 2011 are Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, and Hung-Ming Tsai and titled "Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells, US Patent Application Serial No. 13/031,829; and the inventors filed on March 6, 2012, Lars P. Heineck and Jonathan U.S. Patent Application Serial No. 13/413,402, entitled, <RTIgt;''''''""""""""""""

In addition and in any event, the conductive lines 60 can be made in any of a number of ways. As an example, in one embodiment it is contemplated that the sidewalls of the openings in which the dielectric material 50 is formed may not be as vertical as shown. For example, this can be formed by etching into the semiconductor material and it is tapered to be narrower at its bottom than at its top. Such openings may also and/or alternatively be fabricated whereby the wire 60 will be necked inwardly at or near the top at the location at which it is located and then widened laterally outward to a deeper extent in the substrate. The deposition of dielectric material 64/66 can be performed thereby forming a sealed longitudinal tubular or tubular void space in which the conductive material of conductive line 60 will be received. In one possible technique, such individual tubes can then be opened at their tops and thereafter filled with a conductive material 60. The conductive material can then be recessed inwardly to the top of the front tube and subsequently sealed with a dielectric material. An access device will be formed over it, followed by formation of vias 68 and conductive lines 70. As an alternative, after opening the top of the otherwise sealed tube, it may be continuous or in any of the embodiments forming FIG. 7 or FIG. 8 prior to depositing the conductive material to be used for the conductive line 60. The dielectric bottom surface is etched through spaced apart locations.

As a further alternative, a sealless tubular or sealed tubular void may be formed. For example, an upwardly open trench between adjacent digit lines can be formed. The sidewalls and the substrate may be covered with a dielectric material in a manner that does not form a sealed, tubular void therein, thereby maintaining the trench open upwardly. The dielectric material can then be anisotropically etched from the substrate to expose the underlying semiconductor material 22 when one of the configurations of FIG. 7 or FIG. 8 is formed. Its sidewalls may remain covered by a dielectric material. The electrically conductive material can then be deposited, recessed back, covered with a dielectric, and then subsequently formed into access lines.

In use, region 81 can be formed at any suitable time during manufacture.

13 through 15 show an alternative embodiment substrate segment 10j. The same numbering from the embodiments set forth above has been used where appropriate, with the suffix "j" indicating certain structural differences. The semiconductor pedestal 24 and the data sensing line 44 are not shown in FIG. 13 for purposes of simplicity and clarity, but may be included similarly to what is shown and described above with respect to the top view of FIG. Individual conductive lines 60 can be considered to have respective tops 73. A conductive line 70j electrically couples the individual conductive lines 60 to each other with the line top 73 directly abutting the conductive line 70j. A conductive via 68j can be electrically coupled to the conductive line 70j and extend vertically therefrom. In one embodiment, the individual access lines are oriented parallel to each other with the conductive lines 70j oriented parallel to the access lines. In one embodiment, at least two conductive lines 70j electrically couple the conductive lines 60 to each other. In one embodiment, the two conductive lines 70j are oriented parallel to the access lines 40a, 40b and, in an embodiment as shown, are proximate to opposite ends of the array column 36.

The structure of Figures 13 through 15 can be made easier than some of the other embodiments described above. For example, providing one of the gap widths at one end of the array of access lines than the access lines within the array can inherently result in an array during reactive ion etching at one of the dielectric materials 50. The deep trench is etched at the end. This allows the conductive line 70j to be formed simultaneously with the formation of the access lines 40a, 40b. For example, a deeper trench at the end of the array rather than within the array will cause the conductive line 70j to extend inwardly to connect with the conductive line 60. Therefore, the conductive material of the access lines 40a, 40b and the conductive material of the conductive line 70j can sink at the same time product. Additionally, conductive vias 68j can be formed simultaneously with the example conductive contacts 77 that are electrically coupled to the individual access line pairs 40a, 40b.

The structures set forth above can be fabricated into any suitable architecture or size. In one example, the individual memory cells of the above architecture may have a 4F ² horizontal footprint, where "F" is formed using a feature edge formed by a material from which the smallest feature is formed vertically. The minimum lateral feature size of these smallest features.

to sum up

In some embodiments, an array comprises a vertically oriented transistor. The array includes a number of column access lines and a number of rows of data/sensing lines. The individual columns in the column contain one of the access lines in the interconnected transistors. Individual rows in a row contain data/sensing lines that interconnect one of the transistors in the row. The array includes a plurality of electrically conductive lines that extend individually in a manner that is longitudinally parallel and laterally interposed between the data/sensing lines.

In some embodiments, an array comprises a vertically oriented transistor. The array includes a number of column access lines and a number of rows of data/sensing lines. The individual columns in the column contain one of the access lines in the interconnected transistors. Individual rows in a row contain data/sensing lines that interconnect one of the transistors in the row. The array includes a plurality of electrically conductive lines that extend individually in a manner that is longitudinally parallel and laterally interposed between adjacent data/sensing lines. The individual conductive lines have respective substrates separated from the underlying semiconductor material by a dielectric material. The individual conductive lines are electrically coupled to a suitable potential to at least reduce parasitic capacitance and/or crosstalk between adjacent data/sensing lines. The individual conductive lines are electrically coupled to each other near at least one or each respective end thereof.

In some embodiments, an array comprises a vertically oriented transistor. The array includes a number of column access lines and a number of rows of data/sensing lines. The individual columns in the column contain one of the access lines in the interconnected transistors. Individual rows in a row contain data/sensing lines that interconnect one of the transistors in the row. The array includes a plurality of electrically conductive lines that extend individually in a manner that is longitudinally parallel and laterally interposed between the data/sensing lines. Individual conductive lines have a plurality of spaced apart locations that are parallel along the longitudinal direction of the individual conductive lines and are electrically coupled to the underlying half Individual substrates of the conductor material. The underlying substrate material is provided at a suitable potential to at least reduce parasitic capacitance and/or crosstalk between adjacent data/sensing lines.

In some embodiments, an array comprises a vertically oriented transistor. The array includes a number of column access lines and a number of rows of data/sensing lines. The individual columns in the column contain one of the access lines in the interconnected transistors. Individual rows in a row contain data/sensing lines that interconnect one of the transistors in the row. The array includes a plurality of electrically conductive lines that extend individually in a manner that is longitudinally parallel and laterally interposed between the data/sensing lines. The individual conductive lines have respective substrates that are directly abutted and electrically coupled to the semiconductor material that is continuously longitudinally along the underlying individual conductive lines. The underlying substrate material is provided at a suitable potential to at least reduce parasitic capacitance and/or crosstalk between adjacent data/sensing lines.

In some embodiments, an array comprises a vertically oriented transistor. The array includes a number of column access lines and a number of rows of data/sensing lines. The individual columns in the column contain one of the access lines in the interconnected transistors. Individual rows in a row contain data/sensing lines that interconnect one of the transistors in the row. The array includes a plurality of electrically conductive lines that extend individually in a manner that is longitudinally parallel and laterally interposed between the data/sensing lines. The individual conductive lines have respective tops that are directly abutted and electrically coupled to one of the conductive lines that electrically couple the individual conductive lines to each other. Conductive lines that electrically couple individual conductive lines to each other are provided at a suitable potential to at least reduce parasitic capacitance and/or crosstalk between adjacent data/sense lines.

In accordance with the regulations, the subject matter disclosed herein has been set forth in a specific language of more or less structural and analytical features. It should be understood, however, that the invention is not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the scope of such patent applications is to be provided in a full range by the wording of the wording, and is appropriately explained in accordance with the teachings of equivalents.

2-2‧‧‧ line

3-3‧‧‧ line

4-4‧‧‧ line

5-5‧‧‧ line

12‧‧‧Array or subarray area/array

14‧‧‧Circuit area/area

16‧‧‧Vertically oriented transistor/transistor

24‧‧‧Semiconductor/semiconductor base with semiconductor

30‧‧‧Vertical external source area/vertical external drain area/external source area/external drain area/area/source area/bungee area

36‧‧‧ Column/Array Column

38‧‧‧

40a‧‧‧Access line/access line pair/gate line pair/access gate line

40b‧‧‧Access Line/Access Line Pair/Gate Pair/Access Gate Line

41‧‧‧Interconnection lines

42‧‧‧gate dielectric

44‧‧‧data/sensing line

44a‧‧‧Flexible wire/pair/line

44b‧‧‧Flexible wire/pair/line

45‧‧‧Interconnection lines

50‧‧‧ dielectric materials

60‧‧‧Conductive wire/wire/conductive material

68‧‧‧through hole

70‧‧‧Overlying conductive wire/wire/conductive wire

Claims (22)

An array comprising vertically oriented transistors, the array comprising a plurality of column access lines and a plurality of rows of data/sensing lines, the array comprising: individual columns of the columns comprising one of the interconnecting transistors Taking a line; an individual row of the rows comprising one of the data/sensing lines interconnecting the transistors in the row; and a plurality of conductive lines, the individual conductive lines of the conductive lines being longitudinally parallel and laterally interposed The way between the data/sensing lines is immediately adjacent. An array of claim 1 wherein the individual conductive lines are electrically coupled to each other. An array of claim 1, wherein the individual conductive lines are electrically coupled to a suitable potential to at least reduce parasitic capacitance and/or crosstalk between the data/sensing lines in close proximity. An array of claim 1 wherein the individual conductive lines are surrounded by a dielectric material within the array. An array of claim 1 wherein the individual conductive lines have respective substrates separated from the underlying semiconductor material by a dielectric material. An array of claim 1 wherein the individual conductive lines have respective substrates that are directly abutted and electrically coupled to the underlying semiconductor material. The array of claim 1, wherein the individual conductive lines have respective tops that are directly abutted and electrically coupled to one of the conductive lines that electrically couple the individual conductive lines to each other. An array of claim 7, wherein the individual access lines are positioned in parallel with each other, the conductive lines electrically coupling the individual conductive lines to each other oriented parallel to the access lines. An array of claim 1, wherein the individual conductive lines extend vertically inward relative to a data/sensing line immediately adjacent thereto. An array of claim 1, wherein the individual conductive lines extend vertically outward relative to a data/sensing line immediately adjacent thereto. An array of claim 1 wherein the individual conductive lines extend vertically inwardly and outwardly relative to the immediately adjacent data/sensing line. An array of claim 1, wherein the individual conductive lines extend vertically inwardly relative to the immediately adjacent data/sensing line and not vertically outward relative to the immediately adjacent data/sensing line. An array of claim 1, wherein the individual conductive lines have respective facade thicknesses across all of the facade thicknesses of the data/sensing lines immediately adjacent thereto. An array of claim 1, wherein the array comprises a memory array comprising one of a vertical external source/drain region electrically coupled to one of the individual transistors in the vertically oriented transistors Device. The array of claim 1 wherein the individual vertically oriented transistors comprise a semiconductor-containing pedestal comprising a vertical external source/drain region and a vertical internal source/drain region The equal vertical source/drain regions are consecutively connected in individual rows of the rows to include at least a portion of the data/sensing line in individual rows of the rows. An array comprising vertically oriented transistors, the array comprising a plurality of column access lines and a plurality of rows of data/sensing lines, the array comprising: individual columns of the columns comprising one of the interconnecting transistors Taking a line; an individual row of the rows comprising one of the data/sensing lines interconnecting the transistors in the row; and a plurality of conductive lines, the individual conductive lines of the conductive lines being longitudinally parallel and laterally interposed Adjacent to the manner between the data/sensing lines, the individual conductive lines have respective substrates separated from the underlying semiconductor material by a dielectric material, the individual conductive lines being electrically coupled to a suitable potential To at least reduce the proximity Parasitic capacitance and/or crosstalk between the data/sensing lines that are electrically coupled to each other near at least one end or at respective ends thereof. An array comprising vertically oriented transistors, the array comprising a plurality of column access lines and a plurality of rows of data/sensing lines, the array comprising: individual columns of the columns comprising one of the interconnecting transistors Taking a line; an individual row of the rows comprising one of the data/sensing lines interconnecting the transistors in the row; and a plurality of conductive lines, the individual conductive lines of the conductive lines being longitudinally parallel and laterally interposed Extending between the data/sensing lines in close proximity, the individual conductive lines having a plurality of spaced apart locations that are parallel along the longitudinal direction of the individual conductive lines directly abut and electrically coupled to the underlying semiconductor material The respective substrates, at a suitable potential, provide the underlying substrate material to at least reduce parasitic capacitance and/or crosstalk between the data/sensing lines in close proximity. An array of claim 17, wherein the semiconductor material underlying the substrates has a highly doped region vertically above a lower doped region, the substrates directly contacting the spaced apart locations By this higher doped region. An array comprising vertically oriented transistors, the array comprising a plurality of column access lines and a plurality of rows of data/sensing lines, the array comprising: individual columns of the columns comprising one of the interconnecting transistors Taking a line; an individual row of the rows comprising one of the data/sensing lines interconnecting the transistors in the row; and a plurality of conductive lines, the individual conductive lines of the conductive lines being longitudinally parallel and laterally interposed Adjacent to the manner between the data/sensing lines, the individual conductive lines have direct abutment and are electrically coupled to the longitudinally longitudinally along the individual conductive lines The respective substrates of the underlying semiconductor material, at a suitable potential, provide the underlying substrate material to at least reduce parasitic capacitance and/or crosstalk between the data/sensing lines in close proximity. An array comprising vertically oriented transistors, the array comprising a plurality of column access lines and a plurality of rows of data/sensing lines, the array comprising: individual columns of the columns comprising one of the interconnecting transistors Taking a line; an individual row of the rows comprising one of the data/sensing lines interconnecting the transistors in the row; and a plurality of conductive lines, the individual conductive lines of the conductive lines being longitudinally parallel and laterally interposed Adjacent to the manner between the data/sensing lines, the individual conductive lines have respective tops that are directly abutted and electrically coupled to one of the conductive lines that electrically couple the individual conductive lines to each other, at a suitable potential Providing the conductive lines that electrically couple the individual conductive lines to each other to at least reduce parasitic capacitance and/or crosstalk between the data/sensing lines in close proximity. An array of claim 20, wherein the individual access lines are oriented parallel to one another, the conductive lines electrically coupling the individual conductive lines to each other oriented parallel to the access lines. An array of claim 20, comprising at least two electrically conductive lines electrically coupling the individual electrically conductive lines to each other, the electrically conductive lines directly abutting longitudinally parallel and laterally between the data/sensing lines in close proximity The manner extends the respective tops of the conductive lines.