TW201419140A - Reconfigurable instruction encoding, execution method and electronic apparatus - Google Patents

Abstract

Reconfigurable instruction encoding, execution method and electronic apparatus are provided. The instruction encoding method, in an embodiment, generates an instruction encoding table and an instruction mapping table by performing encoding on pairs of adjacent instructions of an application in terms of the pairs' respective usage times and then further performing repetitive encoding, and generates executable code of the application according to the instruction encoding table. The reconfigurable instruction execution method includes the following. An instruction code remapping table is loaded into a processing unit of an electronic apparatus, wherein the processing unit includes an instruction remapping module, an instruction decoding module, and an execution module. A first instruction signal of an application program is fetched by the processing unit. According to the instruction remapping table, the first instruction signal is converted to a target instruction signal by the instruction remapping module. The target instruction signal is decoded by the instruction decoding module and the decoded target instruction signal is executed by the execution module.

Description

Reconfigurable instruction coding method, execution method and electronic device

The disclosure relates to a reconfigurable instruction encoding method, an execution method, and a processor architecture.

When compiling a program for a certain processor, the compiler converts the source code of the application into machine code according to a fixed instruction table corresponding to one of the processor instruction set architectures. ) for such a processor to perform a corresponding arithmetic action.

In addition, when the application program is executed in an arithmetic device, the machine code of the application stored in the memory of the computing device is transmitted to the bus bar and reaches the processor of the computing device, which may result in continuous execution of the command. The phase of the signal on the command bus changes drastically, which causes frequent conversion of the signal logic level at the input of the circuit, accompanied by severe power consumption.

The disclosure relates to a reconfigurable instruction encoding method, an execution method, and a processor architecture.

According to an embodiment, a reconfigurable instruction execution method is presented. The method is performed on an electronic device and includes the following steps. Loading a command code mapping table to a processing unit of an electronic device, wherein the processing unit comprises a command mapping module, an instruction decoding module and an execution module. By means of the processing unit, one of the first instruction signals of an application is retrieved. By The instruction maps the module, and according to the instruction code, the first command signal is converted into a target command signal. The target decoding signal is decoded by the instruction decoding module, and the decoded target instruction signal is executed by executing the module.

According to another embodiment, an electronic device is provided. The electronic device includes a processing unit for mapping the table according to an instruction code for executing the instruction. The processing unit includes a command mapping module, an instruction decoding module and an execution module. The instruction mapping module, according to the instruction code mapping table, converts one of the first instruction signals from the processing unit into a target instruction signal. The instruction decoding module decodes the target command signal. The execution module executes the decoded target command signal.

According to another embodiment, a reconfigurable instruction encoding method is provided. This method includes the following steps. The pairing distribution of adjacent instructions of an application is counted, and an instruction pairing set is found. The command pairing set includes a plurality of instruction pairs of the application with higher usage rate. The instruction pairing of the instruction pairing the higher usage rate is encoded to give each instruction a similar instruction encoding, thereby generating an instruction encoding table, wherein the instruction encoding table has the same number of instructions as an original instruction encoding table. And at least a plurality of instructions corresponding to different instruction codes in the instruction code table and the original instruction code table. An instruction code mapping table is generated, wherein the instruction code mapping table stores the mapping relationship of the instruction encoding table pair to the original instruction encoding table.

According to another embodiment, an information storage medium readable by an arithmetic device is provided, on which a program code is stored, and the execution of the code can implement the reconfigurable instruction encoding method described above.

In order to better understand the above and other aspects of the present disclosure, various embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Embodiments of the reconfigurable instruction encoding method, execution method, and processor architecture are provided below. Some embodiments propose a processor architecture having a processor mapping module that enables the processor to execute an application based on a reconfigured instruction set. Some embodiments propose a method of compiling an application that produces a reconfigured instruction set. Some embodiments further propose a reconfigurable instruction encoding method that reduces the Hamming distance between adjacent instructions.

Figure 1 is a block diagram of one embodiment of a hardware architecture 1 of reconfigurable instruction encoding. The hardware architecture 1 includes a processing unit 10 and a memory unit 20. The following processing unit 10 includes a command mapping module 110, an instruction decoding module 120, and an execution module 130 as an example. However, the processing unit 10 is not limited thereto, and the processing unit 10 may also be implemented as a single or multi-core processor, or the processor may be a pipeline architecture circuit or a very long instruction word (Very long instruction word, VLIW) or other architectural circuit implementation. For example, the command mapping module 110 of the processing unit 10 can be included in an instruction capture module 100 or coupled between an instruction capture module and the instruction decoding module 120.

In FIG. 1 , the processing unit 10 is configured to perform an action on the table 210 according to an instruction code, for example, executing an execution code 220 of an application. The instruction mapping module 110 converts the first instruction signal S1 from the processing unit 10 into a target instruction signal S2 according to the instruction code mapping table 210. The instruction decoding module 120 is configured to solve the target command signal S2 code. The execution module 130 executes the decoded target command signal. The memory unit 20 is coupled to the processing unit 10 via a bus 30, for example, to store a plurality of execution codes of the instruction code mapping table 210 and an application 220. The memory unit 20 can be implemented as the same or different memory modules. Group or device. In addition, during execution of the application execution code 220, the processing unit 10 may retrieve at least one or more instructions from the memory unit 20, and execute at least one or more instructions of the code 220, which may be parallel or serial data signals. , can be represented by the first command signal S1.

In Figure 1, processing unit 10 has its own instruction set architecture, such as a Reduced Instruction Set (RISC) based processor architecture, such as a microprocessor based interprocessor-free interleaved microprocessor (Microprocessor without Interlocked) Pipeline Stage, MIPS) architecture. By having the architecture of the instruction mapping module 110, the processing unit 10 can execute an application that is generated (or compiled) based on a reconfigured instruction set. The instruction mapping code represented by the instruction mapping module 110 according to the target command signal S2 outputted by the instruction code mapping table 210 conforms to the instruction set of the processing unit 10 itself. Therefore, the instruction decoding module 120 can be decoded according to the instruction set of the processing unit 10 itself and executed by the execution module 130. Thus, processing unit 10 can be considered a processing unit that can dynamically adjust the set of instructions.

Please refer to FIG. 2, which is a flowchart of one embodiment of a reconfigurable instruction execution method. The hardware architecture 1 of FIG. 1 is exemplified below, but the method of FIG. 2 is not limited thereto.

In step S110, an instruction code is loaded into the processing unit 10 of one of the electronic devices. The electronic device can be regarded as the processing unit 10, or It can be regarded as a system on chip based on the processing unit 10, and can be regarded as various computing devices based on the processing unit 10, such as a smart phone, a tablet, a notebook, a personal computer, or various mobile devices or embedded. System such as multimedia player. Step S110 can be implemented. Before the processing unit 10 executes an application according to the instruction code mapping table, the processing unit 10 causes the instruction mapping module 110 to load the corresponding instruction code mapping table. Step S110 can be implemented to pre-store one or more instruction code mapping tables in the processing unit 10, so that it can be used when executing an application execution, and the corresponding instruction code mapping corresponding to the executed application can be implemented. table.

In step S120, the processing unit 10 retrieves one of the first command signals S1 of an application. Step S120 can be implemented by one of the processing unit 10 to capture the module or the instruction mapping module 110. For another example, the processing unit 10 obtains the instruction code mapping table from the memory unit 20 of the electronic device and retrieves the first command signal S1, and the first command signal S1 represents at least one of the plurality of execution codes of the application.

In step S130, the first mapping signal S1 is converted into a target command signal S2 by the instruction mapping module 110 according to the loaded instruction code mapping table.

In step S140, the target decoding signal S2 is decoded by the instruction decoding module 120, and the decoded target instruction signal is executed by the execution module 130.

In the converting step S130, for example, the first command signal S1 includes an encoded instruction code (for example, 1001 represents an instruction ADD), and the target command signal S2 includes an original instruction code (for example, 1110 represents an instruction). ADD), the instruction code mapping table stores the mapping of the encoded code to the mapping of one of the original instructions to one. According to the mapping relationship of the instruction code, the first mapping signal S1 is converted into the target instruction signal S2 by the instruction mapping module 110. In another example, the instruction code mapping table may also store a multi-to-one mapping relationship that encodes a plurality of different encoded instruction codes (eg, 1001, 1101 representing the same instruction ADD).

In an embodiment, steps S110-S140 are performed on an electronic device.

On the other hand, the instruction code mapping table stores a function relationship (one-to-one or/and many-to-one mapping) that maps a plurality of encoded instruction codes to a plurality of original instruction codes, and the application program The execution code is generated based on the coded instruction code tables, and the instructions of the original instruction code table are included in one of the processing units themselves.

From the embodiments described above, processing unit 10 can be considered a processing unit that can dynamically adjust the instruction set encoding. Because the processing unit 10 can execute applications based on different instruction set encodings, it can bring considerable flexibility in implementing the processing unit 10 and executing the application and generate different applications. In an embodiment, for other processor instruction set programs, the instruction code mapping table may be designed or generated, and cooperated with the instruction mapping module, and the conversion operation of the instruction mapping module is based on other processor instruction sets. The program can also be executed in the processing unit 10. In some embodiments, the instruction code mapping table can be designed or generated such that the Hamming distance of two adjacent execution codes in the execution code of the application is less than the entire distribution (ie, the distribution of the instruction pair). The Hamming distance of the execution code of the two neighbors converted by the module according to the instruction code. Related to generating instruction code mapping and reconfiguration The instruction encoding method will be illustrated later.

Please refer to FIG. 3, which is a circuit block diagram of an embodiment of the command mapping module of FIG. 1. In FIG. 3, the command mapping module 300 includes a memory 310 (such as a temporary memory or other memory) and a control circuit 320 (for example, a combination of logic circuits or other circuits). The control circuit 320 is configured to load the instruction code mapping table in the memory 310, and to convert the first instruction signal S1 into the target instruction signal S2 according to the instruction code mapping table.

Figure 4 is a block diagram of another embodiment of a processor architecture for reconfigurable instruction encoding. The architecture of FIG. 4 includes an instruction capture module 400 and a multiplexer 420 as compared to the processing unit 10 of FIG. The instruction capture module 400 is configured to capture the first command signal S1. The plurality of inputs of the multiplexer 420 are coupled to a command mapping module 410 and the instruction capture module 400. The output of the multiplexer 420 is coupled to the instruction decoding module 120. The processing unit 40 controls the multiplexer 420 to select the output of the command mapping module 410 and the command capture module 400 as a multiplex according to an indication signal (for example, a system circuit from an operating system or an electronic device of the electronic device). The output of the 420. In an embodiment, processing unit 40 may have a mapping mode and a raw mode. In the original mode, the processing unit 40 can execute the execution code of the program compiled by the original instruction encoding (for example, the system program or the operating system command, or the general application) without the processing of the command mapping module 410. Therefore, the multiplexer 420 is used to process the output transfer instruction decoding module 120 of the instruction capture module 400. In the mapping mode, by the processing of the mapping module 410, the processing unit 40 can execute the execution code of the program compiled with the encoded instruction set (eg, an application). The program, as shown in the example shown in FIG. 5 below, uses the multiplexer 420 to transfer the output of the command mapping module 410 to the instruction decoding module 120 for processing. In addition, in another embodiment, in the original mode, the command mapping module 410 can be brought into a power saving state. As such, embodiments of the processor architecture of the reconfigurable instruction code can be implemented in a variety of ways, and are not limited thereto.

Figure 5 is a flow diagram of one embodiment of a reconfigurable instruction encoding method. This embodiment can be implemented in an arithmetic device having a processor and a memory. Step S10 represents a process in which the source code of the application is compiled into an object code based on a certain instruction set, for example, by a compiler. The object code is such as a machine code or an executable code or a binary code. In the process of generating the target code in step S10, the original code is compiled into a code represented by a combination language or a pseudo code, and finally converted into a target code based on a certain instruction set encoding, which can be The instruction decoding module and the execution module processing of the processor constructed based on the instruction set.

In step S20, program profiling is performed, and an instruction encoding table and an instruction code mapping table are generated by using the instruction pairing distribution in the statistical code (eg, in a combined language). Step S20 can be implemented, for example, in a compiler or as one or more software modules used by the compiler. The instruction encoding table is used by the compiling process of step S10, and step S10 converts the code represented by the combined language into the target code based on the instruction encoding table instead of the original instruction set encoding. The correspondence between the instructions in the instruction code table and the instruction code (ie, machine code) is different from the original instruction set code, so it can be regarded as the reconfigured instruction set code. Therefore, the instruction code map The table is used when the object code is executed by a processing unit constructed based on the original instruction set encoding. As shown in the first to fourth embodiments, the processing unit enables the application to execute by using the instruction mapping module to map the table according to the instruction code. The instruction code mapping table stores the mapping relationship of this instruction encoding table to an original instruction encoding table. The command code mapping table and the target code can all be included in an application file, or can be separated into different files or software modules.

Figure 6 is a flow diagram of an embodiment of the code profiling step of Figure 5 for implementing a reconfigurable instruction encoding method.

As shown in step S210, the pairing distribution of the adjacent instructions of an application is counted, and an instruction pairing set (for example, at least some instructions in the original instruction encoding table) is found, and the instruction pairing set includes the application. Multiple instruction pairs with higher usage rates (such as more occurrences).

In step S220, a plurality of instruction pairs (some or all) of the higher usage rate are encoded in the instruction pairing pair to give each instruction a similar instruction encoding, thereby generating a first instruction encoding table. The first instruction encoding table has the same number of instructions as a raw instruction encoding table, and at least a plurality of instructions correspond to different instruction encodings in the first instruction encoding table and the original instruction encoding table.

In step S230, according to the first instruction encoding table, finding the Hamming distance of the pairing instruction in the instruction pairing set, and according to the instruction, the Hamming distance and the number of occurrences of the pairing instructions of the pairing set, from the instruction pairing set Find out the multiple instructions.

In step S240, the found instructions are repeatedly encoded to obtain a second instruction encoding table. Repeat coding gives each found command At least one additional instruction code. This second instruction encoding table is extended based on the aforementioned first instruction encoding table and includes such additional instruction encoding.

In step S250, an instruction code mapping table is generated, wherein the instruction code mapping table stores the mapping relationship of the second instruction encoding table to the original instruction encoding table.

Thus, a compiler can generate an execution code of the application according to the second instruction encoding table and the instructions of the application.

In some embodiments, an encoding mode selection module or step may be implemented in the compiler or the interpreter to cause the compiler and the interpreter to generate consecutive inter-instruction instructions when an instruction corresponds to a plurality of encoded instruction encodings. The machine code with the least change in signal phase on the bus. The coding mode of the compiler selects a module or a step, and selects an optimal coding mode according to the instruction coding table, so that the distance between the front and rear instructions is shorter. For example, in processing two adjacent instructions, such as for instructions IN1-IN2, IN1 corresponds to (1001, 0101), and IN2 corresponds to (0100), and the instruction code that enables the commanding distances of IN1 and IN2 to be small is selected, that is, IN1:0101, IN2:0100.

Further, in an implementation, the step S220 of generating the instruction code table may include the following. A plurality of instruction pairs for the instruction pairing set are coded according to the usage level in order from the highest usage of the instruction pair to give each of the instructions a similar instruction code. The encoding of the instruction is generated based on the pairing of the instructions.

In some implementations, step S230 determines the instructions for finding out based on various relationships between the Hamming distance and the number of occurrences. For example, it is determined based on the product of the Hamming distance and the number of occurrences; in other words, the instructions found in this example are the multiplication of the Hamming distance and the number of occurrences in the instruction pairing set. A larger pairing instruction, such as selecting 2, 4 or 10 multiplied pairing instructions.

The following is an example of an example of a code profiling step. Take the example of PAC-Lite, one of the processors developed by the Taiwan Industrial Technology Research Institute (ITRI)'s Parallel Architecture Core (PAC) program. PAC-Lite uses a 32-bit fixed bit length instruction set. The format of the instruction can be roughly expressed as: oooo ccc fff dddddd sssssttttt aaaaaa, where the opcode associated with the instruction is o representing the type of the opcode. (type) A total of 4 bits, f represents the function of the opcode (a total of 3 bits). An opcode consists of a type code and a function code, namely oooo fff. The original instruction set of PAC-Lite can be illustrated as Table 1.

For the sake of brevity, the instructions represented by the easy-to-remember code in Table 1 only list the type code, and the instructions of the same type can be arranged according to the instructions in Table 1. The order is defined by the function code corresponding to the instruction, for example, by binary code, Gray code or other means. For example, the opcodes for the NOP and TRAP commands can be defined as 0000 000 and 0000 0001, respectively.

In the following description, it is assumed that the processing unit 10 of FIG. 1 is constructed based on the above-described instruction set of the PAC-Lite. In order to reduce the power consumption caused by frequent bus signal switching actions when the application program is transmitted to the bus 30, the method as shown in FIGS. 5 and 6 is used to generate the instruction code table and the command mapping. Table and object code for this application.

In the following, according to the method of FIG. 6, an example of generating a command code table and a command map table will be described.

According to step S210, the pairing distribution of adjacent instructions of an application is counted (as shown in Table 2), and an instruction pairing set is found accordingly. The "instruction pairs" field in Table 2 indicates two adjacent instructions of an application (for example, in a combined language), such as MOVI.H-MOVI.L, ADD-SRLI, ADD-SLLI; field N Represents the number of occurrences of an instruction pair, where all or some of the adjacent instructions in the application code are counted. The instruction pairing set IP0, for example, contains at least some of the instructions in the original instruction encoding table OIT (as shown in Table 1). The instruction pairing set includes a plurality of instruction pairs of the application with higher usage rate. For example, the statistical distribution of the instruction pairs is sorted according to the level. As shown in Table 2, the instruction pairs with more occurrences (that is, the higher usage rate) can be arranged first, and the instructions with fewer occurrences (that is, the usage rate is lower) can be arranged. Paired in the back.

According to step S220, a plurality of instruction pairs of the higher usage rate in the instruction pairing set IP0 are encoded to give the instruction codes of the respective instructions to be matched, thereby generating a first instruction encoding table IET0 (as shown in Table 3). For example, the first 5 pairs, 10 pairs, or the pair of instructions whose usage rate exceeds one threshold in Table 2 (if the number of occurrences is more than 1000), or all the pairs of instructions in Table 2 are encoded. For example, encoding is started from the instruction pair with the highest usage rate in the instruction pairing set IP0, and then the instruction pair is encoded according to the usage rate. The encoding action here means redefining the opcode of the two instructions in the pair of instructions, such as the type code or function code of the opcode of this example or both, so that the two instructions have similar (ie, the Hamming distance is small) The instruction code. For example, the type codes of the instructions in Table 1, such as MOVI.H, MOVI.L, ADD, SW, SH, have been changed to 0111, 0111, 0011, 0010, and 0010 in Table 3, respectively. Based on this type of code, it is more configurable Function code, so that two adjacent instructions have similar instruction codes. For example, the field T of Table 2 indicates that after the encoding action, for example, the Hamming distance or the toggle count of the instruction to ADD-SRLI is changed from the original 5 (ie, the number in parentheses) to 2, and the instruction is ADD-SLLI. The Hamming distance was changed from 4 to 3. In addition, the first instruction encoding table as shown in Table 3 has the same number of instructions as the original instruction encoding table OIT shown in Table 1, and at least a plurality of instructions (for example, MOVI.H, MOVI.L, ADD, SW) And SH) corresponding to different instruction codes in the first instruction encoding table and the original instruction encoding table.

In addition, according to Table 2, the total toggle count of the instruction pair of the application, that is, the sum of the number of occurrences of all instruction pairs and the number of conversions, is reduced from the original 168968 to 117420 after encoding. That is, it is reduced by 30.50%.

Then, according to step S230, according to the first instruction coding table, find out This instruction pairs the Hamming distances of all paired instructions in IP0 (such as the number of converted instruction pairs in column T of Table 2), and according to the instruction, the Hamming distance and appearance of these pairing instructions The number of times (for example, its product) finds a plurality of instructions IP1 from the instruction pair set IP0. As shown in Table 4, according to the product (P) of the Hamming distance and the number of occurrences of the pairing instruction, the order is sorted from large to small, thereby finding a plurality of pairing instructions (ie, instruction pairs) IP1 having a higher product, for example, taking a product. A higher first 5 pairs, 10 pairs, or a pair of instructions whose product exceeds a threshold (eg, 1000 or more) to perform the repetitive encoding in the next step. For convenience of explanation, in this example, the first four pairs of the number of products in Table 4 are selected (the * is added).

According to step S240, the found commands IP1 are repeatedly encoded to obtain a second command encoding table IET1. For example, as shown in Table 5, the repetitive encoding step gives each of these found instructions IP1 (such as SLLI, ADD, SRLI, SH) at least one additional instruction code. When deciding how to assign additional instruction encoding, set a topological relationship between these found instructions, for example, let the Hamming distance between the SLLI-ADD, ADD-SRLI, and SRLI-SH instructions be 1 Instruction code. In addition, the second instruction encoding table IET1 of this example is extended based on the first instruction encoding table IET0 as shown in Table 3 and includes these additional instruction encodings as shown in Table 5. Thus, the instructions of the repetitive encoding action in the second instruction encoding table have two different instruction encodings, such as the addition operation ADD having two instruction encodings: 0011 000 and 0110 011.

However, the manner in which the repetition coding gives an additional instruction code is not limited to this. For example, the reserved segments or reserved bits in the first instruction encoding table IET0 as shown in Table 3 (such as possible encodings that are not used in some types) may be utilized, and the above-mentioned instructions are found. The set IP1 can also determine the reserved sections to be filled according to a topological relationship, thereby generating an additional instruction code corresponding to the reconfiguration code. In addition, the repetitive coding can also use the reserved section and the extended section (ie, the new type is shown in Table 5) to give additional instruction coding. In addition, when the above-mentioned found instructions are repeatedly coded, each instruction may be given a different or the same number of additional instructions. code. These additional instruction codes may have the same or different type codes, and the topological relationship between these instructions may also correspond to different or the same Hamming distance.

According to step S250, an instruction code mapping table is generated, wherein the instruction code mapping table stores the mapping relationship between the second instruction encoding table IET1 and the original instruction encoding table OIT (as shown in Table 1). For example, as shown in Table 6, the instruction code mapping table stores a mapping relationship that maps a plurality of instruction codes representing the same instruction to an original instruction code, such as the addition instruction ADD, in the second instruction. There are two different encodings in the coding table IET1. In addition, as shown in Table 6, the instruction code mapping table also stores a mapping relationship of a reconfigured coded code pair to an original instruction code, such as an instruction to store a 32-bit block into a data memory. SW.

According to the second instruction encoding table IET1 of the above example, the total number of conversions of the instruction pair of the application is further reduced from the original 168968 to 73740 after the repeated encoding, that is, the reduction is 56.36%.

Therefore, the processing unit 10 implemented by the original instruction encoding table of the processor PAC-Lite can execute the second instruction according to the example by the instruction mapping module 110 according to the instruction code mapping table generated by the foregoing example. The object code of the application generated by the encoding table IET1. Application therefore The Hamming distance of the two adjacent execution codes in the execution code of the formula is less than the Hamming distance of the execution code of the two neighbors converted by the module 110 according to the instruction code mapping table, and the execution code A lower switching loss will occur when transmitting on the bus 30, thereby helping to reduce the power consumption of the electronic device of the processing unit 10 when executing the application.

In addition to the above description of the instruction set using the PAC-Lite processor, the above embodiments of the method shown in Figures 5 and 6 can be applied to other suitable instruction set architectures, such as 32-bit MIPS processors. The instruction set of the fixed-length code, for example, its instruction format can be expressed as: ooooooss sssttttt dddddaaa aaffffff, related to the instruction are o:opcode (6-bit) and f:function (6-bit). Another example is ARM's 32-bit instruction set architecture or other instruction set architecture such as 32 or 64 bits. We can use the method of the embodiment and the instruction set architecture of the electronic device on other processors in a manner similar to the above examples.

The embodiment of the above code profiling step S20 is exemplified by the second instruction encoding table. However, the implementation is not limited thereto. As in some embodiments, the code profiling step S20 may be implemented to generate a first instruction encoding table (IET0) based on steps S210 and S220, and generate an instruction code mapping table based on the first instruction encoding table, where the first instruction The code table (IET0) is used by the compiler to generate the execution code of the application. The code map maps the first instruction code table (IET0) to the original instruction code table (OIT). The relationship. In addition, in some embodiments, the code profiling step S20 may be implemented in other manners, for example, based on steps S210, S230 to S250, wherein the first instruction encoding table according to the original step S230 may use the original instruction encoding table. instead. Again The embodiments different from FIG. 6 can be further optimized or processed to generate a new instruction code table, and an instruction code mapping table is generated through step S250.

Furthermore, other embodiments further disclose a computer or computing device readable information storage medium having a code or one or more program modules stored thereon, and the execution of the code can implement the above implementation, for example, FIG. A reconfigured instruction encoding method, wherein the code profiling step can be implemented in accordance with FIG. 6 or other embodiments. The readable information storage media of these embodiments are, for example but not limited to: optical information storage media, magnetic information storage media or memory such as a memory card, firmware or ROM or RAM or a programmable microcontroller Built-in memory. Additionally, the methods described above can be implemented as a library of one or more application interfaces. According to the foregoing embodiment, the code stored in the information storage medium or the one or more program modules can be implemented as a compiler or as one or more software modules used by a compiler.

In summary, although the above is disclosed in the embodiments, it is not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

1‧‧‧ hardware architecture

10‧‧‧Processing unit

20‧‧‧ memory unit

30‧‧‧ Busbars

100‧‧‧Command capture module

110, 300, 410‧‧‧ instruction mapping module

120‧‧‧Instruction Decoding Module

130‧‧‧Execution module

210‧‧‧ instruction code mapping

220‧‧‧Application execution code

310‧‧‧ memory

320‧‧‧Control circuit

400‧‧‧Command capture module

420‧‧‧Multiplexer

S10, S20, S110-S140, S210-S250‧‧‧ steps

Figure 1 is a block diagram of one embodiment of a hardware architecture for reconfigurable instruction encoding.

Figure 2 is an embodiment of a reconfigurable instruction execution method flow chart.

Figure 3 is a circuit block diagram of an embodiment of the command mapping module of Figure 1.

Figure 4 is a block diagram of another embodiment of a processor architecture for reconfigurable instruction encoding.

Figure 5 is a flow diagram of one embodiment of a reconfigurable instruction encoding method.

Figure 6 is a flow chart showing an embodiment of the code profile analysis step of Figure 5.

1‧‧‧ hardware architecture

10‧‧‧Processing unit

20‧‧‧ memory unit

30‧‧‧ Busbars

100‧‧‧Command capture module

110‧‧‧Command mapping module

120‧‧‧Instruction Decoding Module

130‧‧‧Execution module

210‧‧‧ instruction code mapping

220‧‧‧Application execution code

Claims (22)

A reconfigurable instruction execution method, implemented in an electronic device, comprising: loading a command code mapping table to a processing unit of the electronic device, wherein the processing unit comprises a command mapping module and an instruction decoding module And an execution module; the processing unit captures a first instruction signal of an application; and the module reflects the module, and the first instruction signal is converted into a table according to the instruction code a target instruction signal; and the target instruction signal is decoded by the instruction decoding module, and the decoded target instruction signal is executed by the execution module. The reconfigurable instruction execution method of claim 1, wherein the processing unit obtains the instruction code mapping table from a memory unit of the electronic device and retrieves the first instruction signal, the first instruction The signal represents at least one of a plurality of execution codes of the application. The reconfigurable instruction execution method of claim 1, wherein in the converting step, the first instruction signal comprises an encoded instruction code, the target instruction signal comprising an original instruction code, the instruction code The mapping table stores the coded instruction code paired as a mapping relationship of the original instruction code; and according to the instruction code, the pair mapping of the table is performed by the instruction mapping module A command signal is converted to the target command signal. The reconfigurable instruction execution method of claim 1, wherein in the converting step, the first instruction signal comprises a The encoded instruction code, the target instruction signal includes an original instruction code, and the instruction code mapping table stores a plurality of different coded instruction code pairs as a multi-to-one mapping relationship of the original instruction code; The mapping of the mapping of the pair of pixels to the table is performed by the instruction mapping module to convert the first instruction signal into the target instruction signal. The reconfigurable instruction execution method of claim 2, wherein the instruction code mapping table stores a function relationship of a plurality of coded instruction codes to a plurality of original instruction codes, and the application program The execution codes are based on the coded instruction codes, and the instructions of the original instruction code are included in one of the processing units. The reconfigurable instruction execution method of claim 5, wherein the coded instruction code has a first plurality of coded instruction codes corresponding to the many-to-one mapping of the original instruction codes. relationship. The reconfigurable instruction execution method of claim 6, wherein the Hamming distance of two adjacent execution codes of the execution codes of the application captured by the processor is less than The command mapping module according to the instruction code maps the Hamming distance of the two adjacent execution codes of the converted table. An electronic device, comprising: a processing unit, configured to perform an instruction execution according to an instruction code, wherein the processing unit comprises: a command mapping module, according to the instruction code mapping table, the processing unit Extracting one of the first command signals into a target command signal; and an instruction decoding module decoding the target command signal; And an execution module, which executes the decoded target command signal. The electronic device of claim 8, further comprising: a memory unit for storing the instruction code mapping table and a plurality of execution codes of an application; wherein the first instruction signal represents the execution code At least one of them. The electronic device of claim 9, wherein the processing unit loads the instruction code mapping table before executing the application according to the instruction code mapping table. The electronic device of claim 8, wherein the command mapping module comprises: a memory; and a control circuit for loading the instruction code in the memory and for The instruction code maps the table and converts the first command signal into the target command signal. The electronic device of claim 8, further comprising: an instruction capture module for capturing the first command signal; and a multiplexer, the plurality of inputs of the multiplexer being coupled The command is directed to the module and the command capture module, and the plurality of outputs of the multiplexer are coupled to the command decode module; wherein the processing unit controls the multiplexer to select the command map according to an indication signal The output of the module and one of the instruction capture modules is used as the output of the multiplexer. An electronic device as claimed in claim 8, wherein the electronic device The instruction code mapping table stores a function relationship of a plurality of coded instruction codes to a plurality of original instruction codes, and the execution code of the application is based on the coded instruction codes, and the original instruction code instructions are Included in one of the processing units of the processing unit. The electronic device of claim 13, wherein the Hamming distance of two adjacent execution codes of the execution codes of the application captured by the processor is less than the module corresponding to the instruction. According to the instruction code, the Hamming distance of the execution code of the two neighbors after the conversion of the table is mapped. A reconfigurable instruction encoding method includes: counting a pairing distribution of adjacent instructions of an application, and finding an instruction pairing set, wherein the instruction pairing set includes a plurality of applications having a higher usage rate Instruction pairing; encoding the pair of instructions for the higher usage rate of the instruction pairing pair to give each instruction a similar instruction encoding, thereby generating an instruction encoding table, wherein the instruction encoding table has the same number as an original instruction encoding table And the at least one of the plurality of instructions corresponding to the instruction encoding table and the original instruction encoding table corresponding to different instruction encoding; and generating an instruction code mapping table, wherein the instruction code mapping table stores the instruction encoding table Reflects the mapping relationship of the original instruction encoding table. The reconfigurable instruction encoding method of claim 15, wherein the step of generating the instruction encoding table comprises: pairing the instructions of the instruction pairing set according to the usage rate according to the highest usage rate. An instruction pairing begins to encode the pair of instructions to give each of the instructions a similar instruction encoding; and encoding the encoded instruction based on the pairing of the instructions to generate the instruction Order the code list. The reconfigurable instruction encoding method as described in claim 15 further includes: compiling and generating an execution code of the application according to the instruction encoding table and the instruction of the application. The reconfigurable instruction encoding method of claim 17, wherein the instruction encoding is performed by encoding the instruction pairing set to give each instruction a similar instruction encoding, thereby generating the instruction encoding table. The method is a first instruction encoding table, and the method further comprises: (b1) finding a Hamming distance of the pairing instruction of the instruction pairing set according to the first instruction encoding table, and matching the pairing according to the instruction pairing set a Hamming distance and an occurrence number of the instruction, finding a plurality of instructions from the instruction pairing set; and (b2) repeatedly encoding the found instructions to obtain a second instruction encoding table, wherein the repeated encoding is assigned to each Identifying at least one additional instruction code, the second instruction coding table extending based on the first instruction code table and including the additional instruction code; wherein the step of generating the instruction code pair table and generating In the step of executing the code of the application, the instruction encoding table is replaced by the second instruction encoding table to perform the steps. The reconfigurable instruction encoding method according to claim 18, wherein in the step (b1), the found instructions are pairs with a larger product of the Hamming distance and the number of occurrences in the pairing of the instruction pair. instruction. The reconfigurable instruction encoding method according to claim 18, wherein in the step of generating an execution code of the application, according to the second instruction encoding table, generating two adjacent instructions of the application Execution code with a small distance. The reconfigurable instruction encoding method according to claim 17, wherein when the execution code of the application is executed on an electronic device based on the original instruction encoding table, the electronic device according to the instruction code mapping table Execute after the execution code of the application is converted. An arithmetic-readable information storage medium having stored thereon a program code for performing the steps of the reconfigurable instruction encoding method of any one of claims 15 to 20.