TW201415658A - Semiconductor device layer and fabricating method thereof - Google Patents

Abstract

A fabricating method of semiconductor device layer is provided. First, a patterned mask is formed on a substrate, wherein the patterned mask has an opening to expose a portion of the substrate. Thereafter, a semiconductor device layer is formed on the substrate which is not covered by the patterned mask, wherein cross-sectional area of the semiconductor device layer located outside the opening is gradually increased as the height thereof is increased. Afterwards, the patterned mask is removed.

Description

Semiconductor element layer and method of manufacturing same

The present invention relates to a semiconductor device layer, and more particularly to a semiconductor device layer having good photoelectric conversion efficiency.

With the advancement of semiconductor technology, today's light-emitting diodes have high-intensity output, and the light-emitting diodes have the advantages of power saving, small size, low voltage driving, and no mercury, so the light-emitting diode has Widely used in the field of display and lighting. In general, the luminous efficiency of a light-emitting diode mainly depends on the internal quantum efficiency of the light-emitting layer and the external quantum efficiency, that is, the light extraction efficiency. The increase in internal quantum efficiency depends on the epitaxial quality of the semiconductor layer and the film stacking of the semiconductor layer, and the increase in external quantum efficiency depends on whether the light emitted by the LED chip can be effectively guided out. In other words, the external quantum efficiency is related to other optical designs outside the LED array.

1 is a schematic cross-sectional view of a conventional light-emitting diode wafer. Referring to FIG. 1 , a conventional LED chip 100 includes a substrate 110 , a semiconductor device layer 120 , and a semiconductor device An N-type electrode 130a and a P-type electrode 130b. The semiconductor device layer 120 is disposed on the substrate 110, and the semiconductor device layer 120 includes an N-type semiconductor layer 122, a light-emitting layer 124, and a P-type semiconductor layer 126. The N-type semiconductor layer 122 is disposed on the substrate 110, and the light-emitting layer 124 is disposed. The P-type semiconductor layer 126 is disposed on a portion of the N-type semiconductor layer 122, and the P-type semiconductor layer 126 is disposed on the light-emitting layer 124. In addition, the N-type electrode 130a is disposed on the N-type semiconductor layer 122 and electrically connected to the N-type semiconductor layer 122, and the P-type electrode 130b is disposed on the P-type semiconductor layer 126 and electrically connected to the P-type semiconductor layer 126. connection.

As can be seen from FIG. 1, the light emitted by the light-emitting layer 124 in the LED wafer 100 is transmitted in various directions. However, a part of the light may cause total reflection inside the LED wafer, and the resulting Light loss will greatly reduce the luminous efficiency of the light-emitting diode wafer. Therefore, how to improve the structure of the light-emitting diode wafer, to reduce the chance of the light emitted by the light-emitting layer to generate total reflection in the light-emitting diode wafer and to improve the luminous efficiency of the light-emitting diode wafer, the designer must face One of the topics.

The present invention provides a semiconductor device layer and a method of manufacturing the same.

The present invention proposes a method of manufacturing a semiconductor element layer. First, a patterned mask layer is formed on a substrate, wherein the patterned mask layer has an opening to expose a portion of the substrate. Then, a semiconductor device layer is formed on the substrate not covered by the patterned mask layer, wherein the semiconductor device layer outside the opening has different cross-sectional areas at different heights, and the cross-sectional area of the semiconductor device layer outside the opening Decrease as the height of the place increases. Then, remove the patterned mask layer.

In an embodiment of the invention, the semiconductor device layer located in the opening has different cross-sectional areas at different heights, and the cross-sectional area of the semiconductor device layer located in the opening The height of the place increases and increases. In one embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area area. In another embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area .

In an embodiment of the invention, the semiconductor device layer located in the opening has the same cross-sectional area at different heights, and the cross-sectional area of the semiconductor device layer located in the opening is maintained constant as the height is increased, so as to be located at the opening. The sidewalls of the inner semiconductor device layer are substantially perpendicular to the surface of the substrate. In one embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area area. In another embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area .

In an embodiment of the invention, the semiconductor device layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer stacked in sequence. In one embodiment, the luminescent layer described above is formed within the opening. In another embodiment, the luminescent layer described above is formed outside the opening.

In an embodiment of the invention, the epitaxial rate of the semiconductor device layer on the substrate is greater than the epitaxial rate on the patterned mask layer.

In an embodiment of the invention, the material of the patterned mask layer comprises yttrium oxide, tantalum nitride, gallium oxide, titanium oxide or magnesium nitride.

In an embodiment of the invention, the patterned mask layer further comprises a plurality of A protrusion located in the opening, the protrusion being located on the substrate exposed by the opening, and the protrusion being covered by the semiconductor element layer.

The present invention proposes another method of manufacturing a semiconductor element layer. First, a semiconductor layer is formed on a substrate. Next, a patterned mask layer is formed on the semiconductor layer, wherein the patterned mask layer has an opening to expose a portion of the semiconductor layer. Then, a semiconductor device layer is formed on the semiconductor layer not covered by the patterned mask layer, wherein the semiconductor device layer outside the opening has different cross-sectional areas at different heights, and the cross-sectional area of the semiconductor device layer outside the opening Decreased as the height of the place increases. The patterned mask layer is then removed.

In an embodiment of the invention, the layers of semiconductor elements located within the openings have different cross-sectional areas at different heights, and the cross-sectional area of the layers of semiconductor elements located within the openings increases as the height of the layers increases. In one embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area area. In another embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area .

In an embodiment of the invention, the semiconductor device layer located in the opening has the same cross-sectional area at different heights, and the cross-sectional area of the semiconductor device layer located in the opening is maintained constant as the height is increased, so as to be located at the opening. The sidewall of the semiconductor element layer within is substantially perpendicular to the surface of the semiconductor layer. In one embodiment, the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area area. In another embodiment, the semiconductor device layer outside the opening has a first maximum The cross-sectional area, and the semiconductor element layer located in the opening has a second maximum cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area.

In an embodiment of the invention, the semiconductor device layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer stacked in sequence. In one embodiment, the luminescent layer described above is formed within the opening. In another embodiment, the luminescent layer described above is formed outside the opening.

In an embodiment of the invention, the semiconductor layer has the same conductivity type as the first type doped semiconductor layer.

In an embodiment of the invention, the epitaxial rate of the semiconductor device layer on the semiconductor layer is greater than the epitaxial rate on the patterned mask layer.

In an embodiment of the invention, the material of the patterned mask layer comprises yttrium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride.

In an embodiment of the invention, the patterned mask layer further includes a plurality of protrusions located in the openings, the protrusions being located on the semiconductor layer exposed by the openings, and the protrusions being covered by the semiconductor element layer.

The invention further provides a semiconductor device layer comprising a first portion and a second portion, wherein the second portion is located on the first portion, the second portion has different cross-sectional areas at different heights, and the cross-sectional area of the second portion follows Decrease in height.

In an embodiment of the invention, the first portion has different cross-sectional areas at different heights, and the cross-sectional area of the first portion increases as the height increases. In one embodiment, the second portion has a first maximum cross-sectional area and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. In another embodiment, the second portion has a first maximum cross-sectional area, and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area product. Further, the second portion has a top surface, and the top surface is, for example, a curved surface.

In an embodiment of the invention, the first portion has the same cross-sectional area at different heights, and the cross-sectional area of the first portion is maintained constant as the height of the portion increases. In one embodiment, the second portion has a first maximum cross-sectional area and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. In another embodiment, the second portion has a first maximum cross-sectional area and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second largest cross-sectional area. Further, the second portion has a top surface, and the top surface is, for example, a curved surface.

In an embodiment of the invention, the first portion and the second portion include a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer stacked in sequence. In a preferred embodiment, the luminescent layer is located in the first portion. In another embodiment, the luminescent layer shape described above is located in the second portion.

In an embodiment of the invention, the semiconductor device layer further includes a plurality of protrusions embedded in the first portion. In a preferred embodiment, the material of the protrusions includes yttrium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride.

In the method of fabricating the semiconductor device layer of the present invention, the semiconductor element layer is formed in the opening of the patterned mask layer such that the cross-sectional area of the semiconductor element layer outside the opening decreases as the height of the layer increases.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Light Diode Wafer

110‧‧‧Substrate

120‧‧‧Semiconductor component layer

122‧‧‧N type semiconductor layer

124‧‧‧Lighting layer

126‧‧‧P type semiconductor layer

130a‧‧‧N type electrode

130b‧‧‧P type electrode

200, 200a, 200b, 200c, 200d‧‧‧ light emitting diode chips

210‧‧‧Substrate

220‧‧‧Semiconductor layer

222‧‧‧ patterned mask layer

224‧‧‧ openings

226‧‧‧ side wall

228‧‧‧ Protrusion

230‧‧‧Semiconductor component layer

230a‧‧‧Part I

230b‧‧‧Part II

232‧‧‧First type doped semiconductor layer

234‧‧‧Lighting layer

236‧‧‧Second type doped semiconductor layer

240a‧‧‧electrode

240b‧‧‧electrode

260‧‧‧current dispersion layer

300, 300a, 300b, 300c, 300d‧‧‧ light emitting diode chips

400‧‧‧High power LED chip

C, C ₁ , C ₂ ‧ ‧ turning points

S‧‧‧ side wall

Wmax ₁ ‧‧‧Maximum cross-sectional area of the first part

Wmax ₂ ‧‧‧The maximum cross-sectional area of the second part

1 is a schematic cross-sectional view of a conventional light-emitting diode wafer.

2 and 2' are schematic cross-sectional views showing a light emitting diode wafer according to a first embodiment of the present invention.

3 is a flow chart showing a method of manufacturing a light-emitting diode wafer according to a first embodiment of the present invention.

4A to 4D are schematic cross-sectional views showing a process of manufacturing a light-emitting diode wafer according to a first embodiment of the present invention.

5 and 5' are schematic cross-sectional views showing a light emitting diode wafer according to a second embodiment of the present invention.

6 and 6' are schematic cross-sectional views showing a light emitting diode wafer according to a third embodiment of the present invention.

7 and 7' are schematic cross-sectional views showing a light emitting diode wafer according to a fourth embodiment of the present invention.

8 and 8' are schematic cross-sectional views showing a light emitting diode wafer according to a fifth embodiment of the present invention.

9 and 9' are schematic cross-sectional views showing a light emitting diode wafer according to a sixth embodiment of the present invention.

Fig. 10 is a flow chart showing a method of manufacturing a light-emitting diode wafer according to a sixth embodiment of the present invention.

11A to 11E are schematic cross-sectional views showing a flow of a method of manufacturing a light-emitting diode wafer according to a sixth embodiment of the present invention.

12 and 12' are schematic cross-sectional views showing a light emitting diode wafer according to a seventh embodiment of the present invention.

13 and FIG. 13' are cross-sectional views showing a light emitting diode wafer according to an eighth embodiment of the present invention; intention.

14 and 14' are schematic cross-sectional views showing a light emitting diode wafer according to a ninth embodiment of the present invention.

15 and 15' are schematic cross-sectional views showing a light emitting diode wafer according to a tenth embodiment of the present invention.

16A and 16B are a top view and a cross-sectional view, respectively, of a high power LED chip of an eleventh embodiment of the present invention.

In the light-emitting diode wafer of the present invention, the shape of the semiconductor element layer is defined by the cross-sectional area of the semiconductor element layer, wherein all the cross-sectional areas refer to the cross-sectional area perpendicular to the height direction.

[First Embodiment]

2 is a cross-sectional view showing a light emitting diode wafer according to a first embodiment of the present invention. Referring to FIG. 2, the LED assembly 200 of the present embodiment includes a substrate 210, a semiconductor layer 220, a semiconductor device layer 230, a first electrode 240a, and a second electrode 240b.

In general, the substrate 210 is mostly selected from materials having good light transmittance and heat dissipation characteristics, and is, for example, a sapphire substrate, a SiC substrate, a bismuth (Si) substrate, a gallium arsenide (GaAs) substrate, or the like. Gallium oxide, gallium nitride (GaN), lithium aluminate (LiAlO 2 ) substrate, lithium gallium silicate (LiGaO 2 ) substrate, aluminum nitride (AlN) substrate or other substrate suitable for epitaxy. In the embodiment, the semiconductor layer 220 is disposed on the substrate 210.

The semiconductor element layer 230 is disposed on the semiconductor layer 220. The semiconductor device layer 230 includes a first portion 230a and a second portion 230b, wherein the second portion 230b is located on the first portion 230a. The first portion 230a has, for example, the same cross-sectional area at different heights. In other words, the sidewall S of the first portion 230a is substantially perpendicular to the surface of the semiconductor layer 220. The second portion 230b has different cross-sectional areas at different heights, and the cross-sectional area of the second portion 230b decreases as the height of the portion increases. That is, in the direction away from the substrate 210, the cross-sectional area of the semiconductor element layer 230 is first maintained constant, and then gradually decreases, and the semiconductor element layer 230 has a turning point C which is located at the boundary between the first portion 230a and the second portion 230b. At the office. In other words, the maximum cross-sectional area Wmax _{2 of the} second portion 230b is substantially equal to the maximum cross-sectional area Wmax _{1 of the} first portion 230a.

In addition, the semiconductor device layer 230 including the first portion 230a and the second portion 230b includes a first type doped semiconductor layer 232, a light emitting layer 234, and a second type doped semiconductor layer 236 which are sequentially stacked. In the present embodiment, the first type doped semiconductor layer 232 is located in the first portion 230a, and the light emitting layer 234 and the second type doped semiconductor layer 236 are located in the second portion 230b. Of course, in another embodiment, the light emitting layer may also be located in the first portion, or the second type doped semiconductor layer may also be located in the first portion. In other words, the present invention does not limit the first type doped semiconductor layer, the light emitting layer, and the first The arrangement of the doped semiconductor layer in the semiconductor device layer. Furthermore, in the present embodiment, the semiconductor layer 220 and the first type doped semiconductor layer 232 have the same conductivity type, for example, the same N-type semiconductor layer, the luminescent layer 234 is a multiple quantum well luminescent layer, and the second The doped semiconductor layer 236 is a P-type semiconductor layer. Of course, in other embodiments, the semiconductor layer and the first type semiconductor layer may also be the P type semiconductor layer, and the second type semiconductor layer may be the N type semiconductor layer.

In this embodiment, in order to further improve the luminous efficiency of the LED wafer 200, the LED array 200 further includes a current dispersion layer 260 disposed on the second type doped semiconductor layer 236 and the second electrode 240b. between. The material of the current dispersion layer 260 is, for example, indium tin oxide, indium zinc oxide, indium tin zinc oxide, cerium oxide, zinc oxide, zinc gallium oxide, aluminum zinc oxide, cadmium tin oxide, cadmium zinc oxide, Or other suitable material material.

As shown in FIG. 2, the first electrode 240a is disposed on the semiconductor layer 220 and electrically connected to the semiconductor layer 220, wherein the semiconductor layer 220 has the same conductive shape as the first type doped semiconductor layer 232. The second electrode 240b is disposed on the second portion 230b and electrically connected to the second type doped semiconductor layer 236 via the current dispersion layer 260.

In the present embodiment, the light emitted by the light-emitting layer 234 can be effectively guided out of the light-emitting diode wafer 200 by the sidewall of the semiconductor device layer 230. In other words, the configuration of the semiconductor device layer 230 can reduce the chance of the total light reflection in the light-emitting diode wafer 200 caused by the light emitted from the light-emitting layer 234, so that the light extraction efficiency of the light-emitting diode wafer 200 is greatly increased. . Therefore, the light emitting diode wafer 200 has good luminous efficiency.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 2'. As can be seen from FIG. 2', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

The formation mechanism of the concave curved surface described above is described as follows. Taking organometallic vapor phase epitaxy as an example, in the process of semiconductor epitaxial growth, the growth rate of the epitaxial film is proportional to the concentration of the gas phase reactant, and in the mask layer of this embodiment, it is almost impossible to grow up. In the crystal film, the epitaxial film can be smoothly grown only at the opening of the mask layer. On the other hand, the migration rate (or diffusion length) of the gas phase reactant introduced during epitaxial growth is related to the growth temperature, pressure or different gas phase reactant concentration ratio, and thus, it is caused to be close to the mask. The rate of growth of the epitaxial film at the layer/opening junction is greater than the rate of growth at the center of the opening, The top surface of the second part is made into a concave surface. In other words, the center position of the top surface has a height difference from the edge, and the height difference can be controlled by the size of the opening of the mask layer, in addition to being controlled by the epitaxial growth condition. It is worth noting that when the opening size is large, the height difference between the center and the edge position of the epitaxial layer is large. Conversely, when the opening size is small, the height difference between the center and the edge position of the epitaxial layer is small.

Only the structure of the light-emitting diode wafer 200 of the present embodiment will be described above. Next, a method of manufacturing the light-emitting diode wafer 200 will be described in detail with reference to FIGS. 3 and 4A to 4D.

3 is a flow chart showing a method of manufacturing a light-emitting diode wafer according to a first embodiment of the present invention. 4A to 4D are schematic cross-sectional views showing a process of manufacturing a light-emitting diode wafer according to a first embodiment of the present invention.

Referring to FIG. 3 and FIG. 4A simultaneously, first, in step S300, the semiconductor layer 220 is formed on the substrate 210. The method of forming the semiconductor layer 220 is, for example, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxial (MBE) method, or other suitable epitaxial growth method.

Next, in step S310, a patterned mask layer 222 is formed on the semiconductor layer 220, wherein the patterned mask layer 222 has an opening 224 to expose a portion of the semiconductor layer 220. The method for forming the patterned mask layer 222 is, for example, sequentially forming a mask material layer (not shown) on the semiconductor layer 220 and a photoresist layer (not shown) having an opening pattern, and then using the photoresist layer as a mask. A portion of the mask material layer is removed to form a patterned mask layer 222 having openings 224. The material of the patterned mask layer 222 is, for example, hafnium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride.

Please refer to FIG. 3 and FIG. 4B at the same time, and then proceed to step S320. A semiconductor device layer 230 is formed on the semiconductor layer 220 covered by the mask layer 222. In detail, the patterned mask layer 222 is used as a mask, and an epitaxial process is performed on the semiconductor layer 220 to form a first portion 230a located in the opening 224 and a second portion 230b outside the opening 224. The epitaxial rate of the semiconductor device layer 230 on the semiconductor layer 220 is greater than the epitaxial rate on the patterned mask layer 222. In this embodiment, the sidewall 226 of the patterned mask layer 222 is substantially perpendicular to the surface of the semiconductor layer 220. Therefore, the cross-sectional area of the semiconductor device layer in the opening 224 is maintained constant as the height is increased to form a portion. The first part 230a. The cross-sectional area of the semiconductor element layer outside the opening 224 may decrease as the height of the layer increases to form the second portion 230b. The semiconductor device layer 230 including the first portion 230a and the second portion 230b includes a first type doped semiconductor layer 232, a light emitting layer 234, and a second type doped semiconductor layer 236 which are sequentially stacked.

Please refer to FIG. 3 and FIG. 4C at the same time, and then proceed to step S330 to remove the patterned mask layer 222. A method of removing the patterned mask layer 222 is, for example, a wet etching method. Next, in order to improve the light-emitting efficiency of the light-emitting diode, the current dispersion layer 260 may be formed on the second-type doped semiconductor layer 236 before forming the second electrode electrically connected to the second-type doped semiconductor layer 236.

Referring to FIG. 3 and FIG. 4D simultaneously, in step S340, a plurality of electrodes 240a, 240b are formed to be electrically connected to one of the semiconductor layer 220 and the semiconductor device layer 230, respectively, to complete the LED array. 200 production. In detail, the first electrode 240a and the second electrode 240b are formed on the semiconductor layer 220 and the current dispersion layer 260, wherein the first electrode 240a is electrically connected to the semiconductor layer 220, and the second electrode 240b is doped with the second type. The semiconductor layer 236 is electrically connected.

Generally, in a conventional process of a light-emitting diode wafer, a first type doped semiconductor material layer, a luminescent material layer, and a second type doped half are sequentially stacked on a substrate. a layer of conductive material, and then removing a portion of the first type doped semiconductor material layer, a portion of the luminescent material layer, and a portion of the second type doped semiconductor material layer in a manner such as a dry etching process to form a semiconductor device layer And exposing the first type doped semiconductor layer to be electrically connected to the electrode. However, in the present invention, by performing an epitaxial process on the substrate exposed by the opening, that is, completing the fabrication of the semiconductor device layer, and making the semiconductor device layer have a special configuration, the light emitted by the light-emitting layer can be effectively guided. Photodiode wafer. In other words, in the present embodiment, the method of fabricating the LED wafer has the feature of simplifying the process steps.

[Second embodiment]

FIG. 5 is a cross-sectional view showing a light emitting diode wafer according to a second embodiment of the present invention. Referring to FIG. 5, in the present embodiment, the structure and manufacturing method of the LED array 200a are similar to those of the LED array 200 of the first embodiment, and the following is only for the second embodiment and the second embodiment. The main differences of an embodiment are explained.

In the present embodiment, the maximum cross-sectional area Wmax ₂ of the second portion 230b of the semiconductor element layer 230 is greater than the maximum cross-sectional area Wmax _{1 of the} first portion 230a. That is, the semiconductor element layer 230 has two transition points C ₁ , C ₂ . In detail, during the fabrication of the semiconductor device layer 230, the parameters of the epitaxial process or the thickness of the patterned mask layer (not shown) are adjusted, for example, to make the thickness of the patterned mask layer (not shown). Less than the thickness of the patterned mask layer 220 depicted in FIG. 4A, the profile of the semiconductor device layer 230 can be controlled.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 5'. As can be seen from FIG. 5', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Third embodiment]

Figure 6 is a cross-sectional view showing a light emitting diode wafer according to a third embodiment of the present invention. Referring to FIG. 6 , in the embodiment, the structure and manufacturing method of the LED array 200b are similar to the structure and manufacturing method of the LED array 200 of the first embodiment, and the following is only for the third embodiment and the third embodiment. The main differences of an embodiment are explained.

In the present embodiment, the side wall S of the first portion 230a is sandwiched by an angle θ with the surface of the semiconductor layer 220. Moreover, the maximum cross-sectional area Wmax _{2 of the} second portion 230b is substantially equal to the maximum cross-sectional area Wmax _{1 of the} first portion 230a. That is, in the direction away from the substrate 210, the cross-sectional area of the semiconductor element layer 230 is first increased, and then decreased, and the semiconductor element layer 230 has the turning point C. In detail, in the process of the LED package 200b, the sidewall of the patterned mask layer (not shown) used is, for example, at an angle to the surface of the semiconductor layer such that the first portion 230a in the opening is cut. The area increases as the height increases.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 6'. As can be seen from FIG. 6', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

Fourth Embodiment

Fig. 7 is a cross-sectional view showing a light emitting diode wafer according to a fourth embodiment of the present invention. Referring to FIG. 7, in the present embodiment, the structure and manufacturing method of the LED wafer 200c are similar to those of the LED sub-200b of the third embodiment, and the following is only for the fourth embodiment and the The main differences between the three embodiments are explained.

In the present embodiment, the sidewall S of the first portion 230a is at an angle θ with the surface of the semiconductor layer 220, and the cross-sectional area of the first portion 230a is increased as the height of the portion is increased. Further, the maximum cross-sectional area Wmax _{2 of the} second portion 230b is greater than the maximum cross-sectional area Wmax _{1 of the} first portion 230a. That is, the semiconductor element layer 230 has two transition points C ₁ , C ₂ . In detail, in the process of the LED package 200c, the sidewall of the patterned mask layer (not shown) is used at an angle to the surface of the semiconductor layer, and the thickness of the patterned mask layer is, for example, less than The thickness of the patterned mask layer used to fabricate the light-emitting diode wafer 200b of the third embodiment.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 7'. As can be seen from FIG. 7', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Fifth Embodiment]

Figure 8 is a cross-sectional view showing a light emitting diode wafer according to a fifth embodiment of the present invention. Referring to FIG. 8 , in the embodiment, the structure and manufacturing method of the LED wafer 200 d are similar to the structure and manufacturing method of the LED array 200 of the first embodiment, and the following is only for the fifth embodiment and the first embodiment. The main differences of an embodiment are explained.

In the embodiment, the LED array 200d further includes a plurality of protrusions 228. The protrusion 228 is disposed between the semiconductor layer 220 and the first portion 230a, and the material thereof is, for example, hafnium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride. The protrusions 228 allow the light emitted from the light-emitting layer 234 of the light-emitting diode wafer 200d to be more easily scattered to further enhance the light-emitting efficiency of the light-emitting diode wafer 200d. In detail, the process of the LED chip 200d The patterned mask layer (not shown) used further includes a plurality of protrusions located in the openings, and the protrusions are located on the semiconductor layer exposed by the openings. The method for forming the patterned mask layer is, for example, sequentially forming a mask material layer and a photoresist layer on the semiconductor layer, wherein the photoresist layer has an opening pattern and a protrusion pattern, and the protrusion pattern is located in the opening pattern, and then the photoresist layer For the mask, a portion of the mask material layer is removed to form a patterned mask layer having openings and protrusions. It should be noted that in other embodiments, the LED chip may also be provided with protrusions to further improve the luminous efficiency of the LED wafer.

In the above embodiments, the light emitting diode wafers 200, 200a, 200b, 200c, and 200d include the substrate 210 and the semiconductor layer 220, and the first electrode 240a is disposed on the semiconductor layer 220. However, the present invention Not limited to this. In the sixth to tenth embodiments to be described later, the LED chips 300, 300a, 300b, 300c, and 300d do not include the substrate and the semiconductor layer, and the LED chips 300, 300a, and 300b, The electrodes 240a, 240b of 300c, 300d are in an upright distribution.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 8'. As can be seen from FIG. 8', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Sixth embodiment]

Figure 9 is a cross-sectional view showing a light emitting diode wafer according to a sixth embodiment of the present invention. Referring to FIG. 9, in the present embodiment, the LED array 300 includes a semiconductor element layer 230, a first electrode 240a, and a second electrode 240b. The structure of the semiconductor element layer 230 is similar to that of the semiconductor element layer 230 in FIG. 2, and can be referred to the first embodiment. In short, the semiconductor device layer 230 includes a first portion 230a and a second portion 230b, and the semiconductor device layer 230 includes a first type doped semiconductor layer 232, a light emitting layer 234, and a second type doped semiconductor stacked in sequence. Layer 236. It should be noted that, in this embodiment, the first electrode 240a and the second electrode 240b are in an upright distribution, and the first electrode 240a is disposed on the first portion 230a and electrically connected to the first type doped semiconductor layer 232. The second electrode 240b is disposed on the second portion 230b and electrically connected to the second type doped semiconductor layer 234. In addition, the LED wafer 300 further includes a current dispersion layer 260 disposed between the second type doped semiconductor layer 236 and the second electrode 240b.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 9'. As can be seen from FIG. 9', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

Next, a method of manufacturing the light-emitting diode wafer 300 will be described with reference to FIGS. 10 and 11A to 11E.

Fig. 10 is a flow chart showing a method of manufacturing a light-emitting diode wafer according to a sixth embodiment of the present invention. 11A to 11E are schematic cross-sectional views showing a flow of a method of manufacturing a light-emitting diode wafer according to a sixth embodiment of the present invention.

Referring to FIG. 10 and FIG. 11A simultaneously, first, step S400 is performed to form a patterned mask layer 222 on the substrate 210, wherein the patterned mask layer 222 has an opening 224 to expose a portion of the substrate 210. The method for forming the patterned mask layer 222 is, for example, sequentially forming a mask material layer (not shown) on the substrate 210 and a photoresist layer (not shown) having an opening pattern, and then using the photoresist layer as a mask. Removing a portion of the mask material layer to form an opening Patterned mask layer 222 of 224. The material of the patterned mask layer 222 is, for example, hafnium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride.

Referring to FIG. 10 and FIG. 11B simultaneously, then step S410 is performed to form the semiconductor device layer 230 on the substrate 210 not covered by the patterned mask layer 222. In detail, the patterned mask layer 222 is used as a mask to perform an epitaxial process on the substrate 210 to form a first portion 230a located within the opening 224 and a second portion 230b outside the opening 224. The epitaxial rate of the semiconductor device layer 230 on the substrate 210 is greater than the epitaxial rate on the patterned mask layer 222. In this embodiment, the sidewall 226 of the patterned mask layer 222 is substantially perpendicular to the surface of the substrate 210. Therefore, the cross-sectional area of the semiconductor device layer in the opening 224 is maintained constant as the height of the substrate is increased to form a Part 230a. The cross-sectional area of the semiconductor element layer outside the opening 224 may decrease as the height of the layer increases to form the second portion 230b. The semiconductor device layer 230 including the first portion 230a and the second portion 230b includes a first type doped semiconductor layer 232, a light emitting layer 234, and a second type doped semiconductor layer 236 which are sequentially stacked.

Please refer to FIG. 10 and FIG. 11C at the same time, and then proceed to step S420 to remove the patterned mask layer 222. A method of removing the patterned mask layer 222 is, for example, a wet etching method.

Referring to FIG. 10 and FIG. 11D simultaneously, step S430 is performed to remove the substrate 210 to expose the semiconductor device layer 230, that is, expose the first type doped semiconductor layer 232. The method of removing the substrate 210 is, for example, a laser lift-off process. In addition, in order to improve the light-emitting efficiency of the light-emitting diode, the current dispersion layer 260 may be formed on the second-type doped semiconductor layer 236 before forming the second electrode electrically connected to the second-type doped semiconductor layer 236.

Referring to FIG. 10 and FIG. 11E simultaneously, step S440 is performed to form a plurality of electrodes 240a and 240b electrically connected to the semiconductor device layer 230 to complete the light emitting diode. Fabrication of bulk wafer 300. In detail, the first electrode 240a and the second electrode 240b are formed on the first type doped semiconductor layer 232 and the current dispersion layer 260, respectively. The first electrode 240a is electrically connected to the first type doped semiconductor layer 232, and the second electrode 240b is electrically connected to the second type doped semiconductor layer 236.

In the present embodiment, the light emitted by the light-emitting layer 234 can be effectively guided out of the light-emitting diode wafer 300 by the sidewall of the semiconductor device layer 230. In other words, the configuration of the semiconductor device layer 230 can reduce the chance of the total light reflection in the light-emitting diode wafer 300 caused by the light emitted from the light-emitting layer 234, so that the light extraction efficiency of the light-emitting diode wafer 300 is greatly increased. . Therefore, the light emitting diode wafer 300 has good luminous efficiency.

[Seventh embodiment]

Figure 12 is a cross-sectional view showing a light emitting diode wafer in accordance with a seventh embodiment of the present invention. Referring to FIG. 12, in the present embodiment, the structure and manufacturing method of the LED array 300a are similar to those of the LED array 300 of the sixth embodiment, and the following is only for the seventh embodiment and the The main differences between the six embodiments are explained.

In this embodiment, during the fabrication of the semiconductor device layer 230, the parameters of the epitaxial process or the thickness of the patterned mask layer (not shown) are adjusted, for example, to make a patterned mask layer (not shown). The thickness of the patterned mask layer 220 is less than that of the patterned mask layer 220 shown in FIG. 11A to form the semiconductor device layer 230 as shown in FIG. The structure of the semiconductor device layer 230 is similar to that of the semiconductor device layer 230 of the light-emitting diode wafer 200a described in the second embodiment, and can be referred to the second embodiment, and will not be described herein.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface, such as Figure 12' is shown. As can be seen from FIG. 12', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Eighth Embodiment]

Figure 13 is a cross-sectional view showing a light emitting diode wafer according to an eighth embodiment of the present invention. Referring to FIG. 13, in the present embodiment, the structure and manufacturing method of the LED wafer 300b are similar to those of the LED array 300 of the sixth embodiment, and only the eighth embodiment and the The main differences between the six embodiments are explained.

In the process of the LED array 300b, the sidewall of the patterned mask layer (not shown) is, for example, at an angle to the surface of the substrate (not shown) such that the first portion 230a within the opening is cut. The area is increased as the height is increased to form the semiconductor element layer 230 as shown in FIG. The structure of the semiconductor device layer 230 is similar to that of the semiconductor device layer 230 of the LED package 200b described in the third embodiment, and can be referred to the third embodiment, and will not be described herein.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 13'. As can be seen from FIG. 13', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

Ninth Embodiment

Figure 14 is a cross-sectional view showing a light emitting diode wafer according to a ninth embodiment of the present invention. Referring to FIG. 14, in the embodiment, the structure and manufacturing method of the LED wafer 300c are similar to the structure and manufacturing method of the LED array 300 of the sixth embodiment, Only the main differences between the ninth embodiment and the sixth embodiment will be described below.

In the process of the LED array 300c, the sidewall of the patterned mask layer (not shown) is at an angle to the surface of the substrate (not shown), and the thickness of the patterned mask layer is, for example, less than The thickness of the patterned mask layer 220 of the light-emitting diode wafer 300 of the sixth embodiment is used to form the semiconductor device layer 230 as shown in FIG. The structure of the semiconductor device layer 230 is similar to that of the semiconductor device layer 230 of the light-emitting diode wafer 200c described in the fourth embodiment, and can be referred to the fourth embodiment, and will not be described herein.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 14'. As can be seen from FIG. 14', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Tenth embodiment]

Figure 15 is a cross-sectional view showing a light emitting diode wafer according to a tenth embodiment of the present invention. Referring to FIG. 15, in the present embodiment, the structure and manufacturing method of the LED wafer 300d are similar to the structure and manufacturing method of the LED array 300 of the sixth embodiment, and the following is only for the tenth embodiment and the The main differences between the six embodiments are explained.

In the embodiment, the LED chip 300d further includes a plurality of protrusions 228. The protrusion 228 is disposed between the first electrode 240a and the first portion 230a. That is, in the process of the LED array 300d, the patterned mask layer (not shown) further includes a plurality of protrusions located in the opening, and the protrusions are located on the substrate exposed by the openings (not drawn) Show). The protrusions 228 allow the light emitted from the light-emitting layer 234 of the light-emitting diode wafer 300d to be more easily scattered to further enhance the light-emitting efficiency of the light-emitting diode wafer 300d. worth taking note of In other embodiments, the LED chip may also be provided with protrusions to further enhance the luminous efficiency of the LED wafer.

It should be noted that the top surface of the second portion 230b of the semiconductor device layer 230 may be a flat surface as shown in FIG. However, in other possible embodiments of the present invention, the top surface of the second portion 230b of the semiconductor device layer 230 may also be a curved surface as shown in Fig. 15'. As can be seen from FIG. 15', the top surface of the second portion 230b is a concave curved surface, and the concave surface has a height difference between the center position and the edge, for example, between 1 micrometer and 5 micrometers, and a preferred height. The drop is 2.5 microns.

[Eleventh Embodiment]

16A and 16B are a top view and a cross-sectional view, respectively, of a high power LED chip of an eleventh embodiment of the present invention. Referring to FIG. 16A and FIG. 16B, in the embodiment, the semiconductor device layer 230 in the high power LED chip 400 has a finger-shaped pattern, and the electrode 240b disposed on the semiconductor device layer 230. There is also a finger pattern, and the electrode 240a disposed on the semiconductor layer 220 also has a finger pattern. In addition, the cross-sectional profile of the semiconductor device layer 230 can be as shown in FIG. 2, FIG. 2', FIG. 5, FIG. 5', FIG. 6, FIG. 6', FIG. 7, FIG. 7', FIG. 8, FIG. 8', FIG. 9', Fig. 12, Fig. 12', Fig. 13, Fig. 13', Fig. 14, Fig. 14', Fig. 15 or Fig. 15' are the same.

Similarly, as in the first to tenth embodiments described above, the top surface of the second portion 230b of the semiconductor device layer 230 of the present embodiment may be a flat surface or a curved surface.

In summary, in the method of fabricating a light-emitting diode wafer of the present invention, a semiconductor element layer is formed in the opening of the patterned mask layer such that the cross-sectional area of the semiconductor element layer outside the opening increases with height And decrement. In this way, the semiconductor device layer has a special configuration, and can effectively extract the light emitted by the light-emitting layer out of the light-emitting diode. The wafer is used to reduce the chance that light emitted by the luminescent layer will cause total reflection in the luminescent diode wafer. Therefore, the light extraction efficiency of the light-emitting diode wafer can be greatly improved, so that the light-emitting diode wafer has good light-emitting efficiency. In addition, in the method of fabricating a light-emitting diode wafer, the semiconductor element layer formed in the opening does not need to be subjected to a patterning step and removes part of the doped semiconductor material layer or part in a manner such as a dry etching process. The luminescent material layer has the advantage of simplifying the process steps by exposing the doped semiconductor layer to be electrically connected to the electrodes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

200‧‧‧Light Diode Wafer

210‧‧‧Substrate

220‧‧‧Semiconductor layer

230‧‧‧Semiconductor component layer

230a‧‧‧Part I

230b‧‧‧Part II

232‧‧‧First type doped semiconductor layer

234‧‧‧Lighting layer

236‧‧‧Second type doped semiconductor layer

240a‧‧‧electrode

240b‧‧‧electrode

260‧‧‧current dispersion layer

C‧‧‧ turning point

S‧‧‧ side wall

Wmax ₁ ‧‧‧Maximum cross-sectional area of the first part

Wmax ₂ ‧‧‧The maximum cross-sectional area of the second part

Claims (41)

A method of fabricating a semiconductor device layer, comprising: forming a patterned mask layer on a substrate, wherein the patterned mask layer has an opening to expose a portion of the substrate; and the patterned mask layer is not Forming a semiconductor device layer on the covered substrate, wherein the semiconductor device layer outside the opening has different cross-sectional areas at different heights, and the cross-sectional area of the semiconductor device layer outside the opening increases with the height Decrement; and remove the patterned mask layer. The method of fabricating a semiconductor device layer according to claim 1, wherein the semiconductor device layer located in the opening has a different cross-sectional area at different heights, and a cross-sectional area of the semiconductor device layer located in the opening The height of the place increases and increases. The method of fabricating a semiconductor device layer according to claim 2, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum The cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 2, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum a cross-sectional area, and the first largest cross-sectional area is greater than the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 1, wherein the semiconductor device layer located in the opening has the same cross-sectional area at different heights, and the cross-sectional area of the semiconductor device layer located in the opening Maintain at the height of the height Certainly, the sidewall of the semiconductor element layer located within the opening is substantially perpendicular to the surface of the substrate. The method of fabricating a semiconductor device layer according to claim 5, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum The cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 5, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum a cross-sectional area, and the first largest cross-sectional area is greater than the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 1, wherein the semiconductor device layer comprises a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer stacked in sequence. The method of manufacturing a semiconductor device layer according to claim 8, wherein the light-emitting layer is formed in the opening. The method of manufacturing a semiconductor device layer according to claim 8, wherein the light-emitting layer is formed outside the opening. The method of fabricating a semiconductor device layer according to claim 1, wherein an epitaxial rate of the semiconductor device layer on the substrate is greater than an epitaxial rate on the patterned mask layer. The method of fabricating a semiconductor device layer according to claim 1, wherein the material of the patterned mask layer comprises ruthenium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride. A method of manufacturing a semiconductor device layer according to claim 1, wherein The patterned mask layer further includes a plurality of protrusions located in the opening, the protrusions are located on the substrate exposed by the opening, and the protrusions are covered by the semiconductor element layer. A method of fabricating a semiconductor device layer, comprising: forming a semiconductor layer on a substrate; forming a patterned mask layer on the semiconductor layer, wherein the patterned mask layer has an opening to expose a portion of the semiconductor layer Forming a semiconductor device layer on the semiconductor layer not covered by the patterned mask layer, wherein the semiconductor device layer outside the opening has different cross-sectional areas at different heights, and the semiconductor is located outside the opening The cross-sectional area of the component layer decreases as the height is increased; and the patterned mask layer is removed. The method of fabricating a semiconductor device layer according to claim 14, wherein the semiconductor device layer located in the opening has different cross-sectional areas at different heights, and a cross-sectional area of the semiconductor device layer located in the opening The height of the place increases and increases. The method of fabricating a semiconductor device layer according to claim 15, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum The cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 15, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum a cross-sectional area, and the first largest cross-sectional area is greater than the second largest cross-sectional area. A method of manufacturing a semiconductor device layer according to claim 14, Wherein the semiconductor device layer located in the opening has the same cross-sectional area at different heights, and the cross-sectional area of the semiconductor element layer located in the opening is maintained constant as the height is increased, so that the inner portion is located in the opening The sidewall of the semiconductor device layer is substantially perpendicular to the surface of the semiconductor layer. The method of fabricating a semiconductor device layer according to claim 18, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum The cross-sectional area, and the first maximum cross-sectional area is substantially equal to the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 18, wherein the semiconductor device layer outside the opening has a first maximum cross-sectional area, and the semiconductor device layer located in the opening has a second maximum a cross-sectional area, and the first largest cross-sectional area is greater than the second largest cross-sectional area. The method of fabricating a semiconductor device layer according to claim 14, wherein the semiconductor device layer comprises a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer stacked in sequence. The method of manufacturing a semiconductor device layer according to claim 21, wherein the light-emitting layer is formed in the opening. The method of manufacturing a semiconductor device layer according to claim 21, wherein the light-emitting layer is formed outside the opening. The method of fabricating a semiconductor device layer according to claim 21, wherein the semiconductor layer and the first type doped semiconductor layer have the same conductivity type. The method of fabricating a semiconductor device layer according to claim 14, wherein an epitaxial rate of the semiconductor device layer on the semiconductor layer is greater than an epitaxial rate on the patterned mask layer. The method of fabricating a semiconductor device layer according to claim 14, wherein the material of the patterned mask layer comprises ruthenium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride. The method of fabricating a semiconductor device layer according to claim 14, wherein the patterned mask layer further comprises a plurality of protrusions located in the opening, the protrusions being located on the semiconductor layer exposed by the opening, And the protrusions are covered by the semiconductor element layer. A semiconductor device layer comprising a first portion and a second portion, the second portion being located on the first portion, the second portion having different cross-sectional areas at different heights, and a cross-sectional area of the second portion being Decrease in height. The semiconductor device layer of claim 28, wherein the first portion has different cross-sectional areas at different heights, and the cross-sectional area of the first portion increases as the height increases. The semiconductor device layer of claim 29, wherein the second portion has a first maximum cross-sectional area, and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to The second largest cross-sectional area. The semiconductor device layer of claim 29, wherein the second portion has a first maximum cross-sectional area, and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second Maximum cross-sectional area. The semiconductor device layer of claim 29, wherein a top surface of the second portion is a curved surface. The semiconductor device layer of claim 28, wherein the first portion has the same cross-sectional area at different heights, and the cross-sectional area of the first portion is maintained constant as the height of the portion increases. The semiconductor device layer of claim 33, wherein the second portion has a first maximum cross-sectional area, and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is substantially equal to The second largest cross-sectional area. The semiconductor device layer of claim 33, wherein the second portion has a first maximum cross-sectional area, and the first portion has a second largest cross-sectional area, and the first maximum cross-sectional area is greater than the second Maximum cross-sectional area. The semiconductor device layer of claim 33, wherein a top surface of the second portion is a curved surface. The semiconductor device layer of claim 28, wherein the first portion and the second portion comprise a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor stacked in sequence Floor. The semiconductor device layer of claim 37, wherein the luminescent layer is located in the first portion. The semiconductor device layer of claim 37, wherein the light emitting layer is located in the second portion. The semiconductor device layer of claim 28, further comprising a plurality of protrusions, wherein the protrusions are embedded in the first portion. The semiconductor device layer of claim 40, wherein the material of the protrusions comprises yttrium oxide, tantalum nitride, titanium oxide, gallium oxide or magnesium nitride.