TW201415554A - METHOD FOR FORMING Cu WIRING, AND COMPUTER-READABLE MEMORY MEDIUM - Google Patents

METHOD FOR FORMING Cu WIRING, AND COMPUTER-READABLE MEMORY MEDIUM Download PDF

Info

Publication number
TW201415554A
TW201415554A TW102124320A TW102124320A TW201415554A TW 201415554 A TW201415554 A TW 201415554A TW 102124320 A TW102124320 A TW 102124320A TW 102124320 A TW102124320 A TW 102124320A TW 201415554 A TW201415554 A TW 201415554A
Authority
TW
Taiwan
Prior art keywords
film
forming
alloy
wiring
wafer
Prior art date
Application number
TW102124320A
Other languages
Chinese (zh)
Inventor
Tadahiro Ishizaka
Atsushi Gomi
Kenji Suzuki
Tatsuo Hatano
Takashi Sakuma
Toshiaki Fujisato
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201415554A publication Critical patent/TW201415554A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/046—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a method for forming Cu wiring in which the Cu wiring is formed in a recess of a predetermined pattern formed on a substrate. This method for forming Cu wiring includes: a step for forming a barrier film on at least the surface of the recess (step 2); a step for forming, by PVD, a Cu alloy film containing an alloy component in an amount such that the electromigration resistance is higher than that of pure Cu and the resistance value is within an allowable range, and embedding the Cu alloy film in the recess having a barrier film formed on the surface (step 4); a step for forming a build-up layer on the Cu alloy film (step 5); and a step for polishing the entire surface by CMP and forming the Cu wiring in the recess (step 7).

Description

Cu配線的形成方法及電腦可讀取之記憶媒體 Method for forming Cu wiring and computer readable memory medium

本發明關於一種於形成於基板之溝槽或孔洞般的凹部形成Cu配線之Cu配線形成方法及電腦可讀取記憶媒體。 The present invention relates to a Cu wiring forming method and a computer readable memory medium for forming a Cu wiring in a recess formed in a trench or a hole of a substrate.

半導體元件的製造中，係對半導體晶圓重複進行成膜處理或蝕刻處理等各種處理來製造期望的元件，但近年來，對應於半導體元件高速化、配線圖案微細化、高集積化之要求，而被要求配線的低電阻化(導電性提升)及電子遷移阻抗的提升。 In the production of a semiconductor element, various processes such as a film formation process or an etching process are repeated on a semiconductor wafer to produce a desired element. However, in recent years, in response to the demand for higher speed of semiconductor elements, miniaturization of wiring patterns, and higher integration, The wiring is required to have low resistance (increased conductivity) and improved electron mobility.

對應於上述觀點，轉變成將導電性高於鋁(Al)或鎢(W)(電阻低)且電子遷移阻抗(electromigration resistance)優異的銅(Cu)使用於配線材料。 In response to the above viewpoint, copper (Cu) which is superior in electrical conductivity to aluminum (Al) or tungsten (W) (low resistance) and excellent in electron migration resistance is used for the wiring material.

作為Cu配線之形成方法，已提出一種技術，其係於形成有溝槽或孔洞之層間絕緣膜整體以PVD(即電漿濺射)形成鉭金屬(Ta)、鈦(Ti)、氮化鉭膜(TaN)、氮化鈦膜(TiN)等所構成的阻隔膜，於阻隔膜上同樣地藉由電漿濺射形成Cu種晶膜，再於其上施予Cu鍍覆來完全填補溝槽或孔洞，且藉由CMP(Chemical Mechanical Polishing：化學機械研磨)處理對晶圓表面之多餘的銅薄膜及阻隔膜進行研磨處理來加以去除(例如專利文獻1)。 As a method of forming a Cu wiring, a technique has been proposed in which an interlayer insulating film formed with a trench or a hole is formed by PVD (ie, plasma sputtering) to form a base metal (Ta), titanium (Ti), or tantalum nitride. A barrier film made of a film (TaN) or a titanium nitride film (TiN) is formed on the barrier film by plasma sputtering to form a Cu seed film, and then Cu plating is applied thereon to completely fill the groove. The groove or the hole is removed by polishing the excess copper film and the barrier film on the surface of the wafer by CMP (Chemical Mechanical Polishing) (for example, Patent Document 1).

但由於半導體元件的設計規則變得更加微細化，導致電流密度上昇，伴隨其，縱使使用Cu作為配線材料而電子遷移阻抗仍然不夠充分。於是，已提出一種配線形成製程，其作為一種目的在於提高電子遷移阻抗來謀求配線可靠度的進一步提 升之技術，係將Cu合金(Cu-Al、Cu-Mn、Cu-Mg、Cu-Ag、Cu-Sn、Cu-Pb、Cu-Zn、Cu-Pt、Cu-Au、Cu-Ni、Cu-Co等)使用於種晶層來取代Cu種晶膜(非專利文獻1等)。 However, since the design rule of the semiconductor element is further miniaturized, the current density is increased, and even if Cu is used as the wiring material, the electron transfer resistance is insufficient. Accordingly, a wiring forming process has been proposed, which is intended to improve the electron transfer impedance to further improve wiring reliability. Ascending technology, Cu alloy (Cu-Al, Cu-Mn, Cu-Mg, Cu-Ag, Cu-Sn, Cu-Pb, Cu-Zn, Cu-Pt, Cu-Au, Cu-Ni, Cu) -Co or the like) is used in place of a seed layer to replace a Cu seed film (Non-Patent Document 1 and the like).

專利文獻1：日本特開2006-148075號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-148075

非專利文獻1：Nogami et.al.IEDM2010 pp764-767 Non-Patent Document 1: Nogami et.al.IEDM2010 pp764-767

然而，隨著上述般之半導體元件的設計規則日益微細化，溝槽寬度或孔洞直徑成為數十nm，若於上述般之狹窄溝槽或孔洞等的凹部內，如專利文獻1般地以電漿濺射形成阻隔膜或種晶膜後藉由Cu鍍覆來填補溝槽或孔洞的情況，會發生填補性不夠充分而導致孔隙產生等之問題。 However, as the design rule of the above-described semiconductor element is increasingly fine, the groove width or the hole diameter is several tens of nm, and in the case of the above-described narrow groove or hole or the like, as in Patent Document 1, electricity is used. After the slurry is sputtered to form a barrier film or a seed film, the surface of the trench or the hole is filled by Cu plating, and the problem that the filling property is insufficient and pores are generated may occur.

又，上述非專利文獻1的技術雖可謀求電子遷移阻抗的提升，但由於係利用Cu鍍覆，因此上述填補性的問題本質上並未解決。 Further, although the technique of Non-Patent Document 1 can improve the electron transport resistance, the above-described problem of the filling property is not substantially solved because Cu plating is used.

再者，配線中會含有合金成分及Cu鍍覆中的雜質，而亦發生配線電阻變高之情況。 Further, the wiring contains the alloy component and the impurities in the Cu plating, and the wiring resistance also increases.

本發明有鑑於上述情事，係提供一種於溝槽或孔洞般的凹部形成Cu配線之際，不會產生孔隙等且可盡量抑制配線電阻上昇，來獲得電子遷移阻抗高的Cu配線之Cu配線形成方法，以及記憶有使Cu配線形成系統執行該Cu配線形成方法的程式之電腦可讀取記憶媒體。 In view of the above, the present invention provides a Cu wiring in which a Cu wiring having a high electron transfer resistance is obtained without causing an increase in wiring resistance as long as the Cu wiring is formed in a recessed portion such as a groove or a hole. The method and the computer readable memory medium storing a program for causing the Cu wiring forming system to execute the Cu wiring forming method.

為解決上述課題，本發明第1觀點提供一種Cu配線形成方法，係在形成於基板之特定圖案的凹部內形成Cu配線，具有以下工序：於至少該凹部的表面形成阻隔膜之工序；藉由PVD形成含有電子遷移阻抗高於純Cu且電阻值為容許範圍程度的合金成分之Cu合金膜，而以該Cu合金膜來填補於該表面形成有阻隔膜之該凹部內之工序；於該Cu合金膜上形成累積層之工序；以及藉由CMP進行整面研磨而於該凹部內形成Cu配線之工序。 In order to solve the above problems, a first aspect of the present invention provides a Cu wiring forming method in which a Cu wiring is formed in a recess formed in a specific pattern of a substrate, and a step of forming a barrier film on at least the surface of the recess; The PVD forms a Cu alloy film containing an alloy composition having an electron transport resistance higher than that of pure Cu and a resistance value to a permissible range, and the Cu alloy film fills the recessed portion of the resistive film on the surface; a step of forming a buildup layer on the alloy film; and a step of forming a Cu wire in the recess by CMP full-surface polishing.

本發明中，較佳地，係對應於成膜條件來決定進行PVD時之靶材的合金成分濃度，以使該Cu合金膜的合金成分濃度成為特定值。較佳地，於形成該阻隔膜後，且於形成該Cu合金膜之前，另具有形成Ru膜之工序。較佳地，該Ru膜係藉由CVD所形成。 In the present invention, it is preferable to determine the alloy component concentration of the target in the PVD in accordance with the film formation conditions so that the alloy component concentration of the Cu alloy film becomes a specific value. Preferably, after the barrier film is formed, and before the formation of the Cu alloy film, a step of forming a Ru film is further provided. Preferably, the Ru film is formed by CVD.

較佳地，該Cu合金膜的形成係於收納有基板之處理容器內，藉由電漿生成氣體來生成電漿，且由與欲獲得之Cu合金膜相同的Cu合金所構成之靶材使粒子濺射，在該電漿中使粒子離子化，並對該基板施加偏壓電功率，藉以將離子吸引至基板上之裝置而進行。 Preferably, the Cu alloy film is formed in a processing container in which the substrate is housed, and a plasma is generated by the plasma to generate a plasma, and the target is made of the same Cu alloy as the Cu alloy film to be obtained. Particle sputtering is performed by ionizing particles in the plasma and applying bias electric power to the substrate to attract ions to the substrate.

該累積層的形成可藉由PVD來形成Cu合金膜或純Cu膜而進行。又，較佳地，該累積層的形成係在形成該Cu合金膜後，藉由相同裝置來形成相同的Cu合金而進行。 The formation of the accumulation layer can be performed by forming a Cu alloy film or a pure Cu film by PVD. Further, preferably, the formation of the accumulation layer is performed by forming the Cu alloy film and forming the same Cu alloy by the same apparatus.

構成該Cu合金膜之Cu合金可選自Cu-Al、Cu-Mn、Cu-Mg、Cu-Ag、Cu-Sn、Cu-Pb、Cu-Zn、Cu-Pt、Cu-Au、Cu-Ni、Cu-Co及Cu-Ti。 The Cu alloy constituting the Cu alloy film may be selected from the group consisting of Cu-Al, Cu-Mn, Cu-Mg, Cu-Ag, Cu-Sn, Cu-Pb, Cu-Zn, Cu-Pt, Cu-Au, Cu-Ni. , Cu-Co and Cu-Ti.

當中又以Cu-Mn及Cu-Al為佳，特佳為Cu-Mn。該阻隔膜可使用選自Ti膜、TiN膜、Ta膜、TaN膜、Ta/TaN的2層膜、TaCN膜、W膜、WN膜、WCN膜、Zr膜、ZrN膜、V膜、VN膜、Nb膜、NbN膜所構成之群。 Among them, Cu-Mn and Cu-Al are preferred, and Cu-Mn is particularly preferred. The barrier film may be a 2-layer film selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, and a Ta/TaN film, a TaCN film, a W film, a WN film, a WCN film, a Zr film, a ZrN film, a V film, and a VN film. , a group of Nb film and NbN film.

本發明第2觀點提供一種電腦可讀取記憶媒體，係在電腦上動作，而記憶有用以控制Cu配線形成系統的程式，其中該程式在執行時會使電腦控制該Cu配線形成系統，以進行如上述第1觀點之Cu配線的形成方法。 A second aspect of the present invention provides a computer readable memory medium that operates on a computer and memorizes a program for controlling a Cu wiring forming system, wherein the program causes the computer to control the Cu wiring forming system to perform A method of forming a Cu wiring according to the first aspect described above.

依據本發明，由於係藉由PVD來形成含有電子遷移阻抗高於純Cu且電阻值為容許範圍程度的合金成分之Cu合金膜，並將Cu合金膜埋入於凹部內，故可防止藉由Cu鍍覆來填補的情況般之孔隙的產生，又，由於PVD法的雜質較少，故能夠以高精確度形成配線電阻的上昇較少、電子遷移阻抗高、且具有容許範圍的電阻值之組成的Cu合金膜。於是，便可獲得不 會產生孔隙等且可盡量抑制配線電阻上昇之電子遷移阻抗高的Cu配線。 According to the present invention, since a Cu alloy film containing an alloy composition having an electron transport resistance higher than that of pure Cu and having a resistance value to a permissible range is formed by PVD, and the Cu alloy film is buried in the concave portion, it can be prevented from being The generation of pores in the case of Cu plating is filled, and since the PVD method has fewer impurities, it is possible to form a resistance with less rise in wiring resistance, high electron transfer resistance, and an allowable range with high accuracy. A Cu alloy film composed of. So you can get no A Cu wiring having a high electron mobility and high resistance to increase in wiring resistance can be suppressed as much as possible.

1‧‧‧成膜系統 1‧‧‧film formation system

12a、12b‧‧‧阻隔膜成膜裝置 12a, 12b‧‧‧Resistance film forming device

14a、14b‧‧‧Ru內襯膜成膜裝置 14a, 14b‧‧‧Ru inner film forming device

22a、22b‧‧‧Cu合金膜成膜裝置 22a, 22b‧‧‧Cu alloy film forming device

24a、24b‧‧‧Cu膜成膜裝置 24a, 24b‧‧‧Cu film forming device

201‧‧‧下部構造 201‧‧‧ Lower structure

202‧‧‧層間絕緣膜 202‧‧‧Interlayer insulating film

203‧‧‧溝槽 203‧‧‧ trench

204‧‧‧阻隔膜 204‧‧‧Resistive diaphragm

205‧‧‧Ru內襯膜 205‧‧‧Ru lining film

206‧‧‧Cu合金膜 206‧‧‧Cu alloy film

207‧‧‧累積層 207‧‧‧ accumulation layer

208‧‧‧Cu配線 208‧‧‧Cu wiring

209‧‧‧罩蓋層 209‧‧‧ Cover

W‧‧‧半導體晶圓(被處理基板) W‧‧‧Semiconductor wafer (substrate to be processed)

圖1係顯示本發明一實施型態之Cu配線形成方法之流程圖。 Fig. 1 is a flow chart showing a method of forming a Cu wiring according to an embodiment of the present invention.

圖2A係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2A is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2B係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2B is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2C係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2C is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2D係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2D is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2E係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2E is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2F係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2F is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2G係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2G is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖2H係用以說明本發明一實施型態之Cu配線形成方法之工序剖視圖。 Fig. 2H is a cross-sectional view showing the steps of a method of forming a Cu wiring according to an embodiment of the present invention.

圖3A係顯示僅使配線內為Cu-Mn合金的情況，配線寬度與配線中Mn濃度的關係之圖式。 Fig. 3A is a view showing the relationship between the wiring width and the Mn concentration in the wiring in the case where only the inside of the wiring is a Cu-Mn alloy.

圖3B係顯示亦使累積的Cu為Cu-Mn合金的情況，配線寬度與配線中Mn濃度的關係之圖式。 Fig. 3B is a view showing the relationship between the wiring width and the Mn concentration in the wiring in the case where the accumulated Cu is a Cu-Mn alloy.

圖4係顯示使用Cu-Mn合金靶材(Mn0.2at.%)來進行寬度20nm之配線的填補實驗時的填補狀態之SEM相片。 4 is a SEM photograph showing a filled state in a filling experiment of a wiring having a width of 20 nm using a Cu-Mn alloy target (Mn 0.2 at. %).

圖5係顯示可應用於本發明實施型態之Cu配線形成方法的實施之多腔室形式成膜系統的一例之俯視圖。 Fig. 5 is a plan view showing an example of a multi-chamber form film forming system which can be applied to the implementation of the Cu wiring forming method of the embodiment of the present invention.

圖6係顯示圖5之成膜系統所搭載之用以形成Cu合金膜的Cu合金膜成膜裝置之剖視圖。 Fig. 6 is a cross-sectional view showing a Cu alloy film forming apparatus for forming a Cu alloy film mounted on the film forming system of Fig. 5.

圖7係顯示圖5之成膜系統所搭載之用以形成Ru內襯膜的Ru膜成膜裝置之剖視圖。 Fig. 7 is a cross-sectional view showing a Ru film forming apparatus for forming a Ru inner liner film mounted on the film forming system of Fig. 5.

以下，參閱添附圖式具體說明本發明之實施型態。 Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

<Cu配線形成方法之一實施型態> <One implementation form of Cu wiring forming method>

首先，參閱圖1之流程圖及圖2A至圖2H之工序剖視圖來加以說明Cu配線形成方法之一實施型態。 First, an embodiment of the Cu wiring forming method will be described with reference to the flowchart of FIG. 1 and the process cross-sectional views of FIGS. 2A to 2H.

本實施型態中，首先準備半導體晶圓(以下，簡稱作晶圓)W，其係於下部構造201(省略詳細說明)上具有SiO2膜、Low-k膜(SiCO、SiCOH等)等之層間絕緣膜202，該層間絕緣膜202係以特定圖案形成有溝槽203及用以連接至下層配線之介層孔(Via,，圖中未顯示)(步驟1，圖2A)。上述晶圓W較佳宜藉由除氣(Degas)製程或預清洗(Pre-Clean)製程，來去除絕緣膜表面的水分或蝕刻/灰化時的殘渣。 In the present embodiment, first, a semiconductor wafer (hereinafter, simply referred to as a wafer) W is provided, which is provided with a SiO 2 film, a Low-k film (SiCO, SiCOH, etc.), etc., in the lower structure 201 (details are omitted). The interlayer insulating film 202 is formed with a groove 203 and a via hole (Via, not shown) connected to the underlying wiring in a specific pattern (step 1, FIG. 2A). Preferably, the wafer W is preferably subjected to a Degas process or a Pre-Clean process to remove moisture on the surface of the insulating film or residue during etching/ashing.

接下來，形成阻隔膜204，其係於包含溝槽203及介層孔的表面之整面將Cu遮蔽(阻隔)來抑制Cu的擴散(步驟2，圖2B)。 Next, a barrier film 204 is formed which shields (blocks) Cu from the entire surface including the surface of the trench 203 and the via hole to suppress diffusion of Cu (step 2, FIG. 2B).

阻隔膜204較佳為相對於Cu具有高阻隔性且具有低電阻者，較佳可使用Ti膜、TiN膜、Ta膜、TaN膜、Ta/TaN的2層膜。又，亦可使用TaCN膜、W膜、WN膜、WCN膜、Zr膜、ZrN膜、V膜、VN膜、Nb膜、NbN膜等。Cu配線由於埋入於溝槽或孔洞內之Cu的體積愈大則電阻愈低，故阻隔膜較佳宜形成為非常地薄，由上述觀點來看，其厚度較佳為1~20nm。更佳為1~10nm。阻隔膜可藉由離子化PVD(Ionized physical vapored position；iPVD)，例如電漿濺射來成膜。又，亦可藉由通常的濺射、離子鍍覆(Ion Plating)等其他的PVD來成膜，或是亦可藉由CVD或ALD、使用電漿之CVD或ALD 來成膜。 The barrier film 204 preferably has a high barrier property with respect to Cu and has low resistance. A Ti film, a TiN film, a Ta film, a TaN film, and a Ta/TaN two-layer film are preferably used. Further, a TaCN film, a W film, a WN film, a WCN film, a Zr film, a ZrN film, a V film, a VN film, an Nb film, an NbN film, or the like can also be used. The Cu wiring has a lower resistance due to the larger volume of Cu buried in the trench or the hole. Therefore, the barrier film is preferably formed to be extremely thin. From the above viewpoint, the thickness is preferably from 1 to 20 nm. More preferably, it is 1 to 10 nm. The barrier film can be formed by ionized PVD (iPVD), such as plasma sputtering. Further, it may be formed by ordinary sputtering or other PVD such as ion plating, or by CVD or ALD, plasma CVD or ALD. To form a film.

接下來，於阻隔膜204上形成Ru內襯膜205(步驟3，圖2C)。Ru內襯膜由增加所埋入之Cu體積來降低配線電阻之觀點來看，較佳宜形成為較薄，例如1~5nm。 Next, a Ru liner film 205 is formed on the barrier film 204 (step 3, FIG. 2C). The Ru inner liner film is preferably formed to be thin, for example, 1 to 5 nm from the viewpoint of increasing the buried Cu volume to lower the wiring resistance.

由於Ru的浸濕性高於Cu，因此藉由於Cu的基底形成Ru內襯膜，在藉由下一次的iPVD來形成Cu膜時，可確保良好的Cu移動性，可使阻塞溝槽或孔洞的開口之懸突部分(overhang)不易產生。於是，便不會使微細溝槽或孔洞產生孔隙來確實地將Cu埋入。 Since the wettability of Ru is higher than that of Cu, a Ru inner liner film is formed by the base of Cu, and when the Cu film is formed by the next iPVD, good Cu mobility can be ensured, and the groove or the hole can be blocked. The overhang of the opening is not easy to produce. Therefore, pores are not formed in the fine grooves or holes to reliably embed Cu.

Ru內襯膜可藉由熱CVD且使用十二羰三釕(Ru3(CO)12)作為成膜原料來形成。藉此，便可以高階梯覆蓋率形成高純度且薄的Ru膜。此時的成膜條件例如處理容器內的壓力為1.3~66.5Pa的範圍，成膜溫度(晶圓溫度)為150~250℃的範圍。Ru內襯膜205亦可藉由CVD或PVD而使用十二羰三釕以外的其他成膜原料，例如(環戊二烯)(2,4-二甲基環戊二烯)釕、雙(環戊二烯)(2,4-甲基環戊二烯)釕、(2,4-二甲基環戊二烯)(乙基環戊二烯)釕、雙(2,4-甲基環戊二烯)(乙基環戊二烯)釕般之釕的環戊二烯化合物來成膜。 The Ru inner liner film can be formed by thermal CVD and using dodecyltriazine (Ru 3 (CO) 12 ) as a film forming raw material. Thereby, a high-purity and thin Ru film can be formed at a high step coverage. The film formation conditions at this time are, for example, a range of 1.3 to 66.5 Pa in the processing container, and a film formation temperature (wafer temperature) of 150 to 250 ° C. The Ru inner liner film 205 may also use other film forming materials other than dodecacarbonyl triazine by CVD or PVD, such as (cyclopentadienyl) (2,4-dimethylcyclopentadiene) ruthenium, bis ( Cyclopentadiene) (2,4-methylcyclopentadiene) fluorene, (2,4-dimethylcyclopentadienyl) (ethylcyclopentadiene) fluorene, bis(2,4-methyl A cyclopentadiene compound of cyclopentadienyl) (ethylcyclopentadiene) is formed into a film.

此外，若溝槽或介層孔的開口較寬而不易產生懸突部分的情況，則不一定要形成Ru內襯膜205，亦可於阻隔膜上直接形成Cu膜。 Further, if the opening of the trench or the via hole is wide and the overhang portion is not easily generated, the Ru liner film 205 does not have to be formed, and the Cu film may be directly formed on the barrier film.

接下來，藉由PVD形成低純度的Cu合金所構成之Cu合金膜206，來幾乎完全地填補溝槽203及介層孔(圖中未顯示)(步驟4，圖2D)。此時的成膜較佳宜使用iPVD，例如電漿濺射。 Next, the Cu alloy film 206 composed of a low-purity Cu alloy is formed by PVD to completely fill the trench 203 and the via hole (not shown) (step 4, FIG. 2D). Preferably, the film formation at this time uses iPVD, such as plasma sputtering.

通常之PVD成膜的情況雖因Cu的凝集，而容易產生阻塞溝槽或孔洞的開口之懸突部分，但藉由使用iPVD，且調整施加在晶圓之偏壓功率來控制Cu離子的成膜作用與電漿生成氣體之離子(Ar離子)的蝕刻作用，則可使Cu移動來抑制懸突部分的生成，縱使是開口狹窄的溝槽或孔洞，仍可獲得良好的填補性。此時，從使Cu具有流動性來獲得良好填補性之觀點來 看，較佳為Cu會遷移之高溫製程(65~350℃)。又，如上述般，藉由於Cu合金膜206的基底設置浸濕性高於Cu之Ru內襯膜205，由於Cu不會在Ru內襯膜上凝集而會流動，故縱使是微細凹部處，仍可抑制懸突部分的生成，不會產生孔隙，可確實地將Cu埋入。 In the case of PVD film formation, the overhanging portion of the opening that blocks the trench or the hole is likely to occur due to the aggregation of Cu. However, by using iPVD, the bias power applied to the wafer is adjusted to control the formation of Cu ions. The etching action of the membrane action and the ions of the plasma generating gas (Ar ions) allows Cu to move to suppress the formation of the overhang portion, and even if it is a groove or a hole having a narrow opening, good filling property can be obtained. At this time, from the viewpoint of making Cu fluid, to obtain good filling. Look, it is better to have a high temperature process (65~350 °C) where Cu will migrate. Further, as described above, since the Ru inner liner film 205 having a higher wettability than Cu is provided on the base of the Cu alloy film 206, since Cu does not aggregate on the Ru inner liner film and flows, even if it is a fine concave portion, The formation of the overhang portion can be suppressed, pores are not generated, and Cu can be surely buried.

此外，若溝槽或孔洞的開口寬度較大之情況等，不易生成懸突部分的情況，藉由Cu不會遷移之低溫製程(-50~0℃)，則亦可以高速來成膜。 Further, when the width of the opening of the groove or the hole is large, it is difficult to form the overhang portion, and the film can be formed at a high speed by a low-temperature process (-50 to 0 ° C) in which Cu does not migrate.

又，Cu膜成膜時之處理容器內的壓力(製程壓力)較佳為1~100mTorr(0.133~13.3Pa)，更佳為35~90mTorr(4.66~12.0Pa)。 Further, the pressure (process pressure) in the processing container at the time of film formation of the Cu film is preferably from 1 to 100 mTorr (0.133 to 13.3 Pa), more preferably from 35 to 90 mTorr (4.66 to 12.0 Pa).

構成Cu合金膜206之Cu合金可舉出Cu-Al、Cu-Mn、Cu-Mg、Cu-Ag、Cu-Sn、Cu-Pb、Cu-Zn、Cu-Pt、Cu-Au、Cu-Ni、Cu-Co、Cu-Ti等。當中又以Cu-Mn、Cu-Al為佳，Cu-Mn特佳。 Examples of the Cu alloy constituting the Cu alloy film 206 include Cu-Al, Cu-Mn, Cu-Mg, Cu-Ag, Cu-Sn, Cu-Pb, Cu-Zn, Cu-Pt, Cu-Au, and Cu-Ni. , Cu-Co, Cu-Ti, etc. Among them, Cu-Mn and Cu-Al are preferred, and Cu-Mn is particularly preferred.

此時的合金成分濃度(含有率)為電子遷移阻抗高於純Cu，且可獲得容許的電阻值之值。亦即，電子遷移阻抗雖因存在有合金成分而提升，但由於電阻值會降低，因此合金成分係控制為可提升電子遷移阻抗，同時不會使電阻值上昇至無法容許的值之量。但由該值係依合金成分的種類而異，故較佳宜配合合金成分來適當地設定。例如，若為Cu-Mn，則Mn濃度為0.1at.%左右即非常充分，較佳範圍為0.05~1at.%。若為Cu-Al合金，則較佳範圍為0.05~2at.%，Cu合金膜206雖係使用欲獲得之Cu合金製的靶材來成膜，但此時靶材的合金組成與所成膜之Cu合金膜組成的關係會依壓力等的成膜條件而變化，故必須調整靶材的合金組成，以便能夠在實際採用的製造條件中獲得期望的合金組成。此外，施加在Cu合金靶材之直流電力較佳為4~12Kw，更佳為6~10kW。 The alloy component concentration (content ratio) at this time is a value in which the electron transport resistance is higher than that of pure Cu, and an allowable resistance value can be obtained. That is, although the electron transport resistance is improved by the presence of the alloy component, since the resistance value is lowered, the alloy composition is controlled so as to increase the electron transfer resistance without increasing the resistance value to an unacceptable value. However, since this value varies depending on the type of the alloy component, it is preferable to appropriately set the alloy component. For example, in the case of Cu-Mn, the Mn concentration is about 0.1 at.%, which is very sufficient, and preferably in the range of 0.05 to 1 at.%. In the case of a Cu-Al alloy, the preferred range is 0.05 to 2 at.%, and the Cu alloy film 206 is formed by using a target made of a Cu alloy to be obtained, but at this time, the alloy composition of the target and the film formation are formed. The relationship of the composition of the Cu alloy film varies depending on the film forming conditions such as pressure, and it is necessary to adjust the alloy composition of the target so that the desired alloy composition can be obtained in practically employed manufacturing conditions. Further, the direct current power applied to the Cu alloy target is preferably 4 to 12 Kw, more preferably 6 to 10 kW.

如此般將Cu合金埋入溝槽203及介層孔(孔洞)內後，為之後的平坦化處理做準備，於Cu合金膜206上成膜累積層207(步驟5，圖2E)。 After the Cu alloy is buried in the trench 203 and the via hole (hole) in this manner, the deposition layer 207 is formed on the Cu alloy film 206 (step 5, FIG. 2E) in preparation for the subsequent planarization process.

累積層207可接連著Cu合金膜206，藉由iPVD等之PVD 來成膜相同的Cu合金膜而形成，或是藉由PVD或鍍覆來形成純Cu膜。但從獲得良好產能之觀點，以及簡化裝置之觀點等來看，較佳宜使用與形成Cu合金膜206時相同的PVD(iPVD)裝置形成與Cu合金膜206相同的Cu合金膜來形成累積層207。由於累積層207幾乎不需考慮填補性，故以PVD進行成膜時，較佳宜以高於Cu合金膜206之成膜速度來形成。 The accumulation layer 207 may be connected to the Cu alloy film 206 by PVD of iPVD or the like. The same Cu alloy film is formed to form a film, or a pure Cu film is formed by PVD or plating. However, from the viewpoint of obtaining good productivity and the viewpoint of simplifying the device, it is preferable to form the same Cu alloy film as the Cu alloy film 206 by using the same PVD (iPVD) device as when the Cu alloy film 206 is formed to form a cumulative layer. 207. Since the buildup layer 207 hardly needs to be considered for filling, it is preferable to form it at a film formation rate higher than that of the Cu alloy film 206 when film formation is performed by PVD.

如此地成膜至累積層207為止後，依需要進行退火處理(步驟6，圖2F)。藉由此退火處理，來使Cu合金膜206變得穩定，且使Cu合金膜206中的合金成分移動至膜的上面，來抑制Cu的電子遷移。 After the film formation to the accumulation layer 207 as described above, annealing treatment is performed as needed (step 6, FIG. 2F). By this annealing treatment, the Cu alloy film 206 is stabilized, and the alloy component in the Cu alloy film 206 is moved to the upper surface of the film to suppress electron migration of Cu.

之後，藉由CMP(Chemical Mechanical Polishing)研磨晶圓W表面的整面，來去除累積層207、Ru內襯膜205、阻隔膜204以進行平坦化(步驟7，圖2G)。藉此於溝槽及介層孔(孔洞)內形成Cu配線208。 Thereafter, the entire surface of the surface of the wafer W is polished by CMP (Chemical Mechanical Polishing) to remove the accumulation layer 207, the Ru liner film 205, and the barrier film 204 to be planarized (Step 7, FIG. 2G). Thereby, the Cu wiring 208 is formed in the trench and the via hole (hole).

之後，於經CMP研磨後的Cu配線208上形成介電體(例如SiCN)所構成的罩蓋層209(步驟8，圖2H)。此時的成膜可藉由CVD來進行。 Thereafter, a cap layer 209 composed of a dielectric (for example, SiCN) is formed on the Cu wiring 208 after CMP polishing (step 8, FIG. 2H). Film formation at this time can be performed by CVD.

依據本實施型態，由於係藉由PVD來將含有電子遷移阻抗高於純Cu且電阻值為容許範圍程度的合金成分之Cu合金膜埋入溝槽或孔洞，故可防止藉由Cu鍍覆來填補的情況般之孔隙的產生，又，由於PVD法的雜質較少，故能夠以高精確度形成配線電阻的上昇較少、電子遷移阻抗高、且具有容許範圍的電阻值之組成的Cu合金膜。於是，可獲得不會產生孔隙等且可盡量抑制配線電阻上昇之電子遷移阻抗高的Cu配線。 According to the present embodiment, since the Cu alloy film containing the alloy composition having the electron mobility resistance higher than that of the pure Cu and having the resistance value to the allowable range is buried in the groove or the hole by the PVD, the Cu plating can be prevented by the Cu plating. In the case of the filling of the pores, the PVD method has a small amount of impurities, so that Cu with a low rise in wiring resistance, high electron transfer resistance, and a resistance range of an allowable range can be formed with high accuracy. Alloy film. As a result, it is possible to obtain a Cu wiring having high electron mobility resistance which does not cause voids or the like and which can suppress the increase in wiring resistance as much as possible.

此外，上述一連串的工序中，形成阻隔膜204之步驟2、形成Ru內襯膜205之步驟3、形成Cu合金膜206之步驟4、形成累積層207之步驟5雖然不曝露在大氣中而是在真空中連續成膜為佳，但亦可在該等任一步驟中曝露於大氣中。 Further, in the above-described series of steps, the step 2 of forming the barrier film 204, the step 3 of forming the Ru inner liner film 205, the step 4 of forming the Cu alloy film 206, and the step 5 of forming the accumulation layer 207 are not exposed to the atmosphere but It is preferred to continuously form a film in a vacuum, but it may be exposed to the atmosphere in any of the steps.

<Cu合金膜的形成例> <Formation Example of Cu Alloy Film>

接下來，說明Cu合金膜的形成例。 Next, an example of formation of a Cu alloy film will be described.

上述非專利文獻1係於基底上形成Cu合金種晶後再藉由Cu鍍覆來進行埋入，但係求得相當於使此時Cu合金種晶的組成為Cu-0.5at%Mn與Cu-0.8at%Mn之情況，亦即，使溝槽整體為Cu-Mn合金之情況的Mn濃度。此處係假設以底部覆蓋率80%、側邊覆蓋率20%來形成厚度30nm的Cu-Mn合金種晶層，在進行Cu鍍覆後，Mn會因退火而均勻地擴散之情況，來求得Mn濃度。 In the above-mentioned Non-Patent Document 1, a Cu alloy seed crystal is formed on a substrate and then buried by Cu plating. However, the composition corresponding to the seeding of the Cu alloy at this time is Cu-0.5 at% Mn and Cu. -0.8 at % Mn, that is, the Mn concentration in the case where the entire groove is a Cu-Mn alloy. Here, it is assumed that a Cu-Mn alloy seed layer having a thickness of 30 nm is formed with a bottom coverage of 80% and a side coverage of 20%. After Cu plating, Mn is uniformly diffused by annealing. The Mn concentration was obtained.

圖3A係顯示僅使配線(溝槽)內為Cu-Mn合金的情況，配線(溝槽)寬度與配線(Cu-Mn膜)中Mn濃度的關係之圖式。又，圖3B係顯示亦使累積的Cu(累積層：高度200nm)為Cu-Mn合金的情況，配線(溝槽)寬度與配線(Cu-Mn膜)中Mn濃度的關係之圖式。 3A is a view showing a relationship between the width of the wiring (groove) and the Mn concentration in the wiring (Cu-Mn film) in the case where only the inside of the wiring (groove) is a Cu-Mn alloy. In addition, FIG. 3B is a view showing a relationship between the width of the wiring (groove) and the Mn concentration in the wiring (Cu-Mn film) in the case where the accumulated Cu (accumulation layer: height: 200 nm) is a Cu-Mn alloy.

例如，在假想到累積層為止為Cu-Mn合金之圖3B中，若使習知技術中之Cu-Mn合金種晶的Mn濃度為0.5at.%，當欲埋入之配線寬度小於30nm的情況，則必須使約0.1at.%的Mn殘留於溝槽內。此處，如上所述，靶材合金組成與所成膜之Cu合金膜組成的關係會依壓力等成膜條件而變化，例如藉由iPVDCu來進行流動性佳的成膜而使壓力高達90mTorr左右的情況，由於已知膜中的Mn濃度會成為靶材濃度的大約一半(參閱日本特開2008-210971號公報)，因此iPVD裝置中使用的Cu-Mn合金靶材，其只要使用Mn濃度為0.2at.%的靶材即可。 For example, in FIG. 3B in which a Cu-Mn alloy is assumed to be a cumulative layer, if the Mn concentration of the Cu-Mn alloy seed crystal in the prior art is 0.5 at.%, when the wiring width to be buried is less than 30 nm, In this case, about 0.1 at.% of Mn must remain in the grooves. Here, as described above, the relationship between the composition of the target alloy and the composition of the Cu alloy film to be formed varies depending on film formation conditions such as pressure, for example, iPVDCu is used for film formation with good fluidity, and the pressure is as high as about 90 mTorr. In the case where the Mn concentration in the film is known to be about half of the target concentration (refer to Japanese Laid-Open Patent Publication No. 2008-210971), the Cu-Mn alloy target used in the iPVD device is used as long as the Mn concentration is 0.2at.% of the target can be.

<填補性評價> <filling evaluation>

接下來，使用Cu-Mn合金靶材(Mn0.2at.%)，來進行寬度20nm之溝槽的填補實驗。此處係在藉由iPVD形成4nm的TaN基底膜，藉由CVD形成2nm的Ru內襯膜後，以下述條件藉由iPVD來形成20nm的Cu-Mn合金膜而進行填補。 Next, a filling experiment of a trench having a width of 20 nm was performed using a Cu-Mn alloy target (Mn 0.2 at. %). Here, a TaN base film of 4 nm was formed by iPVD, and a Ru inner liner film of 2 nm was formed by CVD, and then a 20 nm Cu-Mn alloy film was formed by iPVD under the following conditions to be filled.

壓力：12Pa Pressure: 12Pa

靶材直流電流：7kW Target DC current: 7kW

偏壓高頻電功率：4kW Bias high frequency electric power: 4kW

處理溫度：250℃ Processing temperature: 250 ° C

其結果，如圖4之掃描型電子顯微鏡(SEM)相片所示，確認寬度20nm的溝槽已被充分填補。 As a result, as shown in the scanning electron microscope (SEM) photograph of Fig. 4, it was confirmed that the groove having a width of 20 nm was sufficiently filled.

<可應用於本發明實施型態的實施之成膜系統> <Film forming system applicable to the implementation of the embodiment of the invention>

接下來，針對可應用於本發明實施型態之Cu配線形成方法的實施之成膜系統加以說明。圖5係顯示可應用於本發明實施型態之Cu配線形成方法的實施之多腔室形式成膜系統的一例之俯視圖。 Next, a film formation system which can be applied to the implementation of the Cu wiring forming method of the embodiment of the present invention will be described. Fig. 5 is a plan view showing an example of a multi-chamber form film forming system which can be applied to the implementation of the Cu wiring forming method of the embodiment of the present invention.

成膜系統1具有形成阻隔膜及Ru內襯膜之第1處理部2、形成純Cu膜及Cu合金膜之第2處理部3、及搬出入部4，係用以於晶圓W形成Cu配線，會進行直到形成上述實施型態的累積層為止。 The film formation system 1 includes a first treatment portion 2 that forms a barrier film and a Ru inner liner film, a second treatment portion 3 that forms a pure Cu film and a Cu alloy film, and a carry-in/out portion 4 for forming a Cu wiring on the wafer W. It will proceed until the accumulation layer of the above embodiment is formed.

第1處理部2具有：平面形狀呈七角形之第1真空搬送室11；以及，連接於對應該第1真空搬送室11的4個邊之壁部之2個阻隔膜成膜裝置12a,12b及2個Ru內襯膜成膜裝置14a,14b。阻隔膜成膜裝置12a及Ru內襯膜成膜裝置14a與阻隔膜成膜裝置12b及Ru內襯膜成膜裝置14b係配置於線對稱的位置處。 The first processing unit 2 includes a first vacuum transfer chamber 11 having a rectangular parallelepiped shape, and two barrier film forming devices 12a and 12b connected to the wall portions of the four sides of the first vacuum transfer chamber 11 And two Ru inner liner film forming apparatuses 14a and 14b. The barrier film forming device 12a and the Ru inner film forming device 14a, the barrier film forming device 12b, and the Ru inner film forming device 14b are disposed at line symmetrical positions.

對應第1真空搬送室11的其他2個邊之壁部係連接有分別進行晶圓W的除氣處理之除氣室5a,5b。又，第1真空搬送室11之除氣室5a與5b之間的壁部係連接有在第1真空搬送室11與後述第2真空搬送室21之間進行晶圓W的傳遞之傳遞室5。 The degassing chambers 5a and 5b for performing the degassing treatment of the wafer W are connected to the wall portions of the other two sides of the first vacuum transfer chamber 11 . Further, the wall portion between the degassing chambers 5a and 5b of the first vacuum transfer chamber 11 is connected to a transfer chamber 5 for transferring the wafer W between the first vacuum transfer chamber 11 and the second vacuum transfer chamber 21, which will be described later. .

阻隔膜成膜裝置12a,12b、Ru內襯膜成膜裝置14a,14b、除氣室5a,5b及傳遞室5係透過閘閥G而連接於第1真空搬送室11的各邊，該等係藉由開放相對應的閘閥G而與第1真空搬送室11相連通，藉由關閉相對應的閘閥G而自第1真空搬送室11被阻隔。 The barrier film forming apparatuses 12a and 12b and the Ru inner liner film forming apparatuses 14a and 14b, the degassing chambers 5a and 5b, and the transfer chamber 5 are connected to the respective sides of the first vacuum transfer chamber 11 through the gate valve G. The first vacuum transfer chamber 11 is opened by opening the corresponding gate valve G, and is blocked from the first vacuum transfer chamber 11 by closing the corresponding gate valve G.

第1真空搬送室11內保持為特定的真空氛圍，當中設置有相對於阻隔膜成膜裝置12a,12b、Ru內襯膜成膜裝置14a,14b、除氣室5a,5b及傳遞室5進行晶圓W的搬出入之第1 搬送機構16。該第1搬送機構16係配設於第1真空搬送室11的略中央處，具有可旋轉及伸縮之旋轉/伸縮部17，該旋轉/伸縮部17的前端設置有用以支撐晶圓W之2個支撐臂18a,18b，該等2個支撐臂18a,18b係以朝向相反方向之型態而安裝於旋轉/伸縮部17。 The first vacuum transfer chamber 11 is maintained in a specific vacuum atmosphere, and is provided with respect to the barrier film forming devices 12a and 12b, the Ru inner film forming devices 14a and 14b, the degassing chambers 5a and 5b, and the transfer chamber 5. The first move of the wafer W Transport mechanism 16. The first transfer mechanism 16 is disposed at a substantially center of the first vacuum transfer chamber 11, and has a rotatable and expandable/retractable rotating/expanding portion 17, and a front end of the rotating/expanding portion 17 is provided to support the wafer W 2 The support arms 18a, 18b are attached to the rotation/expansion portion 17 in a shape opposite to each other.

第2處理部3具有：平面形狀呈八角形之第2真空搬送室21；連接於對應該第2真空搬送室21之相對向的2個邊之壁部，而用以成膜Cu合金膜的2個Cu合金膜成膜裝置22a,22b；以及，用以成膜純Cu膜或Cu合金膜之2個Cu膜成膜裝置24a及24b。 The second processing unit 3 has a second vacuum transfer chamber 21 having an octagonal planar shape, and a wall portion that is connected to two sides facing the second vacuum transfer chamber 21 to form a Cu alloy film. Two Cu alloy film forming apparatuses 22a and 22b; and two Cu film forming apparatuses 24a and 24b for forming a pure Cu film or a Cu alloy film.

對應於第2真空搬送室21之第1處理部2側的2個邊之壁部係分別連接有上述除氣室5a,5b，除氣室5a與5b之間的壁部連接有上述傳遞室5。亦即，傳遞室5及除氣室5a以及5b皆設置於第1真空搬送室11與第2真空搬送室21之間，傳遞室5的兩側配置有除氣室5a及5b。再者，搬出入部4側的邊係連接有可進行大氣搬送及真空搬送之加載互鎖室6。 The degassing chambers 5a and 5b are connected to the wall portions of the two sides on the first processing unit 2 side of the second vacuum transfer chamber 21, and the transfer chamber is connected to the wall portion between the degassing chambers 5a and 5b. 5. In other words, the transfer chamber 5 and the degassing chambers 5a and 5b are provided between the first vacuum transfer chamber 11 and the second vacuum transfer chamber 21, and the degassing chambers 5a and 5b are disposed on both sides of the transfer chamber 5. Further, a load lock chamber 6 capable of performing atmospheric transfer and vacuum transfer is connected to the side of the carry-in/out portion 4.

Cu合金膜成膜裝置22a,22b、Cu膜成膜裝置24a,24b、除氣室5a,5b及加載互鎖室6係透過閘閥G而連接於第2真空搬送室21的各邊，該等係藉由開放相對應的閘閥而與第2真空搬送室21相連通，藉由關閉相對應的閘閥G而自第2真空搬送室21被阻隔。又，傳遞室5係不透過閘閥G而連接於第2搬送室21。 The Cu alloy film forming apparatuses 22a and 22b, the Cu film forming apparatuses 24a and 24b, the degassing chambers 5a and 5b, and the load lock chamber 6 are connected to the respective sides of the second vacuum transfer chamber 21 through the gate valve G, and the like. The second vacuum transfer chamber 21 is connected to the second vacuum transfer chamber 21 by opening the corresponding gate valve, and is blocked from the second vacuum transfer chamber 21 by closing the corresponding gate valve G. Further, the transfer chamber 5 is connected to the second transfer chamber 21 without passing through the gate valve G.

第2真空搬送室21內保持為特定的真空氛圍，當中設置有相對於Cu合金膜成膜裝置22a,22b、Cu膜成膜裝置24a,24b、除氣室5a,5b、加載互鎖室6及傳遞室5進行晶圓W的搬出入之第2搬送機構26。該第2搬送機構26係配設於第2真空搬送室21的略中央處，具有可旋轉及伸縮的旋轉/伸縮部27，該旋轉/伸縮部27的前端設置有用以支撐晶圓W之2個支撐臂28a,28b，該等2個支撐臂28a,28b係以朝向相反方向之型態而安裝於旋轉/伸縮部27。 The second vacuum transfer chamber 21 is maintained in a specific vacuum atmosphere, and is provided with Cu alloy film forming apparatuses 22a and 22b, Cu film forming apparatuses 24a and 24b, degassing chambers 5a and 5b, and a load lock chamber. The transfer chamber 5 performs the second transfer mechanism 26 for carrying in and out of the wafer W. The second transfer mechanism 26 is disposed at a substantially center of the second vacuum transfer chamber 21, and has a rotatable/expandable portion 27 that is rotatable and expandable and contractible. The front end of the rotary/expandable portion 27 is provided to support the wafer W 2 The support arms 28a, 28b are attached to the rotation/expansion portion 27 in a shape opposite to each other.

搬出入部4係挾置著上述加載互鎖室6而設置於第2處理部3的相反側，具有連接於加載互鎖室6之大氣搬送室31。加載互鎖室6與大氣搬送室31之間的壁部設置有閘閥G。大氣搬送室31之與連接於加載互鎖室6的壁部相對向之壁部係設置有連接托架C(其係收納作為被處理基板的晶圓W)之2個連接埠32,33。該等連接埠32,33分別設置有圖中未顯示之擋門，將收納有晶圓W之狀態的托架C或空的托架C直接安裝在該等連接埠32,33，此時將擋門卸除以防止外氣的侵入同時與大氣搬送室31相連通。又，大氣搬送室31的側面設置有對位室34，於該處進行晶圓W的對位。大氣搬送室31內設置有相對於托架C進行晶圓W的搬出入及加載互鎖室6進行晶圓W的搬出入之大氣搬送用搬送機構36。該大氣搬送用搬送機構36具有2個多關節臂，可沿著托架C的配列方向在軌道38上行走，將晶圓W載置於分別之前端的機械手指37上來進行上述搬送。 The loading/unloading unit 4 is disposed on the opposite side of the second processing unit 3 with the load lock chamber 6 disposed thereon, and has an atmospheric transfer chamber 31 connected to the load lock chamber 6. A gate valve G is provided in a wall portion between the load lock chamber 6 and the atmospheric transfer chamber 31. The connection port C (which is a wafer W as a substrate to be processed) is provided to the wall portion of the atmospheric transfer chamber 31 and connected to the wall portion of the load lock chamber 6 so as to be connected to the wall portion. Each of the ports 32, 33 is provided with a door (not shown), and the carrier C or the empty carrier C in which the wafer W is stored is directly mounted to the ports 32, 33. The door is removed to prevent intrusion of outside air and communicate with the atmospheric transfer chamber 31. Further, a aligning chamber 34 is provided on the side surface of the atmospheric transfer chamber 31, and the wafer W is aligned there. In the atmospheric transfer chamber 31, an atmospheric transfer transport mechanism 36 that carries in and out of the wafer W and loads the lock chamber 6 to carry in and out the wafer W with respect to the carrier C is provided. The atmospheric transfer transport mechanism 36 has two multi-joint arms, and can travel on the rails 38 along the arrangement direction of the carriage C, and the wafers W are placed on the mechanical fingers 37 at the front ends to perform the above-described transport.

上述成膜系統1具有用以控制該成膜系統1的各構成部之控制部40。該控制部40具備：執行各構成部的控制之微處理器(電腦)所構成的製程控制器41；作業員為了管理成膜系統1而進行指令的輸入操作等之鍵盤、或可視化地顯示成膜系統1的運轉狀況之顯示器等所構成的使用者介面42；以及，儲存有藉由製程控制器41的控制來實現成膜系統1所執行的處理之控制程式、或對應於各種資訊及處理條件來使處理裝置的各構成部執行處理之程式(即配方)之記憶部43。此外，使用者介面42及記憶部43係連接於製程控制器41。 The film forming system 1 described above has a control unit 40 for controlling each component of the film forming system 1. The control unit 40 includes a process controller 41 including a microprocessor (computer) that performs control of each component, and a keyboard that is visually displayed by an operator to perform an input operation of a command to manage the film formation system 1 or the like. a user interface 42 formed of a display or the like of the operation state of the membrane system 1; and a control program for realizing processing performed by the film formation system 1 by the control of the process controller 41, or corresponding to various information and processing The condition is such that each component of the processing device executes the memory portion 43 of the program (i.e., recipe) of the process. Further, the user interface 42 and the memory unit 43 are connected to the process controller 41.

上述配方被記憶在記憶部43中的記憶媒體43a。記憶媒體可為硬碟，或是CDROM、DVD、快閃記憶體等的可移動性者。又，亦可從其他裝置透過例如專用回線來適當地傳送配方。 The above recipe is memorized in the memory medium 43a in the memory unit 43. The memory medium can be a hard disk, or a removable person such as a CDROM, a DVD, or a flash memory. Further, the recipe can be appropriately transferred from other devices through, for example, a dedicated return line.

然後，依需要，依據來自使用者介面42的指示等，從記憶部43呼叫出任意的配方並使製程控制器41執行，藉以在製程控制器41的控制下，於成膜系統1進行期望的處理。 Then, if necessary, an arbitrary recipe is called from the memory unit 43 and executed by the process controller 41 in accordance with an instruction from the user interface 42, etc., whereby the film forming system 1 performs the desired operation under the control of the process controller 41. deal with.

上述成膜系統1中，從托架C藉由大氣搬送用搬送機構36將形成有具有溝槽或孔洞的特定圖案之晶圓W取出，並搬送至加載互鎖室6，將該加載互鎖室6減壓至與第2真空搬送室21相同程度的真空度後，藉由第2搬送機構26將加載互鎖室6的晶圓W取出，經由第2真空搬送室21搬送至除氣室5a或5b，來進行晶圓W的除氣處理。之後，藉由第1搬送機構16取出除氣室5a(5b)的晶圓W，經由第1真空搬送室11搬入至阻隔膜成膜裝置12a或12b，來成膜上述般的阻隔膜。阻隔膜成膜後，藉由第1搬送機構16從阻隔膜成膜裝置12a或12b將晶圓W取出，並搬入至Ru內襯膜成膜裝置14a或14b，來成膜上述般的Ru內襯膜。Ru內襯膜成膜後，藉由第1搬送機構16從Ru內襯膜成膜裝置14a或14b將晶圓W取出，並搬送至傳遞室5。之後，藉由第2搬送機構26將晶圓W取出，經由第2真空搬送室21搬入至Cu合金膜成膜裝置22a或22b來形成上述般的Cu合金膜。之後，於Cu合金膜上形成累積層，累積層的形成可在相同的Cu合金膜成膜裝置22a或22b內連續形成Cu合金膜而進行，或是藉由第2搬送機構26從Cu合金膜成膜裝置22a或22b將晶圓W取出，並搬入至Cu膜成膜裝置24a或24b，而在該處形成純Cu膜或Cu合金膜來作為累積層。 In the film forming system 1 described above, the wafer W on which the specific pattern having the grooves or holes is formed is taken out from the carrier C by the atmospheric transfer transfer mechanism 36, and is transferred to the load lock chamber 6, and the load is interlocked. After the chamber 6 is decompressed to the same degree of vacuum as the second vacuum transfer chamber 21, the wafer W loaded in the lock chamber 6 is taken out by the second transfer mechanism 26, and is transported to the degassing chamber via the second vacuum transfer chamber 21. 5a or 5b, for degassing the wafer W. After that, the wafer W of the degassing chamber 5a (5b) is taken out by the first transfer mechanism 16 and carried into the barrier film forming apparatus 12a or 12b via the first vacuum transfer chamber 11, thereby forming the above-described barrier film. After the barrier film is formed, the first transfer mechanism 16 takes out the wafer W from the barrier film deposition device 12a or 12b, and carries it into the Ru inner liner film formation device 14a or 14b to form the above-mentioned Ru interior. Lining film. After the Ru liner film is formed, the wafer W is taken out from the Ru liner film forming apparatus 14a or 14b by the first transfer mechanism 16, and is transferred to the transfer chamber 5. After that, the wafer W is taken out by the second transfer mechanism 26, and the Cu alloy film forming apparatus 22a or 22b is carried into the second vacuum transfer chamber 21 to form the above-described Cu alloy film. Thereafter, an accumulation layer is formed on the Cu alloy film, and the formation of the accumulation layer can be performed by continuously forming a Cu alloy film in the same Cu alloy film forming apparatus 22a or 22b, or from the Cu alloy film by the second transfer mechanism 26. The film forming apparatus 22a or 22b takes out the wafer W and carries it into the Cu film forming apparatus 24a or 24b, where a pure Cu film or a Cu alloy film is formed as a buildup layer.

累積層的形成後，將晶圓W搬送至加載互鎖室6，將該加載互鎖室6回復至大氣壓後，藉由大氣搬送用搬送機構36來將形成有Cu膜之晶圓W取出，並返回托架C。重複上述處理，其次數係與托架內的晶圓W相同數量。 After the formation of the accumulation layer, the wafer W is transferred to the load lock chamber 6, and the load lock chamber 6 is returned to the atmospheric pressure, and then the wafer W on which the Cu film is formed is taken out by the atmospheric transfer transfer mechanism 36. And return to bracket C. The above process is repeated in the same number as the wafer W in the carriage.

依據成膜系統1，由於並非在大氣中開放，而是在真空中成膜阻隔膜、內襯膜、Cu合金膜及累積層，故可防止各膜的界面處發生氧化，從而可獲得高性能的Cu配線。 According to the film forming system 1, since the barrier film, the inner liner film, the Cu alloy film, and the accumulation layer are formed in a vacuum instead of being opened in the atmosphere, oxidation at the interface of each film can be prevented, and high performance can be obtained. Cu wiring.

此外，以Cu鍍覆形成累積層的情況，係在成膜Cu合金膜後，將晶圓W搬出。 Further, in the case where the Cu is formed by Cu plating, the wafer W is carried out after the Cu alloy film is formed.

<Cu合金膜成膜裝置> <Cu alloy film forming apparatus>

接下來，說明形成Cu合金膜之Cu合金膜成膜裝置22a(22b)的較佳例。 Next, a preferred example of the Cu alloy film forming apparatus 22a (22b) which forms a Cu alloy film will be described.

圖6係顯示Cu合金膜成膜裝置的一例之剖視圖。此處，係以iPVD之ICP(Inductively Coupled Plasma)型電漿濺射裝置作為Cu合金膜成膜裝置，以此為例來加以說明。 Fig. 6 is a cross-sectional view showing an example of a Cu alloy film forming apparatus. Here, an ICP (Inductively Coupled Plasma) plasma sputtering apparatus using iPVD is used as a Cu alloy film forming apparatus, and this will be described as an example.

如圖6所示，該Cu合金膜成膜裝置22a(22b)具有藉由例如鋁等而形成為筒體狀之處理容器51。該處理容器51為接地狀態，其底部52設置有排氣口53，排氣口53連接有排氣管54。排氣管54係連接有進行壓力調整之節流閥55及真空幫浦56，可將處理容器51內真空抽氣。又，處理容器51的底部52係設置有將特定氣體導入至處理容器51內之氣體導入口57。該氣體導入口57連接有氣體供應配管58，氣體供應配管58係連接有用以供應作為電漿激發用氣體之稀有氣體(例如Ar氣體)或其他需要的氣體(例如N2氣體)等之氣體供應源59。又，氣體供應配管58係介裝有氣體流量控制器、閥體等所構成的氣體控制部60。 As shown in FIG. 6, the Cu alloy film forming apparatus 22a (22b) has a processing container 51 formed into a cylindrical shape by, for example, aluminum or the like. The processing container 51 is in a grounded state, and a bottom portion 52 is provided with an exhaust port 53 to which an exhaust pipe 54 is connected. The exhaust pipe 54 is connected to a throttle valve 55 for performing pressure adjustment and a vacuum pump 56, and the inside of the processing container 51 can be evacuated. Further, the bottom portion 52 of the processing container 51 is provided with a gas introduction port 57 for introducing a specific gas into the processing container 51. The gas introduction port 57 is connected to a gas supply pipe 58 which is connected to a gas supply for supplying a rare gas (for example, Ar gas) as a plasma excitation gas or other required gas (for example, N 2 gas). Source 59. Further, the gas supply pipe 58 is provided with a gas control unit 60 including a gas flow controller, a valve body, and the like.

處理容器51內設置有用以載置被處理基板(即晶圓W)之載置機構62。該載置機構62具有形成為圓板狀之載置台63，及支撐載置台63且為接地之中空筒體狀的支柱64。載置台63係由例如鋁合金等的導電性材料所構成，透過支柱64而為接地。載置台63中設置有冷卻套65，透過圖中未顯示之冷媒流道來供應冷媒。又，載置台63內埋入有在冷卻套65上以絕緣材料加以披覆之電阻加熱器87。電阻加熱器87係從圖中未顯示之電源被供電。載置台63設置有熱電耦(圖中未顯示)，依據該熱電耦所檢測之溫度，來控制對冷卻套65之冷媒的供應及對電阻加熱器87的供電，藉此可將晶圓溫度控制為特定溫度。 A mounting mechanism 62 for placing a substrate to be processed (i.e., wafer W) is disposed in the processing container 51. The mounting mechanism 62 has a mounting table 63 formed in a disk shape, and a column 64 having a hollow cylindrical shape that supports the mounting table 63 and is grounded. The mounting table 63 is made of a conductive material such as aluminum alloy, and is grounded by the support 64. A cooling jacket 65 is provided in the mounting table 63, and the refrigerant is supplied through a refrigerant flow path (not shown). Further, an electric resistance heater 87 which is covered with an insulating material on the cooling jacket 65 is embedded in the mounting table 63. The electric resistance heater 87 is supplied with power from a power source not shown. The mounting table 63 is provided with a thermocouple (not shown), and according to the temperature detected by the thermocouple, the supply of the refrigerant to the cooling jacket 65 and the power supply to the electric resistance heater 87 are controlled, thereby controlling the wafer temperature. For a specific temperature.

載置台63的上面側係設置有例如氧化鋁等之介電體組件66a當中埋入有電極66b所構成的薄圓板狀靜電夾具66，可藉由靜電力來吸附保持晶圓W。又，支柱64的下部係貫穿處理容器51之底部52的中心部所形成之插通孔67而朝下方延伸。 支柱64可藉由圖中未顯示之升降機構而上下移動，藉此使載置機構62整體地升降。 On the upper surface side of the mounting table 63, a thin disk-shaped electrostatic chuck 66 in which an electrode 66b is embedded in a dielectric device 66a such as alumina is provided, and the wafer W can be adsorbed and held by an electrostatic force. Further, the lower portion of the pillar 64 extends downward through the insertion hole 67 formed in the center portion of the bottom portion 52 of the processing container 51. The pillar 64 can be moved up and down by an elevating mechanism not shown in the drawing, whereby the mounting mechanism 62 is integrally moved up and down.

圍繞支柱64般地設置有結構為可伸縮之蛇腹狀的金屬波紋管68，該金屬波紋管68的上端係氣密地接合於載置台63的下面，又，下端係氣密地接合於處理容器51之底部52的上面，可維持處理容器51內的氣密性，同時容許載置機構62的升降移動。 A metal bellows 68 having a bellows structure which is configured to be retractable is provided around the support 64. The upper end of the metal bellows 68 is airtightly joined to the lower surface of the mounting table 63, and the lower end is airtightly joined to the processing container. The upper surface of the bottom portion 52 of the 51 maintains the airtightness in the processing container 51 while allowing the lifting and lowering movement of the mounting mechanism 62.

又，底部52係直立地設置有朝向上方之例如3根(圖2中僅顯示2根)支撐銷69，又，對應於該支撐銷69而於載置台63形成有銷插通孔70。因此，當使載置台63下降時，便會以貫穿銷插通孔70之支撐銷69的上端部來承受晶圓W，可將該晶圓W在從外部侵入的搬送臂(圖中未顯示)之間進行移載。於是，處理容器51的下部側壁係設置有供搬送臂侵入用之搬出入口71，該搬出入口71設置有可開閉之閘閥G。該閘閥G的相反側設置有前述第2真空搬送室21。 Further, the bottom portion 52 is provided with, for example, three (only two are shown in FIG. 2) support pins 69 facing upward, and a pin insertion hole 70 is formed in the mounting table 63 corresponding to the support pins 69. Therefore, when the mounting table 63 is lowered, the wafer W is received by the upper end portion of the support pin 69 penetrating the pin insertion hole 70, and the wafer W can be invaded from the outside (not shown in the drawing) Transfer between. Then, the lower side wall of the processing container 51 is provided with a carry-out port 71 for intrusion of the transfer arm, and the carry-out port 71 is provided with an openable and closable gate valve G. The second vacuum transfer chamber 21 is provided on the opposite side of the gate valve G.

又，上述靜電夾具66的電極66b係透過供電線72而連接有夾具用電源73，從該夾具用電源73對電極66b施加直流電壓，而藉由靜電力來吸附保持晶圓W。又，供電線72係連接有偏壓用高頻電源74，透過該供電線72來對靜電夾具66的電極66b供應偏壓用高頻電功率，藉以對晶圓W施加偏壓電功率。該高頻電功率的頻率較佳為400kHz~60MHz，係採用例如13.56MHz。 Further, the electrode 66b of the electrostatic chuck 66 is connected to the power supply 73 for the jig through the power supply line 72, and a DC voltage is applied to the electrode 66b from the power supply 73 for the clamp, and the wafer W is adsorbed and held by the electrostatic force. Further, the power supply line 72 is connected to the bias high-frequency power source 74, and the bias voltage high-frequency electric power is supplied to the electrode 66b of the electrostatic chuck 66 through the power supply line 72, whereby bias electric power is applied to the wafer W. The frequency of the high-frequency electric power is preferably 400 kHz to 60 MHz, and is, for example, 13.56 MHz.

另一方面，處理容器51的頂部係透過O型環等密封組件77而氣密地設置有由例如氧化鋁等介電體所構成且相對於高頻具有穿透性之穿透板76。然後，該穿透板76的上部係設置有於處理容器51內的處理空間S使作為電漿激發用氣體之稀有氣體(例如Ar氣體)電漿化來產生電漿之電漿產生源78。此外，亦可取代Ar而使用其他稀有氣體(例如He、Ne、Kr等)來作為該電漿激發用氣體。 On the other hand, the top of the processing container 51 is airtightly provided with a penetrating plate 76 made of a dielectric material such as alumina and having transparency with respect to high frequency, through a sealing member 77 such as an O-ring. Then, the upper portion of the penetrating plate 76 is provided with a plasma generating source 78 which generates a plasma by plasma-treating a rare gas (for example, Ar gas) as a plasma excitation gas in the processing space S in the processing container 51. Further, other rare gases (for example, He, Ne, Kr, etc.) may be used in place of Ar as the plasma excitation gas.

電漿產生源78係具有對應於穿透板76所設置之誘導線圈 80，該誘導線圈80連接有電漿產生用之例如13.56MHz的高頻電源81，透過上述穿透板76對處理空間S導入高頻電功率而形成誘導電場。 The plasma generating source 78 has an induction coil corresponding to the penetrating plate 76. 80. The induction coil 80 is connected to a high-frequency power source 81 for generating a plasma, for example, 13.56 MHz, and introduces high-frequency electric power into the processing space S through the transmission plate 76 to form an induced electric field.

又，穿透板76的正下方係設置有用以使所導入的高頻電功率擴散之例如鋁所構成的隔板82。然後，該隔板82的下部係設置有圍繞上述處理空間S的上部側邊且例如剖面朝向內側呈傾斜之環狀(截頭圓錐殻狀)的Cu合金所構成之靶材83，該靶材83係連接有施加Ar離子吸引用的直流電力之靶材用電壓可變式直流電源84。此外，亦可取代直流電源而使用交流電源。靶材83係由與Cu合金膜相同種類的Cu合金所形成。 Further, a spacer 82 made of, for example, aluminum for diffusing the introduced high-frequency electric power is provided directly below the penetrating plate 76. Then, a lower portion of the partition plate 82 is provided with a target 83 composed of a Cu alloy which surrounds the upper side of the processing space S and has an annular shape (frustum-shell shape) which is inclined toward the inner side, for example, the target material A voltage variable type DC power supply 84 for a target to which DC power for attracting Ar ions is applied is connected to the 83 system. In addition, AC power can be used instead of DC power. The target 83 is formed of the same type of Cu alloy as the Cu alloy film.

又，靶材83的外周側係設置有對其賦予磁場之磁石85。靶材83會因電漿中的Ar離子而被濺射成為Cu的金屬原子或金屬原子團，且通過電漿中時大部分會被離子化。 Further, a magnet 85 to which a magnetic field is applied is provided on the outer peripheral side of the target 83. The target 83 is sputtered into a metal atom or a metal atom of Cu due to Ar ions in the plasma, and is mostly ionized when passing through the plasma.

又，該靶材83的下部係設置有圍繞上述處理空間S且由例如鋁或銅所構成的圓筒狀保護蓋組件86。該保護蓋組件86為接地，且其下部係朝內側彎曲而位在載置台63的側部附近。因此，保護蓋組件86內側的端部便會圍繞載置台63的外周側般所設置。 Further, a lower portion of the target member 83 is provided with a cylindrical protective cover assembly 86 that surrounds the processing space S and is made of, for example, aluminum or copper. The protective cover assembly 86 is grounded, and its lower portion is bent toward the inner side and is located near the side of the mounting table 63. Therefore, the end portion of the inner side of the protective cover assembly 86 is disposed around the outer peripheral side of the mounting table 63.

此外，Cu合金膜成膜裝置的各構成部亦受到上述控制部40的控制。 Further, each component of the Cu alloy film forming apparatus is also controlled by the above-described control unit 40.

在上述方式構成的Cu合金膜成膜裝置中，將晶圓W搬入至圖6所示之處理容器51內，將該晶圓W載置於載置台63上且藉由靜電夾具66來吸附，而在控制部40的控制下進行以下動作。此時，載置台63係藉由依據熱電耦(圖中未顯示)所檢測之溫度，來控制對冷卻套65之冷媒的供應及對電阻加熱器87的供電而受到溫度控制。 In the Cu alloy film forming apparatus configured as described above, the wafer W is carried into the processing container 51 shown in FIG. 6, and the wafer W is placed on the mounting table 63 and adsorbed by the electrostatic chuck 66. The following operations are performed under the control of the control unit 40. At this time, the mounting table 63 is controlled in temperature by controlling the supply of the refrigerant to the cooling jacket 65 and the supply of the electric resistance to the electric resistance heater 87 by the temperature detected by the thermocouple (not shown).

首先，藉由使真空幫浦56動作而在已成為特定的真空狀態之處理容器51內，操作氣體控制部60並以特定流量導入Ar氣體且控制節流閥55，來將處理容器51內維持為特定真空度。之後，從可變直流電源84對直流電力施加靶材83，且從 電漿產生源78的高頻電源81對誘導線圈80供應高頻電功率(電漿電力)。另一方面，從偏壓用高頻電源74對靜電夾具66的電極66b供應特定的偏壓用高頻電功率。 First, by operating the vacuum pump 56, the gas control unit 60 is operated in a specific vacuum state, and the Ar gas is introduced at a specific flow rate, and the throttle valve 55 is controlled to maintain the inside of the processing container 51. For a specific degree of vacuum. Thereafter, the target 83 is applied to the DC power from the variable DC power source 84, and The high frequency power source 81 of the plasma generating source 78 supplies high frequency electric power (plasma power) to the induction coil 80. On the other hand, a specific bias high-frequency electric power is supplied from the bias high-frequency power source 74 to the electrode 66b of the electrostatic chuck 66.

藉此，處理容器51內中，便會因供應至誘導線圈80之高頻電功率而形成氬電漿且生成氬離子，該等離子會被吸引靠近施加在靶材83之直流電壓而衝撞靶材83，該靶材83被濺射而釋放出粒子。此時，因施加在靶材83之直流電壓而釋放出的粒子量會受到最佳控制。 Thereby, in the inside of the processing container 51, argon plasma is formed due to the high-frequency electric power supplied to the induction coil 80, and argon ions are generated, which are attracted to the DC voltage applied to the target 83 to collide with the target 83. The target 83 is sputtered to release particles. At this time, the amount of particles released due to the DC voltage applied to the target 83 is optimally controlled.

又，來自被濺射的靶材83之粒子在通過電漿中時，大部分會被離子化。此處，從靶材83釋放出的粒子會成為混合有受到離子化者與電中性的中性原子之狀態而朝下方飛散而去。特別是，將該處理容器51內的壓力某種程度地提高，藉以提高電漿密度，藉此可以高效率來使粒子離子化。此時的離子化率係藉由從高頻電源81所供應之高頻電功率來進行控制。 Further, most of the particles from the sputtered target 83 are ionized when passing through the plasma. Here, the particles released from the target 83 are dispersed in a state in which an ionized person and an electrically neutral neutral atom are mixed and scattered downward. In particular, the pressure in the processing container 51 is increased to some extent, thereby increasing the plasma density, whereby the particles can be ionized with high efficiency. The ionization rate at this time is controlled by the high frequency electric power supplied from the high frequency power source 81.

然後，當離子因從高頻電源74對靜電夾具66的電極66b所施加之偏壓用高頻電功率而進入形成於晶圓W面上之厚度數mm左右的離子鞘層區域時，會具有強指向性而朝晶圓W側加速般地被吸引，沉積在晶圓W而形成Cu合金膜。 Then, when the ions enter the ion sheath layer region having a thickness of about several mm formed on the surface of the wafer W by the high frequency electric power applied from the high frequency power source 74 to the electrode 66b of the electrostatic chuck 66, it is strong. The directivity is attracted to the wafer W side by directivity, and is deposited on the wafer W to form a Cu alloy film.

此時，係將晶圓溫度設定為較高(65~350℃)，且調整從偏壓用高頻電源74對靜電夾具66的電極66b所施加之偏壓功率來調整Cu合金的成膜與藉由Ar之蝕刻，藉此使Cu合金的流動性良好，則縱使開口狹窄的溝槽或孔洞，仍可以良好的填補性來將Cu合金埋入。具體來說，若使Cu合金成膜量(成膜率)為TD，使藉由電漿生成用氣體的離子之蝕刻量(蝕刻率)為TE，則較佳宜將偏壓功率調整為0≦TE/TD<1，更佳為0<TE/TD<1。 At this time, the wafer temperature is set to be high (65 to 350 ° C), and the bias power applied from the bias high-frequency power source 74 to the electrode 66b of the electrostatic chuck 66 is adjusted to adjust the film formation of the Cu alloy. By the etching of Ar, the fluidity of the Cu alloy is improved, and even if the opening or the groove or the hole is narrow, the Cu alloy can be buried with good filling properties. Specifically, when the film forming amount (film forming rate) of the Cu alloy is T D and the etching amount (etching rate) of ions by the plasma generating gas is T E , it is preferable to adjust the bias power. 0 ≦ T E / T D < 1, more preferably 0 < T E / T D < 1.

從獲得良好填補性的觀點來看，處理容器51內的壓力(製程壓力)較佳為1~100mTorr(0.133~13.3Pa)，更佳為35~90mTorr(4.66~12.0Pa)，對靶材之直流電力較佳為4~12kW，更佳為6~10kW。 From the viewpoint of obtaining a good filling property, the pressure (process pressure) in the processing container 51 is preferably from 1 to 100 mTorr (0.133 to 13.3 Pa), more preferably from 35 to 90 mTorr (4.66 to 12.0 Pa), to the target. The DC power is preferably 4 to 12 kW, more preferably 6 to 10 kW.

此外，若溝槽或孔洞的開口較寬之情況等，可將晶圓溫度 設定為較低(-50~0℃)，且使處理容器51內的壓力更低來進行成膜。藉此，可提高成膜率。又，上述情況不限於iPVD，亦可使用通常的濺射、離子鍍覆等之通常的PVD。 In addition, if the opening of the trench or the hole is wide, the wafer temperature can be increased. Film formation was carried out by setting it to a lower temperature (-50 to 0 ° C) and lowering the pressure in the processing container 51. Thereby, the film formation rate can be improved. Further, the above case is not limited to iPVD, and ordinary PVD such as sputtering or ion plating may be used.

<Cu膜成膜裝置> <Cu film forming device>

Cu膜成膜裝置24a(24b)基本上可使用與圖6所示之Cu合金膜成膜裝置22a(22b)同樣的裝置。此時，靶材83只要對應於欲獲得的膜來適當地調整材料即可。又，不須重視填補性的情況等，則不限於iPVD，而亦可使用通常的濺射、離子鍍覆等通常的PVD。 The Cu film forming apparatus 24a (24b) can basically use the same apparatus as the Cu alloy film forming apparatus 22a (22b) shown in Fig. 6. At this time, the target 83 may be appropriately adjusted in accordance with the film to be obtained. In addition, it is not limited to iPVD, and ordinary PVD such as sputtering or ion plating may be used, without paying attention to the filling property.

<阻隔膜成膜裝置> <Resistance film forming device>

作為阻隔膜成膜裝置12a(12b)，只要將靶材83改變為所使用之材料，則可使用與圖6之成膜裝置同樣結構的成膜裝置而藉由電漿濺射來進行成膜。又，不限於電漿濺射，可為通常的濺射、離子鍍覆等其他的PVD，或是CVD(Chemical Vapor Deposition)或ALD(Atomic Layer Deposition)、使用電漿之CVD或ALD來進行成膜。從降低雜質之觀點來看，較佳為PVD。 As the barrier film forming apparatus 12a (12b), as long as the target 83 is changed to the material to be used, film formation by the plasma deposition method using the film forming apparatus having the same structure as that of the film forming apparatus of Fig. 6 can be used. . Further, it is not limited to plasma sputtering, and may be formed by other PVD such as ordinary sputtering or ion plating, or CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), plasma CVD or ALD. membrane. From the viewpoint of reducing impurities, PVD is preferred.

<Ru膜成膜裝置> <Ru film forming device>

接下來，說明用以形成Ru內襯膜之Ru內襯膜成膜裝置14a(14b)。Ru內襯膜較佳地可藉由熱CVD來形成。圖7係顯示Ru內襯膜成膜裝置的一例之剖視圖，係藉由熱CVD來形成Ru膜。 Next, a Ru inner liner film forming apparatus 14a (14b) for forming a Ru inner liner film will be described. The Ru liner film is preferably formed by thermal CVD. Fig. 7 is a cross-sectional view showing an example of a Ru liner film forming apparatus, in which a Ru film is formed by thermal CVD.

如圖7所示，該Ru內襯膜成膜裝置14a(14b)具有由例如鋁等而形成為筒體之處理容器101。處理容器101的內部係配置有用以載置晶圓W之例如AlN等陶瓷所構成的載置台102，該載置台102內設置有加熱器103。該加熱器103係藉由從加熱器電源(圖中未顯示)被供電而發熱。 As shown in Fig. 7, the Ru inner liner film forming apparatus 14a (14b) has a processing container 101 formed of a cylinder such as aluminum. The inside of the processing container 101 is provided with a mounting table 102 made of a ceramic such as AlN on which the wafer W is placed, and a heater 103 is provided in the mounting table 102. The heater 103 generates heat by being supplied with power from a heater power source (not shown).

處理容器101的頂壁處，與載置台102呈對向地設置有用以將Ru膜形成用的處理氣體或吹淨氣體等噴淋狀地導入至處理容器101內之噴淋頭104。噴淋頭104的上部具有氣體導入口105，其內部形成有氣體擴散空間106，其底面形成有多個 氣體噴出孔107。氣體導入口105連接有氣體供應配管108，氣體供應配管108係連接有用以供應Ru膜形成用的處理氣體或吹淨氣體等之氣體供應源109。又，氣體供應配管108係介裝有氣體流量控制器、閥體等所構成的氣體控制部110。用以形成Ru膜之氣體如上所述，較佳可舉出十二羰三釕(Ru3(CO)12)。此十二羰三釕可藉由熱分解而形成Ru膜。 At the top wall of the processing container 101, a shower head 104 for introducing a processing gas for forming a Ru film or a purge gas into the processing container 101 in a shower shape is provided in opposition to the mounting table 102. The upper portion of the shower head 104 has a gas introduction port 105 in which a gas diffusion space 106 is formed, and a plurality of gas ejection holes 107 are formed on the bottom surface thereof. A gas supply pipe 108 is connected to the gas introduction port 105, and the gas supply pipe 108 is connected to a gas supply source 109 for supplying a processing gas or a purge gas for forming a Ru film. Further, the gas supply pipe 108 is provided with a gas control unit 110 including a gas flow controller, a valve body, and the like. As described above, the gas for forming the Ru film is preferably dodecyltriazine (Ru 3 (CO) 12 ). This dodecacarbonyl triazine can form a Ru film by thermal decomposition.

處理容器101的底部設置有排氣口111，該排氣口111連接有排氣管112。排氣管112係連接有進行壓力調整之節流閥113及真空幫浦114，可將處理容器101內抽真空。 The bottom of the processing container 101 is provided with an exhaust port 111 to which an exhaust pipe 112 is connected. The exhaust pipe 112 is connected to a throttle valve 113 for performing pressure adjustment and a vacuum pump 114, and the inside of the processing container 101 can be evacuated.

載置台102係設置有可相對於載置台102的表面突陷之晶圓搬送用的3根(僅圖示2根)晶圓支撐銷116，該等晶圓支撐銷116被固定在支撐板117。然後，晶圓支撐銷116係藉由以氣壓缸等的驅動機構118來升降桿體119，而透過支撐板117被升降。此外，符號120為波紋管。另一方面，處理容器101的側壁形成有晶圓搬出入口121，在打開閘閥G之狀態下，在與第1真空搬送室11之間處進行晶圓W的搬出入。 The mounting table 102 is provided with three (only two) wafer support pins 116 for wafer transfer that can be protruded with respect to the surface of the mounting table 102, and the wafer support pins 116 are fixed to the support plate 117. . Then, the wafer support pin 116 is lifted and lowered by the support plate 117 by the drive mechanism 118 such as a pneumatic cylinder. Further, symbol 120 is a bellows. On the other hand, the wafer carry-out port 121 is formed in the side wall of the processing container 101, and the wafer W is carried in and out between the first vacuum transfer chamber 11 in a state where the gate valve G is opened.

在上述Ru內襯膜成膜裝置14a(14b)中，打開閘閥G，將晶圓W載置於載置台102上後，關閉閘閥G，將處理容器101內藉由真空幫浦114來排氣而將處理容器101內調整為特定壓力，同時藉由加熱器103且透過載置台102來將晶圓W加熱至特定溫度之狀態下，從氣體供應源109經由氣體供應配管108及噴淋頭104將十二羰三釕(Ru3(CO)12)氣體等的處理氣體朝處理容器101內導入。藉此，處理氣體便會在晶圓W上進行反應，而於晶圓W的表面形成有Ru膜。 In the Ru liner film forming apparatus 14a (14b), the gate valve G is opened, the wafer W is placed on the mounting table 102, the gate valve G is closed, and the inside of the processing chamber 101 is exhausted by the vacuum pump 114. The inside of the processing chamber 101 is adjusted to a specific pressure, and the wafer W is heated to a specific temperature by the heater 103 and transmitted through the mounting table 102, and the gas supply source 109 and the shower head 104 are supplied from the gas supply source 109. A processing gas such as a ruthenium tricarbonyl (Ru 3 (CO) 12 ) gas or the like is introduced into the processing container 101. Thereby, the processing gas reacts on the wafer W, and a Ru film is formed on the surface of the wafer W.

有關Ru膜的成膜，亦可將十二羰三釕以外的其他成膜原料，例如將上述般之釕的環戊二烯化合物使用於如O2氣體般之分解氣體。又，亦可藉由PVD來形成Ru膜。但由可獲得良好的階梯覆蓋率，且減少膜的雜質之觀點來看，較佳宜使用十二羰三釕而藉由CVD來成膜。 Regarding the film formation of the Ru film, other film-forming materials other than the dodecyl triazine may be used, for example, the above-mentioned cyclopentadiene compound is used as a decomposition gas such as O 2 gas. Further, the Ru film can also be formed by PVD. However, from the viewpoint of obtaining good step coverage and reducing impurities of the film, it is preferred to form a film by CVD using tridecacarbonyl triazine.

<其他工序中使用的裝置> <Device used in other processes>

雖可藉由以上的成膜系統1來進行直到上述實施型態之累積層的形成為止，但其之後的退火工序、CMP工序、罩蓋層成膜工序則可使用退火裝置、CMP裝置、罩蓋層成膜裝置來對從成膜系統1搬出後的晶圓W進行。該等裝置可為通常所使用的結構。以該等裝置與成膜系統1來構成Cu配線形成系統，且藉由具有與控制部40相同功能之共通的控制部來一起進行控制，藉此，便可以一個配方來一起控制上述實施型態所示之方法。 The formation of the accumulation layer of the above-described embodiment can be carried out by the film formation system 1 described above, but the annealing step, the CMP step, and the cap layer forming step can be performed using an annealing device, a CMP device, or a cover. The cap layer film forming apparatus performs the wafer W that has been carried out from the film forming system 1. These devices can be of the type commonly used. The Cu wiring forming system is configured by the apparatus and the film forming system 1, and is controlled by a control unit having the same function as the control unit 40, whereby the above-described embodiment can be controlled together by one recipe. The method shown.

<其他應用> <Other applications>

以上，雖已針對本發明之實施型態加以說明，但本發明不限於上述實施型態，可做各種變化。例如，成膜系統不限於圖5般的型態，亦可為於一個搬送裝置連接有全部的成膜裝置之型態。又，可非為圖5般之多腔室形式的系統，可以相同的成膜系統來形成阻隔膜、Ru內襯膜、純Cu膜(純Cu種晶膜)、Cu合金膜當中的一部分，而藉由個別地設置之裝置，經由大氣曝露來成膜其餘的部分，或是以個別的裝置，經由大氣曝露來成膜所有的膜。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the film forming system is not limited to the type shown in Fig. 5, and may be a type in which all of the film forming apparatuses are connected to one conveying device. Moreover, instead of the multi-chamber system of the form shown in FIG. 5, a part of the barrier film, the Ru inner liner film, the pure Cu film (pure Cu seed film), and the Cu alloy film may be formed by the same film forming system. On the other hand, all the films are formed by atmospheric exposure to form the remaining portions, or by individual means, by atmospheric exposure.

再者，上述實施型態中，雖係顯示將本發明之方法應用於具有溝槽與介層孔(孔洞)之晶圓，但無需贅言亦可將本發明應用於僅具有溝槽的情況，或僅具有孔洞的情況。又，可應用於單鑲嵌構造、雙鑲嵌構造、三維組裝構造等各種構造之元件中的填補。又，上述實施型態中，雖係以半導體晶圓作為被處理基板，以此為例來加以說明，但半導體晶圓不僅是矽，而亦包含GaAs、SiC、GaN等之化合物半導體，再者，不限於半導體晶圓，當然亦可將本發明應用於液晶顯示裝置等的FPD(平板顯示器)所使用之玻璃基板，或陶瓷基板等。 Furthermore, in the above embodiment, although the method of the present invention is applied to a wafer having trenches and via holes (holes), it is needless to say that the present invention can also be applied to a case where only trenches are provided. Or only with holes. Moreover, it can be applied to the filling of components of various structures such as a single damascene structure, a dual damascene structure, and a three-dimensional assembly structure. Further, in the above-described embodiment, a semiconductor wafer is used as a substrate to be processed, and this is exemplified. However, the semiconductor wafer includes not only germanium but also a compound semiconductor such as GaAs, SiC or GaN. The present invention is not limited to a semiconductor wafer, and the present invention can be applied to a glass substrate used for an FPD (flat panel display) such as a liquid crystal display device, or a ceramic substrate.

步驟1‧‧‧準備具有形成有溝槽的層間絕緣膜之晶圓 Step 1‧‧‧ Preparing a wafer having an interlayer insulating film formed with a trench

步驟2‧‧‧形成阻隔膜 Step 2‧‧‧ Forming a barrier film

步驟3‧‧‧形成Ru內襯膜 Step 3‧‧‧Forming a Ru inner liner

步驟4‧‧‧藉由PVD(iPVD)形成Cu合金膜來幾乎完全地填補溝槽 Step 4‧‧‧ Fill the trench almost completely by forming a Cu alloy film by PVD (iPVD)

步驟5‧‧‧形成累積層 Step 5‧‧‧ Forming a cumulative layer

步驟6‧‧‧退火 Step 6‧‧‧ Annealing

步驟7‧‧‧藉由CMP進行整面研磨而形成Cu配線 Step 7‧‧‧Cutting the entire surface by CMP

步驟8‧‧‧於Cu配線上形成介電體所構成的罩蓋層 Step 8‧‧‧ forming a cap layer composed of a dielectric body on the Cu wiring

Claims (12)

一種Cu配線的形成方法，係在形成於基板之特定圖案的凹部內形成Cu配線，具有以下工序：於至少該凹部的表面形成阻隔膜之工序；藉由PVD形成含有電子遷移阻抗高於純Cu且電阻值為容許範圍程度的合金成分之Cu合金膜，而以該Cu合金膜來填補於該表面形成有阻隔膜之該凹部內之工序；於該Cu合金膜上形成累積層之工序；以及藉由CMP進行整面研磨而於該凹部內形成Cu配線之工序。 A method for forming a Cu wiring, wherein a Cu wiring is formed in a recess formed in a specific pattern of a substrate, and a step of forming a barrier film on at least a surface of the recess; and forming an electron transport resistance higher than pure Cu by PVD formation And a Cu alloy film having a resistance value as an alloy component of an allowable range, wherein the Cu alloy film fills a step in which the concave portion of the barrier film is formed; and a process of forming a buildup layer on the Cu alloy film; The step of forming a Cu wiring in the recess by CMP full-surface polishing. 如申請專利範圍第1項之Cu配線的形成方法，其中係對應於成膜條件來決定進行PVD時之靶材的合金成分濃度，以使該Cu合金膜的合金成分濃度成為特定值。 In the method for forming a Cu wiring according to the first aspect of the invention, the alloy component concentration of the target in the PVD is determined in accordance with the film formation conditions so that the alloy component concentration of the Cu alloy film becomes a specific value. 如申請專利範圍第1項之Cu配線的形成方法，其係於形成該阻隔膜後，且於形成該Cu合金膜之前，另具有形成Ru膜之工序。 The method for forming a Cu wiring according to the first aspect of the patent application is the step of forming a Ru film after forming the barrier film and before forming the Cu alloy film. 如申請專利範圍第3項之Cu配線的形成方法，其中該Ru膜係藉由CVD所形成。 A method of forming a Cu wiring according to claim 3, wherein the Ru film is formed by CVD. 如申請專利範圍第1項之Cu配線的形成方法，其中該Cu合金膜的形成係於收納有基板之處理容器內，藉由電漿生成氣體來生成電漿，且由與欲獲得之Cu合金膜相同的Cu合金所構成之靶材使粒子濺射，在該電漿中使粒子離子化，並對該基板施加偏壓電功率，藉以將離子吸引至基板上之裝置而進行。 The method for forming a Cu wiring according to the first aspect of the invention, wherein the Cu alloy film is formed in a processing container in which the substrate is housed, and a plasma is generated by the plasma to generate a plasma, and the Cu alloy to be obtained is obtained. A target made of a Cu alloy having the same film is sputtered with particles, and ions are ionized in the plasma, and bias electric power is applied to the substrate to attract ions to the device on the substrate. 如申請專利範圍第1項之Cu配線的形成方法，其中該累積層的形成係藉由PVD來形成Cu合金膜或純Cu膜而進行。 A method of forming a Cu wiring according to the first aspect of the invention, wherein the formation of the accumulation layer is performed by forming a Cu alloy film or a pure Cu film by PVD. 如申請專利範圍第1項之Cu配線的形成方法，其中該累積層的形成係在形成該Cu合金膜後，藉由相同裝置來形成相同的Cu合金而進行。 A method of forming a Cu wiring according to the first aspect of the invention, wherein the formation of the accumulation layer is performed by forming the Cu alloy film and forming the same Cu alloy by the same apparatus. 如申請專利範圍第1項之Cu配線的形成方法，其中構成該Cu合金膜之Cu合金係選自Cu-Al、Cu-Mn、Cu-Mg、Cu-Ag、Cu-Sn、Cu-Pb、Cu-Zn、Cu-Pt、Cu-Au、Cu-Ni、Cu-Co及Cu-Ti。 The method for forming a Cu wiring according to the first aspect of the invention, wherein the Cu alloy constituting the Cu alloy film is selected from the group consisting of Cu-Al, Cu-Mn, Cu-Mg, Cu-Ag, Cu-Sn, Cu-Pb, Cu-Zn, Cu-Pt, Cu-Au, Cu-Ni, Cu-Co, and Cu-Ti. 如申請專利範圍第8項之Cu配線的形成方法，其中構成該Cu合金膜之Cu合金為Cu-Mn。 A method of forming a Cu wiring according to the eighth aspect of the invention, wherein the Cu alloy constituting the Cu alloy film is Cu-Mn. 如申請專利範圍第8項之Cu配線的形成方法，其中構成該Cu合金膜之Cu合金為Cu-Al。 A method of forming a Cu wiring according to the eighth aspect of the invention, wherein the Cu alloy constituting the Cu alloy film is Cu-Al. 如申請專利範圍第1項之Cu配線的形成方法，其中該阻隔膜係選自Ti膜、TiN膜、Ta膜、TaN膜、Ta/TaN的2層膜、TaCN膜、W膜、WN膜、WCN膜、Zr膜、ZrN膜、V膜、VN膜、Nb膜、NbN膜所構成之群。 The method for forming a Cu wiring according to the first aspect of the invention, wherein the barrier film is selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a Ta/TaN 2-layer film, a TaCN film, a W film, a WN film, A group consisting of a WCN film, a Zr film, a ZrN film, a V film, a VN film, an Nb film, and an NbN film. 一種電腦可讀取之記憶媒體，係在電腦上動作，而記憶有用以控制Cu配線形成系統的程式，其中該程式在執行時會使電腦控制該Cu配線形成系統，以進行如申請專利範圍第1項之Cu配線的形成方法。 A computer readable memory medium that operates on a computer and stores a program for controlling a Cu wiring forming system, wherein the program causes the computer to control the Cu wiring forming system during execution to perform the patent application scope A method of forming a Cu wiring of one item.
TW102124320A 2012-07-09 2013-07-08 METHOD FOR FORMING Cu WIRING, AND COMPUTER-READABLE MEMORY MEDIUM TW201415554A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012153244A JP2014017345A (en) 2012-07-09 2012-07-09 Cu WIRING FORMATION METHOD

Publications (1)

Publication Number Publication Date
TW201415554A true TW201415554A (en) 2014-04-16

Family

ID=49915806

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102124320A TW201415554A (en) 2012-07-09 2013-07-08 METHOD FOR FORMING Cu WIRING, AND COMPUTER-READABLE MEMORY MEDIUM

Country Status (3)

Country Link
JP (1) JP2014017345A (en)
TW (1) TW201415554A (en)
WO (1) WO2014010333A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157784B2 (en) * 2016-02-12 2018-12-18 Tokyo Electron Limited Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization
JP6807251B2 (en) * 2017-03-02 2021-01-06 東京エレクトロン株式会社 How to manufacture ruthenium wiring
US10204829B1 (en) * 2018-01-12 2019-02-12 International Business Machines Corporation Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154507A (en) * 1997-07-29 1999-02-26 Sony Corp Manufacture of semiconductor device
US6287435B1 (en) * 1998-05-06 2001-09-11 Tokyo Electron Limited Method and apparatus for ionized physical vapor deposition
JP2000269214A (en) * 1999-03-15 2000-09-29 Toshiba Corp Semiconductor device and manufacture thereof
JP2007081113A (en) * 2005-09-14 2007-03-29 Sony Corp Method for manufacturing semiconductor device
JP2009016782A (en) * 2007-06-04 2009-01-22 Tokyo Electron Ltd Film forming method, and film forming apparatus
JP5396854B2 (en) * 2008-12-25 2014-01-22 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP5193913B2 (en) * 2009-03-12 2013-05-08 東京エレクトロン株式会社 Method for forming CVD-Ru film and method for manufacturing semiconductor device
JP5493096B2 (en) * 2009-08-06 2014-05-14 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP5767570B2 (en) * 2011-01-27 2015-08-19 東京エレクトロン株式会社 Cu wiring forming method, Cu film forming method, and film forming system
KR20140021628A (en) * 2011-03-30 2014-02-20 도쿄엘렉트론가부시키가이샤 Method for forming copper wire

Also Published As

Publication number Publication date
JP2014017345A (en) 2014-01-30
WO2014010333A1 (en) 2014-01-16

Similar Documents

Publication Publication Date Title
TWI602263B (en) Cu wiring formation method and memory medium
WO2012133400A1 (en) Method for forming copper wire
JP5767570B2 (en) Cu wiring forming method, Cu film forming method, and film forming system
JP6257217B2 (en) Method for forming Cu wiring structure
KR101662369B1 (en) METHOD FOR FORMING Cu WIRING AND STORAGE MEDIUM
US8399353B2 (en) Methods of forming copper wiring and copper film, and film forming system
TWI710654B (en) Manufacturing method of Cu wiring
KR20160068668A (en) Copper wiring forming method, film forming system, and storage medium
TWI689013B (en) Cu wiring forming method, semiconductor device manufacturing method, and memory medium
JP5788785B2 (en) Cu wiring forming method and film forming system
TWI651807B (en) Cu wiring manufacturing method
US20140287163A1 (en) Method of forming copper wiring and method and system for forming copper film
KR101800487B1 (en) Method for forming copper wiring and storage mideum
TW201415554A (en) METHOD FOR FORMING Cu WIRING, AND COMPUTER-READABLE MEMORY MEDIUM
KR20170089774A (en) Cu WIRING MANUFACTURING METHOD AND Cu WIRING MANUFACTURING SYSTEM
TW201301443A (en) Deposition method and copper wire forming method
KR101357531B1 (en) METHOD FOR FORMING Cu WIRING, METHOD AND SYSTEM FOR FORMING Cu FILM, AND STORAGE MEDIUM