TW201415544A - Method for forming doping region and method for forming MOS - Google Patents

Abstract

The present invention provides a method of forming a doping region. A substrate is provided, and a poly-silicon layer is formed on the substrate. A silicon oxide layer is formed on the poly-silicon layer. An implant process is performed to form a doping region in the poly-silicon layer. The present invention further provides a method for forming a MOS.

Description

Method of forming doped region and method of forming metal oxide semiconductor transistor

The present invention relates to a method of forming a doped region, and more particularly to a method of forming a doped region in a germanium containing layer.

In the modern information society, micro-processing systems consisting of integrated circuits (ICs) have long been used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc. The use of integrated circuits. With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in the direction of more yuan, more precision and smaller.

In the prior art semiconductor technology, it is a conventional technique to form a doped region in a germanium-containing semiconductor layer to change the conductivity of this region. However, since existing techniques for forming doped regions are often affected by temperature and other parameters, the range of doped regions is not easily controlled. For example, doped regions often have problems with lateral diffusion, making the range of doped regions larger than originally expected. In the structure where the component size is shrinking, the quality of the component is difficult to control, and it becomes a problem to be solved.

The present invention thus provides a way to form doped regions to address the problem of lateral diffusion of the aforementioned doped regions.

In accordance with an embodiment of the present invention, the present invention provides a way to form doped regions. A substrate is first provided, followed by formation of a polysilicon layer on the substrate, followed by formation of a hafnium oxide layer on the polysilicon layer. Finally, an ion implantation process is performed to form a doped region in the polysilicon layer.

In accordance with another embodiment of the present invention, the present invention provides another way of forming doped regions. First, a ruthenium-containing layer is provided, followed by formation of a ruthenium oxide layer on the ruthenium-containing layer. Finally, a doped region is formed in the germanium-containing layer under the hafnium oxide layer.

According to another embodiment of the present invention, the present invention also provides a method of forming a gold oxide semiconductor transistor. A substrate is first provided and a polysilicon layer is formed on the substrate. A first ruthenium oxide layer is formed on the polysilicon layer. Patterned polycrystalline germanium layer. After forming the first hafnium oxide layer, a doped region is formed in the polysilicon layer under the first hafnium oxide layer. A second ruthenium oxide layer is formed on the substrates on both sides of the polysilicon layer. After forming the second hafnium oxide layer, a source/drain region is formed in the substrate under the second hafnium oxide layer.

The present invention provides a method of forming a doped region in a germanium-containing layer, particularly a polysilicon layer, characterized in that a germanium oxide layer is formed on the germanium-containing layer to suppress lateral diffusion of the doped region and thereby enhance The quality of the components.

The present invention will be further understood by those of ordinary skill in the art to which the invention pertains. The constitution of the present invention and the effects to be achieved will be described in detail.

Please refer to FIG. 1 to FIG. 10 , which are schematic diagrams showing the steps of a method for forming a doped region according to the present invention. As shown in FIG. 1, a substrate 300 is first provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. Or a silicon-on-insulator substrate (SOI substrate). A plurality of shallow trench isolation (STI) 302 are then formed in the substrate 300.

As shown in FIG. 2, a selective dielectric layer 306 and a polysilicon layer 304 are integrally formed on the substrate 300. The method of forming the dielectric layer 306 and the polysilicon layer 304 is, for example, a chemical vapor deposition (CVD) process, but is not limited thereto. In one embodiment, the dielectric layer 306 may be a low dielectric constant layer such as hafnium oxide or a niobium nitride compound, or a high dielectric constant layer such as hafnium oxide (HfO ₂ ). And a metal oxide or a metal nitrogen compound such as a hafnium silicon oxide (HfSiO ₄ ) or a hafnium silicon oxynitride (HfSiON), but is not limited thereto.

As shown in FIG. 3, a very thin hafnium oxide layer 308 is formed on the polysilicon layer 304. In a preferred embodiment of the invention, the yttria layer 308 has a thickness of no greater than 50 angstroms, such as from 10 angstroms to 20 angstroms. In one embodiment of the invention, the method of forming the hafnium oxide layer 308 includes an oxygen treatment process or a deposition process. The oxygen treatment process can be, for example, a tempering step, a plasma treatment step, or a chemical solution treatment step. In one embodiment, the tempering step is carried out by introducing a gas containing O ₂ in an environment of about 300 to 500 degrees Celsius, for example, 100% of O ₂ gas is carried out in an environment of 400 degrees Celsius. The plasma treatment step is, for example, the use of a plasma gas containing O ₂ . The chemical solution treatment step is, for example, a solution containing ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O), such as an SC ₁ solution. In another embodiment, the deposition process includes, for example, a chemical vapor deposition process, an atomic layer deposition (ALD) process, and the like, but is not limited thereto.

As shown in FIG. 4, a first doped region 312 is formed in a portion of the polysilicon layer 304. The first doped region 312 is formed, for example, a first patterned photoresist layer 310 is formed on the polysilicon layer 304, which covers a portion of the polysilicon layer 304 and the hafnium oxide layer 308. In a preferred embodiment of the invention, the sidewalls of the first patterned photoresist layer 310 will generally correspond above the shallow trench isolations 302. Then performing an ion implantation process with the first patterned photoresist layer 310 as a mask and selectively performing a tempering process after removing the first patterned photoresist layer 310 to be in the first patterned photoresist A first doped region 312 is formed in a portion of the polysilicon layer 304 covered by the layer 310. In the preferred embodiment of the present invention, the polysilicon layer 304 not covered by the first patterned photoresist layer 310 completely forms the first doped region 312. . However, in other embodiments, the extent of the first doped region 312 may vary depending on the design of the product, for example, only a portion of the polysilicon layer 304 forms the first doped region 312. The dopant of the first doped region 312 has a first conductivity type, which may be an N-type dopant such as phosphorous.

As shown in FIG. 5, a second doped region 316 is formed in a portion of the polysilicon layer 304, wherein the second doped region 316 and the first doped region 312 preferably do not overlap, that is, the first The second doped region 316 may form a region other than the first doped region 316 in the polysilicon layer 304, but the first doped region 312 and the second doped region 316 may not occupy all of the polysilicon layer 304, depending on the product. Design and adjustment. To form the second doped region 316, for example, a second patterned photoresist layer 314 is formed on the polysilicon layer 304 to cover the first doped region 312 of the polysilicon layer 304. Then, the second patterned photoresist layer 314 is used as a mask for an ion implantation process and after the second patterned photoresist layer 314 is removed, a tempering process is selectively performed to prevent the second patterned photoresist from being removed. A second doped region 316 is formed in the polysilicon layer 304 covered by layer 314. In a preferred embodiment of the invention, the polysilicon layer 304 not covered by the second patterned photoresist layer 314 will completely form the second doped region 312. In a preferred embodiment of the invention, the dopant of the second doped region 316 has a second conductivity type, which may be a P-type dopant such as boron. In addition, the tempering process accompanying the first doping region 312 can also be selectively omitted, and the tempering process after the second doping region 316 simultaneously activates the doping of the first doping region 312 and the second doping region 316. quality.

One of the features of the present invention is that a very thin hafnium oxide layer 308 is formed on the polysilicon layer 304 prior to forming the first doped region 312 or the second doped region 316, such that the first doped region 312 or Two doped regions 316 are formed in the polysilicon layer 304 below the hafnium oxide layer 308, respectively. Due to the interface between the extremely thin yttrium oxide layer 308 and the underlying polysilicon layer 304, the following reaction occurs: SiO ₂ +Si → 2 SiO

This causes a phenomenon of "Vacancy diffusion" in the polysilicon layer 304 under the yttrium oxide layer 308 to increase, and a phenomenon of "interstitial diffusion" is lowered. Since the "phosphorus" in the first doping region 312 and the "boron" in the second doping region 316 are mainly diffused by the "gap diffusion" in the polysilicon layer 304, the yttrium oxide layer 308 is formed by the present invention. In a manner, the phenomenon of gap diffusion can be effectively suppressed, thereby avoiding "lateral diffusion" between the first doping region 312 and the second doping region 316, that is, the first doping region 312 and The dopants of the second doped regions 316 do not laterally diffuse and mix with each other. In addition, the present invention can further adjust the layout pattern of the first patterned photoresist layer 310 and the second patterned photoresist layer 314 to position the second doping region 316 and the first doping region 312 at the polysilicon layer 304. They do not laterally abut, such that there is an undoped polysilicon layer 304 interposed between the two. Thus, the present invention can suppress the phenomenon of "Vacancy diffusion" and "Interstitial diffusion" by the yttrium oxide layer 308 above the polysilicon layer 304, and can utilize the second doping region 316 and the A doping region 312 is substantially not laterally abutting to effectively ensure that the dopants of the first doping region 312 and the second doping region 316 do not laterally diffuse and mix with each other.

Subsequently, as shown in FIG. 6, the polysilicon layer 304, the dielectric layer 306, and the hafnium oxide layer 308 are patterned to form a patterned polysilicon layer 304a, a patterned dielectric layer 306a, and a patterned hafnium oxide layer 308a. In one embodiment of the present invention, the patterned dielectric layer 306a can serve as a gate dielectric layer, and the patterned polysilicon layer 304a can serve as a gate. The portion having the first doped region 312 can serve as an N-type. a gate of a MOS transistor (NMOS), and a portion having a second doped region 316 can be used as a P-type gold The gate of an oxygen semiconductor transistor (PMOS). In a subsequent step, a suitable lightly doped drain (LDD), a sidewall spacer, a source/drain region, a metal telluride, etc. (not shown in FIG. 6) may be formed in the substrate 300. That is, a structure of a complementary metal oxide semiconductor transistor (CMOS transistor) can be formed. In a preferred embodiment of the invention, the patterned yttria layer 308a is not removed and remains on the patterned polysilicon layer 304a to maintain its lateral diffusion inhibiting effect. In yet another embodiment, the patterned ruthenium oxide layer 308a can also be removed.

In addition to the above embodiments of the polysilicon layer, the method of the present invention for utilizing the yttrium oxide layer to effectively suppress the side diffusion of the dopant and mixing with each other can also be applied to the ruthenium containing layer of other single crystal germanium, amorphous germanium or epitaxial germanium. in. For example, in one embodiment of the invention, the manner in which the source/drain regions and the lightly doped drain (LDD) are formed may also include forming such an extremely thin layer of tantalum oxide. Referring to FIG. 7, a very thin layer of yttria 318 is formed in the substrate 300 on both sides of the patterned polysilicon layer 304a. In a preferred embodiment of the present invention, the thickness of the yttrium oxide layer 318 is not more than 50 angstroms, for example, 10 angstroms to 20 angstroms, and the yttria layer 318 may be simultaneously formed on the sidewall of the patterned polysilicon layer 304a to form a liner. The structure of the layer. The step of forming the hafnium oxide layer 318 includes an oxygen treatment process or a deposition process. The oxygen treatment process is, for example, a tempering step, a plasma treatment step or a chemical solution treatment step. In one embodiment, the tempering step is carried out by introducing a gas containing O ₂ in an environment of about 300 to 500 degrees Celsius, for example, 100% of O ₂ gas is carried out in an environment of 400 degrees Celsius. The plasma treatment step is, for example, the use of a plasma gas containing O ₂ . The chemical solution treatment step is, for example, a solution containing ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O), such as an SC ₁ solution. In another embodiment, the deposition process includes, for example, a chemical vapor deposition process, an atomic layer deposition (ALD) process, and the like, but is not limited thereto.

Next, as shown in FIG. 8, on both sides of the patterned polysilicon layer 304a, a suitable dopant region, such as a lightly doped drain region 320 and a lightly doped drain region 322, is formed in the substrate 300 under the yttrium oxide layer 318. The lightly doped drain region 320 has the same conductivity type as the first doped region 312, for example, also an N-type dopant; the lightly doped drain region 322 and the second doped region 316 have the same conductivity type, for example, the same It is a P-type dopant. Please refer to FIG. 9 , which is a cross-sectional view taken along line AA' of FIG. 8 . Since the hafnium oxide layer 318 is formed on the lightly doped drain region 320, lateral diffusion of the lightly doped drain region 320, such as diffusion into the channel under the patterned dielectric layer 306a, can be avoided. The component quality of this NMOS. Similarly, since the hafnium oxide layer 318 is formed on the lightly doped drain region 322, lateral diffusion of the lightly doped drain region 322, such as diffusion into the channel below the patterned gate dielectric layer 306a, can be avoided. This improves the component quality of this PMOS.

As shown in FIG. 10, a sidewall 324 may be formed on the sidewall of the patterned polysilicon layer 304a, and then the sidewall 324 and the patterned yttria layer 308a may be used as a mask to form a source/germanium in the substrate 300. Pole 326. Similarly, since the yttrium oxide layer 318 is formed on the source/drain 326 region, lateral diffusion of the source/drain regions 326 can be avoided, and the NMOS device quality can be improved.

Please refer to FIG. 11 , which is a schematic diagram of a method of forming a doped region according to another embodiment of the present invention. The first stage of the present embodiment is the same as the first embodiment to the first embodiment of FIG. 1 to FIG. 3. After the third drawing is completed, as shown in FIG. 11, the polysilicon layer 304, the dielectric layer 306, and the yttrium oxide layer 308 are patterned to A patterned polysilicon layer 304a, a patterned dielectric layer 306a, and a patterned yttrium oxide layer 308a are formed. Then, the first doping region 312 and the second doping region 316 are respectively formed in the patterned polysilicon layer 304a, and the structure as shown in FIG. 6 is also formed, and the subsequent steps are continued from FIGS. 7 to 10. In the present embodiment, the first doped region 312 may be formed together with the lightly doped drain region 320; the second doped region 316 may be formed together with the lightly doped drain region 322. In another embodiment of the present invention, the step of forming the second doping region 316 in the polysilicon layer 304 may be selectively omitted, or the formation of the N-type dopant or the P-type dopant in the polycrystalline germanium layer 304 may be omitted. In one of the steps, it is preferred to omit the P-type dopant.

Please refer to FIG. 12, which is a schematic diagram of a method of forming a doped region according to another embodiment of the present invention. The first stage of the present embodiment is the same as the first embodiment to the second embodiment. After the second drawing is completed, as shown in FIG. 12, the polysilicon layer 304 and the dielectric layer 306 are patterned to form a patterned polysilicon layer. 304a and patterned dielectric layer 306a. Next, a ruthenium oxide layer 308 is formed on the patterned polysilicon layer 304a to form a structure as shown in Fig. 11, and a structure as shown in Figs. 6 to 10 is subsequently formed. In the present embodiment, the hafnium oxide layer 308 on the patterned polysilicon layer 304a may be formed with the hafnium oxide layer 318 on the substrate 300, such that the first doped region 312 may be formed with the lightly doped drain region 320. The second doped region 316 may also be formed together with the lightly doped drain region 322. Of course, it is also possible to selectively omit the formation of the N-type dopant or the P-type dopant in the polysilicon layer 304. The step of one of the qualities.

The invention is characterized in that after forming a very thin yttrium oxide layer on the ruthenium-containing layer, a doped region is directly formed under the ruthenium oxide layer to suppress the "gap diffusion" phenomenon of the doped region, especially the lateral diffusion phenomenon. . Although such a principle can achieve the best effect in the polysilicon layer, it can also be applied to other ranges of mono-silicon, amorphous germanium or epitaxial silicon. In general, the scope of application of the present invention can be applied to structures having doped regions in various germanium-containing layers. For example, the source/drain region may also be a structure of selective epitaxial growth (SEG). Alternatively, the method of forming a doped region of the present invention can also be applied to the source/drain regions of a fin structure in a non-planar transistor. Alternatively, the present invention can also be applied to a photo transistor formed on an epitaxial layer or formed on a germanium substrate having a PN junction.

In summary, the present invention provides a method of forming a doped region in a germanium-containing layer, particularly a polysilicon layer, characterized in that a germanium oxide layer is formed on the germanium-containing layer to suppress the side of the doped region. Diffusion, which improves the quality of the components.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300‧‧‧Base

302‧‧‧Shallow trench isolation

304‧‧‧Polysilicon layer

304a‧‧‧ patterned polycrystalline layer

306‧‧‧Dielectric layer

306a‧‧‧ patterned dielectric layer

308‧‧‧Oxide layer

308a‧‧‧ patterned yttrium oxide layer

310‧‧‧First patterned photoresist layer

312‧‧‧First doped area

314‧‧‧Second patterned photoresist layer

316‧‧‧Second doped area

318‧‧‧Oxide layer

320‧‧‧Lightly doped bungee zone

322‧‧‧Lightly doped bungee zone

324‧‧‧ Sidewall

326‧‧‧Source/Bungee Area

1 to 10 illustrate a method of forming a doped region according to an embodiment of the invention. Step diagram.

FIG. 11 is a schematic diagram showing the steps of forming a doped region according to another embodiment of the present invention.

FIG. 12 is a schematic diagram showing the steps of forming a doped region according to another embodiment of the present invention.

300‧‧‧Base

304a‧‧‧ patterned polycrystalline layer

306a‧‧‧ patterned dielectric layer

308a‧‧‧ patterned yttrium oxide layer

312‧‧‧First doped area

316‧‧‧Second doped area

Claims (20)

A method of forming a doped region, comprising: providing a substrate; forming a polysilicon layer on the substrate; forming a hafnium oxide layer on the polysilicon layer; and performing an ion implantation process under the hafnium oxide layer A doped region is formed in the polysilicon layer. The method for forming a doped region according to claim 1, wherein the ruthenium oxide layer is formed first, and then the ion implantation process is performed. The method of forming a doped region as described in claim 2, further comprising patterning the polysilicon layer. A method of forming a doped region as described in claim 3, wherein the polysilicon layer is first patterned to form the yttrium oxide layer. The method for forming a doped region according to claim 3, wherein the polysilicon layer is first patterned, and then the ion implantation process is performed. The method of forming a doped region according to claim 1, wherein the method of forming the ruthenium oxide layer comprises an oxygen treatment process or a deposition process. A method of forming a doped region as described in claim 1, wherein the yttrium oxide layer has a thickness of less than 50 angstroms. The method of forming a doped region as described in claim 1, wherein the doped region is a gate of a transistor. A method of forming a doped region, comprising: providing a germanium-containing layer; forming a germanium oxide layer on the germanium-containing layer; and forming a doped region in the germanium-containing layer under the germanium oxide layer. The method of forming a doped region according to claim 9, wherein the germanium-containing layer comprises amorphous germanium, single crystal germanium or epitaxial germanium. The method of forming a doped region as described in claim 9 wherein the method of forming the ruthenium oxide layer comprises an oxygen treatment process or a deposition process. The method of forming a doped region according to claim 9, wherein the yttrium oxide layer has a thickness of less than 50 angstroms. The method of forming a doped region according to claim 9, wherein the doped region is a gate of a transistor, a lightly doped drain region or a source/drain region. The method of forming a doped region according to claim 13, wherein the source/drain region has an epitaxial layer. A method of forming a doped region as described in claim 9 wherein the doped region is a PN junction as a photodiode. A method of forming a MOS transistor, comprising: providing a substrate; forming a polysilicon layer on the substrate; forming a first ruthenium oxide layer on the polysilicon layer; patterning the polysilicon layer; forming the first ruthenium oxide layer After the layer, a doped region is formed in the polysilicon layer under the first hafnium oxide layer; a second hafnium oxide layer is formed on the substrate on both sides of the polycrystalline germanium layer: and after the second hafnium oxide layer is formed, A source/drain region is formed in the substrate under the second hafnium oxide layer. The method of forming a MOS transistor according to claim 16, wherein the first ruthenium oxide layer is formed first, and then the polysilicon layer is patterned. The method of forming a MOS transistor according to claim 16, wherein the first ruthenium oxide layer is formed simultaneously with the second ruthenium oxide layer. The method of forming a MOS transistor according to claim 16, wherein the first ruthenium oxide layer and the second ruthenium oxide layer have a thickness of less than 50 angstroms. A method of forming a MOS transistor as described in claim 16 wherein the doped region is an N-type dopant.