TW201411802A - Semiconductor package structure and interposer therefor - Google Patents

Abstract

An interposer for a semiconductor package structure includes a base substrate, a plurality of passive devices formed on the base substrate, and an identification (ID) code. The base substrate includes a first surface and an opposite second surface. The ID code is formed on the first surface or the second surface.

Description

Semiconductor package structure and adapter plate for semiconductor package structure

The present invention relates to a semiconductor package structure and an interposer for a semiconductor package structure, and more particularly to a semiconductor package structure having a stacked wafer and an interposer for a semiconductor package structure.

As semiconductor devices accumulate and increase complexity, the semiconductor industry often uses through silicon vias (TSV) and through silicon interpose (TSI) (also known as "through"). The interposer "" electrically connects the stacked dies to shorten the distance between the dies, reduce the size of the components, and increase the overall operating speed and operating bandwidth.

While the use of TSV structures and interposer boards provides high density horizontal or vertical wafer stacking, electrical continuity or electrical performance within the interposer board is very difficult to detect. Therefore, it is often possible to determine whether the adapter board has defects by testing after the fabrication of the semiconductor package structure is completed. However, at this time, it is often impossible to trace the batch of the defective adapter plate, and therefore it is impossible to know which production step or production environment the related defect is generated.

Therefore, an object of the present invention is to provide a semiconductor package structure and an interposer for a semiconductor package structure, which can solve the problem that the defect interposer cannot be tracked.

According to the patent application scope of the present invention, an adapter board for a semiconductor package structure is provided, the adapter board includes a base substrate, a plurality of passive devices disposed on the bottom plate, And an identification (ID code) formed on the bottom plate.

According to the patent application scope provided by the present invention, there is further provided a semiconductor package structure comprising at least one function die, a carrier substrate, and at least one interposer. The adapter board is disposed between the functional die and the carrier substrate, and electrically connects the functional die and the carrier substrate, and the adapter plate includes an identification code.

According to the semiconductor package structure provided by the present invention and the adapter board for the semiconductor package structure, the adapter board is provided with an identification code, so that after the subsequent test, if the adapter board is found to have defects, it can be transferred The identification code on the board easily traces which batch has a problem and can be processed immediately, thus increasing the yield of the semiconductor package structure and reducing the production cost.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing a preferred embodiment of an interposer for a semiconductor package structure according to the present invention. As shown in FIG. 1, the adapter plate 100 provided in the preferred embodiment includes a bottom plate 102, which may be a germanium substrate or a glass substrate, or any suitable substrate. The bottom plate 102 has a first surface 102a and an opposite second surface 102b. The interposer board 100 further includes a plurality of passive components 110, such as capacitors, resistors, inductors, transformers, etc. required for the integrated circuit, without active components. As shown in FIG. 1 , the adapter plate 100 further includes a plurality of redistribution layers (hereinafter referred to as RDLs) 120 respectively formed on the first surface 102 a and the second surface 102 b of the bottom plate 102 . In addition, the adapter plate 100 further includes a plurality of micro bumps 130 formed on the first surface 102a of the substrate 102, and a plurality of bumps 132 formed on the second surface 102b of the substrate 102. . More importantly, the adapter plate 100 provided in the preferred embodiment further includes a plurality of TSV structures 140 for electrically connecting the micro bumps 130 to the bumps 132.

Referring next to FIGS. 2 through 4, FIGS. 2 through 4 are partial top views of different embodiments of the adapter plate for a semiconductor package structure provided by the present invention. As shown in FIG. 2, the adapter board 100 of the preferred embodiment further includes an identification (ID code) 150 formed on the bottom plate 102. In addition, it should be noted that the identification code 150 may be formed on the first surface 102a or the second surface 102b of the bottom plate 102 as required by the process or product. Such as As shown in FIG. 2 and FIG. 3, the identification code 150 provided in the preferred embodiment includes a metal pattern by forming a metal array pattern on the first surface 102a or the second surface 102b, and then by using a A method of firing or the like trims off certain metal layers in the metal array pattern (for example, the diagonal lines in FIGS. 2 and 3), and forms a special pattern on the first surface 102a or the second surface 102b. The metal pattern is used as the identification code 150 of the preferred embodiment. It should be noted that the metal pattern, or identification code 150, may be fabricated simultaneously with the passive component 110 described above, or may be fabricated simultaneously with the metal wiring within the RDL 120, or with the bumps below the microbumps 130 or bumps 132. An under bump metallization (UBM) layer (not shown), or even fabricated simultaneously with the TSV structure 140. In other words, the identification code 150 can be fabricated on the surface 102a/102b or surface 102a/102b of the backplane 102 simultaneously with one of the above components, depending on the product and process requirements. As shown in Fig. 2, in the preferred embodiment, the identification code 150 has a metal pattern having a pattern of "80A"; as shown in Fig. 3, in the preferred embodiment, the identification code 150 has a pattern of " Metal pattern of AF16". As shown in Figures 2 and 3, the identification code 150 disposed on the interposer 100 has a special pattern so that it can be read by optical microscopy or electrical testing.

See also Figure 4. In another preferred embodiment, the identification code 150 includes a plurality of fuses 152 that may be formed on the first surface 102a or the second surface 102b of the base plate 102 as required by the process or product. Subsequent use of laser or electro-migration (EM) effects to provide open circuit conditions, and An identification code 150 as shown in Fig. 4 is formed on the adapter board 100. In other words, the fuse 152 provided in the preferred embodiment may be a thermal fuse or an e-fuse. As shown in FIG. 4, in the preferred embodiment, the identification code 150 is divided into an X group and a Y group, and the X group and the Y group respectively include 7 fuses 152. In the X group, the last three fuses 152 are blown; and in the Y group, the third, fourth, and sixth fuses 152 are blown. Therefore, in the preferred embodiment, the identification code 150 is a special pattern in which some of the fuses are blown, so that it can be read by an optical microscope. In addition, since the unblowed fuse 152 still provides electrical continuity and the like, the identification code 150 on the adapter plate 100 in the preferred embodiment is more preferably read by electrical testing.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a preferred embodiment of a semiconductor package structure according to the present invention. As shown in FIG. 5, the semiconductor package structure 200 provided by the preferred embodiment includes at least one function die 210. For example, the functional die 210 may be a central processing unit (CPU chip) or a dynamic random access memory (DRAM). In the preferred embodiment, the functional die 210 itself may also have a TSV structure (not shown) that provides an electrical connection. The semiconductor package structure 200 further includes an interposer 100 including a bottom plate 102, a passive component 110, an RDL 120, a microbump 130, a bump 132, a TSV structure 140, an identification code 150, and the like. Since these components have been separately disclosed in the foregoing embodiments, they are not described herein again, and are not illustrated in FIG. 5. As shown in Figure 5, the functional die 210 The microbumps 130 are electrically connected between the functional die 210 and the interposer 100. The microbumps 130 are formed between the functional die 210 and the backplane 100. connection. The semiconductor package structure 200 provided by the preferred embodiment further includes a carrier substrate 220. The carrier substrate 220 may be a laminate substrate or a ceramic substrate, but is not limited thereto. In addition, the carrier substrate 200 further includes a plurality of solder balls 222 for providing electrical connection between the semiconductor package structure 200 and other external circuit structures. As shown in FIG. 5 , since the bump 132 is formed between the bottom plate 100 and the carrier substrate 220 , the bump 132 provides an electrical connection between the adapter plate 100 and the carrier substrate 220 . Briefly, the interposer 100 disposed between the functional die 210 and the carrier substrate 220 electrically connects the functional die 210 and the carrier substrate 220. Through the microbumps 130, the bumps 132 and the TSV structure 140, the different functional dies 120 are integrated on the interposer 100 and electrically connected to the carrier substrate 220. In addition to the advantages of high density and high integration, such a semiconductor package structure 200 has the advantages of low process risk and good stress management effect of the interposer board 100.

In the longitudinal direction, since the adapter plate is fabricated after the entire semiconductor package structure, the electrical continuity or electrical performance of the adapter plate can be known by electrical detection. Therefore, the present invention is further provided with an identification code for reading by an optical microscope or an electrical test on the transfer board. When the adapter board is determined to have a defect via electrical detection, it can be easily known according to the identification code on the adapter board which batch of the adapter board has defects and can be processed immediately, so that the semiconductor can be added. The yield of the package structure and the production cost are reduced.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Adapter plate

102‧‧‧floor

102a‧‧‧ first surface

102b‧‧‧second surface

110‧‧‧ Passive components

120‧‧‧Re-layer

130‧‧‧Microbumps

132‧‧‧Bumps

140‧‧‧through through-hole perforated structure

150‧‧‧ID

152‧‧‧Fuse

200‧‧‧Semiconductor package structure

210‧‧‧ functional grain

220‧‧‧bearing substrate

222‧‧‧ solder balls

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing one embodiment of an interposer for a semiconductor package structure according to the present invention.

2 to 4 are partial top views of different embodiments of an adapter plate for a semiconductor package structure provided by the present invention.

FIG. 5 is a schematic view showing a preferred embodiment of a semiconductor package structure according to the present invention.

100‧‧‧Adapter plate

102‧‧‧floor

102a‧‧‧ first surface

102b‧‧‧second surface

110‧‧‧ Passive components

120‧‧‧Re-layer

130‧‧‧Microbumps

132‧‧‧Bumps

140‧‧‧through through-hole perforated structure

150‧‧‧ID

Claims (20)

An adapter board for a semiconductor package structure, comprising: a base substrate; a plurality of passive devices disposed on the bottom plate; and an identification code (ID code) formed on the base plate On the bottom plate. The adapter plate of claim 1, wherein the identification code comprises a metal pattern formed on a surface of the bottom plate. The adapter plate of claim 2, wherein the metal pattern is read by optical microscopy or electrical test. The adapter plate of claim 1, wherein the identification code comprises a plurality of fuses formed on a surface of the bottom plate. The adapter plate of claim 4, wherein the fuses are read by optical microscopy or electrical testing. The adapter plate of claim 1, further comprising a plurality of redistribution layers (RDL) formed on one of the first surface and the second surface of the bottom plate. The adapter plate described in claim 6 of the patent application further includes a plurality of shapes a micro bump formed on the first surface of the bottom plate, and a plurality of bumps formed on the second surface of the bottom plate. The adapter plate of claim 7, further comprising a plurality of through silicon via (TSV) structures electrically connecting the microbumps to the bumps. The adapter plate of claim 1, wherein the bottom plate comprises a substrate or a glass substrate. A semiconductor package structure comprising: at least one function die; a carrier substrate; and at least one interposer disposed between the functional die and the carrier substrate, the interposer The functional die and the carrier substrate are electrically connected, and the adapter board includes an identification code. The semiconductor package structure of claim 10, wherein the adapter plate further comprises a bottom plate. The semiconductor package structure of claim 11, wherein the substrate comprises a germanium substrate or a glass substrate. The semiconductor package structure of claim 11, wherein the adapter plate further comprises a plurality of layer redistribution layers respectively formed on opposite surfaces of the bottom plate. The semiconductor package structure of claim 13, wherein the adapter plate further comprises a plurality of microbumps formed between the bottom plate and the functional die, and a plurality of the substrate and the carrier substrate are formed on the substrate Bumps between. The semiconductor package structure of claim 14, wherein the adapter plate further comprises a plurality of through-hole perforated structures electrically connecting the micro-bumps to the bumps. The semiconductor package structure of claim 10, wherein the identification code comprises a metal pattern formed on a surface of the interposer. The semiconductor package structure of claim 16, wherein the metal pattern is read by optical microscopy or electrical test. The semiconductor package structure of claim 10, wherein the identification code comprises a plurality of fuses formed on a surface of the adapter plate. The semiconductor package structure as claimed in claim 18, wherein These fuses are read by optical microscopy or electrical testing. The semiconductor package structure of claim 10, wherein the adapter plate further comprises a plurality of passive components.