TW201409447A - Demultiplexer of data driver, LCD display system and demultiplexer driving method of data driver - Google Patents

Abstract

The invention provides a demultiplexer of data driver. The demultiplexer has a first switch and a second switch. The first switch is connected to a first data line, a first control line, and a first source line. The second switch is connected to a second data line, a second control line, and a second source line. The first switch receives a first data signal by the first data line and transmits the first data signal to the first source line, and the second switch receives a second data signal by the second data line and transmits the second data signal to the second source line, wherein the first data signal and the second data signal have a positive data status and a negative data status. When the first data signal and the second data signal in transmission are in positive data status, the first and second control lines are in a first voltage level and a second voltage level so as to turn on/off the first switch and the second switch.

Description

Demultiplexing device for data driver, liquid crystal display system and demultiplexing driving method of the data driver

The invention relates to the technical field of demultiplexer, in particular to a data driver demultiplexing device, a liquid crystal display system and a demultiplexing driving method of the data driver.

1 is a schematic diagram of a demultiplexer of a data driver in a conventional liquid crystal display system. As shown, the demultiplexer 100 is comprised of NMOS switches 101-106. The drains of the NMOS switches 101, 103, and 105 are connected to a first data line (Data1) to receive a first data input signal, and the gates thereof are respectively connected to the first to third control lines (CK1, CK2, CK3) The source is connected to the first, third, and fifth source lines (S1, S3, S5), respectively. The drains of the NMOS switches 102, 104, and 106 are connected to a second data line (Data2) to receive a second data input signal, and the gates thereof are respectively connected to the first to third control lines (CK1, CK2). CK3), whose sources are respectively connected to the second, fourth, and sixth source lines (S2, S4, S6).

2 is a schematic diagram of the operation of a conventional NMOS switch. As shown in the figure, it is dot inversion. In the positive data state, the first to third control lines (CK1, CK2, CK3) are sequentially one. The square wave turns on the corresponding NMOS switch 101, 103, 105, and transmits the first data input signal to the first, third, and fifth source lines (S1, S3, S5).

In the negative data state, the first to third control lines (CK1, CK2, CK3) are sequentially a square wave to turn on the corresponding NMOS switches 102, 104, 106, and the second data is input. The signals are transmitted to the second, fourth, and sixth source lines (S2, S4, S6).

As shown in FIG. 2, in the forward data state, the voltages of the first data input signal and the second data input signal are 0~+4V, and in the negative data state, the first data input signal and the second data input signal are The voltage is 0~-4V. The voltages of the first to third control lines (CK1, CK2, and CK3) are +10V and -6V, respectively, in the forward data state or the negative data state, which causes a lot of energy waste. Therefore, there is still room for improvement in the technology of multiplexing.

The object of the present invention is mainly to provide a data driver demultiplexing device, a liquid crystal display system and a demultiplexing driving method of the data driver to effectively save energy consumption.

According to a feature of the present invention, the present invention provides a data multiplexer for a data driver, coupled to a first source line (S1) and a second source line (S2), including a first switch, and a The second switcher. The first switch is connected to a first data line (Data1), a first control line (CK1), and The first source line (S1), the first switch receives a first data input signal from the first data line, and transmits the first data input signal to the first source line, the first data input signal has a forward data Status and a negative data status. The second switch is connected to a second data line (Data2), a second control line (CK4), and the second source line (S2), and the second switch receives a second data line. a data input signal transmitted to the second source line, the second data input signal having the forward data state and the negative data state; wherein, when the first data input is transmitted in the forward data state The first control line (CK1) and the second control line (CK4) are a first level voltage (+10V) and a second level voltage (-6V), respectively, when the signal and the second data input signal are used. The first switch and the second switch are turned on and off.

According to another feature of the present invention, the present invention provides a liquid crystal display system including a liquid crystal display panel, a gate driver, a data driver, and a display timing controller. The gate driver is connected to the liquid crystal display panel for generating a display scan signal to drive the liquid crystal display panel. The data driver is coupled to the liquid crystal display panel for driving the liquid crystal display panel according to a display pixel signal, the data driver comprising a demultiplexing device. The demultiplexing device includes a first switch and a second switch. The first switch is connected to a first data line (Data1), a first control line (CK1), and the first source line (S1), and the first switch receives a first data line from the first data line. a data input signal transmitted to the first source line, the first data input signal There is a positive data status and a negative data status. The second switch is connected to a second data line (Data2), a second control line (CK4), and the second source line (S2), and the second switch receives a second data line. a data input signal transmitted to the second source line, the second data input signal having the forward data state and the negative data state, wherein the first data input when transmitting the forward data state The first control line (CK1) and the second control line (CK4) are a first level voltage (+10V) and a second level voltage (-6V), respectively, when the signal and the second data input signal are used. The first switch and the second switch are turned on and off. The display timing controller is coupled to the data driver and the gate driver for supplying the data driver and the gate driver to output the display pixel signal and the timing of the display driving signal.

According to still another feature of the present invention, the present invention provides a data multiplexer driving method for a data driver, comprising: (A) using a first switch to transmit data, the first switch being connected to a first data line (Data1), a first control line (CK1), and the first source line (S1), the first switch receives a first data input signal from the first data line, and transmits the first data input signal to the first source a pole line, the first data input signal has a forward data state and a negative data state; (B) a second switch is used to transmit data, and the second switch is connected to a second data line (Data2 a second control line (CK4), and the second source line (S2), the second switch receives a second data input signal from the second data line, and transmits the second data input signal to the second source line The second data input signal has the positive a data status and the negative data status; (C) the first control line (CK1) and the second control line when transmitting the first data input signal and the second data input signal of the forward data state (CK4) is a first level voltage (+10V) and a second level voltage (-6V), respectively, to turn the first switch and the second switch on and off.

3 is an embodiment of a demultiplexing device 300 of the data driver of the present invention. The present invention does not limit the number of switches, source lines, and control lines in the demultiplexing device 300. For convenience of explanation, FIG. 3 shows only six switches 301 to 306.

The demultiplexing device 300 includes a first switch 301 and a second switch 302. In other embodiments, the present invention does not limit the number of switches, source lines, and control lines in the multiplexer 300. The multiplexer 300 may further include a third switch 303 and a fourth. The switch 304, a fifth switch 305, and a sixth switch 306. The manner of connection and the working principle of the switches are known or inferred by those skilled in the art based on the technology of the present invention, and therefore will not be described again.

The demultiplexing device 300 is coupled to a first source line (S1) and a second source line (S2). The first switch 301 is connected to a first data line (Data1), a first control line (CK1), and the first source line (S1). The first switch 301 receives a first data input signal from the first data line and transmits the first data input signal to the first source line, where the first data input signal has A forward data status and a negative data status.

The second switch 302 is connected to a second data line (Data2), a second control line (CK4), and the second source line (S2), and the second switch 302 is configured by the second data line ( Data2) receives a second data input signal and transmits it to the second source line (S2), the second data input signal having the forward data state and the negative data state.

The first switch 301 and the second switch 302 are MOS switches. The first MOS switch is composed of a first NMOS transistor 301, and the second MOS switch is composed of a second NMOS transistor 302.

The gate of the first NMOS transistor 301 receives the first control line (CK1), and the drain is coupled to the first data line (Data1) to receive the first data input signal, and the source thereof is coupled to the first a source line (S1), the gate of the second NMOS transistor 302 receives the second control line (CK4), and the drain is coupled to the second data line (Data2) to receive the second data input signal The source is coupled to the second source line (S2).

4 is a schematic view showing the operation of the switch of the present invention. It is used in dot inversion. As shown in FIG. 4, when the first data input signal is in the forward data state, the second data input signal is in the negative data state. When the first data input signal is in the negative data state, the second data input signal is the forward data state.

The first control line (CK1) and the second control when transmitting the first data input signal and the second data input signal of the forward data state The line (CK4) is a first level voltage and a second level voltage, respectively, to turn on and off the first switch 301 and the second switch 302.

When the first data input signal and the second data input signal of the negative data state are transmitted, the first control line (CK1) and the second control line (CK4) are respectively a third level voltage and a The fourth level voltage is used to turn the first switch 301 and the second switch 302 on and off.

The first level voltage is +10V, the second level voltage is -6V, the third level voltage is +5V, and the fourth level voltage is -6V. That is, when the forward data state is transmitted, the first control line (CK1) and the second control line (CK4) are +10V to enable the first switch 301 and the second switch 302. The first control line (CK1) and the second control line (CK4) are -6V to turn off the first switch 301 and the second switch 302. When transmitting the negative data state, the first control line (CK1) and the second control line (CK4) are +5V to enable the first switch 301 and the second switch 302, the first control The line (CK1) and the second control line (CK4) are -6V to turn off the first switch 301 and the second switch 302.

Fig. 5 is a schematic view showing another operation of the switch of the present invention. It is used in column inversion. Fig. 5 is a diagram showing waveforms of the first control line (CK1) and the second control line (CK4) when line inversion is performed. Before and after the line inversion, in a frame n-1, the first data line (Data1) is the forward data state, and the second data line (Data2) is the negative data state, so the first control Line (CK1) is +10V and -6V respectively to open And closing the first switch 301. The second control line (CK2) is +5V and -6V, respectively, to turn the second switch 302 on and off.

There is a pre-charge pulse between frame n-1 and its next frame n.

In the frame n, the first data line (Data1) is the negative data state, and the second data line (Data2) is the forward data state, so the first control line (CK1) is +5V and -6V to turn the first switch 301 on and off. The second control line (CK2) is +10V and -6V, respectively, to turn the second switch 302 on and off.

The energy consumed by the control lines can be expressed by the following formula: P = (Vh - Vl) × C × f × Vps, where Vh is the high level voltage of the control line, Vl is the low level voltage of the control line, and C is the control The load capacitance on the line, f is the operating frequency, and the voltage supplied by the Vps power supply.

It is known that the energy consumed by the control line of the prior art of FIG. 1 is: P=(10-(-6))×C×f×10+(-6-10)×C×f×(-6)=256 ×C×f. The energy consumed by the control line of the present invention is: P = (10 - (-6)) × C × f / 2 × 10 + (-6 - 10) × C × f / 2 × (-6) + ( 5-(-6))×C×f/2×5+(-6-5)×C×f/2×(-6)=188.5×C×f.

Thus, in theory, the energy consumed by the control line of the present invention can be reduced by 26% over conventional techniques. The invention is applied to low temperature poly-silicon (LTPS) 4.7 吋 high resolution When the (Full-HD) panel is on, the power consumption can be reduced from 66mW to 48mW.

FIG. 6 is another schematic diagram of the operation of the switch of the present invention. It is used in column inversion. The main difference from FIG. 5 is that the second level voltage is -1V. That is, by reducing the voltage levels of the first control line (CK1) and the second control line (CK4), the purpose of reducing power consumption is achieved.

It is known that the energy consumed by the control line of the prior art of FIG. 1 is: P=(10-(-6))×C×f×10+(-6-10)×C×f×(-6)=256 ×C×f. The energy consumed by the control line of the present invention is: P = (10 - (-1)) × C × f / 2 × 10 + (-1-10) × C × f / 2 × (-1) + ( 5-(-6))×C×f/2×5+(-6-5)×C×f/2×(-6)=121×C×f

Thus, in theory, the energy consumed by the control line of the present invention can be reduced by 52% over conventional techniques. The technique of the present invention can reduce the power consumption from 66 mW to 31 mW when applied to a low temperature polycrystalline 4.7 吋 high resolution (Full-HD) panel.

7 is another possible embodiment of the demultiplexing device 700 of the data driver of the present invention. Since the present invention does not limit the number of switches, source lines, and control lines in the demultiplexing device 700, the demultiplexing device The 700 includes a first switch 701 and a second switch 702, and further includes a third switch 703, a fourth switch 704, a fifth switch 705, and a sixth switch 706. The connection mode and working principle of these switches It will be completed or inferred by those skilled in the art based on the technology of the present invention, and therefore will not be described again.

The first switch 701 and the second switch 702 are CMOS switches. FIG. 8 is a circuit diagram of the first switch 701 and the second switch 702 of the present invention. The first switch 701 is composed of a first NMOS transistor 801 and a first PMOS transistor 802. The second switch 702 is composed of a second NMOS transistor 803 and a second PMOS transistor 804.

The gate of the first NMOS transistor 801 receives the first control line (CK1a), and the drain is coupled to the first data line (Data1) to receive the first data input signal, and the source thereof is coupled to the first a source line (S1), the gate of the first PMOS transistor 802 receives the inverted signal (CK1b) of the first control line (CK1a), and the source thereof is coupled to the first data line (Data1) to Receiving the first data input signal, the drain is coupled to the first source line (S1).

The gate of the second NMOS transistor 803 receives the second control line (CK4a), and the drain is coupled to the second data line (Data2) to receive the second data input signal, the source of which is coupled to the first a second source line (S2), the gate of the second PMOS transistor 804 receives the inverted signal (CK4b) of the second control line, and the source thereof is coupled to the second data line (Data2) to receive the first The second data input signal is coupled to the second source line (S2).

Figure 9 is a schematic view of another operation of the switch of the present invention. It is used in the column inversion. FIG. 9 is a diagram showing the first control line (CK1a) and the first control line being inverted when row inversion is performed. The waveform of the signal (CK1b) and the second control line (CK4a) and the inverted signal of the second control line (CK4b).

Before and after the line inversion, in the frame n-1, the first data line (Data1) is in the forward data state, so the first control line (CK1a) is +10V and -1V, respectively, to open and The first NMOS transistor 801 in the first switch 701 is turned off, and the first control line has an inverted signal (CK1b) of +10V to turn off the first PMOS transistor 802 in the first switch 701. .

At this time, the second data line (Data2) is in the negative data state, so the second control line (CK4a) is -6V to turn off the second NMOS transistor 803 in the second switch 702. The inverted signals (CK4b) of the second control line (CK4a) are +5V and -6V, respectively, to turn on and off the second PMOS transistor 804 in the second switch 702.

There is a pre-charge pulse between frame n-1 and its next frame n.

In the frame n, the first data line (Data1) is in the negative data state, so the first control line (CK1a) is -6V to turn off the first NMOS transistor in the first switch 701. 801. The reverse signal (CK1b) of the first control line (CK1a) is +5V and -6V, respectively, to turn on and off the first PMOS transistor 802 in the first switch 701.

At this time, the second data line (Data2) is the forward data state, so the second control line (CK4a) is +10V and -1V, respectively, to turn on and off the second of the second switch 702. NMOS transistor 803, the second The inverted signal (CK4b) of the control line is +10V to turn off the second PMOS transistor 804 in the second switch 702.

Figure 10 is a schematic illustration of the application of the multiplexed device of the present invention to a liquid crystal display system. The liquid crystal display system 1000 includes a liquid crystal display panel 1010, a gate driver 1020, a data driver 1030, and a display timing controller 1040.

The gate driver 1020 is coupled to the liquid crystal display panel 1010 for generating a display scan signal for driving the liquid crystal display panel.

The data driver 1030 is coupled to the liquid crystal display panel 1010 for driving the liquid crystal display panel 1010 according to a display pixel signal. The data driver 1020 includes a demultiplexing device 300. The demultiplexing device 300 includes a first switch 301 and a second switch 302.

The first switch 301 is connected to a first data line (Data1), a first control line (CK1), and the first source line (S1), and the first switch 301 is configured by the first data line ( Data1) receives a first data input signal and transmits it to the first source line (S1), the first data input signal having a forward data state and a negative data state.

The second switch 302 is connected to a second data line (Data2), a second control line (CK4), and the second source line (S2), and the second switch 302 is configured by the second data line ( Data2) receiving a second data input signal and transmitting to the second source line (S2), the second data input signal having the forward data state and the negative data state, wherein when the forward direction is transmitted When the first data input signal and the second data input signal of the data state are The first control line (CK1) and the second control line (CK4) are respectively a first level voltage (+10V) and a second level voltage (-6V) to turn the first switch on and off. And the second switch.

The display timing controller 1040 is coupled to the data driver 1030 and the gate driver 1020 for supplying the data driver 1030 and the gate driver 1020 to output the display pixel signal and the timing of the display driving signal.

11 and FIG. 12 are schematic diagrams of the operation of the demultiplexing device of the data driver of the present invention. In FIG. 11, the demultiplexing device is separated from the liquid crystal driving integrated circuit. In FIG. 12, the demultiplexing device and the liquid crystal driving are performed. The integrated circuit is integrated into the same integrated circuit.

13 is a flow chart of a method of demultiplexing driving of a data driver of the present invention. Referring to the demultiplexing device of the data driver of FIG. 3, first in step (A), a first switch 301 is used to transmit data, and the first switch 301 is connected to a first data line (Data1). a first control line (CK1) and the first source line (S1), the first switch 301 receives a first data input signal from the first data line (Data1), and transmits the first data input signal to the first The source line (S1), the first data input signal has a forward data state and a negative data state.

In the step (B), a second switch 302 is used to transmit data, and the second switch 302 is connected to a second data line (Data2), a second control line (CK4), and the second source. a second line (302), the second switch 302 receives a second data input signal from the second data line (Data2), And transmitting to the second source line (S2), the second data input signal has the forward data state and the negative data state.

In the step (C), when the first data input signal and the second data input signal of the forward data state are transmitted, the first control line (CK1) and the second control line (CK4) are respectively The first quasi-voltage (+10 V) and the second quasi-voltage (-6 V) are used to turn the first switch 301 and the second switch 302 on and off. When the first data input signal and the second data input signal of the negative data state are transmitted, the first control line (CK1) and the second control line (CK4) are respectively a third level voltage (+ 5V) and the second level voltage (-6V) to turn on and off the first switch 301 and the second switch 302.

As can be seen from the foregoing description, the present invention reduces the power consumption by reducing the voltage levels of the first control line (CK1) and the second control line (CK4).

From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

100‧‧‧Demultiplexing device

101, 103, 105‧‧‧ NMOS switchers

102, 104, 106‧‧‧ NMOS switch

300‧‧‧Development multiplexer for data drive

301‧‧‧ first switcher

302‧‧‧Second switcher

303‧‧‧ Third Switcher

304‧‧‧fourth switcher

305‧‧‧ fifth switcher

3060‧‧‧ sixth switcher

700‧‧‧Development multiplexer for data drive

701‧‧‧ first switcher

702‧‧‧Second switcher

703‧‧‧The third switch

704‧‧‧fourth switcher

705‧‧‧ fifth switcher

706‧‧‧ sixth switch

801‧‧‧First NMOS transistor

802‧‧‧First PMOS transistor

803‧‧‧Second NMOS transistor

804‧‧‧Second PMOS transistor

1000‧‧‧LCD system

1010‧‧‧LCD panel

1020‧‧‧gate driver

1030‧‧‧Data Drive

1040‧‧‧Display timing controller

1 is a schematic diagram of a demultiplexing device of a data driver in a conventional liquid crystal display system.

2 is a schematic diagram of the operation of a conventional NMOS switch.

3 is a possible embodiment of a demultiplexing device for a data drive of the present invention.

4 is a schematic view showing the operation of the switch of the present invention.

Fig. 5 is a schematic view showing another operation of the switch of the present invention.

FIG. 6 is another schematic diagram of the operation of the switch of the present invention.

Figure 7 is another possible embodiment of a demultiplexing device for a data drive of the present invention.

8 is a circuit diagram of a first CMOS switch and a second CMOS switch of the present invention.

Figure 9 is a schematic view of another operation of the switch of the present invention.

Figure 10 is a schematic illustration of the application of the multiplexed device of the present invention to a liquid crystal display system.

11 and FIG. 12 are schematic diagrams showing the operation of the demultiplexing device of the data driver of the present invention.

13 is a flow chart of a method of demultiplexing driving of a data driver of the present invention.

300‧‧‧Development multiplexer for data drive

301‧‧‧ first switcher

302‧‧‧Second switcher

303‧‧‧ Third Switcher

304‧‧‧fourth switcher

305‧‧‧ fifth switcher

3060‧‧‧ sixth switcher

Claims (20)

A data multiplexer is coupled to a first source line and a second source line, and includes: a first switch connected to a first data line, a first control line, and the first a first source switch receives a first data input signal from the first data line and transmits the first data input signal to the first source line, the first data input signal has a forward data state and a negative direction a data state; and a second switch connected to a second data line, a second control line, and the second source line, the second switch receiving a second data input signal from the second data line And transmitting to the second source line, the second data input signal has the forward data state and the negative data state; wherein, when the first data input signal and the second data are transmitted in the forward data state When the data is input, the first control line and the second control line are respectively a first level voltage and a second level voltage, and the first switch and the second switch are sequentially turned on and off. The demultiplexing device of the data driver of claim 1, wherein the first control line and the first data input signal and the second data input signal are transmitted when the negative data state is transmitted The second control line is a third level voltage and a fourth level voltage, respectively, to turn on and off the first switch and the second switch. The multiplexer of the data driver as described in item 2 of the patent application scope The device, wherein the first switch and the second switch are MOS switches. The data multiplexer of the data driver of claim 3, wherein the first MOS switch is composed of a first NMOS transistor, and the second MOS switch is composed of a second NMOS device. The composition of the crystal. The multiplexer of the data driver of claim 4, wherein the gate of the first NMOS transistor receives the first control line, and the drain of the first NMOS transistor is coupled to the first data line to receive the a first data input signal, the source of which is coupled to the first source line, the gate of the second NMOS transistor receives the second control line, and the drain of the second NMOS transistor is coupled to the second data line to receive the second A data input signal, the source of which is coupled to the second source line. The data multiplexer of the data driver of claim 5, wherein when the first data input signal is in the forward data state, the second data input signal is the negative data state. The demultiplexing device of the data driver of claim 6, wherein when the first data input signal is in the negative data state, the second data input signal is in the forward data state. The demultiplexing device of the data driver according to claim 2, wherein the first level voltage is +10V, the second level voltage is -6V, and the third level voltage is +5V, The fourth level voltage is -6V. The demultiplexing device of the data driver according to claim 2, wherein the first level voltage is +10 V, and the second level voltage For -1V, the third level voltage is +5V, and the fourth level voltage is -6V. The data multiplexer of the data driver of claim 2, wherein the first switch and the second switch are CMOS switches. The data multiplexer of the data driver of claim 10, wherein the first CMOS switch is composed of a first NMOS transistor and a first PMOS transistor, and the second CMOS switch is configured by A second NMOS transistor and a second PMOS transistor are formed. The multiplexer of the data driver of claim 11, wherein the gate of the first NMOS transistor receives the first control line, and the drain of the first NMOS transistor is coupled to the first data line to receive the The first data input signal has a source coupled to the first source line, a gate of the first PMOS transistor receiving an inverted signal of the first control line, and a source coupled to the first data line Receiving the first data input signal, the drain is coupled to the first source line, the gate of the second NMOS transistor receives the second control line, and the drain is coupled to the second data line to receive the a second data input signal, the source of which is coupled to the second source line, the gate of the second PMOS transistor receives the inverted signal of the second control line, and the source thereof is coupled to the second data line Receiving the second data input signal, the drain is coupled to the second source line. A liquid crystal display system comprising: a liquid crystal display panel; a gate driver connected to the liquid crystal display panel for generating a display scan signal for driving the liquid crystal display panel; a data driver connected to the liquid crystal display panel for electrically connecting according to a display pixel signal The liquid crystal display panel drives the liquid crystal display panel, the data driver includes a demultiplexing device, and the demultiplexing device includes: at least one first switch connected to a first data line, and a first control line, the first switch receives a first data input signal from the first data line, and transmits the signal to the corresponding connected source line, the first data input signal has a forward data state and a negative data state; and at least one second switch connected to a second data line and a second control line, the second switch receiving a second data input signal from the second data line, and transmitting And to the source line of the corresponding connection, the second data input signal has the forward data state and the negative data state, wherein when the forward data state is transmitted When the data input signal and the second data input signal are used, the first control line and the second control line are respectively a first level voltage and a second level voltage to open and close the first switch and the first And a display timing controller connected to the data driver and the gate driver for supplying the data driver and the gate driver to output the display pixel signal and the timing of the display driving signal. The liquid crystal display system of claim 13, wherein the first data input signal and the negative data state are transmitted When the second data input signal is used, the first control line and the second control line are respectively a third level voltage and the second level voltage to turn on and off the first switch and the second switch. The liquid crystal display system of claim 14, wherein the first switch is composed of a first NMOS transistor, and the second switch is composed of a second NMOS transistor. The liquid crystal display system of claim 15, wherein the gate of the first NMOS transistor receives the first control line, and the connected source line is a first source line, and the drain is The first data line is coupled to receive the first data input signal, the source thereof is coupled to the first source line, the gate of the second NMOS transistor receives the second control line, and the connected source The pole line is a second source line, and the drain is coupled to the second data line to receive the second data input signal, and the source is coupled to the second source line. The liquid crystal display system of claim 16, wherein the second data input signal is the negative data state when the first data input signal is in the forward data state. The liquid crystal display system of claim 17, wherein the second data input signal is in the forward data state when the first data input signal is in the negative data state. A multiplexer driving method for a data driver, comprising: (A) using a first switch to transmit data, the first switch being connected to a first data line, a first control line, and the first source a first line, the first switch receives a first data input signal from the first data line And transmitted to the first source line, the first data input signal has a forward data state and a negative data state; and (B) uses a second switch to transmit data, the second switch Connected to a second data line, a second control line, and the second source line, the second switch receives a second data input signal from the second data line, and transmits the second data input signal to the second source a second data input signal having the forward data state and the negative data state; and (C) when transmitting the first data input signal and the second data input signal of the forward data state, the A control line and the second control line are respectively a first level voltage and a second level voltage to turn the first switch and the second switch on and off. The data driver driving data method of claim 19, wherein the first control line and the second when the first data input signal and the second data input signal of the negative data state are transmitted The control lines are respectively a third level voltage and the second level voltage to turn the first switch and the second switch on and off.