TW201409236A - Memory protection - Google Patents

Abstract

An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection logic (9) is configured to: determine the state of a read protection flag for a protected region of the memory (13); detect a memory read request by the processor (7); determine whether the read request is for an address in the protected region of the memory (13); determine whether the processor (7) issued the read request while executing code stored in the protected region of the memory (13); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor (7) issued the read requests while executing code stored in the protected region.

Description

Memory protection

The present invention relates to memory protection in an integrated circuit device.

A microcontroller or system-on-chip device typically stores executable code in memory. It may store in its memory some code (such as an operating system or firmware module) written by the chip manufacturer, and other code written by a client or user (such as software). application). These codes are often stored in non-volatile memory such as EEPROM or flash memory.

There is a need to prevent the user code or an external debug interface from reading or overwriting the code written by the wafer manufacturer without limiting memory access to the code of the wafer manufacturer. This is because the chip manufacturer's code contains business secrets and does not want to be accessed by others. It can also help prevent unintentional damage to the code of the wafer manufacturer due to errors in the user's code.

US Patent No. 8,051,263 describes a memory protection unit that selectively grants or denies memory access requirements based on a set of configurable memory protection attributes for a particular area of memory. Access to the area is based on whether an execution unit is operating on a privileged Or non-privileged mode of operation.

If the user code is executed in an unallowed mode, the mechanism can be used to protect a memory area containing sensitive code from being read by the user code.

However, it is possible for a processor to read sensitive code from the memory in an allowable mode of operation due to a malicious attack and then output the content to the attacker. In addition, not all processors support the execution of modes that are allowed or not allowed.

The invention thus employs different processing methods.

A first object of the present invention is to provide an integrated circuit device including a processor, a memory for storing executable code, and a memory protection logic, wherein the memory protection logic is configured to: determine Reading a state of the protection flag in one of the protected areas of the memory; detecting a memory read requirement of the processor; determining whether the read requirement is for an address in the protected area of the memory Determining whether the processor issues the read request when executing the code stored in the protected area of the memory; and if the read protection flag for the protected area is established, rejecting The read requirement of the address in the protected area, unless at least one of one or more access conditions is met, wherein one of the access conditions is when executing the code stored in the protected area of the memory When the processor Issue such read requests.

A second object of the present invention is to provide a method of controlling memory access on an integrated circuit device, the integrated circuit device comprising a processor and a memory for storing executable code, the method comprising: determining a state of reading a protection flag in a protected area of the memory; detecting a memory read requirement of the processor; determining whether the read requirement is for a protected area of the memory a address; determining whether the processor issues the read request when executing a code stored in the protected area of the memory; and rejecting the read protection flag if the protected area is set up Waiting for a read request in an address in the protected area, unless at least one of one or more access conditions is met, wherein one of the access conditions is when executing a program stored in the protected area The processor issues the read requests when the code is coded.

A still further object of the present invention is to provide a method of controlling memory access on an integrated circuit device, the integrated circuit device comprising a processor and a memory for storing executable code, the method comprising: determining A read protection flag is set in a protected area of the memory; detecting a memory read requirement of the processor; determining that the read requirement is for use in the protected area of the memory One address; Determining that the processor issues the read request when executing the code stored in the protected area of the memory; and allowing the read request.

Therefore, according to the present invention, when a processor needs to read and access a protected area of the memory, the address of the code executed by the processor is used to determine whether the request is allowed. . The requirement originating from the code stored outside the protected area can be rejected (if the read protection flag is properly set up), and the demand from the code stored in the protected area itself is allowed. For many processor architectures, such as those from ARM (RTM), it is important that the code can issue a data read request to an area in which the code itself is stored so that the processor can access the code embedded in the code. The constant in .

The protection is implemented by the memory protection logic, which is preferably arranged to operate independently of the processor. The memory protection logic preferably includes hardware logic separate from the processor. In this way, it can reduce the influence of intentional spoofing of more malicious code than relying on the protection of the privilege modes in the processor.

The chip manufacturer can conveniently store its code in the protected area and set up the read protection flag to prevent a client's code from reading the code of the wafer manufacturer while retaining unrestricted memory. Take its own code. Other sensitive information, such as setting data, can also be stored in the protected area.

If the read protection flag for the protected area is not set, the memory protection logic is preferably set to allow the protection The read requirement of the address in the area. It is very useful in the initial development phase of the device and software. Similarly, if a write protection flag is not set, the memory protection logic is preferably set to allow write access to the address in the protected area.

If the read protection flag of the protected area is set, the memory protection logic is preferably set to reject the read requirement of the address of the protected area unless the processor is executing the stored in the protected area. These read requests are issued when the code in the code (in this case is allowed). The preferred embodiment has only one of the above access conditions. However, other sets of embodiments may still provide multiple access conditions, each of which may effectively override the read protection flag; for example, if the processor is executing a manufacturing stored in ROM The read request is issued when the loader program is launched, and a device understandably allows reading of the protected area.

The memory protection logic can be further similarly set to determine the state of a write protection flag for the protected area, and if the write protection flag for the protected area is established, reject the The write area protects the write requirements of the address, unless the processor issues the write request when executing the code stored in the protected area. The read protection flag can also be used as a write protection flag, or can be a separate flag.

In a preferred embodiment, the memory is a non-volatile memory such as a flash memory. The processor can obtain the code directly from the non-volatile memory when executed, or in some embodiments, at least some of the code can be cached (e.g., in volatile memory). If the device includes this cache, it can be seen that the reference is used to store in the protected area. The code contains a cache copy that executes the code.

In other embodiments, the memory can be a volatile memory, such as a portion of RAM that is reserved for executable code, and the protected area is an area of volatile memory. When the device's power is turned on, the executable code can be copied to the memory (eg, from ROM or flash memory). Alternatively, when the device is in use, segments of the code or individual instructions can be copied to a protected area of the volatile memory as desired.

The processor and memory can be linked by one or more bus bars. The memory protection logic can also be coupled to at least one of the bus bars. The memory protection logic is preferably configured to supervise all accesses to the memory (eg, all read, write, and instruction-fetch operations).

The memory protection logic can determine whether the processor issues the read request when executing the code stored in the protected area of the memory by determining an instruction immediately before the memory access request - Determine whether the address of the (instruction-fetch) operation is located within the protected area. The memory protection logic can be configured to set up a register for each instruction-acquisition operation depending on whether the fetched instruction is located in the protected area. The register may include a binary flag that is set based on whether the address obtained by the instruction is in the protected area.

The memory protection logic can be configured to use an exchange type information on a memory bus to identify an instruction-acquisition operation (eg, distinguishing it from a read requirement). Alternatively, it can be configured to identify an instruction-acquisition operation by deciding the state of a processor pin, or to borrow The fetch instruction is transmitted by the identification bus (eg, having separate data-acquisition and command-acquisition buss in the device). When using the ARM(RTM) Cortex-M0 processor, the memory protection logic can use the HPROT[0] (data/opcode) signal from the Cortex-M0 to distinguish between an opcode fetch and a data access.

The protected area may include several discrete areas or address ranges. However, it is preferred to simplify logic execution by defining a single, continuous address range. In some preferred embodiments, the protected area is variable and is defined by being stored in one or more addresses of the device, such as stored as non-volatile memory.

The protected area can extend between a predetermined constant address and a change point within the memory address range. The constant address can conveniently be a base or destination address for the memory, or even all memory address spaces for the device; for example zero (0x0000 0000). Thereby the area can be succinctly specified as an address defining the variable end point of the protected area in the memory by a single value stored in the device.

The memory protection unit can then be configured to determine whether the read requirement is for an address of the protected area of the memory by whether the address is located at the predetermined constant address and The variable memory address is determined between. This operation can be performed using a relatively small number of logic gates.

In the embodiment, the protected memory area is located in a non-volatile memory, and the apparatus may also include a volatile memory such as a RAM. If a read protection flag for the protected area of the volatile memory is established, the memory protection logic can be additionally set to reject the volatile The read requirements of the protected area address of the memory are issued unless the processor issues the read code stored in the protected area of the non-volatile memory. In this manner, an area of the protected RAM can be used by the code stored in the protected area of the non-volatile memory (eg, for cumulative storage) while being protected from code outside the area, this Sensitive information stored in RAM can be protected by code written by the chip manufacturer.

Similarly, if a write protection flag for the volatile memory is set, the memory protection logic can be set to reject the write requests for the protected memory address of the volatile memory. The write request is issued unless the processor executes the code stored in the protected area of the non-volatile memory. In this way, the client code stored outside the protected area of the non-volatile memory can avoid inadvertently or maliciously changing or overwriting the volatile data to which the code of the protected area of the non-volatile memory belongs.

The non-volatile memory protection flags may also serve as a volatile memory protection flag, or the volatile memory flag may include one or more separation flags.

In any of the foregoing embodiments, the device can include an interface (e.g., one or more pins) to allow memory access by an external debugger or software loader. In a preferred embodiment of the invention, if a debug protection flag for the protected area is established, the memory protection logic is configured to reject protection via some or all of the non-volatile or volatile memory. The read requirement received by the interface of the address in the area. The Protection may similarly be provided for write access to a protected area of volatile or non-volatile memory and/or instruction fetching for a protected area. The memory protection logic can be configured to determine when a debugger acts as a bus master device in a memory bus of the device, and the memory access requirement originates from a debug interface. When the processor is a Cortex-M0 of ARM (RTM), the processor can use the HMASTER signal of the Cortex-M0 to distinguish the execution of the processor core and the debugger.

The memory protection logic can be further configured to determine a state of a read protection flag of a user area of one of the memory of the executable code. The user area may include some or all of the memory adjacent to but exclude the protected code area in the address space. If the read protection flag for the user area is established, the memory protection logic can be set to reject the read and/or received from the debug interface and/or received from the debug interface. Write requirements. In this way, a client or other user can protect their user application code from unauthorized access by third parties; for example, based on confidentiality reasons.

In some embodiments, the apparatus includes integrated radio frequency communication logic, such as a radio frequency transmitter and/or receiver (i.e., a radio-on-a-chip). A firmware module including a code for implementing an RF stack can be stored in a protected area of the code memory. A software application bound to the firmware module can be stored outside of the protected area.

Embodiments of the present invention are particularly applicable to devices that do not have a conventional operating system, but allow a user to develop native code to execute directly on the processor. Because the devices cannot rely on an operation The system controls memory access and protects any confidential software library or module that the device manufacturer installs on the device.

In any embodiment of the invention, the read and/or write protection flags are preferably stored in non-volatile memory. In use, the flags are of course cached in a register or a RAM. A protection flag can be exactly one element of a larger set of values. It can be encoded in any suitable manner. In some embodiments, each such protection flag is stored as a binary flag or a bit field.

One or more protection flags can be stored in a protection-setting area of the non-volatile memory. Preferably, the apparatus includes non-volatile memory control logic configured to avoid writing to any portion of the protection-set area unless the portion is in an erased state. Preferably, the non-volatile memory control logic is further configured to allow the protection-set region to be erased only when a protected area of the non-volatile memory is in an erased state.

In this manner, the protection flags cannot be rewritten without first erasing any data stored in the non-volatile memory protected area. The sensitive executable code stored in the protected area cannot therefore be read by simply resetting the read protection flag for the non-volatile memory.

This vision is novel and creative. Therefore, from a still further perspective, the present invention provides an integrated circuit device including a processor, non-volatile memory, non-volatile memory control logic, and memory protection logic, wherein: The memory protection logic is configured to control access to a protectable area of the non-volatile memory according to a protection setting data stored in a protection-setting area of the non-volatile memory; the non-volatile memory control logic Configuring to avoid writing to any portion of the protection-set area unless the portion is in an erased state; and the non-volatile memory control logic is configured to allow the protected area only if it is in an erased state Protection - The setting area is erased.

From another point of view, the present invention provides a method for controlling memory access on an integrated circuit device including a processor and non-volatile memory, the method comprising: storing in the non-volatile memory a protection-setting area protection setting data to control access to a protected area of the non-volatile memory; avoid writing any part of the protection-setting area unless the part belongs to an erased state; only if The protection-set area is allowed to be erased when the protected area is in an erased state.

The features and embodiments thereof previously described may also be additional features of these embodiments, as appropriate. In particular, as previously described, the protectable area can be a protected area of the non-volatile memory, and the protection setting data can include one or more protection flags as previously described.

Preferably, the non-volatile memory control logic operates independently of the processor. It preferably includes a different logic gate separate from the processor. In this way, a malicious or unnoticed program cannot ignore the non-volatile memory control logic and execute code on the processor. In the preferred embodiment, the memory protection logic is similarly independent of the processor.

US 6,952,778 describes a microcontroller that provides protection of memory block reads and/or writes that implement memory in accordance with established rules. These rules allocate the respective levels of memory blocks and are stored in a supervised non-volatile memory. When it has begun to be programmed according to the needs of an end user, the block security level can be enhanced unless the supervisor non-volatile memory is erased and the microcontroller is restarted. This causes the user-defined default security level to be re-stored.

However, the method relies on the successful restoration of the preset security level to cause the memory blocks to be adequately protected. If an attacker can be bound to restart the processing of the microcontroller, the contents of the memory may be lost and protected by the attacker.

In contrast, the preferred embodiment of the present invention uses specialized non-volatile memory control logic and memory protection logic to ensure that the protection settings data can only be severed after any sensitive information has been erased from the device. Set.

The non-volatile memory control logic can be set such that the only mechanism provided by the non-volatile memory control logic to erase the protection-set area is an instruction that erases the protectable area and the protection-set area. This can be an instruction to erase all non-volatile memory on the device.

If the protection-setting area and the protectable area include In the same memory page or erasable block, the non-volatile memory control logic is preferably configured to erase all of the formed protectable regions before erasing any pages or blocks forming part of the protection-setting region Page or block. In this way, if the erase operation is interrupted before completion, if the protectable area has not been completely erased, the protection setting data will still be presented, thereby continuing to provide protection.

The memory protection logic can be set such that when the protection-set region is in an erased state, access to the protectable region is the highest level in the sequence of the restriction levels. It limits access to the protected area by presetting, for example, assuming that a user forgets to set a new setting profile after erasing, providing additional security.

By allowing writing to the protection-setting area in an erased state, the protection setting information can be set during the manufacturing process or authorization, as well as during any subsequent reprogramming of the device.

The non-volatile memory control logic is preferably configured to receive an instruction to write a portion of the protection-set area and to check if the portion is an erased state to respond to the instruction before allowing the write. This can be done by reading the portion and determining a natural erase state of the non-volatile memory type. For example, after a page has been erased, the flash memory has a binary "1" on each bit. The memory control logic thereby checks whether each bit is "1" before allowing the write operation. Other memory types can of course also read "0" or have other essential erase states.

Alternatively, the non-volatile memory region may include an erase The status flag is reset when the area is erased, but when a first write operation is performed to the area, the flags are set by the non-volatile memory control logic. In this case, the non-volatile memory control logic may check one or more erase status flags before allowing a write operation to a portion of the protection-set region.

The memory-protection set area can store one or more values that define a protectable area of the non-volatile memory and/or a protected area that defines the volatile memory as previously described. In this way, an attacker cannot change the definition of the protected area without first destroying the content.

The above embodiments are merely examples for convenience of explanation, and are not limited to the above embodiments.

2‧‧‧Highest level supply module

4a‧‧‧High-level main module

4b, 4c‧‧‧ Other major modules

6‧‧‧Submodule

Around 6a, 6b, 6c‧‧

8‧‧‧Submodule

10‧‧‧ hour pulse control

52‧‧‧Requirement of resource requirements

54‧‧‧Reset demand line

56‧‧‧Price level setting

58‧‧‧clock source input

60‧‧‧ Partner demand input

62‧‧‧ Partner demand output

64‧‧‧ interface

12, 12a, 12b, 12c, 12d‧‧‧ state machine

14 16 22‧‧"Interface

28‧‧‧Ultra Low Battery (ULP) Register

30‧‧‧Main voltage register

32‧‧‧ switch

34‧‧‧RC (resistance-capacitor) oscillator

36‧‧‧Crystal oscillator

38‧‧‧ Clock source section

40‧‧‧buffer

50‧‧‧Resource demand line

65‧‧‧Setting interface

66‧‧‧clock output

68‧‧‧Reset output

69‧‧‧Status output

70,72,74,76,78,80‧‧‧ main modules

82,84,86‧‧‧downstream links

88‧‧‧Required reset link

90‧‧‧Reset downstream links

92‧‧‧ Partner requirements

The preferred embodiments of the present invention will be described herein, but by way of example only, and with reference to the accompanying drawings in which: FIG. 1 is a schematic diagram of a microcontroller of an embodiment of the invention; FIG. A schematic diagram of the main software components in the architecture; and Figure 3 is a schematic memory map of the microcontroller.

1 shows an integrated circuit microcontroller 1 or a radio-on-a-chip including a resistor-capacitor oscillator and/or receivable from an off-chip. An input clock logic 3 of a crystal oscillator (not shown), a power management circuit 5, a processor 7 (such as an ARM (RTM) Cortex-M0), a memory protection unit 9, a random access memory Body (RAM) 11, a flash memory controller 20, a flash memory 13. A radio frequency communication logic 17, one or more peripherals 15, and an input/output circuit 19.

These components are interconnected using suitable wiring and/or bus bars (not shown). The microcontroller 1 can use a Harvard architecture or a von Neumann architecture. The memory protection unit 9 is configured to intercept all memory access instructions from the processor 7 to the RAM 11 and to the flash memory controller 20.

The microcontroller 1 also has a debug interface 18 that can be used to load data into the flash memory 13 and to debug the processor 7. It does not directly access the RAM 11 and the flash memory 13, but must access the memory via the memory protection unit 9 and the flash memory controller 20.

In use, the microcontroller 1 can be coupled to a number of external components, such as a power supply, a radio frequency antenna, a crystal oscillator, a plurality of inductors, an output device, and the like.

Figure 2 shows the software components that can be mounted on the microcontroller 1. Connected to the microcontroller 1 hardware is a selected hardware abstraction layer 21, such as the ARM (RTM) Cortex microcontroller software interface standard. Above it is a firmware module 23 and a separate software application 27.

The firmware module 23 is a binary application comprising a plurality of embedded software blocks. A radio frequency protocol block 31 implements one or more wireless protocol stacks. A radio frequency event manager 33 provides access schedules and sets of events for the radio frequency communication logic 17. A database 35 provides shared hardware resource management and functions, such as random number generation, setting interception, and prioritization Sequence, power management (for example, enabling and disabling several peripherals), encryption functions, etc. A firmware manager 37 supports enabling and disabling the firmware module and enabling and disabling the wireless protocol stack.

The firmware module 23 does not need to be a complete operating system, and does not need to support multiplex processing, memory allocation, and the like.

An application interface (API) 29 for the firmware module 23 allows the software application 27 to invoke the function functions in the firmware module 23. It can be implemented entirely using system calls. When an ARM (RTM) processor is used, each API function prototype is mapped to a firmware function at compile time via an associated supervisor call unit. This mapping can be provided to the developer of the software application 27 to allow the function to be called correctly.

The firmware module 23 can pass an event to the software application 27 as a software interrupt, the content being suspended until it is read (polled) by the application software 27. This reading is done via an API call (eg event_get()).

FIG. 3 shows how the RAM 11 and the flash memory 13 are shared between the firmware module 23 and the software application 27. The flash memory 13 is assigned a number of addresses from zero (0x0000 0000) to SizeOfProgMem to store executable code.

Other areas of the flash memory 13 that may be located on its own flash page extend from MemConfigStart to MemConfigEnd and are used to store configuration data for use by the memory protection unit 9. In one set of embodiments, this page extends from 0x1000 0000 to 0x1000 07ff, but as with all of the address values mentioned herein, these values are based on the particular processor architecture used on any given embodiment.

The RAM 11 is configured to rise from an address of 0x2000 0000 to an address of 0x2000 0000+SizeOfRAM.

The program area of the flash memory 13 includes two restricted areas on both sides of the address CLEAN0 (code length area 0). The area 0 between zero and CLEAN0 is where the firmware module 23 is loaded. A firmware interrupt vector table is stored at address zero. Area 1 rising from CLEAN0 to SizeOfProgMem is where the software application is loaded. It may also have an interrupt vector table located at address CLEAN0.

The RAM 11 similarly has a region 0 from the base address 0x2000 000 to RLENR0, and a region 1 extending upward from RLENR0. RAM area 0 provides heap storage for the firmware module, while RAM area 1 provides stacked storage for the software application 27. A call stack is shared between the firmware module 23 and the software application 27, and grows downward from (0x2000 0000 + SizeOfRAM). The memory allocated to the call stack must be large enough to meet the requirements of the software application 27 and the firmware module 23.

The values of CLEANR0 and RLENR0 are stored in the memory protection setting area of the flash memory 13.

At the time of power supply, the related data stored in the memory protection setting area of the flash memory 13 is copied to the memory setting register accessible by the memory protection logic 9. The registers can only be written by a hardware state machine that is executed only when the microcontroller 1 is booted, such that the only way to change the contents of the registers is to change the memory protection settings of the flash memory 13. Information in the area.

The memory protection logic 9 is configured to intercept all memory access requirements (e.g., data extraction or instruction fetch operations) from the processor 7 to the flash memory 13 and the RAM 11. It can recognize an instruction-extraction operation from a "transaction type" on the memory bus. For the processor 7, all instruction fetches from the flash memory 13 are generated. If the address of the fetched instruction is less than CLEAR0, the memory protection logic 9 updates a single bit in a "firm region" register. The meta flag is 1, and if the address of the fetched instruction is greater than or equal to CLEAR0, the memory protection logic 9 updates the flag to zero.

For each data access request, the memory protection logic 9 determines whether the access requirement is from the firmware module 23 or elsewhere by checking the value of the "firm region" register. It can be set to detect whether the source of the request is the debug interface 18 or a direct memory access (DMA) unit by determining the identity of the active memory bus master. It also accesses the memory protection settings register and determines whether to allow or deny the access requirement based on the state of the "firm region" register and the identity of the bus primary device.

In some preferred embodiments, the software application 27 is denied read and write accesses to the flash region 0 and to the RAM region 0. This protects the confidentiality of the firmware module 23 and prevents the software application from inadvertently or maliciously writing to the memory area allocated to the firmware module 23, thereby increasing robustness and security. The software application flash area 1 can also be protected from being read access, for example via an external debug interface 18 for protection from being read back.

Figure 4 shows a decision table that the microcontroller 1 can implement for protection of the flash memory 13 during unauthorized access. Of course other alternative implementations are possible.

The two binary flags are stored in the memory-protection setting area of the flash memory 13 (and are copied to the scratchpad at startup). The first set flag is used to avoid data read and write accesses to all of the program flashes via the debug interface 18. The flag of the second setup avoids any data read and write accesses other than the code execution of the region 0 itself to all of the region 0 flash memory. The execution access (i.e., instruction fetch) of the processor 7 is still allowed even if the data read access is denied.

If an attack can change the data stored in the memory-protection setting area of the flash memory 13, the protection mechanism can be skipped. However, the flash memory controller 20 avoids writing to the memory-protection setting area unless it is in an erased state. In addition, the flash memory controller 20 avoids erasing of the memory-protection setting area unless area 0 and area 1 of the flash memory 13 have been erased first. It uses digital logic to implement a finite state machine to achieve these conditions.

If the flash memory controller 20 receives an instruction to write a string to an address of the memory-protection set area, it will first read the content present on the address and will only allow the write. If the existing content is all "1" in the binary, it indicates that the address has not been written in an erasure of the flash memory of the memory-protection setting area. If the check fails, it will reject the write and issue an exception for processor 7.

If the flash memory controller 20 receives an instruction to wipe In addition to the entire flash memory 13, it will first respond by erasing the contents of flash area 0 and flash area 1 before erasing the memory-protection setting area. For this reason, the memory-protection setting area is preferably stored in its own erasable flash page, separated from any stylized area of the flash memory 13.

The flash memory controller 20 will reject any instructions to erase only the memory-protection setting area.

It will be apparent to those skilled in the art that the microcontroller 1 can also be configured to prevent execution of code other than area 0 of the flash memory 13 to access important features, such as low level functions associated with the radio frequency communication logic 17. The function's register, the power control logic 5, a direct-memory access (DMA) controller, or an interrupt register.

It is to be understood by those skilled in the art that the above-described embodiments are only intended to be illustrative, and the scope of the invention is intended to be limited by the scope of the claims.

1‧‧‧Integrated Circuit Microcontroller

3‧‧‧ clock logic

5‧‧‧Power Management Circuit

7‧‧‧ Processor

9‧‧‧Memory Protection Unit

11‧‧‧ Random access memory

13‧‧‧Flash memory

15‧‧‧around

17‧‧‧RF communication logic

18‧‧‧Debugging interface

19‧‧‧Input/Output Circuit

20‧‧‧Flash Memory Controller

Claims (29)

An integrated circuit device includes a processor, a memory for storing executable code, and a memory protection logic, wherein the memory protection logic is configured to: determine one of the protected areas for the memory Reading a status of the protection flag; detecting a memory read requirement of the processor; determining whether the read requirement is for an address in the protected area of the memory; determining whether the processor is executing The read request is issued when the code stored in the protected area of the memory is issued; if the read protection flag for the protected area is set, the address used in the protected area is rejected Read request, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor issues the read when executing the code stored in the protected area demand. The device of claim 1, wherein the memory protection logic comprises hardware logic separate from the processor. The device of claim 1 or 2, wherein if the read protection flag for the protected area is not set, the memory protection logic is set to allow for the protected memory. The read requirement of the address in the body area. A device as claimed in any one of the preceding claims, wherein, if the read protection flag for the protected area is set, the record The memory protection logic is configured to reject the read requirement for the address in the protected area unless the processor issues the read request when executing the code stored in the protected area. The apparatus of any one of the preceding claims, wherein the memory protection logic is further configured to determine a state of a write protection flag for the protected area and, if used for the protected area A write flag is set to reject the write request for the address in the protected area unless the processor issues the write request when executing the code stored in the protected area. A device as claimed in any one of the preceding claims, wherein the memory system is a non-volatile memory. A device as claimed in any of the preceding claims, wherein the memory protection logic is configured to supervise all access to the memory. The device of any one of the preceding claims, wherein the memory protection logic is configured to set up a register for each instruction-acquisition operation according to whether the address of the fetch instruction is located in the protected area. on. The device of any one of the preceding claims, wherein the memory protection logic is configured to determine whether the processor issues the read request when executing a code stored in the protected area of the memory, It is determined whether the address of the operation is located in the protected area by determining an instruction immediately before the memory access requirement. A device as claimed in any one of the preceding claims, wherein the protected area is variable and is defined by one or more addresses stored in the device. A device as claimed in any one of the preceding claims, wherein the protected area of the memory extends between a predetermined invariant address and a variable point within the memory range, and the memory protection The unit is configured to determine whether the read requirement is for an address in the protected area by determining whether the address is located at the preset invariant address and the variable memory address Decide between. A device as claimed in any one of the preceding claims, wherein the memory system for storing executable code is a non-volatile memory, and the device further comprises volatile memory, and wherein, if used A read flag of the protected area of the volatile memory is set, the memory protection logic being further configured to reject the read requirement for the protected area address of the volatile memory, unless the processor is These read requests are issued when the code stored in the protected area of the non-volatile memory is executed. A device as claimed in any one of the preceding claims, comprising an interface to allow memory access by an external debugger or software reader, wherein a debug flag is provided for the area When the flag is set, the memory protection logic is configured to reject read requests received via the interface for addresses in one or more protected areas of the volatile or non-volatile memory. The device of any one of the preceding claims, comprising an integrated radio frequency communication logic, wherein a firmware module including a code for implementing a radio frequency protocol stack is stored in a protected area of the code memory. And a memory in which the software application selectively associated with the firmware module is stored outside the protected area. The device of any one of the preceding claims, comprising non-volatile memory and a protection-setting area configured to store the protection flag or the protection flag in the non-volatile memory, Wherein the apparatus further includes non-volatile memory control logic configured to avoid writing to any portion of the protection-set area unless the portion is in an erased state. The device of claim 15, wherein the non-volatile memory control logic is further configured to allow the protection when only a protected area of the non-volatile memory is in an erased state - The setting area is erased. A method of controlling memory access on an integrated circuit device, the integrated circuit device including a processor and memory for storing executable code, the method comprising: determining a protected for the memory a state of a read protection flag of the area; detecting a memory read requirement of the processor; determining whether the read requirement is for an address in the protected area of the memory; determining whether the processor is The read request is issued when executing the code stored in the protected area of the memory; if the read protection flag is used for the protected area to be established, rejecting the bit in the protected area The read request in the address, unless at least one of the one or more access conditions is met, wherein one of the access conditions is when the code stored in the protected area is executed, the processor issues the same Read the requirements. A method of controlling memory access on an integrated circuit device, the integrated circuit device including a processor and memory for storing executable code, the method comprising: determining a protected for the memory a read protection flag of the area is set up; detecting a memory read requirement of the processor; determining that the read requirement is for an address in the protected area of the memory; determining the processor The read request is issued when executing the code stored in the protected area of the memory; and the read request is allowed. An integrated circuit device includes a processor, non-volatile memory, non-volatile memory control logic, and memory protection logic, wherein: the memory protection logic is based on a protection-setting stored in the non-volatile memory The protection setting data in the area is configured to control access to a protectable area of the non-volatile memory; the non-volatile memory control logic is configured to avoid writing to any portion of the protection-setting area, Unless the portion is in an erased state; and the non-volatile memory control logic is configured to allow the protection-set region to be erased only if the protectable region is in an erased state. The device of claim 19, wherein the non-volatile memory control logic and/or memory protection logic comprises a plurality of logic gates separate from the processor. The device of claim 19 or 20, wherein the non-volatile memory control logic is set such that the unique mechanism provided by the non-volatile memory control logic for erasing the protection-setting region It is an instruction to erase both the protectable area and the protected-set area. The device of any one of claims 19 to 21, wherein the protection-setting area and the protectable area comprise different memory pages or erasable blocks, and the non-volatile memory control logic is The page is set to erase all pages or blocks forming the protectable area before erasing any pages or blocks forming part of the protection-setting area. The device of any one of claims 19 to 22, wherein the memory protection logic is set such that when the protection-setting area is in an erased state, the protected area is stored Take the highest level in an ordered group of restricted levels. The device of any one of claims 19 to 23, wherein the non-volatile memory control logic is configured to receive an instruction to write to a portion of the protection-setting region, and A response is allowed before the write to check that the portion is in an erased state. The device of claim 24, wherein the non-volatile memory system is of a type having a naturally erased state, and wherein the non-volatile memory control logic is configured to read the portion and Determine whether it is in the naturally erased state to check that the portion is in an erased state. The device of any one of claims 19 to 24, wherein the non-volatile memory comprises a plurality of regions, the regions comprising a plurality of erase-state flags, wherein the device is configured to be used for each Resetting a respective erase-state flag when an area is erased, wherein the non-volatile memory control logic is configured to set up a respective one when a first write operation is performed to each region An erase-state flag, and wherein the non-volatile memory control logic is configured to check one or more erased status flags before allowing a write operation to a portion of the protection-set region . The apparatus of any one of claims 19 to 26, configured to store, in the memory-protection setting area, one or more values defining the protectable area of the non-volatile memory And/or define a protected area of volatile memory. The device of any one of claims 19 to 27, wherein the protection setting data includes a read protection flag for the protectable area of the non-volatile memory, and wherein the memory protection logic is Setting to: determine a state of the read protection flag; detect a memory read requirement of the processor; determine whether the read requirement is for an address in the protected area of the memory; Whether the processor issues the read request when executing the code stored in the protected area of the memory; If the read protection flag for the protectable area is established, the read requirement for the address in the protectable area is rejected unless at least one of one or more access conditions is met, wherein One of the equal access conditions is that the processor issues the read requests when executing the code stored in the protectable area. A method of controlling memory access on an integrated circuit device, the integrated circuit device comprising a processor and non-volatile memory, the method comprising: storing in a protection-setting area of the non-volatile memory Protection setting data to control access to a protected area of the non-volatile memory; avoid writing any part of the protection-setting area unless the part is in an erased state; and only if The protected area is allowed to be erased when the protected area is in an erased state.